AD8180ANZ [ADI]
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| 型号： | AD8180ANZ |
| 厂家： | 
ADI |
| 描述： | 暂无描述 复用器 开关 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
750 MHz, 3.8 mA
a
10 ns Switching Multiplexers
AD8180/AD8182*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
High Speed
> 750 MHz Bandwidth (–3 dB)
750 V/s Slew Rate
Fast Settling Time of 14 ns to 0.1%
Low Power: 3.8 mA (AD8180), 6.8 mA (AD8182)
Excellent Video Specifications (RL ≥ 1 k⍀)
Gain Flatness of 0.1 dB Beyond 100 MHz
0.02% Differential Gain Error
0.02؇ Differential Phase Error
Low Glitch: < 35 mV
Low All-Hostile Crosstalk of –80 dB @ 5 MHz
High “OFF” Isolation of –90 dB @ 5 MHz
Low Cost
IN0
GND
IN1
1
2
3
4
8
7
6
5
SELECT
+1
DECODER
ENABLE
OUT
+1
+V
S
–V
S
AD8180
IN0 A
GND
1
2
3
4
5
6
14 SELECT A
13
+1
DECODER
ENABLE A
IN1 A
12 OUT A
+1
+V
S
–V
AD8182
11
S
IN1 B
GND
10 OUT B
+1
9
8
ENABLE B
DECODER
Fast Output Disable Feature for Connecting Multiple Devices
IN0 B
7
+1
SELECT B
APPLICATIONS
Pixel Switching for “Picture-In-Picture”
Switching in LCD and Plasma Displays
Video Switchers and Routers
Table I. Truth Table
PRODUCT DESCRIPTION
SELECT
ENABLE
OUTPUT
The AD8180 (single) and AD8182 (dual) are high speed 2-to-1
multiplexers. They offer –3 dB signal bandwidth greater than
750 MHz along with slew rate of 750 V/µs. With better than
80 dB of crosstalk and isolation, they are useful in many high
speed applications. The differential gain and differential phase
error of 0.02% and 0.02°, along with 0.1 dB flatness beyond
100 MHz make the AD8180 and AD8182 ideal for professional
video multiplexing. They offer 10 ns switching time making
them an excellent choice for pixel switching (picture-in-picture)
while consuming less than 3.8 mA (per 2:1 mux) on ±5 V sup-
ply voltages.
0
1
0
1
0
0
1
1
IN0
IN1
High Z
High Z
Both devices offer a high speed disable feature allowing the
output to be configured into a high impedance state. This al-
lows multiple outputs to be connected together for cascading
stages while the “OFF” channels do not load the output bus.
They operate on voltage supplies of ±5 V and are offered in 8-
and 14-lead plastic DIP and SOIC packages.
500mV
/DIV
5ns/DIV
Figure 1. AD8180/AD8182 Switching Characteristics
*Protected under U.S. Patent Number 5,955,908.
REV. B
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ TA = +25؇C, VS = ؎5 V, RL = 2 k⍀ unless otherwise noted)
AD8180/AD8182–SPECIFICATIONS
AD8180A/AD8182A
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
Channel Switching Time1
Channel-to-Channel
50% Logic to 10% Output Settling
50% Logic to 90% Output Settling
50% Logic to 99.9% Output Settling
ENABLE to Channel ON Time2
50% Logic to 90% Output Settling
ENABLE to Channel OFF Time2
50% Logic to 90% Output Settling
Channel Switching Transient (Glitch)3
IN0 = +1 V, IN1 = –1 V; RL = 1 kΩ
IN0 = +1 V, IN1 = –1 V; RL = 1 kΩ
IN0 = +1 V, IN1 = –1 V; RL = 1 kΩ
SEL = 0 or 1
IN0 = +1 V, –1 V or IN1 = –1 V, +1 V; RL = 1 kΩ
SEL = 0 or 1
5
10
14
ns
ns
ns
10.5
ns
IN0 = +1 V, –1 V or IN1 = –1 V, +1 V; RL = 1 kΩ
All Inputs Are Grounded, RL = 1 kΩ
11
±25 /±35
ns
mV
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Input Current
Logic “0” Input Current
SEL and ENABLE Inputs
SEL and ENABLE Inputs
SEL, ENABLE = +4 V
SEL, ENABLE = +0.4 V
2.0
V
V
nA
µA
0.8
200
3
10
2
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)4
–3 dB Bandwidth (Small Signal)4
–3 dB Bandwidth (Large Signal)
–3 dB Bandwidth (Large Si
0.1 dB Bandwidth4, 5
AD8180R VIN = 50 mV rms, RL = 5 kΩ
750
640
120
110
930
780
150
135
100
210
210
750
14
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
AD8182R VIN = 50 mV rms, RL = 5 kΩ
AD8180R VIN = 1 V rms, RL = 5 kΩ
AD8182R VIN = 1 V rms, RL = 5 kΩ
VIN = 50 mV rms, RL = 5 kΩ, RS = 0 Ω
AD8180R VIN = 50 mV rms, RL = 1 kΩ–5 kΩ, RS = 150 Ω
AD8182R VIN = 50 mV rms, RL = 1 kΩ–5 kΩ, RS = 125 Ω
2 V Step
0.1 dB Bandwidth4, 5
Slew Rate
Settling Time to 0.1%
2 V Step
DISTORTION/NOISE PERFORMANCE
Differential Gain
Differential Phase
ƒ = 3.58 MHz, RL = 1 kΩ
ƒ = 3.58 MHz, RL = 1 kΩ
0.02
0.02
–80
–65
–78
–63
–89
–93
4.5
0.04
0.04
%
Degrees
dB
dB
dB
dB
dB
dB
nV/√Hz
dBc
All Hostile Crosstalk6
AD8180R ƒ = 5 MHz, RL = 1 kΩ
ƒ = 30 MHz, RL = 1 kΩ
AD8182R ƒ = 5 MHz, RL = 1 kΩ
ƒ = 30 MHz, RL = 1 kΩ
AD8180R ƒ = 5 MHz, RL = 30 Ω
AD8182R ƒ = 5 MHz, RL = 30 Ω
ƒ = 10 kHz–30 MHz
All Hostile Crosstalk6
OFF Isolation7
OFF Isolation7
Voltage Noise
Total Harmonic Distortion
ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kΩ
–78
DC/TRANSFER CHARACTERISTICS
Voltage Gain8
VIN = ±1 V, RL = 2 kΩ
VIN = ±1 V, RL = 10 kΩ
0.982
0.993
1
V/V
V/V
mV
mV
mV
µV/°C
µA
µA
0.986
Input Offset Voltage
12
15
4
TMIN to TMAX
Channel-to-Channel
Input Offset Voltage Matching
Input Offset Drift
Input Bias Current
0.5
11
1
5
7
TMIN to TMAX
Input Bias Current Drift
12
nA/°C
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
1
2.2
1.5
1.5
±3.3
MΩ
pF
pF
V
Channel Enabled (R Package)
Channel Disabled (R Package)
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Current
RL = 500 Ω9
±3.0
±3.1
30
27
V
mA
Ω
Output Resistance
Enabled
Disabled
Disabled (R Package)
1
10
1.7
MΩ
pF
Output Capacitance
POWER SUPPLY
Operating Range
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Quiescent Current
±4
54
45
±6
V
dB
dB
mA
mA
mA
mA
mA
+PSRR
–PSRR
+VS = +4.5 V to +5.5 V, –VS = –5 V
–VS = –4.5 V to –5.5 V, +VS = +5 V
All Channels “ON”
TMIN to TMAX
All Channels “OFF”
TMIN to TMAX
57
51
3.8/6.8
4.5/8
4.75/8.5
2/3
1.3/2
4
2/3
AD8182, One Channel “ON”
OPERATING TEMPERATURE RANGE
–40
+85
°C
–2–
REV. B
AD8180/AD8182
NOTES
1ENABLE pin is grounded. IN0 = +1 V dc, IN1 = –1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value
(+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa.
2ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set
IN0 = +1 V dc, IN1 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆tOFF is the disable
time, ∆tON is the enable time.
3All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing RL.
4Decreasing RL lowers the bandwidth slightly. Increasing CL lowers the bandwidth considerably (see Figure 19).
5A resistor (RS) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce band-
width (see Figure 20.)
6Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with VIN = 0.707 V rms and monitor output at ƒ = 5 and 30 MHz.
RL = 1 kΩ (see Figure 13).
7Mux is disabled (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simulate
RON of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the load imped-
ance determines the crosstalk.
8Voltage gain decreases for lower values of RL. The resistive divider formed by the mux enabled output resistance (27 Ω) and RL causes a gain which decreases as RL decreases
(i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for RL = 1 kΩ).
9Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
While the AD8180 and AD8182 are internally short circuit
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves shown in Figures 2 and 3.
Internal Power Dissipation2
AD8180 8-Lead Plastic DIP (N) . . . . . . . . . . . . . . . . 1.3 Watts
AD8180 8-Lead Small Outline (R) . . . . . . . . . . . . . . 0.9 Watts
AD8182 14-Lead Plastic DIP (N) . . . . . . . . . . . . . . . 1.6 Watts
AD8182 14-Lead Small Outline (R) . . . . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . Observe Power Derating Curves
Storage Temperature Range
2.0
8-LEAD PLASTIC DIP PACKAGE
T
= +150؇C
J
1.5
N and R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . +300°C
NOTES
1.0
0.5
0
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
8-LEAD SOIC PACKAGE
2Specification is for device in free air: 8-Lead Plastic DIP Package: θJA = 90°C/W;
8-Lead SOIC Package: θJA = 155°C/W; 14-Lead Plastic Package: θJA = 75°C/W;
14-Lead SOIC Package: θJA = 120°C/W, where PD = (TJ–TA)/θJA
.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
ORDERING GUIDE
Temperature
Range
Package
Package
Option
Figure 2. AD8180 Maximum Power Dissipation vs.
Temperature
Model
Description
AD8180AN
AD8180AR
–40°C to +85°C 8-Lead Plastic DIP
–40°C to +85°C 8-Lead SOIC
AD8180AR-REEL –40°C to +85°C 13" Reel SOIC
AD8180AR-REEL7 –40°C to +85°C 7" Reel SOIC
–40°C to +85°C 14-Lead Plastic DIP
–40°C to +85°C 14-Lead Narrow SOIC R-14
AD8182AR-REEL –40°C to +85°C 13" Reel SOIC
AD8182AR-REEL7 –40°C to +85°C 7" Reel SOIC
N-8
SO-8
SO-8
SO-8
N-14
2.5
T
= +150؇C
J
AD8182AN
AD8182AR
2.0
1.5
1.0
0.5
14-LEAD
PLASTIC DIP PACKAGE
R-14
R-14
AD8180-EB
AD8182-EB
Evaluation Board
Evaluation Board
MAXIMUM POWER DISSIPATION
14-LEAD SOIC
The maximum power that can be safely dissipated by the
AD8180 and AD8182 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. AD8182 Maximum Power Dissipation vs.
Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8180/AD8182 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD8180/AD8182–Typical Performance Curves
V
= 50mV rms
= 5k⍀
8180R
8182R
IN
1
R
R
L
S
= 0⍀
0
–1
–2
–3
500mV
/DIV
–4
–5
–6
–7
1M
10M
100M
1G
5ns/DIV
FREQUENCY – Hz
Figure 4. Channel Switching Characteristics
Figure 7. Small Signal Frequency Response
V
R
R
= 50mV rms
= 5k⍀
= 0⍀
IN
L
S
1.0
0.8
0.6
0.4
DUT OUT
250mV
/DIV
8180R
8182R
0.2
0.0
–0.2
–0.4
10ns/DIV
1M
10M
100M
1G
FREQUENCY – Hz
Figure 5. Enable and Disable Switching Characteristics
Figure 8. Gain Flatness vs. Frequency
3
0
V
V
= 1.0V rms
= 0.5V rms
= 0.25V rms
R
= 1k⍀
IN
L
–3
IN
–6
–9
V
IN
50mV
/DIV
–12
–15
–18
V
= 125mV rms
= 62.5mV rms
IN
IN
–21
–24
–27
V
1M
10M
100M
1G
25ns/DIV
FREQUENCY – Hz
Figure 6. Channel Switching Transient (Glitch)
Figure 9. Large Signal Frequency Response
REV. B
–4–
AD8180/AD8182
–10
–20
–30
–40
–50
V
R
= 0.707V rms
= 1k⍀
IN
50⍀
OUT A
1k⍀
1
3
L
50⍀
OUT B
1k⍀
5
7
50mV
/DIV
VIN
50⍀
AD8182
–60
–70
–80
AD8182R
AD8180R
–90
–100
–110
5ns/DIV
0.1M
1M
10M
FREQUENCY – Hz
100M
1G
Figure 10. Small Signal Transient Response
Figure 13. All-Hostile Crosstalk vs. Frequency
–10
ALL INPUTS = 0.446V rms
R
= 30⍀
L
–20
–30
–40
–50
8180R OR
8182R
OUT A
ENABLE A = LOGIC 1
ENABLE B = LOGIC 0
30⍀
500mV
/DIV
50⍀
50⍀
OUT B
VIN
30⍀
–60
–70
–80
AD8182
–90
8182R
ENABLE A/B = LOGIC 1
–100
–110
0.03M 0.1M
5ns/DIV
1M
10M
100M
1G
FREQUENCY – Hz
Figure 11. Large Signal Transient Response
Figure 14. “OFF” Isolation vs. Frequency
100
0.020
0.015
R
=
1k⍀
L
0.010
NTSC
0.005
0.000
–0.005
–0.010
–0.015
–0.020
1
2
3
4
5
6
7
8
9
10
11
IRE
10
0.02
0.01
0.00
–0.01
–0.02
1
2
3
4
5
6
7
8
9
10
11
IRE
1
10
100
1k
10k
100k
1M
10M 30M
FREQUENCY – Hz
Figure 12. Differential Gain and Phase Error
Figure 15. Voltage Noise vs. Frequency
REV. B
–5–
AD8180/AD8182–Typical Performance Curves
+1
0
–25
V
= 2V p-p
C
0pF
=
OUT
L
R
= 1k⍀
L
–35
–45
–55
–65
–75
V
R
= 500mV rms
= 5k⍀
IN
–1
L
C
= 100pF
= 33pF
–2
–3
C
10pF
=
C
33pF
=
L
L
L
C
+0.1
0
–4
–5
–6
L
2ND HARMONIC
–0.1
C
= 100pF
L
–0.2
–0.3
–0.4
–7
–8
–9
3RD HARMONIC
–85
–95
100k
200M
100M
1M
4M
10M
40M
100M
400M
1G
1M
10M
150M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Harmonic Distortion vs. Frequency
Figure 19. Frequency Response vs. Capacitive Load
31.6M
3.16M
120
100
80
+1
R
= 0⍀
S
Z
(DISABLED)
OUT
0
R
= 75⍀
S
–1
V
R
= 50mV rms
= 5k⍀
IN
R
= 150⍀
S
–2
–3
1.0
0.8
L
Z
(ENABLED)
316k
31.6k
3.16k
IN
R
= 0⍀
S
–4
–5
0.6
0.4
60
40
Z
(ENABLED)
OUT
0.2
–6
–7
–8
–9
R
= 75⍀
S
0
316
20
0
–0.2
R
= 150⍀
S
31.6
–0.4
1G
1k
10k
100k
1M
10M
100M
1M
4M
10M
40M
100M
400M
1G
FREQUENCY – Hz
FREQUENCY – Hz
Figure 17. Disabled Output and Input Impedance vs.
Frequency
Figure 20. Frequency Response vs. Input Series Resistance
5
4
3
2
1
0
–10
–20
–30
0
–1
–2
–40
–50
–60
–70
+PSRR
–PSRR
–3
–4
–5
–5
–4
–3
–2
–1
0
1
2
3
4
5
0.03
0.1
1
10
100
500
FREQUENCY – MHz
INPUT VOLTAGE – Volts
Figure 18. Power Supply Rejection vs. Frequency
Figure 21. Output Voltage vs. Input Voltage, RL = 1 kΩ
REV. B
–6–
AD8180/AD8182
THEORY OF OPERATION
for RL > 10 kΩ. For heavier loads, the dc gain is approximately
that of the voltage divider formed by the output impedance of
the mux (typically 27 Ω) and RL.
The AD8180 and AD8182 video multiplexers are designed for
fast-switching (10 ns) and wide bandwidth (> 750 MHz). This
performance is attained with low power dissipation (3.8 mA per
active channel) through the use of proprietary circuit techniques
and a dielectrically-isolated complementary bipolar process.
These devices have a fast disable function that allows the out-
puts of several muxes to be wired in parallel to form a larger mux
with little degradation in switching time. The low disabled output
capacitance (1.7 pF) of these muxes helps to preserve the system
bandwidth in larger matrices. Unlike earlier CMOS switches,
the switched open-loop buffer architecture of the AD8180 and
AD8182 provides a unidirectional signal path with minimal switch-
ing glitches and constant, low input capacitance. Since the input
impedance of these muxes is nearly independent of the load imped-
ance and the state of the mux, the frequency response of the ON
channels in a large switch matrix is not affected by fanout.
High speed disable clamp circuits at the bases of Q5–Q8 (not
shown) allow the buffers to turn off quickly and cleanly without
dissipating much power once off. Moreover, these clamps shunt
displacement currents flowing through the junction capacitances
of Q1–Q4 away from the bases of Q5–Q8 and to ac ground
through low impedances. The two-pole high pass frequency
response of the T switch formed by these clamps is a significant
improvement over the one-pole high pass response of a simple
series CMOS switch. As a result, board and package parasitics,
especially stray capacitance between inputs and outputs may
limit the achievable crosstalk and off isolation.
LAYOUT CONSIDERATIONS:
Realizing the high speed performance attainable with the
AD8180 and AD8182 requires careful attention to board layout
and component selection. Proper RF design techniques and low
parasitic component selection are mandatory.
Figure 22 shows a block diagram and simplified schematic of the
AD8180, which contains two switched buffers (S0 and S1) that
share a common output. The decoder logic translates TTL-
compatible logic inputs (SELECT and ENABLE) to internal,
differential ECL levels for fast, low-glitch switching. The SELECT
input determines which of the two buffers is enabled, unless the
ENABLE input is HIGH, in which case both buffers are disabled
and the output is switched to a high impedance state.
Wire wrap boards, prototype boards, and sockets are not recom-
mended because of their high parasitic inductance and capaci-
tance. Instead, surface-mount components should be soldered
directly to a printed circuit board (PCB). The PCB should have
a ground plane covering all unused portions of the component
side of the board to provide a low impedance ground path. The
ground plane should be removed from the area near input and
output pins to reduce stray capacitance.
AD8180
I1
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/4 inch of each power pin. An additional large
(4.7 µF–10 µF) tantalum capacitor should be connected in
parallel with each of the smaller capacitors for low impedance
supply bypassing over a broad range of frequencies.
SELECT
1
2
3
4
8
7
6
5
IN0
Q5
Q7
Q3
Q1
S0
I3
GND
ENABLE
DECODER
Signal traces should be as short as possible. Stripline or micros-
trip techniques should be used for long signal traces (longer
than about 1 inch). These should be designed with a character-
istic impedance of 50 Ω or 75 Ω and be properly terminated at
the end using surface mount components.
OUT
IN1
I2
Q6
Q8
Q4
Q2
S1
Careful layout is imperative to minimize crosstalk. Guards
(ground or supply traces) must be run between all signal traces
to limit direct capacitive coupling. Input and output signal lines
should fan out away from the mux as much as possible. If mul-
tiple signal layers are available, a buried stripline structure hav-
ing ground plane above, below, and between signal traces will
have the best crosstalk performance.
–V
S
+V
S
I4
Figure 22. Block Diagram and Simplified Schematic of the
AD8180 Multiplexer
Each open-loop buffer is implemented as a complementary
emitter follower that provides high input impedance, symmetric
slew rate and load drive, and high output-to-input isolation due to
its β2 current gain. The selected buffer is biased ON by fast
switched current sources that allow the buffer to turn on quickly.
Dedicated flatness circuits, combined with the open-loop architec-
ture of the AD8180 and AD8182, keep peaking low (typically
< 1 dB) when driving high capacitive loads, without the need for
external series resistors at the input or output. If better flatness
response is desired, an input series resistance (RS) may be used
(refer to Figure 20), although this will increase crosstalk. The dc
gain of the AD8180 and AD8182 is almost independent of load
Return currents flowing through termination resistors can also
increase crosstalk if these currents flow in sections of the finite-
impedance ground circuit that is shared between more than one
input or output. Minimizing the inductance and resistance of the
ground plane can reduce this effect, but further care should be
taken in positioning the terminations. Terminating cables directly
at the connectors will minimize the return current flowing on the
board, but the signal trace between the connector and the mux will
look like an open stub and will degrade the frequency response.
Moving the termination resistors close to the input pins will im-
prove the frequency response, but the terminations from neigh-
boring inputs should not have a common ground return.
REV. B
–7–
AD8180/AD8182
APPLICATIONS
Multiplexing two RGB Video Sources
With no signal present, the total quiescent current of the cir-
cuit in Figure 23 is 25.6 mA (3.8 mA + 6.8 mA + 3 × 5 mA), or
about 8.5 mA per channel. If either the AD8013 or AD8073
are used, the quiescent current will decrease to about 6.5 mA
per channel.
A common video application requires two RGB sources to be
multiplexed together before the selected signal is applied to a
monitor. Typically one source would be the PC’s normal output,
the second source might be a specialized source such as MPEG
video. Figure 23 shows how such a circuit could be realized
using the AD8180 and AD8182 and three current feedback op
amps. The video inputs to the multiplexers are terminated with
75 Ω resistors. This has the effect of halving the signal amplitude
of the applied signals.
To reduce power consumption further, three AD8011 single
op amps can be used. With a quiescent current of 1 mA, this
will reduce the per channel quiescent current to about 4.5 mA.
Table II. Amplifier Options for RGB Multiplexer
Op Amp Comments
Because all three multiplexers are permanently active, the
ENABLE pins are tied permanently low. The three SELECT
pins are tied together and this signal is used to select the source.
In order to drive a 75 Ω back terminated load (RL = 150 Ω), the
multiplexer outputs are buffered using the AD8001 current feed-
back op amp. A gain of two compensates for the signal halving by
the AD8001 output back termination resistor so that the system
has an overall gain of unity.
AD8001 Highest Bandwidth, 440 MHz (G = +2), ISY = 5 mA
AD8011 Lower Power Consumption, Bandwidth (G = +2) =
210 MHz, ISY = 1 mA
AD8013 Triple Op Amp, Bandwidth (G = +2) = 140 MHz,
ISY = 3.4 mA
AD8073 Lower Power Triple Op Amp, Bandwidth (G = +2) =
100 MHz, ISY = 3.5 mA
If lower speed and crosstalk can be tolerated, either of the triple
op amps, AD8013 or AD8073, can replace the three AD8001 op
amps in the above circuit. Because both devices have bandwidths
in the 100 MHz to 140 MHz range at a gain of +2, these ampli-
fiers will dominate the frequency response of the circuit.
681⍀
681⍀
681⍀
681⍀
+V
S
10F
+
0.1F
MPEG
75⍀
AD8001
R
G
B
0.1F
75⍀
8
7
6
5
1
2
3
4
+1
10F
+
ENABLE
DECODER
–V
S
+1
75⍀
681⍀
+V
AD8180
–V
S
S
+V
S
10F
0.1F
0.1F
+
+
+
R
G
B
0.1F
10F
10F
75⍀
1
2
3
4
5
6
7
14
13
12
11
10
9
+1
75⍀
MONITOR
ENABLE A
AD8001
DECODER
0.1F
0.1F
0.1F
+1
75⍀
10F
AD8182
+
+
+
+V
–V
S
S
75⍀
10F
+1
–V
10F
S
DECODER
ENABLE B
681⍀
75⍀
+1
8
+V
S
10F
+
R
G
B
0.1F
COMPUTER
GRAPHICS
R
TERM
75⍀
AD8001
0.1F
10F
+
SELECT
–V
S
Figure 23. Multiplexing Two Component Video Sources
REV. B
–8–
AD8180/AD8182
Picture-in-Picture or Pixel Switching
CONTROL AND TIMING
Many high end display systems require simultaneous display of
two video pictures (from two different sources) on one screen.
Video conferencing is one such example. In this case the remote
site might be displayed as the main picture with a picture of the
local site “inset” for monitoring purposes. The circuit in Fig-
ure 23 could also be used to implement this “picture-in-picture”
application.
R
G
IN0 A
IN1 A
C
C
D
CDS
OUT A
CDS
AD876 8/10-BIT
20MSPS
A/D
100⍀
Implementing a picture-in-picture algorithm is difficult for
several reasons. Both sources are being displayed simultaneously
(i.e., during the same frame), both sources are in real time, and
both must be synchronized. Figure 24 shows the raster scan-
ning that takes place in all monitors. During every horizontal
scan that includes part of the inset, the source must be switched
twice (i.e., from main to inset and from inset to main). To avoid
screen artifacts, it is critical that switching is clean and fast. The
AD8180 and AD8182, in the above application, switch and
settle to 0.1% accuracy in 14 ns. We quadratically add this
value to the 10 ns settling time of the AD8001, and get an over-
all settling time of 17.2 ns. This yields a sharp, artifact-free
border between the inset and the main video.
AD8182
IN1 B
B
CDS
REFERENCE
OUT B
IN0 B
4:1 MUX TRUTH TABLE
SEL A, SEL B ENA, ENB OUTA, OUTB
0
0
1
1
0
1
0
1
IN0A
IN0B
IN1A
IN1B
Figure 25. Color Document Scanner
The next step in the data acquisition process involves digitizing
the three signal streams. Assuming that the analog to digital
converter chosen has a fast enough sample rate, multiplexing
the three streams into a single ADC is generally more eco-
nomic than using one ADC per channel. In the example
shown, we use the two 2-to-1 multiplexers in the AD8182 to
create a 4-to-1 multiplexer. The enable control pins on the
multiplexers allow the outputs to be wired directly together.
INSET VIDEO
Because of its high bandwidth, the AD8182 is capable of driv-
ing the switched capacitor input stage of the AD876 without
additional buffering. In addition to having the required the
bandwidth, it is necessary to consider the settling time of the
multiplexer. In this case, the ADC has a sample rate of 20 MHz
which corresponds to a sampling period of 50 ns. Typically,
one phase of the sampling clock is used for conversion (i.e., all
levels are held steady) and the other phase is used for switch-
ing and settling to the next channel. Assuming a 50% duty cycle,
the signal chain must settle within 25 ns. With a settling time to
0.1% of 14 ns, the multiplexer easily satisfies this criterion.
MULTIPLEXER MUST SWITCH
CLEANLY ON EACH CROSSING
MAIN VIDEO
Figure 24. “Picture-in-Picture,” Pixel Switching
Color Document Scanner
Figure 25 shows a block diagram of a Color Document Scan-
ner. Charge Coupled Devices (CCDs) find widespread use in
scanner applications. A monochrome CCD delivers a serial
stream of voltage levels, each level being proportional to the
light shining on that cell. In the case of the color image scanner
shown, there are three output streams, representing red, green
and blue. Interlaced with the stream of voltage levels is a voltage
representing the reset level (or black level) of each cell. A Corre-
lated Double Sampler (CDS) subtracts these two voltages from
each other in order to eliminate the relatively large offsets which
are common with CCDs.
In the example shown, the fourth (spare) channel of the
AD8182 is used to measure a reference voltage. This voltage
would probably be measured less frequently than the R, G and
B signals. Multiplexing a reference voltage offers the advantage
that any temperature drift effects caused by the multiplexer
will equally impact the reference voltage and the to-be-
measured signals. If the fourth channel is unused, it is good
design practice to tie this input to ground.
REV. B
–9–
AD8180/AD8182
The evaluation board is provided with 49.9 Ω termination resis-
tors on all inputs. This is to allow the performance to be evalu-
ated at very high frequencies where 50 Ω termination is most
popular. To use the evaluation board in video applications, the
termination resistors should be replaced with 75 Ω resistors.
EVALUATION BOARD
Evaluation boards for the AD8180R and AD8182R are available
which have been carefully laid out and tested to demonstrate the
specified high speed performance of the devices. Figure 26 and
Figure 27 show the schematics of the AD8180 and AD8182
evaluation boards respectively. For ordering information, please
refer to the Ordering Guide.
The multiplexer outputs are loaded with 4.99 kΩ resistors. In
order to avoid large gain errors, these load resistors should be
greater than or equal to 1 kΩ. For connection to external instru-
ments, oscilloscope scope probe adapters are provided. This
allows direct connection of FET probes to the board. For verifi-
cation of data sheet specifications, use of FET probes with a
bandwidth > 1 GHz is recommended because of their low input
capacitance. The probe adapters used on the board have the
same footprint as SMA, SMB and SMC type connectors allow-
ing easy replacement if necessary.
Because the footprint of the AD8180 fits directly on to that of
the AD8182, one board layout can be used for both devices. In the
case of the AD8180, only the top half of the board is populated.
Figure 28 shows the silkscreen of the component side and Fig-
ure 30 shows the silkscreen of the solder side. Figures 29 and 31
show the layout of the component side and solder side respectively.
ENABLE
R8
49.9⍀
SELECT
R9
49.9⍀
IN0
1
2
3
4
+1
8
R1
49.9⍀
OUT
(SCOPE PROBE
7
6
5
DECODER
ADAPTER)
IN1
+1
R10
R7
+V
S
49.9⍀
4.99k⍀
–V
AD8180R
S
C1
0.1F
+
C2
0.1F
+
C4
10F
C3
10F
UNLESS OTHERWISE NOTED, CONNECTORS ARE SMA TYPE
Figure 26. AD8180R Evaluation Board
ENABLE A
R8
49.9⍀
SELECT A
IN0 A
R9
49.9⍀
OUTA
R1
(SCOPE PROBE
ADAPTER)
49.9⍀
IN1 A
1
2
3
4
5
6
7
+1
14
13
12
11
10
9
R7
4.99k⍀
R10
49.9⍀
C1
DECODER
C2
0.1F
0.1F
+1
+V
–V
AD8182R
S
S
+
+
+1
C4
10F
C3
10F
IN1 B
IN0 B
DECODER
R2
49.9⍀
R6
4.99k⍀
OUTB
+1
8
(SCOPE PROBE
ADAPTER)
R3
49.9⍀
SELECT B
R4
49.9⍀
ENABLE B
R5
49.9⍀
UNLESS OTHERWISE NOTED, CONNECTORS ARE SMA TYPE
Figure 27. AD8182R Evaluation Board
–10–
REV. B
AD8180/AD8182
ANALOG
DEVICES
AD8180/82
EVALUATION
BOARD
J10
J9
J1
SEL A
IN0A
EN A
J2
R1
U1
IN1A
J8
R9
R
A
B
8
R7
R10
C1
C2
R5
R2
C3
C4
J3
IN1B
6
R3
R
R4
J7
EN B
J6
SEL B
IN0B
J4
J5
Figure 28. Component Side Silkscreen
Figure 30. Solder Side Silkscreen
Figure 31. Board Layout (Solder Side)
Figure 29. Board Layout (Component Side)
NOTES
1. AD8180R/AD8182R Evaluation Board inputs are configured
with 50 Ω impedance striplines. This FR4 board type has the
following stripline dimensions: 60-mil width, 12-mil gap
between center conductor and outside ground plane “is-
lands,” and 62-mil board thickness.
3. Input termination resistor placement on the evaluation board
is critical to reducing crosstalk. Each termination resistor is
oriented so that ground return currents flow counterclock-
wise to a ground plane “island.” Although the direction of
this ground current flow is arbitrary, it is important that no
two input or output termination resistors share a connection
to the same ground “island.”
2. Several types of SMA connectors can be mounted on this
board: the side-mount type, which can be easily installed at
the edges of the board, and the top-mount type, which is
placed on top. When using the top-mount SMA connector, it
is recommended that the stripline on the outside 1/8" of the
board edge be removed with an X-Acto blade as this unused
stripline acts as an open stub, which could degrade the small-
signal frequency response of the mux.
REV. B
–11–
AD8180/AD8182
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
14-Lead Plastic DIP
(N-14)
(N-8)
0.430 (10.92)
0.348 (8.84)
0.795 (20.19)
0.725 (18.42)
8
5
14
8
7
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
1
4
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558) 0.100 0.070 (1.77)
(2.54)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.014 (0.356)
0.045 (1.15)
BSC
14-Lead SOIC
(R-14)
8-Lead Plastic SOIC
(SO-8)
0.3444 (8.75)
0.3367 (8.55)
0.1968 (5.00)
0.1890 (4.80)
14
8
7
8
1
5
4
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
x 45°
0.0196 (0.50)
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
8°
0°
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
REV. B
–12–
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