AD8189 [ADI]
350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers; 350 MHz的单电源供电（ 5 V ）三2 ： 1多路复用器
| 型号： | AD8189 |
| 厂家： | 
ADI |
| 描述： | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| 文件： | 总24页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
350 MHz Single-Supply (5 V)
Triple 2:1 Multiplexers
AD8188/AD8189
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully buffered inputs and outputs
Fast channel-to-channel switching: 4 ns
Single-supply operation (5 V)
High speed
350 MHz bandwidth (−3 dB) @ 200 mV p-p
300 MHz bandwidth (−3 dB) @ 2 V p-p
Slew rate: 1000 V/μs
Fast settling time: 7 ns to 0.1%
Low current: 19 mA/20 mA
Excellent video specifications: load resistor (RL) = 150 Ω
Differential gain error: 0.05%
Differential phase error: 0.05°
Low glitch
IN0A
1
2
3
4
5
6
7
8
9
24 V
CC
D
23 OE
LOGIC
GND
IN1A
22 SEL A/B
SELECT
V
21 V
REF
CC
20 OUT0
19
ENABLE
0
1
2
IN2A
V
V
CC
EE
18 OUT1
17
V
EE
IN2B
V
CC
16 OUT2
15
V
EE
IN1B 10
11
V
EE
V
14 DV
EE
CC
AD8188/AD8189
IN0B 12
13
V
CC
Figure 1.
All hostile crosstalk
−84 dB @ 5 MHz
−52 dB @ 100 MHz
High off isolation: −95 dB @ 5 MHz
Low cost
Fast, high impedance disable feature for connecting
multiple outputs
Logic-shifted outputs
APPLICATIONS
Switching RGB in LCD and plasma displays
RGB video switchers and routers
GENERAL DESCRIPTION
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
The AD8188 (G = 1) and AD8189 (G = 2) are high speed,
single-supply, triple 2-to-1 multiplexers. They offer −3 dB small
signal bandwidth of 350 MHz and −3 dB large signal bandwidth
of 300 MHz, along with a slew rate in excess of 1000 V/μs. With
−84 dB of all hostile crosstalk and −95 dB off isolation, the parts
are well suited for many high speed applications. The
differential gain and differential phase error of 0.05% and 0.05°
respectively, along with 0.1 dB flatness to 70 MHz, make the
AD8188 and AD8189 ideal for professional and component
video multiplexing. The parts offer 4 ns switching time, making
them an excellent choice for switching video signals, while
consuming less than 20 mA on a single 5 V supply (100 mW).
Both devices have a high speed disable feature that sets the
outputs into a high impedance state. This allows the building of
larger input arrays while minimizing off-channel output
loading. The devices are offered in a 24-lead TSSOP.
INPUT
OUTPUT
–0.5
–1.0
0
5
10
15
20
25
TIME (ns)
Figure 2. AD8189 Video Amplitude Pulse Response,
VOUT = 1.4 V p-p, RL = 150 Ω
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8188/AD8189
TABLE OF CONTENTS
Features .............................................................................................. 1
Full Power Bandwidth vs. −3 dB Large Signal Bandwidth ... 14
Single-Supply Considerations................................................... 14
AC-Coupled Inputs.................................................................... 16
Tolerance to Capacitive Load.................................................... 16
Secondary Supplies and Supply Bypassing ............................. 16
Split-Supply Operation.............................................................. 16
Applications..................................................................................... 17
Single-Supply Operation ........................................................... 17
AC-Coupling............................................................................... 17
DC Restore .................................................................................. 19
High Speed Design Considerations......................................... 20
Evaluation Board ............................................................................ 21
Schematics................................................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 14
High Impedance Disable ........................................................... 14
Off Isolation ................................................................................ 14
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8188/AD8189
SPECIFICATIONS
TA = 25°C. For the AD8188, VS = 5 V, RL = 1 kΩ to 2.5 V. For the AD8189, VS = 5 V, VREF = 2.5 V, RL = 150 Ω to 2.5 V; unless otherwise noted.
Table 1.
AD8188/AD8189
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth (Small Signal)
−3 dB Bandwidth (Large Signal)
0.1 dB Flatness
Slew Rate (10% to 90% Rise Time)
Settling Time to 0.1%
VOUT = 200 mV p-p
VOUT = 2 V p-p
VOUT = 200 mV p-p
VOUT = 2 V p-p, RL = 150 Ω
VIN = 1 V Step, RL = 150 Ω
350
300
70
1000
6/7.5
MHz
MHz
MHz
V/μs
ns
NOISE/DISTORTION PERFORMANCE
Differential Gain
Differential Phase
3.58 MHz, RL = 150 Ω
3.58 MHz, RL = 150 Ω
5 MHz
100 MHz
5 MHz
0.05
0.05
%
Degrees
dB
dB
dB
dB
All Hostile Crosstalk
−84/−78
−52/−48
−90/−85
−84/−95
7/9
Channel-to-Channel Crosstalk, RTI
Off Isolation
Input Voltage Noise
DC PERFORMANCE
5 MHz
f = 100 kHz to 100 MHz
nV/√Hz
Voltage Gain Error
No load
0.1
%
%
%
0.3/ 0.6
Voltage Gain Error Matching
VREF Gain Error
Channel A to Channel B
1 kΩ load
0.04
0.04
0.2/0.5
8.0
0.2/ 0.2
0.6
Input Offset Voltage
6.5/ 7.0 mV
mV
TMIN to TMAX
Input Offset Voltage Matching
Input Offset Drift
Input Bias Current
VREF Bias Current (AD8189 Only)
INPUT CHARACTERISTICS
Input Resistance
Channel A to Channel B
0.2
10/5
1.5
5.0/ 5.5 mV
μV/°C
4/4
μA
μA
1.0
@ 100 kHz
1.8/1.3
0.9/1.0
1.2
MΩ
pF
V
Input Capacitance
Input Voltage Range (About Midsupply)
IN0A, IN0B, IN1A, IN1B, IN2A, IN2B
VREF
+0.9/−1.2
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
RL = 150 Ω
3.1/2.8 3.2/3.0
2.8/2.5 3.0/2.7
85
V p-p
V p-p
mA
Ω
kΩ
pF
Short-Circuit Current
Output Resistance
Enabled @ 100 kHz
Disabled @ 100 kHz
Disabled
0.2/0.35
1000/600
1.5/2.0
Output Capacitance
POWER SUPPLY
Operating Range
3.5
5.5
V
Power Supply Rejection Ratio
+PSRR, VCC = 4.5 V to 5.5 V, VEE = 0 V
−PSRR, VEE = −0.5 V to +0.5 V, VCC = 5.0 V
All channels on
−72/−61
−76/−72
18.5/19.5 21.5/22.5 mA
dB
dB
Quiescent Current
All channels off
TMIN to TMAX, all channels on
3.5/4.5
4.5/5.5
23
mA
mA
15
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Time
50% logic to 50% output settling, INxA = +1 V,
INxB = −1 V
50% logic to 50% output settling, input = 1 V
3.6/4
4/3.8
ns
ns
Enable-to-Channel On Time
Rev. 0 | Page 3 of 24
AD8188/AD8189
AD8188/AD8189
Parameter
Conditions
Min
Typ
Max
Unit
ns
mV
mV
Disable-to-Channel Off Time
Channel Switching Transient (Glitch)
Output Enable Transient (Glitch)
DIGITAL INPUTS
50% logic to 50% output settling, input = 1 V
All channels grounded
All channels grounded
17/5
21/45
64/118
Logic 1 Voltage
SEL A/B, OE
1.6
V
Logic 0 Voltage
SEL A/B, OE
0.6
V
Logic 1 Input Current
Logic 0 Input Current
SEL A/B, OE = 2.0 V
SEL A/B, OE = 0.5 V
45
2
nA
μA
Rev. 0 | Page 4 of 24
AD8188/AD8189
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 2.
Parameter1
Rating
5.5 V
5.5 V
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
Supply Voltage
DVCC to DGND
DVCC to VEE
8.0 V
VCC to DGND
8.0 V
IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, VREF
VEE ≤ VIN ≤ VCC
SEL A/B, OE
D
GND ≤ VIN ≤ VCC
Output Short-Circuit Operation
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 10 sec)
Indefinite
While the AD8188/AD8189 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
2.5
–40°C to +85°C
–65°C to +150°C
300°C
1 Specification is for device in free air (TA = 25°C).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.0
1.5
1.0
0.5
0
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
24-Lead TSSOP1
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
2
θJA
θJC
Unit
Figure 3. Maximum Power Dissipation vs. Temperature
85
20
°C/W
1 Maximum internal power dissipation (PD) should be derated for ambient
temperature (TA) such that PD < (150°C TA)/θJA.
2 θJA is on a 4-layer board (2s 2p).
ESD CAUTION
Rev. 0 | Page 5 of 24
AD8188/AD8189
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0A
1
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
D
2
GND
OE
IN1A
3
SEL A/B
V
4
V
REF
CC
AD8188/
AD8189
IN2A
5
OUT0
V
6
V
CC
TOP VIEW
EE
(Not to Scale)
V
7
EE
OUT1
8
IN2B
V
CC
V
9
EE
OUT2
10
11
12
IN1B
V
EE
V
DV
EE
CC
IN0B
V
CC
Figure 4. AD8188/AD8189 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
IN0A
DGND
IN1A
VREF
Input, High-ZIN. Routed to OUT0 when A is selected.
Ground Reference for Digital Control Circuitry.
Input, High-ZIN. Routed to OUT1 when A is selected.
AD8188: Bypass point for internal reference. Does not affect dc level of output.
AD8189: Input to reference buffers for all channels. Can be used to offset the outputs.
5
IN2A
VCC
VEE
Input, High-ZIN. Routed to OUT2 when A is selected.
Positive Analog Supply. Nominally 5 V higher than VEE.
Negative Analog Supply.
6, 13, 17, 21, 24
7, 9, 11, 15, 19
8
IN2B
IN1B
IN0B
DVCC
OUT2
OUT1
OUT0
SEL A/B
OE
Input, High-ZIN. Routed to OUT2 when B is selected.
Input, High-ZIN. Routed to OUT1 when B is selected.
Input, High-ZIN. Routed to OUT0 when B is selected.
Positive Supply for Digital Control Circuitry. Referenced to DGND.
Output. Can connect to IN2A, IN2B, or disable.
Output. Can connect to IN1A, IN1B, or disable.
Output. Can connect to IN0A, IN0B, or disable.
Logic high selects the three A inputs. Logic low selects the three B inputs.
Output Enable. Logic high enables the three outputs.
10
12
14
16
18
20
22
23
Table 5. Truth Table
SEL A/B
OE
OUT
0
1
1
0
0
0
1
1
High-Z
High-Z
INxA
INxB
Rev. 0 | Page 6 of 24
AD8188/AD8189
TYPICAL PERFORMANCE CHARACTERISTICS
3
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0
0.5
0.4
0.3
0.2
0.1
0
976Ω
DUT
GAIN
2
50Ω
52.3Ω
1
–1
–2
–3
–4
–5
–6
GAIN
0
–1
–2
–3
–4
–5
–6
FLATNESS
FLATNESS
–0.1
–0.2
–0.3
–0.1
–0.2
0.1
1
10
100
1k
10k
0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. AD8188 Frequency Response, VOUT = 200 mV p-p, RL = 1 kΩ
Figure 8. AD8189 Frequency Response, VOUT = 200 mV p-p, RL = 150 Ω
1
0
1
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–6
150Ω
976Ω
–6
–7
–8
DUT
50Ω
52.3Ω
0.1
1
10
FREQUENCY (MHz)
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 6. AD8188 Frequency Response, VOUT = 2 V p-p, RL = 1 kΩ
Figure 9. AD8189 Frequency Response, VOUT = 2 V p-p, RL = 150 Ω
1
1
+85°C
–40°C
+25°C
+25°C
0
–1
–2
–3
–4
–5
–6
0
–1
–2
–3
–4
–5
–6
–40°C
+85°C
150Ω
976Ω
DUT
50Ω
52.3Ω
0.1
1
10
FREQUENCY (MHz)
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 7. AD8188 Large Signal Bandwidth vs. Temperature,
OUT = 2 V p-p, RL = 1 kΩ
Figure 10. AD8189 Large Signal Bandwidth vs. Temperature,
OUT = 2 V p-p, RL = 150 Ω
V
V
Rev. 0 | Page 7 of 24
AD8188/AD8189
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1
10
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. AD8188 All Hostile Crosstalk vs. Frequency
(Drive All INxA, Listen to Output with INxB Selected)
Figure 14. AD8189 All Hostile Crosstalk vs. Frequency
(Drive All INxA, Listen to Output with INxB Selected)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1
1
10
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. AD8188 Adjacent Channel Crosstalk vs. Frequency
(Drive One INxA, Listen to an Adjacent Output with INxB Selected)
Figure 15. AD8189 Adjacent Channel Crosstalk vs. Frequency
(Drive One INxA, Listen to an Adjacent Output with INxB Selected)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. AD8188 Off Isolation vs. Frequency
(Drive Inputs with OE Tied Low)
Figure 16. AD8189 Off Isolation vs. Frequency
(Drive Inputs with OE Tied Low)
Rev. 0 | Page 8 of 24
AD8188/AD8189
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
THIRD
THIRD
SECOND
SECOND
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 17. AD8188 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 Ω
Figure 20. AD8189 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 Ω
0
–10
–20
–30
0
–10
–20
–30
–PSRR
–PSRR
–40
–40
–50
–60
–50
–60
+PSRR
–70
+PSRR
–70
–80
–90
0.01
–80
0.01
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 18. AD8188 PSRR vs. Frequency, RL = 150 Ω
Figure 21. AD8189 PSRR vs. Frequency, RL = 150 Ω
20
20
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
2
2
0
0.01
0
0.01
0.1
1
10
100
1k
10k
0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. AD8188 Input Voltage Noise vs. Frequency
Figure 22. AD8189 Input Voltage Noise vs. Frequency
Rev. 0 | Page 9 of 24
AD8188/AD8189
10k
10k
1k
1k
100
10
100
10
1
1
0.1
0.1
0.1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. AD8188 Input Impedance vs. Frequency
Figure 26. AD8189 Input Impedance vs. Frequency
1k
1k
100
10
100
10
1
1
0.1
0.1
0.1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. AD8188 Enabled Output Impedance vs. Frequency
Figure 27. AD8189 Enabled Output Impedance vs. Frequency
10k
10k
1k
100
10
1k
100
10
1
1
0.1
0.1
0.1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. AD8188 Disabled Output Impedance vs. Frequency
Figure 28. AD8189 Disabled Output Impedance vs. Frequency
Rev. 0 | Page 10 of 24
AD8188/AD8189
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
3.3
2.8
2.3
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
INPUT
INPUT
OUTPUT
OUTPUT
0
0
0
5
10
15
20
25
0
0
0
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 29. AD8188 Small Signal Pulse Response,
VOUT = 200 mV p-p, RL = 1 kΩ
Figure 32. AD8189 Small Signal Pulse Response,
VOUT = 200 mV p-p, RL = 150 kΩ
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
INPUT
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
INPUT
OUTPUT
OUTPUT
–0.5
–1.0
–0.5
–1.0
5
10
15
20
25
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 30. AD8188 Video Amplitude Pulse Response,
VOUT = 700 mV p-p, RL = 1 kΩ
Figure 33. AD8189 Video Amplitude Pulse Response,
VOUT = 1.4 V p-p, RL = 150 kΩ
4.0
3.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUT
INPUT
3.0
3.0
2.5
2.5
2.0
2.0
OUTPUT
1.5
1.5
1.0
1.0
OUTPUT
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
5
10
15
20
25
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 31. AD8188 Large Signal Pulse Response,
OUT = 2 V p-p, RL = 1 kΩ
Figure 34. AD8189 Large Signal Pulse Response,
OUT = 2 V p-p, RL = 150 kΩ
V
V
Rev. 0 | Page 11 of 24
AD8188/AD8189
tSETTLED
tSETTLED
t0
t0
Figure 38. AD8189 Settling Time (0.1%), VOUT = 2 V Step, RL = 150 Ω
TIME (2ns/DIV)
TIME (2ns/DIV)
Figure 35. AD8188 Settling Time (0.1%), VOUT = 2 V Step, RL = 1 kΩ
2.3
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.0
1.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.8
1.3
SEL A/B
OUTPUT
1.0
SEL A/B
OUTPUT
0.8
0.5
0.3
0
–0.3
–0.8
–1.3
–1.8
–2.3
–2.8
–0.5
–1.0
–1.5
–2.0
–2.5
0
5
10
15
20
25
0
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 36. AD8188 Channel-to-Channel Switching Time,
VOUT = 2 V p-p, INxA = 3.5 V, INxB = 1.5 V
Figure 39. AD8189 Channel-to-Channel Switching Time,
VOUT = 2 V p-p, INxA = 3.0 V, INxB = 2.0 V
2.0
1.5
1.0
0.5
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.0
1.5
1.0
0.5
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
SEL A/B
SEL A/B
OUTPUT
OUTPUT
–0.5
–1.0
–0.5
–1.0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
Figure 37. AD8188 Channel Switching Transient (Glitch),
INxA = INxB = 0 V
Figure 40. AD8189 Channel Switching Transient (Glitch),
INxA = INxB = VREF = 0 V
Rev. 0 | Page 12 of 24
AD8188/AD8189
2.0
1.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
2.0
1.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OE
OE
1.0
1.0
0.5
0.5
0
OUTPUT
0
OUTPUT
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
TIME (ns)
Figure 41. AD8188 Enable On/Off Time, VOUT = 0 V to 1 V
Figure 43. AD8189 Enable On/Off Time, VOUT = 0 V to 1 V
1.5
1.0
0.5
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.0
1.5
1.0
0.5
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
OE
OE
OUTPUT
OUTPUT
–0.5
–1.0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
Figure 42. AD8188 Channel Enable/Disable Transient (Glitch)
Figure 44. AD8189 Channel Enable/Disable Transient (Glitch)
Rev. 0 | Page 13 of 24
AD8188/AD8189
THEORY OF OPERATION
The AD8188 (G = 1) and AD8189 (G = 2) are single-supply,
triple 2:1 multiplexers with TTL-compatible global input
switching and output-enable control. Optimized for selecting
between two RGB (red, green, blue) video sources, the devices
have high peak slew rates, maintaining their bandwidth for
large signals. Additionally, the multiplexers are compensated for
high phase margin, minimizing overshoot for good pixel
resolution. The multiplexers also have respectable video
specifications and are superior for switching NTSC or PAL
composite signals.
muxes. In this case, the proper load resistance for the off
isolation calculation is the output impedance of an enabled
AD8188, typically less than a 1/10 Ω.
FULL POWER BANDWIDTH VS. −3 dB LARGE
SIGNAL BANDWIDTH
Note that full power bandwidth for an undistorted sinusoidal
signal is often calculated using the peak slew rate from the equation
Peak Slew Rate
Full Power Bandwidth =
2π × Sinusoid Amplitude
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
B
ΔVOUT
Δt
stages are selected via one logic pin (SEL A/ ) such that all
three outputs simultaneously switch input connections. The
unused input stages are disabled with a proprietary clamp
circuit to provide excellent crosstalk isolation between on and
off inputs while protecting the disabled devices from damaging
reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
measured between the 20% and 80% output levels of a
sufficiently large output pulse. For a natural response, the peak
slew rate can be 2.7 times larger than the average slew rate.
Therefore, calculating a full power bandwidth with a specified
average slew rate gives a pessimistic result. See the Specifications
section for the large-signal bandwidth and average slew rate for
both the AD8188 and AD8189 (large signal bandwidth is defined
as the −3 dB point measured on a 2 V p-p output sine wave).
Figure 17 and Figure 20 contain plots for the second- and third-
order harmonic distortion. Specifying these three aspects of the
signal path’s large signal dynamics allows the user to predict
system behavior for either pulse or sinusoid waveforms.
The transconductance stage is a high slew rate, class AB circuit
that sources signal current into a high impedance node. Each
output stage contains a compensation network and is buffered
to the output by a complementary emitter-follower stage.
Voltage feedback sets the gain with the AD8188 configured as a
unity gain follower, and the AD8189 configured as a gain-of-two
amplifier with a feedback network. This architecture provides
drive for a reverse-terminated video load (150 Ω) with low
differential gain and phase errors, while consuming relatively
little power. Careful chip layout and biasing result in excellent
crosstalk isolation between channels.
SINGLE-SUPPLY CONSIDERATIONS
The AD8188 and AD8189 offer superior large signal dynamics.
The trade-off is that the input and output compliance is limited
to ~1.3 V from either rail when driving a 150 Ω load. The
following sections address some challenges of designing video
systems within a single 5 V supply.
HIGH IMPEDANCE DISABLE
The output-enable logic pin (OE) of the AD8188 and AD8189
controls whether the three outputs are enabled or disabled to a
high impedance state. The high impedance disable allows larger
matrices to be built by busing the outputs together.
The AD8188
The AD8188 is internally wired as a unity-gain follower. Its
inputs and outputs can both swing to within ~1.3 V of either
rail. This affords the user 2.4 V of dynamic range at input and
output that should be enough for most video signals, whether
the inputs are ac- or dc-coupled. In both cases, the choice of output
termination voltage determines the quiescent load current.
In the case of the AD8189 (G = 2), the reference buffers also
disable to a state of high output impedance. This feature
prevents the feedback network of a disabled channel from
loading the output, which is valuable when busing together the
outputs of several muxes.
For improved supply rejection, the VREF pin should be tied to an
ac ground (the more quiet the supply, the better). Internally, the
OFF ISOLATION
VREF pin connects to one terminal of an on-chip capacitor. The
capacitor’s other terminal connects to an internal node. The
consequence of building this bypass capacitor on-chip is
twofold. First, the VREF pin on the AD8188 draws no input bias
current. (Contrast this to the case of the AD8189, where the
The off isolation performance of the signal path is dependent
upon the value of the load resistor, RL. For calculating off
isolation, the signal path can be modeled as a simple high-pass
network with an effective capacitance of 3 fF. Off isolation
improves as the load resistance is decreased. In the case of the
AD8188, off isolation is specified with a 1 kΩ load. However, a
practical application would likely gang the outputs of multiple
VREF pin typically draws 2 μA of input bias current.) Second, on
the AD8188, the VREF pin can be tied to any voltage within the
supply range.
Rev. 0 | Page 14 of 24
AD8188/AD8189
5V
AD8188
MUX SYSTEM
1.3V
1.3V
5V
V
V
= 3.7V
O_MAX
IN0A
IN0B
IN1A
IN1B
IN2A
IN2B
OUT0
OUT1
OUT2
A0
V
OUT
OUT0
= 1.3V
O_MIN
GND
5V
5V
“C_BYPASS”
V
V
REF
REF
1.6V
1.3V
INTERNAL CAP
BIAS REFERENCE
V
= 3.4V
= 1.3V
O_MAX
V
REF
V
O_MIN
DIRECT CONNECTION TO ANY “QUIET” AC GROUND
(FOR EXAMPLE, GND, V , AND V ).
GND
CC
EE
Figure 45. VREF Pin Connection for AD8188 (Differs from AD8189)
Figure 47. Output Compliance of Main Amplifier Channel and Ground Buffer
The AD8189
•
The signal at the VREF pin appears at each output.
Therefore, VREF should be tied to a well bypassed, low
impedance source. Using superposition, it is shown that
The AD8189 uses on-chip feedback resistors to realize the gain-
of-two function. To provide low crosstalk and a high output
impedance when disabled, each set of 500 Ω feedback resistors
is terminated by a dedicated reference buffer. A reference buffer
is a high speed op amp configured as a unity-gain follower. The
three reference buffers, one for each channel, share a single,
high impedance input, the VREF pin (see Figure 46). VREF input
bias current is typically less than 2 μA.
VOUT = 2 × VIN − VREF
•
To maximize the output dynamic range, the reference
voltage should be chosen with care. For example, consider
amplifying a 700 mV video signal with a sync pulse
300 mV below black level. If the user decides to set VREF at
black level to preferentially run video signals on the faster
NPN transistor path, the AD8189 allows a reference
voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8189 is
used, the sync pulse is amplified to 600 mV. Therefore, the
lower limit on VREF becomes 1.3 V + 600 mV = 1.9 V. For
routing RGB video, an advantageous configuration is to
employ +3 V and −2 V supplies, in which case VREF can be
tied to ground.
5V
A0
1×
OUT0
5V
B0
500Ω
VFO
5V
GBUF 0
500Ω
V
REF
If system considerations prevent running the multiplexer on
split supplies, a false ground reference should be employed. A
low impedance reference can be synthesized with a second
operational amplifier. Alternately, a well bypassed resistor
divider can be used. Refer to the Applications section for
further explanation and more examples.
VF-1
5V
GBUF 1
OUT1
OUT2
500Ω 500Ω
VF-2
5V
GBUF 2
500Ω 500Ω
5V
Figure 46. Conceptual Diagram of a Single Multiplexer Channel, G = 2
10kΩ
This configuration has a few implications for single-supply
operation:
100kΩ
0.022µF
V
REF
100Ω
•
On the AD8189, VREF cannot be tied to the most negative
analog supply, VEE. The limits on reference voltage are (see
Figure 47):
OP21
1µF
1µF
FROM 1992 ADI AMPLIFIER
APPLICATIONS GUIDE
VEE + 1.3 V < VREF × VCC − 1.6 V
GND
1.3 V < VREF, 3.4 V on 0 V/5 V supplies
Figure 48. Synthesis of a False Ground Reference
Rev. 0 | Page 15 of 24
AD8188/AD8189
5V
SECONDARY SUPPLIES AND SUPPLY BYPASSING
The high current output transistors are given their own supply
pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise
on-chip and to improve output isolation. Because these
secondary, high current supply pins are not connected on-chip
to the primary analog supplies, VCC/VEE (Pin 6, Pin 7, Pin 9,
Pin 11, Pin 13, and Pin 24), some care should be taken to ensure
that the supply bypass capacitors are connected to the correct
pins. At a minimum, the primary supplies should be bypassed.
Pin 6 and Pin 7 can be a convenient place to accomplish this.
Stacked power and ground planes are a convenient way to
bypass the high current supply pins (see Figure 51).
10kΩ
V
REF
1µF
10kΩ
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
Figure 49. Alternate Method for Synthesis of a False Ground Reference
AC-COUPLED INPUTS
Using ac-coupled inputs presents an interesting challenge for
video systems operating from a single 5 V supply. In NTSC and
PAL video systems, 700 mV is the approximate difference
between the maximum signal voltage and black level. It is
assumed that sync has been stripped. However, given the two
pathological cases shown in Figure 50, a dynamic range of twice
the maximum signal swing is required if the inputs are to be
ac-coupled. A possible solution is to use a dc restore circuit
before the mux.
1
24
23
22
21
20
19
18
17
16
15
14
13
IN0A
V
CC
D
2
GND
OE
3
IN1A
SEL A/B
V
4
V
CC
REF
5
IN2A
OUT0
V
6
MUX1
MUX2
MUX3
V
CC
EE
WHITE LINE WITH BLACK PIXEL
0.1µF
1µF
V
REF
V
7
EE
OUT1
+700mV
V
AVG
V
AVG
8
V
IN2B
–700mV
CC
V
REF
BLACK LINE WITH WHITE PIXEL
+5V
V
9
EE
OUT2
10
11
12
V
IN1B
EE
V
V
V
= V
+ V
INPUT
REF
SIGNAL
~ V
REF
AVG
V
SIGNAL
IS A DC VOLTAGE
REF
V
DV
CC
EE
SET BY THE RESISTORS
GND
IN0B
V
CC
Figure 50. Pathological Case for Input Dynamic Range
Figure 51. Detail of Primary and Secondary Supplies
TOLERANCE TO CAPACITIVE LOAD
SPLIT-SUPPLY OPERATION
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance (REFF) of
Operating from split supplies (for example, [+3 V/−2 V] or
2.5 V) simplifies the selection of the VREF voltage and load
resistor termination voltage. In this case, it is convenient to tie
REFF = (RL || rO)
where RL is the discrete resistive load, and rO is the open loop
output impedance, approximately 15 Ω for these muxes.
VREF to ground. The logic inputs are internally level-shifted to
allow the digital supplies and logic inputs to operate from 0 V
and 5 V when powering the analog circuits from split supplies.
The maximum voltage difference between DVCC and VEE must
not exceed 8 V (see Figure 52).
The load pole (fLOAD) at
1
fLOAD
=
2π REFF CL
DIGITAL SUPPLIES
ANALOG SUPPLIES
(+2.5V)
V
CC
(+5V)
DV
CC
can seriously degrade phase margin and, therefore, stability. The
old workaround is to place a small series resistor directly at the
output to isolate the load pole. While effective, this ruse also
affects the dc and termination characteristics of a 75 Ω system.
The AD8188 and AD8189 are built with a variable compensation
scheme that senses the output reactance and trades bandwidth
for phase margin, ensuring faster settling and lower overshoot
at higher capacitive loads.
8V MAX
(0V)
D
GND
V
(–2.5V)
EE
Figure 52. Split-Supply Operation
Rev. 0 | Page 16 of 24
AD8188/AD8189
APPLICATIONS
If the input is biased at 2.5 V dc, the input signal can potentially
go 700 mV both above and below this point. The resulting 1.8 V
and 2.2 V are within the input signal range for single 5 V
operation. Because the part is unity-gain, the outputs follow the
inputs, and there is adequate range at the output as well.
SINGLE-SUPPLY OPERATION
The AD8188/AD8189 are targeted mainly for use in single-
supply 5 V systems. For operating on these supplies, both VEE
and DGND should be tied to ground, and the control logic pins
should be referenced to ground. Normally, the DVCC supply
needs to be set to the same positive supply as the driving logic.
When the AD8188 is operated from a single supply of 5 V and
ground, ac-coupling is often useful. This is particularly true when
the input signals are a typical RGB source from a PC. These
signals go all the way to ground at the most negative, outside of
the AD8188 input range, when its negative supply is ground.
The closest that the input can go to ground is typically 1.3 V.
For dc-coupled, single-supply operation, it is necessary to set an
appropriate input dc level that is within the specified range of the
amplifier. For the unity-gain AD8188, the output dc level is the
same as the input, while for the gain-of-two AD8189, the VREF
input can be biased to obtain an appropriate output dc level.
There are several basic methods for ac-coupling the inputs.
They all consist of a series capacitor followed by a circuit for
setting the dc operating point of the input and then the AD8188
input. If a termination is provided, it should be located before
the series coupling capacitor.
Figure 53 shows a circuit that provides a gain-of-two and is
dc-coupled. The video input signals must have a dc bias from
their source of approximately 1.5 V. This same voltage is applied
to VREF of the AD8189. The result is that when the video signal
is at 1.5 V, the output is also at the same voltage. This is close to
the lower dynamic range of both the input and the output.
The different circuits vary in the means used to establish the dc
operating point after the coupling capacitor. A straightforward
way to do this is to use a voltage divider for each input.
However, because there are six inputs altogether, 12 resistors are
required to set all of the dc operating points. This means many
components in a small space, but the circuit has the advantage
of having the lowest crosstalk among any of the inputs. This
circuit is shown in Figure 54.
When the input goes most positive, which is 700 mV above the
black level for a standard video signal, it reaches a value of 2.2 V,
and there is enough headroom for the signal. On the output
side, the magnitude of the signal changes by 1.4 V, making the
maximum output voltage 2.2 V + 1.4 V = 3.6 V. This is just
within the dynamic range of the output of the part.
AC-COUPLING
AD8188
A circuit that uses the minimum number of resistors can be
designed. First, create a node, VMID, which serves as the bias
voltage for all of the inputs. Then, a single resistor is used to
connect from each input (inside the ac-coupling capacitor) and
When a video signal is ac-coupled, the amount of dynamic
range required to handle the signal can potentially be double
the amount required for dc-coupled operation. For the unity-
gain AD8188, there is still enough dynamic range to handle an
ac-coupled, standard video signal with 700 mV p-p amplitude.
VMID (see Figure 55).
3V TO 5V 5V
DV
V
CC
CC
IN0A
IN1A
IN2A
REDA
GRNA
AD8189
OUT0
RED
GRN
×2
×2
×2
0.7V MAX
2.2V
BLUA
5V
3.0V
1.5V
1.4V
MAX
3.48kΩ
1.5kΩ
OUT1
1.5V
1.5V
V
REF
TYPICAL OUTPUT LEVELS
(ALL 3 OUTPUTS)
BLACK
LEVEL
BLACK
LEVEL
TYPICAL INPUT LEVELS
(ALL 6 OUTPUTS)
IN0B
IN1B
IN2B
OUT2
OE
REDB
BLU
GRNB
BLUB
D
V
EE
SEL A/B
GND
Figure 53. AD8189 DC-Coupled (Bypassing and Logic Not Shown)
Rev. 0 | Page 17 of 24
AD8188/AD8189
5V
5V
5V
0.1µF
0.1µF
10µF
4.99kΩ
IN0A
RGB
75Ω
75Ω
4.99kΩ
SOURCE A
DV
V
CC
CC
R
AD8188
0.1µF
4.99kΩ
5V
5V
G
B
OUT0
+
–
4.99kΩ
4.99kΩ
IN0B
0.1µF
75Ω
4.99kΩ
IN1A
IN1B
OUT1
+
–
TO A/D,
ETC.
5V
75Ω
75Ω
75Ω
4.99kΩ
0.1µF
5V
4.99kΩ
IN2A
IN2B
0.1µF
4.99kΩ
OUT2
+
–
RGB
SOURCE B
4.99kΩ
R
G
B
SEL A/B
HI = A
LO = B
0.1µF
4.99kΩ
5V
4.99kΩ
V
REF
0.1µF
D
V
OE
GND
EE
HI = ENABLE
LO = DISABLE
Figure 54. AD8188 AC-Coupling Using Separate Voltage Dividers
5V
5V
0.1µF
0.1µF
10µF
V
MID
4.99kΩ
RGB
75Ω
75Ω
SOURCE A
DV
V
CC
CC
IN0A
IN0B
R
G
B
AD8188
0.1µF
0.1µF
V
V
MID
4.99kΩ
OUT0
+
–
MID
4.99kΩ
75Ω
75Ω
IN1A
IN1B
OUT1
+
–
TO A/D,
ETC.
V
V
MID
4.99kΩ
0.1µF
0.1µF
IN2A
IN2B
MID
4.99kΩ
OUT2
+
–
75Ω
75Ω
RGB
SOURCE B
R
G
B
SEL A/B
HI = A
LO = B
0.1µF
0.1µF
V
MID
4.99kΩ
V
REF
D
V
OE
GND
EE
5V
V
MID
100Ω
HI = ENABLE
LO = DISABLE
100Ω
0.1µF
10µF
Figure 55. AD8188 AC-Coupling Using a Single VMID Reference
The circuit in Figure 55 can increase the crosstalk between
inputs, because each input signal creates a small signal on VMID
due to its nonzero impedance. There are several means to
minimize this. First, make the impedance of the VMID divider
small. Small resistor values lower the dc resistance, and good
bypassing to ground minimizes the ac impedance. It is also
possible to use a voltage regulator or another system supply
voltage if it is the correct value. It should be close to the mid-
supply voltage of the AD8188.
The second technique for minimizing crosstalk is to use large
resistor values to connect from the inputs to VMID. The major factor
limiting the value of these resistors is offset caused by the input
bias current (IB) that must flow through these resistors to the
AD8188 inputs. The typical IB for an AD8188 input is 1.5 μA,
which causes an offset voltage of 1.5 mV per 1 kΩ of resistance.
Rev. 0 | Page 18 of 24
AD8188/AD8189
These two techniques can also be combined. Typically, crosstalk
between the RGB signals from the same source is less objectionable
than crosstalk between two different sources. The former can
cause a color or luminance shift, but spatially, everything is
coherent. However, the crosstalk signals from two uncorrelated
sources can create ghost images that are far more objectionable.
input capacitors of the AD8189. The input points of the
AD8189 are switched to a 1.5 V reference by the ADG786,
which works in the following manner:
B
•
•
The SEL A/ signal selects the A or B input to the AD8189. It
also selects the switch positions in the ADG786 such that the
EN
same selected inputs are connected to VREF when
During the horizontal interval, all of the RGB input signals are
HSYNC
is low.
A technique for minimizing crosstalk between two different
sources is to create two separate VMID circuits. Then, the inputs
from each source can be connected to their own VMID node,
minimizing crosstalk between sources.
at a flat black level. A logic signal that is low during
is
of the ADG786. This closes the switches and
EN
applied to the
clamps the black level to 1.5 V. At all other times, the switches
are off and the node at the inputs to the AD8189 floats.
AD8189
When using the gain-of-two AD8189 in a simple ac-coupled
application, there is a dynamic range limitation at the output
caused by its higher gain. At the output, the gain-of-two
produces a signal swing of 1.4 V, but the ac-coupling doubles
this required amount to 2.8 V. The AD8189 outputs can only
swing from 1.4 V to 3.6 V on a 5 V supply, so there are only
2.2 V of dynamic signal swing available at the output.
There are two considerations for sizing the input coupling
capacitors. One is the time constant during the H-pulse
clamping. The other is the droop associated with the capacitor
discharge due to the input bias current of the AD8189. For the
former, it is better to have a small capacitor, but for the latter, a
larger capacitor is better.
The on resistance of the ADG786 and the coupling capacitor
form the time constant of the input clamp. The ADG786 on
resistance is 5 Ω maximum. With a 0.1 μF capacitor, a time
constant of 0.5 μs is created. Thus, a sync pulse of greater than
2.5 μs causes less than 1% error. This is not critical because the
black level from successive lines is very close and the voltage
changes little from line to line.
A standard means for reducing the dynamic range requirements
of an ac-coupled video signal is to use a dc restore. This circuit
works to limit the dynamic range requirements by clamping the
black level of the video signal to a fixed level at the input to the
amplifier. This prevents the video content of the signal from
varying the black level, as happens in a simple ac-coupled circuit.
DC RESTORE
A rough approximation of the horizontal line time for a graphics
system is 30 μs. This varies depending on the resolution and the
vertical rate. The coupling capacitor needs to hold the voltage
relatively constant during this time, while the input bias current
of the AD8189 discharges it.
After ac-coupling a video signal, it is necessary to use a dc
restore to establish where the black level is. Usually, this appears
at the end of a video signal chain. This dc restore circuit needs
to have the required accuracy for the system. It compensates for
all the offsets of the preceding stages. Therefore, if a dc restore
circuit is to be used only for dynamic range limiting, it does not
require great dc accuracy.
The change in voltage is IB times the line time divided by the
capacitance. With an IB of 2.5 μA, a line time of 30 μs, and a
0.1 μF coupling capacitor, the amount of droop is 0.75 mV. This
is roughly 0.1% of the full video amplitude and is not observable
A dc restore circuit using the AD8189 is shown in Figure 56.
Two separate sources of RGB video are ac-coupled to the 0.1 μF
in the video display.
3V TO 5V 5V
5V
V
DD
DV
V
CC
CC
0.1µF
0.1µF
0.1µF
IN0A
IN1A
IN2A
REDA
GRNA
BLUA
ADG786
S1A
AD8189
OUT0
D1
D2
RED
GRN
BLU
×2
×2
×2
S1B
5V
V
REF
S2A
S2B
3.48kΩ
1.5kΩ
OUT1
OUT2
1.5V
+
10µF
V
V
REF
REF
0.1µF
0.1µF
0.1µF
0.1µF
IN0B
IN1B
IN2B
S3A
S3B
REDB
GRNB
BLUB
D3
GND
V
SS
D
V
OE
SEL A/B
GND
EE
LOGIC
EN A0 A1 A2
HSYNC
2.4V MIN
0.8V MIN
SEL A/B
Figure 56. AD8189 AC-Coupled with DC Restore
Rev. 0 | Page 19 of 24
AD8188/AD8189
HIGH SPEED DESIGN CONSIDERATIONS
The AD8188/AD8189 are extremely high speed switching
amplifiers for routing the highest resolution graphic signals.
Extra care is required in the circuit design and layout to ensure
that the full resolution of the video is realized.
very close to the pins of the part with minimum extra circuit
length in the path. It is also helpful to have a large VCC plane on
a circuit board layer that is closely spaced to the ground plane.
This creates a low inductance interplane capacitance, which is
very helpful in supplying the fast transient currents that the part
demands during high resolution signal transitions.
First, the board should have at least one layer of a solid ground
plane. Long signal paths should be referenced to a ground plane
as controlled-impedance traces. All bypass capacitors should be
Rev. 0 | Page 20 of 24
AD8188/AD8189
EVALUATION BOARD
An evaluation board has been designed and is offered for
running the AD8188/AD8189 on a single supply. The inputs
and outputs are ac-coupled and terminated with 75 Ω resistors.
For the AD8189, a potentiometer is provided to allow setting
The logic control signals can be statically set by adding or
removing a jumper. If a fast signal is required to drive the logic
pins, an SMA connector can be used to deliver the signal, and a
place for a termination resistor is provided.
VREF at any value between VCC and ground.
Figure 57. Component Side Board Layout
Figure 58. Circuit Side Board Layout
Rev. 0 | Page 21 of 24
AD8188/AD8189
Figure 59. Component Side Silkscreen
Figure 60. Circuit Side Silkscreen
Rev. 0 | Page 22 of 24
AD8188/AD8189
SCHEMATICS
0 6 9 1 - 6 0 2 3
Figure 61. Single-Supply Evaluation Board
Rev. 0 | Page 23 of 24
AD8188/AD8189
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 62. 24-Lead Thin Shrink Small Outline Package [TSSOP]
[RU-24]
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RU-24
RU-24
AD8188ARUZ1
AD8188ARUZ-RL1
AD8188ARUZ-R71
AD8189ARUZ1
AD8189ARUZ-RL1
AD8189ARUZ-R71
AD8188Z-EVALZ1
AD8189Z-EVALZ1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel
24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel
24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel
Evaluation Board
RU-24
RU-24
RU-24
RU-24
Evaluation Board
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06239-0-10/06(0)
Rev. 0 | Page 24 of 24
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