AD8195ACPZ_技术文档

HDMI/DVI Buffer with Equalization

Data Sheet

AD8195

FEATURES

FUNCTIONAL BLOCK DIAGRAM

1 input, 1 output HDMI/DVI link

Enables HDMI 1.3a-compliant front panel input

4 TMDS channels per link

PARALLEL

AVCC

Supports 250 Mbps to 2.25 Gbps data rates

Supports 25 MHz to 225 MHz pixel clocks

Equalized inputs for operation with long HDMI cables

(20 m at 2.25 Gbps)

Preemphasized outputs

Fully buffered unidirectional inputs/outputs

50 Ω on-chip terminations

AD8195

AMUXVCC

VTTI

AVEE

CONTROL

LOGIC

VTTO

+

–

4

+

–

IP[3:0]

IN[3:0]

OP[3:0]

ON[3:0]

BUFFER

EQ

PE

HIGH SPEED

BUFFERED

VREF_IN

VREF_OUT

Low added jitter

SCL_IN

SDA_IN

SCL_OUT

SDA_OUT

Transmitter disable feature

2

Reduces power dissipation

Disables input termination

CEC_IN

CEC_OUT

3 auxiliary buffered channels per link

Bidirectional buffered DDC lines (SDA and SCL)

Bidirectional buffered CEC line with integrated pull-up

resistors (27 kΩ)

LOW SPEED BUFFERED

BIDIRECTIONAL

Independently powered from 5 V of HDMI input

connector

Figure 1.

Logic level translation (3.3 V, 5 V)

Input/output capacitance isolation

Standards compatible: HDMI, DVI, HDCP, DDC, CEC

40-lead LFCSP_VQ package (6 mm × 6 mm)

TYPICAL APPLICATION

HDTV SET

MEDIA CENTER

SET-TOP BOX

DVD PLAYER

GAME

CONSOLE

HDMI

RECEIVER

APPLICATIONS

Front panel buffer for advanced television (HDTV) sets

4:1 HDMI

SWITCH

AD8195

GENERAL DESCRIPTION

BACK PANEL

CONNECTORS

FRONT PANEL

CONNECTOR

The AD8195 is an HDMI/DVI buffer featuring equalized TMDS

inputs and preemphasized TMDS outputs, ideal for systems with

long cable runs. The AD8195 includes bidirectional buffering

for the DDC bus and bidirectional buffering with integrated

pull-up resistors for the CEC bus. The DDC and CEC buffers

are powered independently of the TMDS buffers so that DDC/

CEC functionality can be maintained when the system is powered

off. The AD8195 meets all the requirements for sink tests as

defined in Section 8 of the HDMI Compliance Test 1.3c.

Figure 2. Typical AD8195 Application for HDTV Sets

PRODUCT HIGHLIGHTS

1. Enables a fully HDMI 1.3a-compliant front panel input.

2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats and greater than UXGA

(1600 × 1200) DVI resolutions.

3. Input cable equalizer enables use of long cables; more than

20 meters (24 AWG) at data rates of up to 2.25 Gbps.

4. Auxiliary buffer isolates and buffers the DDC bus and CEC

line for a single chip, fully HDMI 1.3a-compliant solution.

5. Auxiliary buffer is powered independently from the TMDS

link so that DDC/CEC functionality can be maintained

when the system is powered off.

The AD8195 is specified to operate over the −40°C to +85°C

temperature range.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD8195

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 13

Input Channels ........................................................................... 13

Output Channels ........................................................................ 13

Preemphasis ................................................................................ 14

Auxiliary Lines............................................................................ 14

Applications Information.............................................................. 15

Front Panel Buffer for Advanced TV....................................... 15

Cable Lengths and Equalization............................................... 16

TMDS Output Rise/Fall Times................................................. 16

PCB Layout Guidelines.............................................................. 16

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Typical Application........................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

TMDS Performance Specifications............................................ 3

Auxiliary Channel Performance Specifications........................ 4

Power Supply and Control Logic Specifications ...................... 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation ..................................................... 5

ESD Caution.................................................................................. 5

REVISION HISTORY

8/12—Rev. A to Rev. B

8/11—Rev. 0 to Rev. A

Changed Data Rate = 3 Gbps to

Changed Data Rate = 2.25 Gbps to

Data Rate = 2.25 Gbps .................................................. Throughout

Changes to Features Section, General Description Section, and

Product Highlights Section ............................................................. 1

Changes to Table 1............................................................................ 3

Changes to specifications statements in Typical Performance

Characteristics Section..................................................................... 8

Changes to Figure 19...................................................................... 11

Changes to Theory of Operation Section and to

Input Channels Section.................................................................. 13

Changes to Output Channels Section.......................................... 13

Changes to Preemphasis Section.................................................. 14

Changes to Cable Lengths and Equalization Section and

PCB Layout Guidelines Section.................................................... 16

Added Unused DDC/CEC Buffers Section................................. 18

Data Rate = 2.25 Gbps .................................................. Throughout

Changes to Features Section, General Description Section, and

Product Highlights Section..............................................................1

Changes to Table 1.............................................................................3

Changes to Table 3.............................................................................4

Changes to Figure 5 Caption and Figure 7 Caption .....................8

Added Figure 6 and Figure 8; Renumbered Sequentially ............8

Moved Figure 9 and Figure 11 .........................................................9

Changes to Figure 9 Caption and Figure 11 Caption ...................9

Added Figure 10 and Figure 12 .......................................................9

Moved Figure 14 and Figure 16.................................................... 10

Changes to Figure 14 Caption and Figure 16 Caption .............. 10

Added Figure 15 and Figure 17 .................................................... 10

Changes to Figure 18, Figure 19, and Figure 21......................... 11

Changes to Input Channels Section............................................. 13

Changes to Output Channels Section.......................................... 13

Changes to Preemphasis Section.................................................. 14

Changes to Cable Lengths and Equalization Section, TMDS

Output Rise/Fall Times Section, and PCB Layout Guidelines

Section.............................................................................................. 16

Changes to Auxiliary Control Signals Section ........................... 18

8/08—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet

AD8195

SPECIFICATIONS

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AMUXVCC = 5 V, VREF_IN = 5 V, VREF_OUT = 5 V, AVEE = 0 V, differential input

swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

TMDS PERFORMANCE SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ Max

Unit

TMDS DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel

Bit Error Rate (BER)

Added Data Jitter

Added Clock Jitter

NRZ

2.25

Gbps

PRBS 2²³− 1

10⁻⁹

DR ≤ 2.25 Gbps, PRBS 2⁷− 1

31

1

ps p-p

ps rms

ps

Differential Intrapair Skew

Differential Interpair Skew

TMDS EQUALIZATION PERFORMANCE

Receiver¹

At output

30

ps

Boost frequency = 1.5 GHz

12

6

dB

Transmitter²

TMDS INPUT CHARACTERISTICS

Input Voltage Swing

Input Common-Mode Voltage (V_ICM

TMDS OUTPUT CHARACTERISTICS

High Voltage Level

Differential

150

AVCC − 800

1200

AVCC

mV

)

Single-ended, high speed channel

DR = 2.25 Gbps

AVCC − 200

AVCC − 600

50

AVCC + 10

AVCC − 400 mV

150

mV

Low Voltage Level

Rise/Fall Time (20% to 80%)³

90

ps

TMDS TERMINATION

Input Termination Resistance

Output Termination Resistance

Single-ended

50

Ω

¹Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard.

²Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard.

³Output rise/fall time measurement excludes external components, such as HDMI connector or external ESD protection diodes. See the Applications Information

section for more information.

Rev. B | Page 3 of 20

AD8195

Data Sheet

AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DDC CHANNELS

Input Capacitance, C_AUX

Input Low Voltage, V_IL

Input High Voltage, V_IH

Output Low Voltage, V_OL

Output High Voltage, V_OH

Rise Time

DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz

10

15

0.5

VREF¹

0.4

pF

V

ns

μA

0.7 × VREF¹

I_OL= 5 mA

0.25

VREF¹

140

10% to 90%, no load

90% to 10%, C_LOAD= 400 pF

Input voltage = 5.0 V

Fall Time

Leakage

100

200

10

CEC CHANNEL

Input Capacitance, C_AUX

DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz,

2 kΩ pull-up resistor from CEC_OUT to 3.3 V

5

25

pF

Input Low Voltage, V_IL

Input High Voltage, V_IH

Output Low Voltage, V_OL

Output High Voltage, V_OH

Rise Time

0.8

V

2.0

2.5

0.25

3.3

50

0.6

10% to 90%, C_LOAD= 1500 pF, R_PULL-UP= 27 kΩ;

or C_LOAD= 7200 pF, R_PULL-UP= 3 kΩ

90% to 10%, C_LOAD= 1500pF, R_PULL-UP= 27 kΩ;

or C_LOAD= 7200 pF, R_PULL-UP= 3 kΩ

100

10

µs

Fall Time

5

µs

Pull-Up Resistance

Leakage

27

kΩ

µA

Off leakage test conditions²

1.8

¹VREF is the voltage at the reference pin (VREF_IN for SCL_IN and SDA_IN, or VREF_OUT for SCL_OUT and SDA_OUT); nominally 5.0 V.

²Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3b Section 8, Test ID 8-14: “Remove power (mains) from DUT. Connect CEC line

to 3.63 V via 27 kΩ 5% resistor with ammeter in series. Measure CEC line leakage.”

POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

AVCC

AMUXVCC

VREF_IN, VREF_OUT

QUIESCENT CURRENT

AVCC

Operating range (3.3 V 10%)

Operating range (5 V 10%)

3

4.5

3

3.3

5

3.6

5.5

V

Output disabled

20

40

mA

μA

Output enabled, no preemphasis (0 dB)

Output enabled, maximum preemphasis (6 dB)

Input termination on

Output termination on, no preemphasis

Output termination on, maximum preemphasis

32

66

40

50

80

54

50

100

200

20

VTTI

VTTO

80

VREF_IN

VREF_OUT

AMUXVCC

120

10

μA

mA

POWER DISSIPATION

Output disabled

116

180

736

254

663

1047

mW

Output enabled, no preemphasis (0 dB)

Output enabled, maximum preemphasis (6 dB)

TX_EN, PE_EN

PARALLEL CONTROL INTERFACE

Input High Voltage, V_IH

Input Low Voltage, V_IL

2.4

V

0.8

Rev. B | Page 4 of 20

Data Sheet

AD8195

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 4.

Parameter

Rating

3.7 V

AVCC + 0.6 V

5.5 V

Table 5.

Package

AVCC to AVEE

VTTI

VTTO

θ_JA

θ_JC

Unit

40-Lead LFCSP_VQ

36

5.0

°C/W

AMUXVCC

VREF_IN

VREF_OUT

5.5 V

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8195

is limited by the associated rise in junction temperature. The

maximum safe junction temperature for plastic encapsulated

devices is determined by the glass transition temperature of the

plastic, approximately 150°C. Temporarily exceeding this limit

may cause a shift in parametric performance due to a change in

the stresses exerted on the die by the package. Exceeding a junction

temperature of 175°C for an extended period can result in device

failure. To ensure proper operation, it is necessary to observe

the maximum power derating as determined by the thermal

resistance coefficients.

Internal Power Dissipation

High Speed Input Voltage

1.81 W

AVCC − 1.4 V < V_IN<

AVCC + 0.6 V

High Speed Differential Input Voltage

Parallel Control Input Voltage

2.0 V

AVEE − 0.3 V < V_IN<

AVCC + 0.6 V

−65°C to +125°C

−40°C to +85°C

150°C

Storage Temperature Range

Operating Temperature Range

Junction Temperature

ESD, Human Body Model

Input Pins Only

5 kV

3 kV

All Other Pins

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. B | Page 5 of 20

AD8195

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN0

IP0

1

2

3

4

5

6

7

8

9

30 AVCC

29 PE_EN

28 TX_EN

27 AVEE

26 AVCC

25 AVCC

24 AVEE

23 AVCC

22 AVCC

21 COMP

PIN 1

INDICATOR

IN1

IP1

VTTI

IN2

IP2

AD8195

TOP VIEW

(Not to Scale)

IN3

IP3

AVCC 10

NOTES

1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF

THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE

ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER

TO MEET THERMAL SPECIFICATIONS.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

HS I

Description

1

2

3

4

5

6

7

8

9

IN0

High Speed Input Complement.

High Speed Input.

IP0

HS I

IN1

HS I

High Speed Input Complement.

High Speed Input.

IP1

HS I

VTTI

IN2

Power

HS I

Input Termination Supply. Nominally connected to AVCC.

High Speed Input Complement.

High Speed Input.

IP2

HS I

IN3

HS I

High Speed Input Complement.

High Speed Input.

IP3

HS I

10, 16, 22, 23, 25, 26, 30 AVCC

Power

HS O

Power

HS O

Control

Power

Control

Positive Analog Supply. 3.3 V nominal.

High Speed Output Complement.

High Speed Output.

11

12

13

14

15

17

18

19

20

21

ON0

OP0

VTTO

ON1

OP1

Output Termination Supply. Nominally connected to AVCC.

High Speed Output Complement.

High Speed Output.

ON2

OP2

High Speed Output Complement.

High Speed Output.

ON3

OP3

High Speed Output Complement.

High Speed Output.

COMP

Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.

Negative Analog Supply. 0 V nominal.

24, 27, 37, Exposed Pad AVEE

28

29

TX_EN

PE_EN

High Speed Output Enable Parallel Interface.

High Speed Preemphasis Enable Parallel Interface.

Rev. B | Page 6 of 20

Data Sheet

AD8195

Pin No.

31

Mnemonic

CEC_OUT

AMUXVCC

VREF_OUT

SDA_OUT

SCL_OUT

VREF_IN

CEC_IN

Type¹

Description

LS I/O

CEC Output Side.

32

Power

Reference

LS I/O

Positive Auxiliary Buffer Supply. 5 V nominal.

DDC Output Side Pull-Up Reference Voltage.

DDC Output Side Data Line Input/Output.

DDC Output Side Clock Line Input/Output.

DDC Input Side Pull-Up Reference Voltage.

CEC Input Side.

33

34

35

LS I/O

36

Reference

LS I/O

38

39

SDA_IN

LS I/O

DDC Input Side Data Line.

40

SCL_IN

LS I/O

DDC Input Side Clock Line

¹HS = high speed, LS = low speed, I = input, and O = output.

Rev. B | Page 7 of 20

AD8195

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷− 1,

TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

AD8195

DIGITAL

PATTERN

GENERATOR

SERIAL DATA

ANALYZER

EVALUATION

BOARD

SMA COAX CABLE

REFERENCE EYE DIAGRAM AT TP1

TP1

TP2

TP3

Figure 4. Test Circuit Diagram for Rx Eye Diagrams

0.125UI/DIV AT 2.25Gbps

Figure 5. Rx Eye Diagram at TP2

(Cable = 2 Meters, 24 AWG, Data Rate = 2.25 Gbps)

Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB

(Cable = 2 Meters, 24 AWG, Data Rate = 2.25 Gbps)

0.167UI/DIV AT 3.0Gbps

Figure 6. Rx Eye Diagram at TP2

(Cable = 2 Meters, 24 AWG, Data Rate = 3 Gbps)

Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB

(Cable = 2 Meters, 24 AWG, Data Rate = 3 Gbps)

Rev. B | Page 8 of 20

Data Sheet

AD8195

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷− 1,

TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

0.125UI/DIV AT 2.25Gbps

Figure 9 Rx Eye Diagram at TP2

Figure 11. Rx Eye Diagram at TP3, EQ = 12 dB

(Cable = 20 Meters, 24 AWG, Data Rate = 2.25 Gbps)

0.167UI/DIV AT 3.0Gbps

Figure 10 Rx Eye Diagram at TP2

(Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps)

Figure 12. Rx Eye Diagram at TP3, EQ = 12 dB

(Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps)

Rev. B | Page 9 of 20

AD8195

Data Sheet

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷− 1,

TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

AD8195

SERIAL DATA

ANALYZER

DIGITAL

PATTERN

GENERATOR

EVALUATION

BOARD

SMA COAX CABLE

REFERENCE EYE DIAGRAM AT TP1

TP1

TP2

TP3

Figure 13. Test Circuit Diagram for Tx Eye Diagrams

0.125UI/DIV AT 2.25Gbps

Figure 14. Tx Eye Diagram at TP2, PE = 0 dB, Data Rate = 2.25 Gbps

Figure 16. Tx Eye Diagram at TP3, PE = 0 dB, Data Rate = 2.25 Gbps

(Cable = 6 Meters, 24 AWG)

0.167UI/DIV AT 3.0Gbps

Figure 15. Tx Eye Diagram at TP2, PE = 0 dB, Data Rate = 3.0 Gbps

Figure 17. Tx Eye Diagram at TP3, PE = 0 dB, Data Rate = 3.0 Gbps

(Cable = 6 Meters, 24 AWG)

Rev. B | Page 10 of 20

Data Sheet

AD8195

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷− 1,

data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

0.6

0.5

0.4

0.3

0.2

0.1

0

0.6

0.5

0.4

0.3

0.2

0.1

0

ALL CABLES = 24 AWG

PE = 6dB

ALL CABLES = 24 AWG

3.0Gbps

1080p, 12-BIT

1.65Gbps

3.0Gbps

1080p, 12-BIT

1080p, 8-BIT

720p/1080i,

8-BIT

1.65Gbps

720p/1080i,

8-BIT

480p, 8-BIT

0

5

10

15

20

25

0

2

4

6

8

10

12

14

16

INPUT CABLE LENGTH (m)

OUTPUT CABLE LENGTH (m)

Figure 18. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)

Figure 21. Jitter vs. Output Cable Length (See Figure 13 for Test Setup)

50

40

30

1.2

1.0

0.8

0.6

0.4

0.2

0

DJ p-p

20

10

RJ rms

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

DATA RATE (Gbps)

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

DATA RATE (Gbps)

Figure 19. Jitter vs. Data Rate

Figure 22. Eye Height vs. Data Rate

50

40

30

20

10

0

1.2

1.0

0.8

0.6

0.4

0.2

0

DJ p-p

RJ rms

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.0

3.1

3.2

3.3

3.4

3.5

3.6

SUPPLY VOLTAGE (V)

Figure 20. Jitter vs. Supply Voltage

Figure 23. Eye Height vs. Supply Voltage

Rev. B | Page 11 of 20

AD8195

Data Sheet

T_A= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2⁷− 1,

data rate = 3 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

80

70

60

50

40

30

20

10

0

50

45

40

35

30

25

20

15

10

5

DJ p-p

RJ rms

0

0.5

1.0

1.5

2.0

2.5

2.7

2.9

3.1

3.3

3.5

3.7

100

10

DIFFERENTIAL INPUT VOLTAGE SWING (V)

INPUT COMMON-MODE VOLTAGE (V)

Figure 24. Jitter vs. Differential Input Voltage Swing

Figure 27. Jitter vs. Input Common-Mode Voltage

50

40

30

20

10

0

120

115

110

105

100

95

DJ p-p

90

85

RJ rms

80

–40

–15

10

35

60

85

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 25. Jitter vs. Temperature

Figure 28. Differential Input Resistance vs. Temperature

120

100

80

60

40

20

0

0.5

0.4

0.3

0.2

0.1

0

RISE

FALL

–40

–20

0

20

40

60

80

0

1

2

3

4

5

6

7

8

9

TEMPERATURE (°C)

LOAD CURRENT (mA)

Figure 26. Rise and Fall Time vs. Temperature

Figure 29.DDC/CEC Output Logic Low Voltage (V_OL) vs. Load Current

Rev. B | Page 12 of 20

Data Sheet

AD8195

THEORY OF OPERATION

The primary function of the AD8195 is to buffer a single (HDMI

or DVI) link. The HDMI or DVI link consists of four differential,

high speed channels and three auxiliary single-ended, low speed

control signals. The high speed channels include a data-word clock

and three transition minimized differential signaling (TMDS)

data channels running at 10× the data-word clock frequency for

data rates up to 2.25 Gbps. The three low speed control signals

consist of the display data channel (DDC) bus (SDA and SCL)

and the consumer electronics control (CEC) line.

OUTPUT CHANNELS

Each high speed output differential pair is terminated to the

3.3 V VTTO power supply through two single-ended 50 Ω

on-chip resistors (see Figure 31).

VTTO

50Ω

OPx

ONx

All four high speed TMDS channels are identical; that is, the

pixel clock can be run on any of the four TMDS channels.

Receive channel compensation is provided for the high speed

channels to support long input cables. The AD8195 also includes

selectable preemphasis for driving high loss output cables.

I

OUT

AVEE

Figure 31. High Speed Output Simplified Schematic

In the intended application, the AD8195 is placed between a

source and a sink, with long cable runs on the input and output.

The output termination resistors of the AD8195 back terminate

the output TMDS transmission lines. These back terminations,

as `recommended in the HDMI specification, act to absorb

reflections from impedance discontinuities on the output traces,

improving the signal integrity of the output traces and adding

flexibility to how the output traces can be routed. For example,

interlayer vias can be used to route the AD8195 TMDS outputs

on multiple layers of the PCB without severely degrading the

quality of the output signal. Note that the arrangement of the

ESD structures cause current to flow into the TMDS outputs

when in the off state. The AD8195 outputs will not meet the

requirements of Test ID 7-3 (TMDS-VOFF) of the HDMI

Compliance Test Specification 1.3c. These outputs should only

interface to an internal system node and should not be interfaced

to an HDMI output connector.

INPUT CHANNELS

Each high speed input differential pair terminates to the 3.3 V

VTTI power supply through a pair of single-ended 50 Ω on-chip

resistors, as shown in Figure 30. When the transmitter of the

AD8195 is disabled by setting the TX_EN control pin, the input

termination resistors are also disabled to provide a high impedance

node at the TMDS inputs.

The input equalizer provides 12 dB of high frequency boost.

No specific cable length is suggested for this equalization level

because cable performance varies widely between manufacturers;

however, in general, the AD8195 does not degrade or over-

equalize input signals, even for short input cables. The AD8195

can equalize more than 20 meters of 24 AWG cable at 2.25 Gbps,

over reference cables that exhibit an insertion loss of −15 dB.

VTTI

The AD8195 has an external control pin, TX_EN, that disables

the transmitter, reducing power when the transmitter is not in

use. Additionally, when the transmitter is disabled, the input

termination resistors are also disabled to present a high impedance

state at the input and indicate to any connected HDMI sources

that the link through the AD8195 is inactive.

50Ω

TX_EN

IPx

INx

CABLE

EQ

Table 7. Transmitter Enable Setting

TX_EN

Function

0

1

Tx/input termination disabled

Tx/input termination enabled

AVEE

Figure 30. High Speed Input Simplified Schematic

The AD8195 also includes two levels of programmable output

preemphasis, 0 dB and 6 dB. The output preemphasis level can

be manually configured by setting the PE_EN pin. No specific

cable length is suggested for use with either preemphasis setting,

as cable performance varies widely among manufacturers.

Table 8. Preemphasis Setting

PE_EN

PE Boost

0

1

0 dB

6 dB

Rev. B | Page 13 of 20

AD8195

Data Sheet

PREEMPHASIS

AUXILIARY LINES

The preemphasized TMDS outputs precompensate the trans-

mitted signal to account for losses in systems with long cable

runs. These long cable runs selectively attenuate the high

frequency energy of the signal, leading to degraded transition

times and eye closure. Similar to a receive equalizer, the goal of

the preemphasis filter is to boost the high frequency energy in

the signal. However, unlike the receive equalizer, the preemphasis

filter is applied before the channel, thus predistorting the

transmitted signal to account for the loss of the channel. The

series connection of the preemphasis filter and the channel

results in a flatter frequency response than that of the channel,

thus leading to improved high frequency energy, improved

transition times, and improved eye opening on the far end of

the channel. Using a preemphasis filter to compensate for

channel losses allows for longer cable runs with or without a

receiver equalizer on the far end of the channel.

The auxiliary (low speed) lines provide buffering for the DDC

and CEC signals. The auxiliary lines are powered independently

from the TMDS link; therefore, their functionality can be

maintained even when the system is powered off. In an application,

these lines can be powered by connecting AMUXVCC to the

5 V supply provided from the video source through the input

HDMI connector.

DDC Buffers

The DDC buffers are 5 V tolerant bidirectional lines that can

carry extended display identification data (EDID), HDCP

encryption, and other information, depending on the specific

application. The DDC buffers are bidirectional and fully support

arbitration, clock synchronization, clock stretching, slave acknowl-

edgement, and other relevant features of a standard mode I²C bus.

The DDC buffers also have separate voltage references for the

input side and the output side, allowing the sink to use internal

bus voltages (3.3 V), alleviating the need for 5 V tolerant I/Os

for system ASICs. The logic level for the DDC_IN bus is set by

the voltage on VREF_IN, and the logic level for the DDC_OUT

bus is set by the voltage on VREF_OUT. For example, if the

DDC_IN bus is using 5 V I²C, the VREF_IN power supply pin

should be connected to a 5 V power supply. If the DDC_OUT

bus is using 3.3 V I²C, the VREF_OUT power supply pin should

be connected to a 3.3 V power supply.

When there is no receive equalizer on the far end of the channel,

the preemphasis filter should allow longer cable runs than

would be acceptable with no preemphasis. When there is both a

preemphasis filter on the near end and a receive equalizer on

the far end of the channel, the allowable cable run should be

longer than either compensation could achieve alone. The pulse

response of a preemphasized waveform is shown in Figure 32.

The output voltage levels and symbol descriptions are listed in

Table 9 and Table 10, respectively. The preemphasis circuit is

designed to work up to 2.25 Gbps and does not perform

suitably at higher data rates.

CEC Buffer

The CEC buffer is a 3.3 V tolerant bidirectional buffer with

integrated pull-up resistors. This buffer enables full compliance

with all CEC specifications, including but not limited to input

capacitance, logic levels, transition times, and leakage (both with

the system power on and off). This allows the CEC functionality

to be implemented in a standard microcontroller that may not

have CEC compliant I/Os. The CEC buffer is powered from the

AMUXVCC supply.

PREEMPHASIS OFF

V

TTO

H

L

V

OCM

OSE-DC

PREEMPHASIS ON

V

TTO

V

H

V

OCM

V

OSE-DC

V

OSE-BOOST

V

L

<T

BIT

Figure 32. Preemphasis Pulse Response

Table 9. Output Voltage Levels

PE Setting

Boost (dB)

I_T(mA)

20

40

V_OSE-DC(mV p-p)

V_OSE-BOOST(mV p-p)

V_OCM(V)

3.050

2.8

V_H(V)

3.3

V_L(V)

2.8

2.3

0

1

0

6

500

1000

Table 10. Symbol Definitions

Symbol

Formula

Definition

V_OSE-DC

V_OSE-BOOST

V_OCM(DC-Coupled)

V_H

V_L

I_T|_{PE = 0}× 25 Ω

I_T× 25 Ω

V_TTO– I_T/2 × 25 Ω

V_OCM+ V_OSE-BOOST/2

V_OCM− V_OSE-BOOST/2

Single-ended output voltage swing after settling

Boosted single-ended output voltage swing

Common-mode voltage when the output is dc-coupled

High single-ended output voltage excursion

Low single-ended output voltage excursion

Rev. B | Page 14 of 20

Data Sheet

AD8195

APPLICATIONS INFORMATION

The rise time of the CEC buffer output is set by the time constant

of the pull-up resistance and the capacitance on the output node.

An additional external pull-up resistance is recommended at

the CEC output to allow for optimal rise times. A Thevenin

equivalent 2 kΩ pull-up to 3.3 V is shown in Figure 34.

FRONT PANEL BUFFER FOR ADVANCED TV

A front panel input provides easy access to an HDMI connector

for connecting devices, such as an HD camcorder or video game

console, to an HDTV. In designs where the main PCB is not

near the side or front of the HDTV, a front panel HDMI input

must be connected to the main board through a cable. The

AD8195 enables the implementation of a front or side panel

HDMI input for an HDTV by buffering the HDMI signals and

compensating for the cable interconnect to the main board.

The VREF_IN and VREF_OUT pins are voltage references for

the input and output pins of DDC buffer. The external pull-up

resistors for the DDC bus should be connected to the same

voltage as applied to the respective VREF pin.

Typically, an EDID EEPROM is placed prior to the AD8195,

as shown in Figure 34. If desired, the EDID EEPROM can be

downstream of the AD8195. This optional configuration is also

illustrated in Figure 34. Regardless of the configuration, the

pull-up voltage at the DDC output should be on even when the

local system power supply is off.

A simplified typical front panel buffer circuit is shown in Figure 33.

The AD8195 is designed to have an HDMI/DVI receiver pinout

at its input and a transmitter pinout at its output. This makes

the AD8195 ideal for use in television set front panel connectors

and AVR-type applications where a designer routes both the

inputs and the outputs directly to HDMI/DVI connectors.

To ensure that the AD8195 operates properly, Pin 21 (COMP)

should be tied to ground through a 10 µF bypass capacitor. A 34 kΩ

pull-up resistor from COMP to AMUXVCC is integrated on chip.

One advantage of the AD8195 in a television set front panel

connector is that all of the high speed signals can be routed on

one side (the topside) of the board. The AD8195 provides 12 dB

of input equalization so it can compensate for the signal degra-

dation of long input cables. In addition, the AD8195 can also

provide up to 6 dB of output preemphasis that boosts the output

TMDS signals and allows the AD8195 to precompensate when

driving long PCB traces or high loss output cables. The net

effect of the input equalization and output preemphasis of the

AD8195 is that the AD8195 can compensate for the signal

degradation of both the input and output cables; it acts to reopen

a closed input data eye and transmit a full swing HDMI signal

to an end receiver.

HDTV SET

MAIN PCB

HDMI RX

AD8195

CABLE

Placement of a shunt resistor from the negative terminal of the

input TMDS clock differential pair to ground is recommended

to prevent amplification of ambient noise resulting in a large

swing signal at the input of the HDMI receiver.

For the CEC and DDC buffer circuits to be active when the

local supply is off, power must be provided to the AD8195

AMUXVCC supply pin from the HDMI source. The 5 V from

the HDMI connector and the local 5 V supply should be isolated

with diodes to prevent contention. Additionally, the diodes

should be selected such that the forward voltage drop from the

local supply is less than from the HDMI source so that current

is not drawn from the HDMI source when the local supply is on.

Figure 33. AD8195 as a Front Panel Buffer for an HDTV

Rev. B | Page 15 of 20

AD8195

Data Sheet

5V

3.3V

AMUXVCC

CABLE OR PCB

INTERCONNECT

1µF

0.01µF

HDMI

CONNECTOR

AMUXVCC

AVCC, VTTI,

VTTO

TMDS

OP3

ON3

D2+

D2–

IPA3

INA3

D2+

D2–

OP2

ON2

D1+

D1–

IPA2

INA2

D1+

D1–

OP1

ON1

OP0

ON0

D0+

D0–

CLK+

CLK–

IPA1

INA1

IPA0

INA0

D0+

D0–

CLK+

CLK–

HDMI

RECEIVER

AD8195

ESD

PROTECTION

(OPTIONAL)

3.3V OR 5V

2kΩ

1kΩ

VREF_OUT

2kΩ

DDC_SCL

DDC_SDA

SCL_OUT

SDA_OUT

5V

VREF_IN

47kΩ

HPD

OPTIONAL EDID

PLACEMENT

DDC_SCL

DDC_SDA

CEC

SCL_IN

SDA_IN

CEC_IN

AMUXVCC

EDID

EEPROM

0.01µF

3kΩ

COMP

10µF

CEC_OUT

AVEE

EDID

EEPROM

0.01µF

6kΩ

TYPICAL EDID

PLACEMENT

CEC

MCU

Figure 34. AD8195 Typical Application Simplified Schematic

CABLE LENGTHS AND EQUALIZATION

PCB LAYOUT GUIDELINES

The AD8195 offers 12 dB of equalization for the high speed inputs.

The equalizer of the AD8195 is optimized for video data rates

of 2.25 Gbps and can equalize more than 20 meters of 24 AWG

HDMI cable at the input for 1080p video with deep color.

The AD8195 is used to buffer two distinctly different types of

signals, both of which are required for HDMI and DVI video.

These signal groups require different treatment when laying out

a PCB.

The length of cable that can be used in a typical HDMI/DVI

application depends on a large number of factors, including the

following:

The first group of signals carries the audiovisual (AV) data encoded

by a technique called transition minimized differential signaling

(TMDS) and, in the case of HDMI, is also encrypted according to

the high bandwidth digital copy protection (HDCP) standard.

•

Cable quality: the quality of the cable in terms of conductor

wire gauge and shielding. Thicker conductors have lower

signal degradation per unit length.

HDMI/DVI video signals are differential, unidirectional, and

high speed (up to 2.25 Gbps). The channels that carry the video

data must have controlled impedance, be terminated at the

receiver, and be capable of operating up to at least 2.25 Gbps. It

is especially important to note that the differential traces that

carry the TMDS signals should be designed with a controlled

differential impedance of 100 Ω. The AD8195 provides single-

ended 50 Ω terminations on chip for both its inputs and outputs.

Transmitter termination is not fully specified by the HDMI

standard, but its inclusion improves the overall system signal

integrity.

•

Data rate: the data rate being sent over the cable. The signal

degradation of HDMI cables increases with data rate.

Edge rates: the edge rates of the source input. Slower input

edges result in more significant data eye closure at the end

of a cable.

•

Receiver sensitivity: the sensitivity of the terminating

receiver.

TMDS OUTPUT RISE/FALL TIMES

The TMDS outputs of the AD8195 are designed for optimal

performance even when external components are connected,

such as external ESD protection, common-mode filters, and

the HDMI connector. In applications where the output of the

AD8195 is connected to an HDMI output connector, additional

ESD protection is recommended. The capacitance of the addi-

tional ESD protection circuits for the TMDS outputs should be

as low as possible. In a typical application, the output rise/fall

times are compliant with the HDMI specification at the output

of the HDMI connector.

The second group of signals consists of low speed auxiliary control

signals used for communication between a source and a sink.

These signals include the DDC bus (this is an I²C bus used to

send EDID information and HDCP encryption keys between

the source and the sink) and the CEC line. These auxiliary signals

are bidirectional, low speed, and transferred over a single-ended

transmission line that does not need to have controlled impedance.

The primary concern with laying out the auxiliary lines is ensuring

that they conform to the I²C bus standard and do not have

excessive capacitive loading.

Rev. B | Page 16 of 20

Data Sheet

AD8195

Both traces of a given differential pair must be equal in length

to minimize intrapair skew. Maintaining the physical symmetry

of a differential pair is integral to ensuring its signal integrity;

excessive intrapair skew can introduce jitter through duty cycle

distortion (DCD). The p and n of a given differential pair should

always be routed together in order to establish the required

100 Ω differential impedance. Enough space should be left

between the differential pairs of a given group so that the n of

one pair does not couple to the p of another pair. For example, one

technique is to make the interpair distance 4 to 10 times wider

than the intrapair spacing.

TMDS Signals

In the HDMI/DVI standard, four differential pairs carry the

TMDS signals. In DVI, three of these pairs are dedicated to

carrying RGB video and sync data. For HDMI, audio data is

also interleaved with the video data; the DVI standard does not

incorporate audio information. The fourth high speed differential

pair is used for the AV data-word clock and runs at one-tenth

the speed of the TMDS data channels.

The four high speed channels of the AD8195 are identical.

No concession was made to lower the bandwidth of the fourth

channel for the pixel clock, so any channel can be used for any

TMDS signal. The user chooses which signal is routed over

which channel. Additionally, the TMDS channels are symmetric;

therefore, the p and n of a given differential pair are interchange-

able, provided the inversion is consistent across all inputs and

outputs of the AD8195. However, the routing between inputs

and outputs through the AD8195 is fixed. For example, Input

Channel 0 is always buffered to Output Channel 0, and so forth.

Any group of four TMDS channels (input or output) should have

closely matched trace lengths to minimize interpair skew. Severe

interpair skew can cause the data on the four different channels

of a group to arrive out of alignment with one another. A good

practice is to match the trace lengths for a given group of four

channels to within 0.05 inches on FR4 material.

The length of the TMDS traces should be minimized to reduce

overall signal degradation. Commonly used PCB material, such

as FR4, is lossy at high frequencies, so long traces on the circuit

board increase signal attenuation, resulting in decreased signal

swing and increased jitter through intersymbol interference (ISI).

The AD8195 buffers the TMDS signals, and the input traces can

be considered electrically independent of the output traces. In

most applications, the quality of the signal on the input TMDS

traces is more sensitive to the PCB layout. Regardless of the data

being carried on a specific TMDS channel, or whether the TMDS

line is at the input or the output of the AD8195, all four high

speed signals should be routed on a PCB in accordance with the

same RF layout guidelines.

Controlling the Characteristic Impedance of a TMDS

Differential Pair

The characteristic impedance of a differential pair depends on a

number of variables, including the trace width, the distance

between the two traces, the height of the dielectric material

between the trace and the reference plane below it, and the

dielectric constant of the PCB binder material. To a lesser

extent, the characteristic impedance also depends upon the

trace thickness and the presence of solder mask.

Layout for the TMDS Signals

The TMDS differential pairs can be either microstrip traces,

routed on the outer layer of a board, or stripline traces, routed

on an internal layer of the board. If microstrip traces are used,

there should be a continuous reference plane on the PCB layer

directly below the traces. If stripline traces are used, they must

be sandwiched between two continuous reference planes in the

PCB stack-up. Additionally, the p and n of each differential pair

must have a controlled differential impedance of 100 Ω. The

characteristic impedance of a differential pair is a function of

several variables, including the trace width, the distance separating

the two traces, the spacing between the traces and the reference

plane, and the dielectric constant of the PCB binder material.

Interlayer vias introduce impedance discontinuities that can

cause reflections and jitter on the signal path; therefore, it is

preferable to route the TMDS lines exclusively on one layer of the

board, particularly for the input traces. In addition, to prevent

unwanted signal coupling and interference, route the TMDS

signals away from other signals and noise sources on the PCB.

There are many combinations that can produce the correct

characteristic impedance. It is generally required to work with

the PCB fabricator to obtain a set of parameters to produce the

desired results.

One consideration is how to guarantee a differential pair with a

differential impedance of 100 Ω over the entire length of the trace.

One technique is to change the width of the traces in a differential

pair based on how closely one trace is coupled to the other. When

the two traces of a differential pair are close and strongly coupled,

they should have a width that produces a 100 Ω differential

impedance. When the traces split apart to go into a connector,

for example, and are no longer so strongly coupled, the width of

the traces should be increased to yield a differential impedance of

100 Ω in the new configuration.

Rev. B | Page 17 of 20

AD8195

Data Sheet

3W

W

3W

TMDS Terminations

The AD8195 provides internal 50 Ω single-ended terminations

for all of its high speed inputs and outputs. It is not necessary to

include external termination resistors for the TMDS differential

pairs on the PCB.

SILKSCREEN

LAYER 1: MICROSTRIP

PCB DIELECTRIC

LAYER 2: REFERENCE PLANE

PCB DIELECTRIC

The output termination resistors of the AD8195 back terminate

the output TMDS transmission lines. These back terminations

act to absorb reflections from impedance discontinuities on the

output traces, improving the signal integrity of the output traces

and adding flexibility to how the output traces can be routed.

For example, interlayer vias can be used to route the AD8195

TMDS outputs on multiple layers of the PCB without severely

degrading the quality of the output signal.

LAYER 3: REFERENCE PLANE

PCB DIELECTRIC

LAYER 4: MICROSTRIP

SILKSCREEN

REFERENCE LAYER

RELIEVED UNDERNEATH

MICROSTRIP

Auxiliary Control Signals

Figure 35. Example Board Stack-Up

There are three single-ended control signals associated with

each source or sink in an HDMI/DVI application. These are

CEC and two DDC lines. The two signals on the DDC bus are

SDA and SCL (serial data and serial clock, respectively). These

three signals can be buffered through the AD8195 and do not

need to be routed with the same strict considerations as the

high speed TMDS signals.

Power Supplies

The AD8195 has four separate power supplies referenced to a

single ground, AVEE. The supply/ground pairs are

•

AVCC/AVEE

VTTI/AVEE

VTTO/AVEE

AMUXVCC/AVEE.

In general, it is sufficient to route each auxiliary signal as a

single-ended trace. These signals are not sensitive to impedance

discontinuities, do not require a reference plane, and can be

routed on multiple layers of the PCB. However, it is best to

follow strict layout practices whenever possible to prevent the

PCB design from affecting the overall application. The specific

routing of the CEC and DDC lines depends on the application

in which the AD8195 is being used.

The AVCC/AVEE (3.3 V) supply powers the core of the AD8195.

The VTTI/AVEE supply (3.3 V) powers the input termination

(see Figure 30). Similarly, the VTTO/AVEE supply (3.3 V)

powers the output termination (see Figure 31). The AMUXVCC/

AVEE supply (5 V) powers the auxiliary buffer core.

In a typical application, all pins labeled AVEE should be connected

directly to ground. All pins labeled AVCC, VTTI, or VTTO

should be connected to 3.3 V, and Pin AMUXVCC should be

tied to 5 V. The AVCC supply powers the TMDS buffers while

AMUXVCC powers the DDC/CEC buffers. The AMUXVCC

pin can be connected to the 5 V supply provided from the input

HDMI connector to ensure that the DDC and CEC buffers

remain functional when the system is powered off. The supplies

can also be powered individually, but care must be taken to

ensure that each stage of the AD8195 is powered correctly.

For example, the maximum speed of signals present on the

auxiliary lines is 100 kHz I²C data on the DDC lines; therefore,

any layout that enables 100 kHz I²C to be passed over the DDC

bus should suffice. The HDMI specification, however, places a

strict 50 pF limit on the amount of capacitance that can be

measured on either SDA or SCL at the HDMI input connector.

This 50 pF limit includes the HDMI connector, the PCB, and

whatever capacitance is seen at the input of the AD8195. There

is a similar limit of 150 pF of input capacitance for the CEC line.

DDC Reference Inputs

The parasitic capacitance of traces on a PCB increases with

trace length. To help ensure that a design satisfies the HDMI

specification, the length of the CEC and DDC lines on the PCB

should be made as short as possible. Additionally, if there is a

reference plane in the layer adjacent to the auxiliary traces in

the PCB stack-up, relieving or clearing out this reference plane

immediately under the auxiliary traces significantly decreases

the amount of parasitic trace capacitance. An example of the

board stack-up is shown in Figure 35.

The VREF_IN and VREF_OUT voltages (3.3 V to 5 V) provide

reference levels for the DDC buffers. Both voltages are referenced

to AVEE. The voltage applied at these reference inputs should

be the same as the pull-up voltage for corresponding DDC bus.

Unused DDC/CEC Buffers

If the DDC and the CEC buffers are not used, the AD8195 does

not require a 5 V supply for AMUXVCC. For operation without

the buffers, tie AMUXVCC to AVCC (nominally 3.3 V) and tie

VREF_IN and VREF_OUT to AVEE (nominally ground).

Other buffer pins can be left floating.

The AD8195 buffers the auxiliary signals; therefore, only the

input traces, connector, and AD8195 input capacitance must be

considered when designing a PCB to meet HDMI specifications.

Rev. B | Page 18 of 20

Data Sheet

AD8195

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.60 MAX

PIN 1

INDICATOR

31

30

40

1

5.85

5.75 SQ

5.65

0.50

BSC

PIN 1

INDICATOR

4.25

4.10 SQ

3.95

EXPOSED

PAD

(BOTTOM VIEW)

10

11

21

20

0.50

0.40

0.30

0.20 MIN

TOP VIEW

4.50 REF

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

0.30

0.23

0.18

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 36. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Package Ordering

Model¹

Temperature Range Package Description

−40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Option

CP-40-1

Quantity

AD8195ACPZ

AD8195ACPZ-R7 −40°C to +85°C

AD8195-EVALZ

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel

Evaluation Board

750

¹Z = RoHS Compliant Part.

Rev. B | Page 19 of 20

AD8195

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D07049-0-8/12(B)

Rev. B | Page 20 of 20


型号：	AD8195ACPZ
厂家：	ADI
描述：	HDMI/DVI Buffer with Equalization HDMI / DVI缓冲器，具有均衡
文件：	总20页 (文件大小：1040K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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