AD8197ASTZ [ADI]
4:1 HDMI/DVI Switch with Equalization; 4 ： 1 HDMI / DVI开关，具有均衡
| 型号： | AD8197ASTZ |
| 厂家： | 
ADI |
| 描述： | 4:1 HDMI/DVI Switch with Equalization |
| 文件： | 总32页 (文件大小：711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4:1 HDMI/DVI Switch with Equalization
Preliminary Data Sheet
AD8197
FEATURES
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Four inputs, one output HDMI™/DVI links
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8191
Four TMDS channels per link
Set-top boxes
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Advanced television (HDTV) sets
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
FUNCTIONAL BLOCK DIAGRAM
Fully buffered unidirectional inputs/outputs
Globally switchable, 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
Four auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and two additional signals
Multiple channel bundling modes
1x (4:1) HDMI/DVI link switch (default)
2x (8:1) TMDS channel and auxiliary signal switch
1x (16:1) TMDS channel and auxiliary signal switch
Output disable feature
Reduced power dissipation
Figure 1.
Removable output termination
TYPICAL APPLICATION
Allows building of larger arrays
Two AD8197s support HDMI/DVI dual-link
Standards compliant: HDMI receiver, HDCP, DVI
Serial (I2C® slave) and parallel control interface
100-lead, 14 mm × 14 mm LQFP, Pb-free package
Figure 2. Typical HDTV Application
The AD8197 is provided in a 100-lead LQFP, Pb-free, surface
mount package specified to operate over the −40°C to +85°C
temperature range.
GENERAL DESCRIPTION
The AD8197 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or allow
the construction of larger arrays using the wire-OR technique.
Flexible channel bundling modes (for both the TMDS channels
and the auxiliary signals) allow the AD8197 to be configured as a
4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single
16:1 switch.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling greater than
1080p HDMI formats with deep color, and UXGA (1600 ×
1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8197
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Read Procedure........................................................................... 17
Switching/Update Delay............................................................ 17
Parallel Control Interface .............................................................. 18
Serial Interface Configuration Registers ..................................... 19
High Speed Device Modes Register......................................... 19
Auxiliary Device Modes Register............................................. 20
Receiver Settings Register ......................................................... 22
Input Termination Pulse Register 1 and Register 2 ............... 22
Receive Equalizer Register 1 and Register 2 ........................... 22
Transmitter Settings Register.................................................... 22
Parallel Interface Configuration Registers .................................. 23
High Speed Device Modes Register......................................... 23
Auxiliary Device Modes Register............................................. 23
Receiver Settings Register ......................................................... 24
Input Termination Pulse Register 1 and Register 2 ............... 24
Receive Equalizer Register 1 and Register 2 ........................... 24
Transmitter Settings Register.................................................... 24
Application Information................................................................ 25
Pinout........................................................................................... 25
Cable Lengths and Equalization............................................... 25
PCB Layout Guidelines.............................................................. 26
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application........................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 13
Introduction................................................................................ 13
Input Channels............................................................................ 13
Output Channels ........................................................................ 13
High Speed (TMDS) Switching Modes ................................... 14
Auxiliary Switch.......................................................................... 14
Auxiliary (Low Speed) Switching Modes................................ 15
Serial Control Interface.................................................................. 16
Reset ............................................................................................. 16
Write Procedure .......................................................................... 16
PrA| Page 2 of 32
Preliminary Data Sheet
SPECIFICATIONS
AD8197
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
Conditions/Comments
Min
Typ Max
Unit
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
Differential Intrapair Skew
Differential Interpair Skew1
EQUALIZATION PERFORMANCE
Receiver (Highest Setting)2
Transmitter (Highest Setting)3
INPUT CHARACTERISTICS
Input Voltage Swing
NRZ
2.25
Gbps
PRBS 223 − 1
10−9
TBD
TBD
TBD
TBD
DR ≤ 2.25 Gbps, PRBS 223 − 1
ps (p-p)
ps (rms)
ps
At output
At output
ps
Boost frequency = 825 MHz
Boost frequency = 825 MHz
12
6
dB
dB
Differential
150
AVCC − 800
1200
AVCC
mV
mV
Input Common-Mode Voltage (VICM
OUTPUT CHARACTERISTICS
High Voltage Level
)
Single-ended high speed channel
Single-ended high speed channel
AVCC − 10
AVCC − 600
75
AVCC + 10
mV
Low Voltage Level
Rise/Fall Time (20% to 80%)
AVCC − 400 mV
135 200
ps
INPUT TERMINATION
Resistance
Single-ended
50
Ω
AUXILIARY CHANNELS
On Resistance, RAUX
On Capacitance, CAUX
Input/Output Voltage Range
POWER SUPPLY
AVCC
100
8
Ω
pF
V
DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz
Operating range
DVEE
3
AMUXVCC
3.6
3.3
V
QUIESCENT CURRENT
AVCC
Outputs disabled
30
48
88
5
35
72
40
60
44
64
mA
mA
mA
mA
mA
mA
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
Input termination on4
Output termination on, no pre-emphasis
Output termination on, maximum
pre-emphasis
100 110
VTTI
VTTO
40
40
80
54
46
90
DVCC
AMUXVCC
3.2
7
8
mA
mA
0.01 0.1
POWER DISSIPATION
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
115
384
704
271 361
574 671
910 1050
mW
mW
mW
TIMING CHARACTERISTICS
Switching/Update Delay
High speed switching register: HS_CH
All other configuration registers
200
1.5
ms
ms
ns
RESET Pulse Width
50
PrA | Page 3 of 32
AD8197
Preliminary Technical Data
Parameter
Conditions/Comments
Min
Typ Max
Unit
SERIAL CONTROL INTERFACE5
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
PARALLEL CONTROL INTERFACE
Input High Voltage, VIH
Input Low Voltage, VIL
2
V
V
V
V
0.8
0.4
2.4
2
V
V
0.8
1 Differential interpair skew is measured between the TMDS pairs of a single link.
2 AD8197 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
5 The AD8197 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
PrA| Page 4 of 32
Preliminary Data Sheet
AD8197
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions: a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θJC is specified for no airflow.
Parameter
Rating
AVCC to AVEE
DVCC to DVEE
DVEE to AVEE
VTTI
VTTO
AMUXVCC
3.7 V
3.7 V
0.3 V
AVCC + 0.6 V
AVCC + 0.6 V
5.5 V
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
100-Lead LQFP
56
19
°C/W
Internal Power Dissipation
High Speed Input Voltage
2.2 W
AVCC − 1.4 V < VIN
AVCC + 0.6 V
<
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8197
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
High Speed Differential Input Voltage
Low Speed Input Voltage
2.0 V
DVEE − 0.3 V < VIN
AMUXVCC + 0.6 V
DVEE − 0.3 V < VIN
DVCC + 0.6 V
−65°C to +125°C
−40°C to +85°C
150°C
<
I2C and Parallel Logic Input Voltage
<
Storage Temperature Range
Operating Temperature Range
Junction Temperature
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation, it
is necessary to observe the maximum power rating as determined
by the coefficients in Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
PrA | Page 5 of 32
AD8197
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Power
HS I
Description
1, 13, 22, 54, 63, 75
AVCC
Positive Analog Supply. 3.3 V nominal.
High Speed Input Complement.
High Speed Input.
2
IN_B0
IP_B0
AVEE
3
HS I
4, 10, 16, 25, 51, 60, 66, 72
Power
HS I
Negative Analog Supply. 0 V nominal.
High Speed Input Complement.
High Speed Input.
5
IN_B1
IP_B1
VTTI
6
HS I
7, 19, 57, 69
Power
HS I
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
8
IN_B2
IP_B2
IN_B3
IP_B3
IN_A0
IP_A0
9
HS I
11
12
14
15
HS I
High Speed Input Complement.
High Speed Input.
HS I
HS I
High Speed Input Complement.
High Speed Input.
HS I
PrA| Page 6 of 32
Preliminary Data Sheet
AD8197
Pin No.
17
Mnemonic
Type1
HS I
Description
IN_A1
IP_A1
High Speed Input Complement.
High Speed Input.
18
HS I
20
IN_A2
IP_A2
HS I
High Speed Input Complement.
High Speed Input.
21
HS I
23
IN_A3
IP_A3
HS I
High Speed Input Complement.
24
HS I
High Speed Input.
26
I2C_ADDR0
I2C_ADDR1
I2C_ADDR2
DVEE
Control
Control
Control
Power
Control
Control
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Control
Control
Control
Control
Control
HS I
I2C Address 1st LSB.
I2C Address 2nd LSB.
I2C Address 3rd LSB.
27
28
29, 95
30
Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal.
Quad Switching Mode High Speed Source Selection Parallel Interface LSB.
Quad Switching Mode High Speed Source Selection Parallel Interface MSB.
Positive Digital Power Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
PP_CH0
PP_CH1
DVCC
31
32, 38, 47
33
ON0
34
OP0
35, 41
36
VTTO
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
ON1
37
OP1
39
ON2
High Speed Output Complement.
High Speed Output.
40
OP2
42
ON3
High Speed Output Complement.
High Speed Output.
43
OP3
44
RESET
PP_PRE0
PP_PRE1
PP_OCL
I2C_SCL
I2C_SDA
IN_D0
IP_D0
IN_D1
IP_D1
IN_D2
IP_D2
IN_D3
IP_D3
IN_C0
IP_C0
Configuration Registers Reset. Normally pulled up to AVCC.
High Speed Pre-Emphasis Selection Parallel Interface LSB.
High Speed Pre-Emphasis Selection Parallel Interface MSB.
High Speed Output Current Level Parallel Interface.
I2C Clock.
45
46
48
49
50
I2C Data.
52
High Speed Input Complement.
High Speed Input.
53
HS I
55
HS I
High Speed Input Complement.
High Speed Input.
56
HS I
58
HS I
High Speed Input Complement.
High Speed Input.
59
HS I
61
HS I
High Speed Input Complement.
High Speed Input.
62
HS I
64
HS I
High Speed Input Complement.
High Speed Input.
65
HS I
67
IN_C1
IP_C1
HS I
High Speed Input Complement.
High Speed Input.
68
HS I
70
IN_C2
IP_C2
HS I
High Speed Input Complement.
High Speed Input.
71
HS I
73
IN_C3
IP_C3
HS I
High Speed Input Complement.
High Speed Input.
74
HS I
76
PP_EN
PP_EQ
AUX_D3
Control
Control
LS I/O
High Speed Output Enable Parallel Interface.
High Speed Equalization Selection Parallel Interface.
Low Speed Input/Output.
77
78
PrA | Page 7 of 32
AD8197
Preliminary Technical Data
Pin No.
79
Mnemonic
AUX_D2
AUX_D1
AUX_D0
AMUXVCC
AUX_C3
Type1
LS I/O
LS I/O
LS I/O
Power
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
Control
Description
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
80
81
82
Positive Auxiliary Multiplexer Supply. 5V typical.
Low Speed Input/Output.
83
84
AUX_C2
Low Speed Input/Output.
85
AUX_C1
Low Speed Input/Output.
86
AUX_C0
Low Speed Input/Output.
87
AUX_COM3
AUX_COM2
AUX_COM1
AUX_COM0
AUX_B3
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Input/Output.
88
89
90
91
92
AUX_B2
Low Speed Input/Output.
93
AUX_B1
Low Speed Input/Output.
94
AUX_B0
Low Speed Input/Output.
96
AUX_A3
Low Speed Input/Output.
97
AUX_A2
Low Speed Input/Output.
98
AUX_A1
Low Speed Input/Output.
99
AUX_A0
Low Speed Input/Output.
100
PP_OTO
High Speed Output Termination Selection Parallel Interface.
1 HS = high speed, LS = low speed, I = input, O = output.
PrA| Page 8 of 32
Preliminary Data Sheet
AD8197
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
Figure 4. Test Circuit Diagram for RX Eye Diagram
Figure 7. RX Eye Diagram at TP3, EQ = 6 dB (Cable = 2 meters, 30 AWG)
Figure 5. RX Eye Diagram at TP2 (Cable = 2 meters, 30 AWG)
Figure 8. RX Eye Diagram at TP3, EQ = 12 dB (Cable = 20 meters, 24 AWG)
Figure 6. RX Eye Diagram at TP2 (Cable = 20 meters, 24 AWG)
PrA | Page 9 of 32
AD8197
Preliminary Technical Data
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
Figure 9. Test Circuit Diagram for TX Eye Diagrams
Figure 10. TX Eye Diagram at TP2, PE = 2 dB
Figure 12. TX Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)
Figure 11. TX Eye Diagram at TP2, PE = 6 dB
Figure 13. TX Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)
PrA| Page 10 of 32
Preliminary Data Sheet
AD8197
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
Figure 15. Jitter vs. Data Rate
Figure 18. Eye Height vs. Data Rate
Figure 16. Jitter vs. Supply Voltage
Figure 19. Eye Height vs. Supply Voltage
PrA | Page 11 of 32
AD8197
Preliminary Technical Data
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
Figure 20. Jitter vs. Differential Input Swing
Figure 23. Jitter vs. Input Common-Mode Voltage
Figure 21. Jitter vs. Temperature
Figure 24. Differential Input Termination Resistance vs. Temperature
Figure 22. Rise and Fall Time vs. Temperature
PrA| Page 12 of 32
Preliminary Data Sheet
AD8197
THEORY OF OPERATION
programming the RX_TO bit in the receiver settings register. By
default, the input termination is enabled. The input
terminations are enabled and cannot be switched when
programming the AD8197 through the parallel control
interface.
INTRODUCTION
The AD8197 is a pin-to-pin HDMI 1.3 receive compliant
replacement for the AD8191. The primary function of the
AD8197 is to switch one of four (HDMI or DVI) single-link
sources to one output. Each HDMI/DVI link consists of four
differential, high speed channels and four auxiliary single-
ended, low speed control signals. The high speed channels
include a data-word clock and three transition minimized
differential signaling (TMDS) data channels running at 10× the
data-word clock frequency for data rates up to 2.25 Gbps. The
four low speed control signals are 5 V tolerant bidirectional
lines that can carry configuration signals, HDCP encryption,
and other information, depending upon the specific
application.
VTTI
50Ω
50Ω
IP_xx
IN_xx
CABLE
EQ
AVEE
Figure 25. High Speed Input Simplified Schematic
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is
provided for the high speed channels where the user can
(manually) select among a number of fixed settings.
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register through the serial
control interface. Alternately, the user can globally control the
equalization level of all eight high speed input channels by
setting the PP_EQ pin of the parallel control interface. No
specific cable length is suggested for a particular equalization
setting because cable performance varies widely between
manufacturers; however, in general, the equalization of the
AD8197 can be set to 12 dB without degrading the signal
integrity, even for short input cables. At the 12 dB setting, the
AD8197 can equalize more than 20 meters of 24 AWG cable at
2.25 Gbps.
The AD8197 switching logic has three modes: quad mode (a
quad 4:1 switch), dual mode (a dual 8:1 switch) and single
mode (one 16:1 switch).
The AD8197 has two control interfaces. Users have the option
of controlling the part through either the parallel control
interface or the I2C serial control interface. The AD8197 has
eight user-programmable I2C slave addresses to allow multiple
2
RESET
AD8197s to be controlled by a single I C bus. A
pin is
provided to restore the control registers of the AD8197 to
default values. In all cases, serial programming values override
any prior parallel programming values and any use of the serial
control interface disables the parallel control interface until the
AD8197 is reset.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two 50 Ω on-chip resistors
(see Figure 26). This termination is user-selectable; it can be
turned on or off by programming the TX_PTO bit of the
transmitter settings register through the serial control interface,
or by setting the PP_OTO pin of the parallel control interface.
When using the serial control interface, all three switching
modes (quad, dual, and single) are accessible and the high speed
channel switching mode is controlled independently of the
auxiliary signal switching mode. When using the parallel
control interface, only the quad switching mode is accessible,
and the same channel select bus (PP_CH[1:0]) simultaneously
switches both the high speed channels and the auxiliary signals.
The output termination resistors of the AD8197 back-terminate
the output TMDS transmission lines. These back-terminations,
as recommended in the HDMI 1.3 specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the AD8197 TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms
following a source switch. The user can program which of the
16 high speed input channels employs this feature by selectively
programming the associated RX_PT bits in the input
The AD8197 output has a disable feature that places the outputs
in a tristate mode. This mode is enabled by programming the
HS_EN bit of the high speed device modes register through the
serial control interface or by setting the PP_EN pin of the
termination pulse register through the serial control interface.
Additionally, all the input terminations can be disconnected by
PrA | Page 13 of 32
AD8197
Preliminary Technical Data
parallel control interface. Larger wire-OR’ed arrays can be
constructed using the AD8197 in this mode.
interfaces. When using the serial control interface, the user
selects which TMDS link is routed to the output by
programming the HS_CH bits of the high speed device modes
register in accordance with the switch mapping listed in Table 8.
When using the parallel control interface, the user selects which
TMDS link is routed to the output by setting the PP_CH bus of
the parallel control interface in accordance with the switch
mapping listed in Table 26.
VTTO
50Ω
50Ω
OPx
ONx
Dual Switching Mode
DISABLE
AVEE
I
OUT
In this mode, the AD8197 behaves as a locked dual [8:1] TMDS
channel switch. The two 8:1 switches share the channel select
input and, therefore, switch together. The user selects which two
out of the eight possible input groups are routed to output by
programming the HS_CH bits of the high speed device modes
register in accordance with the switch mapping listed in Table 9.
This mode is only accessible through the serial control interface.
Figure 26. High Speed Output Simplified Schematic
The AD8197 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8197 are
enabled by programming the TX_PTO bit of the transmitter
settings register or by setting the PP_OTO pin of the parallel
control interface. The internal terminations of the AD8197
default to the setting indicated by PP_OTO upon reset. External
terminations can be provided either by on-board resistors or by
the input termination resistors of an HDMI/DVI receiver. If
both the internal terminations are enabled and external termi-
nations are present, set the output current level to 20 mA by
programming the TX_OCL bit of the transmitter settings
register through the serial control interface or by setting the
PP_OCL pin of the parallel control interface. The output
current level defaults to the level indicated by PP_OCL upon
reset. If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the transmitter settings
register or by setting the PP_OCL pin of the parallel control
interface. The high speed outputs must be disabled if there are
no output termination resistors present in the system.
Single Switching Mode
In this mode, the AD8197 behaves as a single 16:1 TMDS
channel multiplexer; one of the 16 input channels is routed to
all of the outputs. The user selects which input channel is
routed to the outputs by programming the HS_CH bits in the
high speed device modes register in accordance with the switch
mapping listed in Table 10. This mode is only accessible
through the serial control interface.
AUXILIARY SWITCH
The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
standard speed I2C. The schematic equivalent for this passive
connection is shown in Figure 27.
R
AUX
AUX_A0
½C
AUX_COM0
½C
AUX
AUX
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register through the serial control interface,
or by setting the PP_PE bus of the parallel control interface. No
specific cable length is suggested for a particular pre-emphasis
setting because cable performance varies widely between
manufacturers.
Figure 27. Auxiliary Channel Simplified Schematic,
AUX_A0 to AUX_COM0 Routing Example
When turning off the AD8197, care needs to be taken with
the AMUXVCC supply to ensure that the auxiliary multiplexer
pins remain in a high impedance state. A scenario that illustrates
this requirement is one where the auxiliary multiplexer is used
to switch the display data channel (DDC) bus. In some applica-
tions, additional devices can be connected to the DDC bus
(such as an EEPROM with EDID information) upstream of the
AD8197. Extended display identification data (EDID) is a VESA
standard-defined data format for conveying display configuration
information to sources to optimize display use. EDID devices
may need to be available via the DDC bus, regardless of the
state of the AD8197 and any downstream circuit. For this
configuration, the auxiliary inputs of the powered down
AD8197 need to be in a high impedance state to avoid pulling
down on the DDC lines and preventing these other devices
from using the bus.
HIGH SPEED (TMDS) SWITCHING MODES
The AD8197 has three high speed switching modes: quad, dual,
and single. These are selected by programming the HS_SM bits
of the high speed device modes register through the serial
control interface.
Quad Switching Mode
This is the default mode. In quad mode, the AD8197 behaves
like a 4:1 HDMI/DVI link multiplexer routing groups of four
TMDS input channels to the four-channel output. This mode is
accessible through both the serial and the parallel control
PrA| Page 14 of 32
Preliminary Data Sheet
AD8197
When the AD8197 is powered from a simple resistor network,
as shown in Figure 28, it uses the 5 V supply that is required
from any HDMI/DVI source to guarantee high impedance of
the auxiliary multiplexer pins. The AMUXVCC supply does not
draw any static current; therefore, it is recommended that the
resistor network tap the 5 V supplies as close to the connectors
as possible to avoid any additional voltage drop.
Quad Switching Mode
This is the default mode. In quad mode, the AD8197 behaves
like a 4:1 auxiliary link multiplexer, routing groups of four
auxiliary input signals to the four-signal output. The user can
select which group of inputs is routed to the output by program-
ming the AUX_CH bits of the auxiliary device modes register
through the serial control interface in accordance with the
switch mapping listed in Table 13. Alternately, the user can
select which group of inputs is routed to the output by setting
the PP_CH bus of the parallel control interface in accordance
with the switch mapping listed in Table 27.
This precaution does not need to be taken if the DDC
peripheral circuitry is connected to the bus downstream of
the AD8197.
Dual Switching Mode
In this mode, the AD8197 behaves as a locked dual [8:1]
auxiliary signal switch. The two 8:1 switches share the channel
select input and, therefore, switch together. The user selects
which two out of the eight possible input groups are routed to
the output by programming the AUX_CH bits of the auxiliary
device modes register in accordance with the switch mapping
listed in Table 14. This mode is only accessible through the
serial control interface.
Figure 28. Suggested AMUXVCC Power Scheme
Single Switching Mode
AUXILIARY (LOW SPEED) SWITCHING MODES
In this mode the AD8197 behaves as a single 16:1 TMDS
channel multiplexer; a single channel, out of a possible 16, is
routed to all of the outputs. The user selects which input
channel is routed to the outputs by programming the AUX_CH
bits of the auxiliary device modes register in accordance with
the switch mapping listed in Table 15. This mode is only
accessible through the serial control interface.
The AD8197 has three auxiliary switching modes: quad, dual,
and single. These are selected by programming the AUX_SM
bits of the auxiliary device modes register through the serial
control interface. The auxiliary switching mode is independent
of the high speed switching mode whenever the part is
controlled through the serial control interface. When the part is
controlled through the parallel control interface, however, only
quad mode is accessible and the auxiliary switching mode
cannot be independently controlled.
PrA | Page 15 of 32
AD8197
Preliminary Technical Data
SERIAL CONTROL INTERFACE
RESET
4. Wait for the AD8197 to acknowledge the request.
On initial power-up, or at any point in operation, the AD8197
register set can be restored to preprogrammed default values by
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
RESET
pulling the
pin to low in accordance with the specifica-
RESET
6. Wait for the AD8197 to acknowledge the request.
tions in Table 1. During normal operation, however, the
pin must be pulled up to 3.3 V. Following a reset, the prepro-
grammed default values of the AD8197 register set correspond
to the state of the parallel interface configuration registers, as
listed in Table 24. The AD8197 can be controlled through the
parallel control interface until the first serial control event
occurs. As soon as any serial control event occurs, the serial
programming values, corresponding to the state of the serial
interface configuration registers (Table 5), override any prior
parallel programming values, and the parallel control interface
is disabled until the part is subsequently reset.
7. Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
8. Wait for the AD8197 to acknowledge the request.
9. Perform one of the following:
9a. Send a stop condition (while holding the I2C_SCL
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).
WRITE PROCEDURE
To write data to the AD8197 register set, an I2C master (such as
a microcontroller) needs to send the appropriate control signals
to the AD8197 slave device. The signals are controlled by the
I2C master, unless otherwise specified. For a diagram of the
procedure, see Figure 29. The steps for a write procedure are as
follows:
9b. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.
9c. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.
1. Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
2. Send the AD8197 part address (seven bits). The upper four
bits of the AD8197 part address are the static value [1001]
and the three LSBs are set by Input Pin I2C_ADDR2, Input
Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This
transfer should be MSB first.
9d. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.
3. Send the write indicator bit (0).
*
I2C_SCL
R/W
GENERAL CASE
I2C_SDA
FIXED PART
ADDR
START
ADDR
REGISTER ADDR
DATA
STOP
ACK
ACK
ACK
EXAMPLE
I2C_SDA
1
2
3
4
5
6
7
8
9
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE
LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
Figure 29. I2C Write Diagram
PrA| Page 16 of 32
Preliminary Data Sheet
AD8197
I2C_SCL
R/W
R/W
GENERAL CASE
I2C_SDA
FIXED PART
ADDR
FIXED PART
ADDR
START
ADDR
REGISTER ADDR
SR
ADDR
DATA
STOP
ACK
ACK
ACK
ACK
EXAMPLE
I2C_SDA
1
2
3
4
5
6
7
8
9
10 11
12
13
Figure 30. I2C Read Diagram
13b. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the write procedure (previous
Write Procedure section) to perform a write.
READ PROCEDURE
To read data from the AD8197 register set, an I2C master (such
as a microcontroller) needs to send the appropriate control
signals to the AD8197 slave device. The signals are controlled
by the I2C master, unless otherwise specified. For a diagram of
the procedure, see Figure 30. The steps for a read procedure are
as follows:
13c. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.
1. Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
13d. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of this procedure to perform a
read from the same address.
2. Send the AD8197 part address (seven bits). The upper four
bits of the AD8197 part address are the static value [1001]
and the three LSBs are set by Input Pin I2C_ADDR2, Input
Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This
transfer should be MSB first.
SWITCHING/UPDATE DELAY
There is a delay between when a user writes to the configura-
tion registers of the AD8197 and when that state change takes
physical effect. This update delay occurs regardless of whether
the user programs the AD8197 via the serial or the parallel
control interface. When using the serial control interface, the
update delay begins at the falling edge of I2C_SCL for the last
data bit transferred, as shown in Figure 29. When using the
parallel control interface, the update delay begins at the
transition edge of the relevant parallel interface pin. This update
delay is register specific and the times are specified in Table 1.
3. Send the write indicator bit (0).
4. Wait for the AD8197 to acknowledge the request.
5. Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
6. Wait for the AD8197 to acknowledge the request.
7. Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
8. Resend the AD8197 part address (seven bits) from Step 2.
The upper four bits of the AD8197 part address are the
static value [1001] and the three LSBs are set by the Input
Pin I2C_ADDR2, I2C_ADDR1 and Input Pin I2C_ADDR0
(LSB). This transfer should be MSB first.
During a delay window, new values can be written to the
configuration registers but the AD8197 does not physically
update until the end of that register’s delay window. Writing
new values during the delay window does not reset the window;
new values supersede the previously written values. At the end
of the delay window, the AD8197 physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8197 immediately updates and a new
delay window begins.
9. Send the read indicator bit (1).
10. Wait for the AD8197 to acknowledge the request.
11. The AD8197 serially transfers the data (eight bits) held in
the register indicated by the address set in Step 5. This data
is sent MSB first.
12. Acknowledge the data from the AD8197.
13. Perform one of the following:
13a. Send a stop condition (while holding the I2C_SCL
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in Figure 30).
PrA | Page 17 of 32
AD8197
Preliminary Technical Data
PARALLEL CONTROL INTERFACE
The AD8197 can be controlled through the parallel interface
using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO,
and PP_OCL pins. Logic levels for the parallel interface pins
are set in accordance with the specifications listed in Table 1.
Setting these pins updates the parallel control interface
registers, as listed in Table 24. Following a reset, the AD8197
can be controlled through the parallel control interface until the
first serial control event occurs. As soon as any serial control
event occurs, the serial programming values override any prior
parallel programming values, and the parallel control interface
is disabled until the part is subsequently reset. The default serial
programming values correspond to the state of the serial
interface configuration registers, as listed in Table 5.
PrA| Page 18 of 32
Preliminary Data Sheet
AD8197
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I2C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
The least significant bits of the AD8197 I2C part address are set by tying the Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to
3.3 V (Logic 1) or 0 V (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197
is reset as described in the Serial Control Interface section.
Table 5. Serial (I2C) Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr. Default
High Speed
Device
Modes
High
High speed switching
mode select
High speed source select
0x00
0x40
speed
switch
enable
HS_EN
HS_SM[1]
HS_SM[0]
HS_CH[3]
HS_CH[2]
HS_CH[1]
HS_CH[0]
Auxiliary
Device
Modes
Auxiliary
switch
enable
Auxiliary switching
mode select
Auxiliary switch source select
0x01
0x10
0x40
0x01
AUX_EN
AUX_SM[1] AUX_SM[0] AUX_CH[3] AUX_CH[2] AUX_CH[1]
AUX_CH[0]
Receiver
Settings
High speed
input
termination
select
RX_TO
Input
Termination
Pulse 1
Source A and Source B : input termination pulse-on-source switch select
(disconnect termination for a short period of time)
0x11
0x12
0x00
0x00
RX_PT[7] RX_PT[6]
RX_PT[5]
RX_PT[4]
RX_PT[3]
RX_PT[2]
RX_PT[1]
RX_PT [0]
Input
Termination
Source C and Source D: input termination pulse-on-source switch select
(disconnect termination for a short period of time)
Pulse 2
RX_PT[15] RX_PT[14]
RX_PT[13]
Source A and Source B: input equalization level select
RX_EQ[5] RX_EQ[4] RX_EQ[3] RX_EQ[2]
Source C and Source D: input equalization level select
RX_EQ[15] RX_EQ[14] RX_EQ[13] RX_EQ[12] RX_EQ[11] RX_EQ[10]
High speed output
RX_PT[12]
RX_PT[11]
RX_PT[10]
RX_PT[9]
RX_PT[8]
RX_EQ[0]
RX_EQ[8]
Receive
Equalizer 1
0x13
0x14
0x20
0x00
0x00
0x03
RX_EQ[7] RX_EQ[6]
RX_EQ[1]
Receive
Equalizer 2
RX_EQ[9]
Transmitter
Settings
High speed
High speed
output
current level
pre-emphasis level select output
termination
select
select
TX_PE[1]
TX_PE[0]
TX_PTO
TX_OCL
HS_CH[3:0]: High Speed (TMDS) Switch Source Select Bus
HIGH SPEED DEVICE MODES REGISTER
Table 8. Quad Mode, 4× [4:1], High Speed Switch Mapping
HS_EN: High Speed (TMDS) Channels Enable Bit
HS_CH[3:0] O[3:0] Description
Table 6. HS_EN Description
XX00
XX01
XX10
XX11
A[3:0]
B[3:0]
C[3:0]
D[3:0]
High Speed Source A switched to
output
High Speed Source B switched to
output
High Speed Source C switched to
output
High Speed Source D switched to
output
HS_EN Description
0
1
High speed channels off, low power/standby mode
High speed channels on
HS_SM[1:0]: High Speed (TMDS) Switching Mode
Select Bus
Table 7. HS_SM Description
HS_SM[1:0]
Description
00
01
10
11
Quad mode, 4× [4:1]
Dual mode, 2× [8:1]
Single mode, 1× [16:1]
Illegal value; previous value of HS_SM[1:0]
retained
PrA | Page 19 of 32
AD8197
Preliminary Technical Data
Table 9. Dual Mode, 2× [8:1], High Speed Switch Mapping
HS_CH[3:0] O[3:2] O[1:0] Description
AUXILIARY DEVICE MODES REGISTER
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
X000
X001
X010
X011
X100
X101
X110
X111
A1
A3
B1
B3
C1
C3
D1
D3
A0
A2
B0
B2
C0
C2
D0
D2
The A0 and A1 high speed
channels switched to output
The A2 and A3 high speed
channels switched to output
The B0 and B1 high speed
channels switched to output
The B2 and B3 high speed
channels switched to output
The C0 and C1 high speed
channels switched to output
The C2 and C3 high speed
channels switched to output
Table 11. AUX_EN Description
AUX_EN
Description
0
Auxiliary switch off, no low speed input/output
to low speed common input/output
connection
1
Auxiliary switch on
AUX_SM[1:0]: Auxiliary (Low Speed) Switching Mode
Select Bus
Table 12. AUX_SM[1:0] Description
AUX_SM[1:0] Description
The D0 and D1 high speed
channels switched to output
The D2 and D3 high speed
channels switched to output
00
01
10
11
Quad Mode, 4× [4:1]
Dual Mode, 2× [8:1]
Single Mode, 1× [6:1]
Illegal value; previous value of AUX_SM[1:0]
retained
Table 10. Single Mode, 1× [16:1], High Speed Switch
Mapping
HS_CH[3:0] O[3:0] Description
AUX_CH[3:0]: Auxiliary (Low Speed) Switch Source
Select Bus
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A0
A1
A2
A3
B0
B1
B2
B3
C0
C1
C2
C3
D0
D1
D2
D3
High Speed Channel A0 switched to
output
High Speed Channel A1 switched to
output
High Speed Channel A2 switched to
output
High Speed Channel A3 switched to
output
High Speed Channel B0 switched to
output
High Speed Channel B1 switched to
output
High Speed Channel B2 switched to
output
High Speed Channel B3 switched to
output
High Speed Channel C0 switched to
output
High Speed Channel C1 switched to
output
High Speed Channel C2 switched to
output
High Speed Channel C3 switched to
output
High Speed Channel D0 switched to
output
High Speed Channel D1 switched to
output
High Speed Channel D2 switched to
output
High Speed Channel D3 switched to
output
Table 13. Quad Mode, 4× [4:1], Auxiliary Switch Mapping
AUX_CH[3:0] AUX_COM[3:0] Description
XX00
XX01
XX10
XX11
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
AUX_D[3:0]
Auxiliary Source A switched
to output
Auxiliary Source B switched
to output
Auxiliary Source C switched
to output
Auxiliary Source D switched
to output
PrA| Page 20 of 32
Preliminary Data Sheet
AD8197
Table 14. Dual Mode, 2× [8:1], Auxiliary Switch Mapping
Table 15. Single Mode, 1× [16:1], Auxiliary Switch Mapping
AUX_CH[3:0] AUX_COM[3:2] AUX_COM[1:0] Description
AUX_CH[3:0] AUX_COM[3:0] Description
X000
X001
X010
X011
X100
X101
X110
X111
AUX_C0
AUX_C1
AUX_C2
AUX_C3
AUX_D0
AUX_D1
AUX_D2
AUX_D3
AUX_A0
AUX_A1
AUX_A2
AUX_A3
AUX_B0
AUX_B1
AUX_B2
AUX_B3
The A0 and
C0 auxiliary
channels
switched to
output
The A1 and
C1 auxiliary
channels
switched to
output
The A2 and
C2 auxiliary
channels
switched to
output
The A3 and
C3 auxiliary
channels
switched to
output
The B0 and
D0 auxiliary
channels
switched to
output
The B1 and
D1 auxiliary
channels
switched to
output
The B2 and
D2 auxiliary
channels
switched to
output
The B3 and
D3 auxiliary
channels
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AUX_A0
AUX_A1
AUX_A2
AUX_A3
AUX_B0
AUX_B1
AUX_B2
AUX_B3
AUX_C0
AUX_C1
AUX_C2
AUX_C3
AUX_D0
AUX_D1
AUX_D2
AUX_D3
Auxiliary Channel A0
switched to output
Auxiliary Channel A1
switched to output
Auxiliary Channel A2
switched to output
Auxiliary Channel A3
switched to output
Auxiliary Channel B0
switched to output
Auxiliary Channel B1
switched to output
Auxiliary Channel B2
switched to output
Auxiliary Channel B3
switched to output
Auxiliary Channel C0
switched to output
Auxiliary Channel C1
switched to output
Auxiliary Channel C2
switched to output
Auxiliary Channel C3
switched to output
Auxiliary Channel D0
switched to output
Auxiliary Channel D1
switched to output
Auxiliary Channel D2
switched to output
Auxiliary Channel D3
switched to output
switched to
output
PrA | Page 21 of 32
AD8197
Preliminary Technical Data
RECEIVER SETTINGS REGISTER
RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2
RX_TO: High Speed (TMDS) Channels Input Termination
On/Off Select Bit
RX_EQ[X]: High Speed (TMDS) Input X Equalization Level
Select Bit
Table 16. RX_TO Description
Table 19. RX_EQ[X] Description
RX_TO
Description
RX_EQ[X]
Description
0
1
Input termination off
0
1
Low equalization (6 dB)
High equalization (12 dB)
Input termination on (can be pulsed on and off
according to settings in the input termination
pulse register)
Table 20. RX_EQ[X] Mapping
RX_EQ[X]
Corresponding Input TMDS Channel
INPUT TERMINATION PULSE REGISTER 1 AND
REGISTER 2
RX_PT[X]: High Speed (TMDS) Input Channel X
Pulse-On-Source Switch Select Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
D0
Table 17. RX_PT[X] Description
RX_PT[X]
Description
0
Input termination for TMDS Channel X always
connected when source is switched
Bit 8
Bit 9
1
Input termination for TMDS Channel X
disconnected for 100 ms when source switched
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Table 18. RX_PT[X] Mapping
RX_PT[X]
Corresponding Input TMDS Channel
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
D0
TRANSMITTER SETTINGS REGISTER
TX_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (For All TMDS Channels)
Table 21. TX_PE[1:0] Description
TX_PE[1:0]
Bit 8
Bit 9
Description
00
01
10
11
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
TX_PTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All Channels)
Table 22. TX_PTO Description
TX_PTO
Description
0
1
Output termination off
Output termination on
TX_OCL:High Speed (TMDS) Output Current Level Select
Bit (For All Channels)
Table 23. TX_OCL Description
TX_OCL
Description
0
1
Output current set to 10 mA
Output current set to 20 mA
PrA| Page 22 of 32
Preliminary Data Sheet
AD8197
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and
PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface.
The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 24. Parallel Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Speed
High speed
High speed switching
High speed source select
Device Modes
switch enable mode select (quad)
PP_EN
0
0
0
0
0
0
PP_CH[1]
PP_CH[0]
Auxiliary Device
Modes
Auxiliary
Auxiliary switching
Auxiliary switch source select
switch enable mode select (quad)
1
0
0
PP_CH[1]
PP_CH[0]
Receiver
Settings
Input term. on/off
select (termination
always on)
1
Input
Source A and Source B input termination pulse-on-source switch select (termination always on)
Termination
Pulse 1
0
0
0
0
0
0
0
0
0
0
Input
Termination
Pulse 2
Source C and Source D input termination pulse-on-source switch select (termination always on)
0
0
0
0
0
0
Receive
Equalizer 1
Source A and Source B input equalization level select
PP_EQ PP_EQ PP_EQ PP_EQ
Source C and Source D input equalization level select
PP_EQ PP_EQ PP_EQ PP_EQ
Output pre-emphasis Output
level select termination
on/off select
PP_PE[1] PP_PE[0] PP_OTO
PP_EQ PP_EQ
PP_EQ PP_EQ
PP_EQ
PP_EQ
PP_EQ
PP_EQ
Receive
Equalizer 2
Transmitter
Settings
Output current level
select
PP_OCL
HIGH SPEED DEVICE MODES REGISTER
AUXILIARY DEVICE MODES REGISTER
The high speed (TMDS) switching mode is fixed to quad mode
when using the parallel interface.
The auxiliary (low speed) switch is always enabled and the
auxiliary switching mode is fixed to quad mode when using the
parallel interface.
PP_EN: High Speed (TMDS) Channels Enable Bit
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 25. PP_EN Description
Table 27. Quad Auxiliary Switch Mode Mapping
PP_EN Description
PP_CH[1:0] AUX_COM[3:0] Description
0
1
High speed channels off, low power/standby mode
High speed channels on
00
01
10
11
AUX_A[3:0]
AUX_B[3:0]0
AUX_C[3:0]
AUX_D[3:0]
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
Auxiliary Source C switched to
output
Auxiliary Source D switched to
output
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 26. Quad High speed Switch Mode Mapping
PP_CH[1:0] O[3:0] Description
00
01
10
11
A[3:0]
B[3:0]
C[3:0]
D[3:0]
High Speed Source A switched to
output
High Speed Source B switched to
output
High Speed Source C switched to
output
High Speed Source D switched to
output
PrA | Page 23 of 32
AD8197
Preliminary Technical Data
TRANSMITTER SETTINGS REGISTER
RECEIVER SETTINGS REGISTER
PP_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (For All TMDS Channels)
High speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
Table 29. PP_PE[1:0] Description
INPUT TERMINATION PULSE REGISTER 1 AND
REGISTER 2
PP_PE[1:0]
Description
00
01
10
11
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
High speed input (TMDS) channels pulse-on-source switching
fixed to off when using the parallel interface.
RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2
PP_EQ: High Speed (TMDS) Inputs Equalization Level
Select Bit (For All TMDS Input Channels)
PP_OTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All TMDS Channels)
The input equalization cannot be set individually (per channel)
when using the parallel interface; one equalization setting
affects all input channels.
Table 30. PP_OTO Description
PP_OTO
Description
0
1
Output termination off
Output termination on
Table 28. PP_EQ Description
PP_EQ
Description
PP_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All TMDS Channels)
0
1
Low equalization (6 dB)
High equalization (12 dB)
Table 31. TX_OCL Description
PP_OCL
Description
0
1
Output current set to 10 mA
Output current set to 20 mA
PrA| Page 24 of 32
Preliminary Data Sheet
AD8197
APPLICATION INFORMATION
Figure 31. Layout of the TMDS Traces on the AD8197 Evaluation Board (Only Top Signal Routing Layer is Shown)
and output pre-emphasis of the AD8197 is that the AD8197 can
compensate for the signal degradation of both input and output
cables; it acts to reopen a closed input data eye and transmit a
full-swing HDMI signal to an end receiver. More information
on the specific performance metrics of the AD8197 can be
found in the Typical Performance Characteristics section.
The AD8197 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs. It is in-
tended for use as a 4:1 switch in systems with long cable runs
on both the input and/or the output, and is fully HDMI 1.3
receive-compliant.
PINOUT
The AD8197 also provides a distinct advantage in receive-type
applications because it is a fully buffered HDMI/DVI switch.
Although inverting the output pin order of the AD8197 on the
PCB requires a designer to place vias in the high speed signal
path, the AD8197 fully buffers and electrically decouples the
outputs from the inputs. Consequently, the effects of the vias
placed on the output signal lines are not seen at the input of the
AD8197. The programmable output terminations also improve
signal quality at the output of the AD8197. Therefore, the PCB
designer has significantly improved flexibility in the placement
and routing of the output signal path with the AD8197 over
other solutions.
The AD8197 is designed for an HDMI/DVI receiver pinout
at its input and a transmitter pinout at its output. This makes
the AD8197 ideal for use in AVR-type applications where the
designer routes both the inputs and the outputs directly to
HDMI/DVI connectors. This type of layout is used on the
AD8197 evaluation board, as shown in Figure 31. When the
AD8197 is used in receiver type applications, it is necessary to
change the ordering of the output pins on the PCB to match up
with the on-board receiver.
One advantage of the AD8197 in an AVR-type application is
that all of the high speed signals can be routed on one side (the
topside) of the board, as shown in Figure 31. In addition to
12 dB of input equalization, the AD8197 provides up to 6 dB of
output pre-emphasis that boosts the output TMDS signals and
allows the AD8197 to precompensate when driving long PCB
traces or output cables. The net effect of the input equalization
CABLE LENGTHS AND EQUALIZATION
The AD8197 offers two levels of programmable equalization
for the high speed inputs: 6 dB and 12 dB. The equalizer of
the AD8197 supports video data rates of up to 2.25 Gbps. It can
equalize more than 20 meters of 24 AWG HDMI cable at 2.25
PrA | Page 25 of 32
AD8197
Preliminary Technical Data
Gbps, which corresponds to the video format, 1080p with deep
color.
speed, and transferred over a single-ended transmission line
that does not need to have controlled impedance. The primary
concern with laying out the auxiliary lines is ensuring that they
conform to the I2C bus standard and do not have excessive
capacitive loading.
The length of cable that can be used in a typical HDMI/DVI
application depends on a large number of factors, including:
•
Cable quality: the quality of the cable in terms of conductor
wire gauge and shielding. Thicker conductors have lower
signal degradation per unit length.
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
interleaved with the video data; the DVI standard does not
incorporate audio information. The fourth high speed differ-
ential pair is used for the AV data-word clock, and runs at
one-tenth the speed of the TMDS data channels.
•
•
Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.
Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.
•
Receiver sensitivity: the sensitivity of the terminating
receiver.
The four high speed channels of the AD8197 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetrical;
therefore, the p and n of a given differential pair are inter-
changeable, provided the inversion is consistent across all inputs
and outputs of the AD8197. However, the routing between
inputs and outputs through the AD8197 is fixed. For example,
in quad mode, Output Channel 0 always switches between
Input A0, Input B0, Input C0, Input D0, and so forth.
As such, specific cable types and lengths are not recommended
for use with a particular equalizer setting. In nearly all applica-
tions, the AD8197 equalization level can be set to high, or 12 dB,
for all input cable configurations at all data rates, without
degrading the signal integrity.
PCB LAYOUT GUIDELINES
The AD8197 is used to switch two distinctly different types of
signals, both of which are required for HDMI and DVI video.
These signal groups require different treatment when laying out
a PC board.
The AD8197 buffers the TMDS signals and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces are more sensitive to the PCB layout. Regardless of the
data being carried on a specific TMDS channel, or whether the
TMDS line is at the input or the output of the AD8197, all four
high speed signals should be routed on a PCB in accordance
with the same RF layout guidelines.
The first group of signals carries the audiovisual (AV) data.
HDMI/DVI video signals are differential, unidirectional, and
high speed (up to 2.25 Gbps). The channels that carry the video
data must be controlled impedance, terminated at the receiver,
and capable of operating at the maximum specified system data
rate. It is especially important to note that the differential traces
that carry the TMDS signals should be designed with a
controlled differential impedance of 100 Ω. The AD8197
provides single-ended, 50 Ω terminations on-chip for both its
inputs and outputs, and both the input and output terminations
can be enabled or disabled through the serial interface.
Transmitter termination is not required by the HDMI 1.3 standard
but its inclusion improves the overall system signal integrity.
Layout for the TMDS Signals
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. In some applications, such
as using multiple AD8197s to construct large input arrays, the use
of interlayer vias becomes unavoidable. In these situations, the
input termination feature of the AD8197 improves system signal
The audiovisual (AV) data carried on these high speed channels
are encoded by a technique called transmission minimized
differential signaling (TMDS) and in the case of HDMI, is also
encrypted according to the high bandwidth digital copy
protection (HDCP) standard.
The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I2C bus used to send EDID information
and HDCP encryption keys between the source and the sink),
the consumer electronics control (CEC) line, and the hot plug
detect (HPD) line. These auxiliary signals are bidirectional, low
PrA| Page 26 of 32
Preliminary Data Sheet
AD8197
integrity by absorbing reflections. Take care to use vias minimally
and to place vias symmetrically for each side of a given differential
pair. Furthermore, to prevent unwanted signal coupling and
interference, route the TMDS signals away from other signals
and noise sources on the PCB.
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 Ω differential impedance. When the traces
split apart, to go into a connector, for example, and are no
longer so strongly coupled, the width of the traces should be
increased to yield a differential impedance of 100 Ω in the new
configuration.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together to establish the required 100 Ω differ-
ential impedance. Enough space should be left between the
differential pairs of a given group so that the n of one pair does
not couple to the p of another pair. For example, one technique is
to make the interpair distance 4 to 10 times wider than the
intrapair spacing.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8197. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing
differential pairs on multiple layers, it is necessary to also re-
route the corresponding reference plane in order to provide one
continuous ground current return path for the differential
signals. An example of this is illustrated in Figure 32.
Any group of four TMDS channels (Input A, Input B, Input C,
Input D, or the output) should have closely matched trace
lengths to minimize interpair skew. Severe interpair skew can
cause the data on the four different channels of a group to arrive
out of alignment with one another. A good practice is to match
the trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
Minimizing intra- and interpair skew becomes increasingly
important as data rates increase. Any introduced error will
constitute a correspondingly larger fraction of a bit period at
higher data rates.
While the AD8197 features input equalization and output pre-
emphasis, the length of the TMDS traces should be minimized
to reduce overall signal degradation. Commonly used PC board
material, such as FR4, is lossy at high frequencies; therefore,
long traces on the circuit board increase signal attenuation
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
Figure 32. Example Routing of Reference Plane
TMDS Terminations
The AD8197 provides internal, 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on
a number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. It is generally required to work with the PC board
fabricator to obtain a set of parameters to produce the desired
results.
The output termination resistors of the AD8197 back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8197
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
PrA | Page 27 of 32
AD8197
Preliminary Technical Data
3W
W
3W
These four signals can be switched through the auxiliary bus of
the AD8197 and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
SILKSCREEN
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8197 is being used.
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8197, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
Figure 33. Example Board Stackup
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
When the AD8197 is powered up, one set of the auxiliary in-
puts is passively routed to the outputs. In this state, the AD8197
looks like a 100 Ω resistor between the selected auxiliary inputs
and the corresponding outputs as illustrated in Figure 27. The
AD8197 does not buffer the auxiliary signals, therefore, the
input traces, output traces, and the connection through the
AD8197 all must be considered when designing a PCB to meet
HDMI/DVI specifications. The unselected auxiliary inputs of the
AD8197 are placed into a high impedance mode when the device
is powered up. To ensure that all of the auxiliary inputs of the
AD8197 are in a high impedance mode when the device is powered
off, it is necessary to power the AMUXVCC supply as illustrated
in Figure 28.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stack-up, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stackup is shown in Figure 33.
In contrast to the auxiliary signals, the AD8197 buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
PrA| Page 28 of 32
Preliminary Data Sheet
AD8197
RECOMMENDED
Power Supplies
The AD8197 has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
•
•
•
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
EXTRA ADDED INDUCTANCE
•
•
DVCC/DVEE
NOT RECOMMENDED
AMUXVCC/DVEE
Figure 34. Recommended Pad Outline for Bypass Capacitors
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8197. The VTTI/AVEE supply (3.3 V)
powers the input termination (see Figure 25). Similarly, the
VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I2C, then AMUXVCC should be
connected to +5 V relative to DVEE.
In applications where the AD8197 is powered by a single 3.3 V
supply, it is recommended to use two reference supply planes
and bypass the 3.3 V reference plane to the ground reference
plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF
capacitors. The capacitors should via down directly to the
supply planes and be placed within a few centimeters of the
AD8197. The AMUXVCC supply does not require additional
bypassing. This bypassing scheme is illustrated in Figure 35.
In a typical application, all pins labeled AVEE or DVEE should
be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC tied to 5 V. The supplies can also be powered
individually, but care must be taken to ensure that each stage of
the AD8197 is powered correctly.
Power Supply Bypassing
The AD8197 requires minimal supply bypassing. When
powering the supplies individually, place a 0.01 μF capacitor
between each 3.3 V supply pin (AVCC, DVCC, VTTI, and
VTTO) and ground to filter out supply noise. Generally, bypass
capacitors should be placed near the power pins and should
connect directly to the relevant supplies (without long inter-
vening traces). For example, to improve the parasitic inductance
of the power supply decoupling capacitors, minimize the trace
length between capacitor landing pads and the vias as shown in
Figure 34.
Figure 35. Example Placement of Power Supply Decoupling Capacitors
Around the AD8197
PrA | Page 29 of 32
AD8197
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
51
50
0.15
0.05
26
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 36. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ST-100
ST-100
Ordering Quantity
AD8197ASTZ1
AD8197ASTZ-RL1
AD8197-EVAL
−40°C to +85°C
−40°C to +85°C
100-Lead Low Profile Quad Flat Package [LQFP]
100-Lead Low Profile Quad Flat Package [LQFP], Reel
Evaluation Kit
1,000
1 Z = Pb-free part.
Rev. J | Page 30 of 32
Preliminary Data Sheet
NOTES
AD8197
PrA | Page 31 of 32
AD8197
NOTES
Preliminary Technical Data
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06471-0-12/06(PrA)
PrA| Page 32 of 32
相关型号：
AD8197BASTZ
SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, ROHS COMPLIANT, MS-026BED, LQFP-100
ROCHESTER
AD8197BASTZ-RL
SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, ROHS COMPLIANT, MS-026BED, LQFP-100
ROCHESTER
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