AD8200YR-REEL7 [ADI]
OP-AMP, 1000uV OFFSET-MAX, PDSO8, PLASTIC, SOIC-8;
| 型号： | AD8200YR-REEL7 |
| 厂家： | 
ADI |
| 描述： | OP-AMP, 1000uV OFFSET-MAX, PDSO8, PLASTIC, SOIC-8 放大器 光电二极管 |
| 文件： | 总12页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage, Single-Supply
Difference Amplifier
a
AD8200
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High Common-Mode Voltage Range –2 V to +24 V
at a 5 V Supply Voltage
Operating Temperature Range
Die: –40ꢀC to +150ꢀC
SOIC (R) Package
DIE Form
NC
A1
A2
+V
S
8-Lead SOIC: –40ꢀC to +125ꢀC
Supply Voltage Range: 4.7 V to 12 V
Low-Pass Filter (One Pole or Two Pole)
AD8200
100kꢃ
G = X10
+IN
A1
–IN
G = X2
+IN
A2
–IN
EXCELLENT AC AND DC PERFORMANCE
ꢁ6 ꢂV/ꢀC Typ Offset Drift
ꢁ10 ppm/ꢀC Typ Gain Drift
+IN
–IN
OUT
80 dB CMRR Min DC to 10 kHz
10kꢃ
200kꢃ
200kꢃ
PLATFORMS
10kꢃ
Transmission Control
Diesel Injection Control
Engine Management
Adaptive Suspension Control
Vehicle Dynamics Control
NC = NO CONNECT
GND
GENERAL DESCRIPTION
Automotive platforms demand precision components for better
system control. The AD8200 provides excellent ac and dc per-
formance that keeps errors to a minimum in the user’s system.
Typical offset and gain drift in the SOIC package are 6 µV/°C
and 10 ppm/°C, respectively. The device also delivers a mini-
mum CMRR of 80 dB from dc to 10 kHz.
The AD8200 is a single-supply difference amplifier for amplifying
and low-pass filtering small differential voltages in the presence
of a large common-mode voltage. The input CMV range extends
from –2 V to +24 V at a typical supply voltage of 5 V.
The AD8200 is offered in die and packaged form. Both package
options are specified over wide temperature ranges, making the
AD8200 well suited for use in many automotive platforms. The
SOIC package is specified over a temperature range of –40°C to
+125°C. The die is specified from –40°C to +150°C.
The AD8200 features an externally accessible 100 kΩ resistor at
the output of the preamp A1, which can be used for low-pass
filter applications and for establishing gains other than 20.
POWER
DEVICE
INDUCTIVE
LOAD
5V
5V
CLAMP
DIODE
OUTPUT
OUTPUT
BATTERY
14V
+IN NC +V OUT
S
+IN NC +V OUT
S
BATTERY
14V
4 TERM
SHUNT
4 TERM
SHUNT
AD8200
AD8200
–IN GND A1 A2
–IN GND A1 A2
POWER
DEVICE
CLAMP
DIODE
INDUCTIVE
LOAD
COMMON
NC = NO CONNECT
COMMON
NC = NO CONNECT
Figure 1. High-Line Current Sensor
Figure 2. Low-Line Current Sensor
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD8200–SPECIFICATIONS
SINGLE SUPPLY
(TA = 25ꢀC, VS = 5 V, VCM = 0 V, RL = 10 kꢃ, Pin 5 to ground, unless otherwise noted.)
AD8200 SOIC
AD8200 DIE
Parameter
Condition
Min
Typ
Max
Min
Typ
Max
Unit
SYSTEM GAIN
Initial
Error
20
–1
20
–1
VO ≥ 0.1 V dc
VCM = 0.15 V
+1
20
+1
30
%
ppm/°C
vs. Temperature
10
6
25
12
OFFSET VOLTAGE
Offset Voltage (RTI)
vs. Temperature
–1
+1
15
–1
+1
25
mV
µV/°C
INPUT
Input Impedance
Differential
Common-Mode
320
160
–2
400
200
480
240
+24
320
160
–2
400
200
480
240
+24
kΩ
kΩ
V
CMV
Continuous
VCM = 10 V
f = 1 kHz
Common-Mode Rejection1
80
80
80
80
dB
dB
f = 10 kHz2
PREAMPLIFIER
Gain
10
10
Gain Error
Output Voltage Range
Output Resistance
–1
0.02
97
+1
4.8
103
–1
0.02
97
+1
4.8
103
%
V
kΩ
100
2
100
2
OUTPUT BUFFER
Gain
Gain Error
Output Voltage Range
Output Resistance
–1
0.02
+1
4.8
–1
0.02
+1
4.8
%
V
Ω
2
2
DYNAMIC RESPONSE
3 dB Bandwidth
Slew Rate
30
50
0.22
30
50
0.22
kHz
V/µs
NOISE
0.1 Hz to 10 Hz
Spectral Density, 1 kHz, RTI
10
300
10
300
µV p-p
nV/√Hz
POWER SUPPLY
Operating Range
Quiescent Current vs.
Temperature
4.7
12
1
4.7
12
1
V
mA
VO = 0.1 V dc
0.25
80
0.25
80
PSRR
VS = 4.7 V to 12 V
75
75
dB
TEMPERATURE RANGE
For Specified Performance
–40
+125
–40
+150
°C
NOTES
1Source Imbalance < 2 Ω.
2The AD8200 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 k Ω resistor, even the small amounts of pin-
to-pin capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-to-
pin coupling may be neglected in all applications using filter capacitors at Node 3.
Specifications subject to change without notice.
–2–
REV. A
AD8200
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 V
Transient Input Voltage (300 ms) . . . . . . . . . . . . . . . . . . 44 V
Continuous Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Reversed Supply Voltage Protection . . . . . . . . . . . . . . . 0.3 V
Operating Temperature . . . . . . . . . . . (Die) –40°C to +150°C
. . . . . . . . . (SOIC) –40°C to +125°C
1
2
3
4
8
7
6
5
+IN
NC
+V
–IN
AD8200
TOP VIEW
(Not to Scale)
GND
A1
A2
S
OUT
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
NC = NO CONNECT
*Stresses beyond those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; the functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Range Package Description Package Option
Model
AD8200YR
AD8200YR-Reel
AD8200YR-Reel-7 –40°C to +125°C
AD8200YCHIPS
–40°C to +125°C
–40°C to +125°C
Plastic SOIC
Plastic SOIC
Plastic SOIC
N/A
SO-8
SO-8
SO-8
DIE Form
DIE Form
–40°C to +150°C
AD8200YCSURF –40°C to +150°C
N/A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8200 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
METALLIZATION PHOTOGRAPH
+V
S
6
5
OUT
+IN
8
–IN
1
4
A2
2
3
GND
A1
REV. A
–3–
AD8200–Typical Performance Characteristics
(TA = 25ꢀC, VS = 5 V, VCM = 0 V, RL = 10 kꢃ, unless otherwise noted.)
30
25
20
15
10
5
0
30
25
20
15
10
5
–2
–4
–6
–8
–10
–12
+V
CM
0
–V
CM
–5
–10
–15
–20
0
1k
10k
100k
1M
2
3
4
5
SUPPLY VOLTAGE – V
FREQUENCY – Hz
TPC 1. Input Common-Mode Range vs. Supply
TPC 4. Gain vs. Frequency
100
95
90
85
80
75
70
65
60
55
50
0
–5
R
=
L
–10
–15
–20
–25
R
= 10kꢃ TO GND
L
–30
–35
2
10
100
1k
10k
100k
1M
3
4
5
SUPPLY VOLTAGE – V
FREQUENCY – Hz
TPC 2. Output Voltage – VS vs. Supply
TPC 5. Common-Mode Rejection vs. Frequency
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
10
100
1k
10k
FREQUENCY – Hz
LOAD RESISTANCE – ꢃ
TPC 3. Output Voltage Swing vs. Load Resistance
TPC 6. Power Supply Rejection vs. Frequency
–4–
REV. A
AD8200
TEK RUN: 2.5MS/s HI RES
TEK RUN: 2.5MS/s AVERAGE
V
, R = 10kꢃ
OUT
L
1
V
, R = 10kꢃ
OUT
L
1
2
T
MAGNIFIED V
OUT
V
V
IN
3
2
IN
CH1 500mVꢃ CH2 50mVꢃ M 20ꢂs CH1 1.5V
CH1 1V
CH 2 10mV M 20ꢂs CH1 1.36V
CH3 100mV
TPC 7. Pulse Response
TPC 8. Settling Time
THEORY OF OPERATION
The AD8200 consists of a preamp and buffer arranged as shown
in Figure 3. Like-named resistors have equal values.
To minimize these errors while extending the common-mode
range, a dedicated feedback loop is employed to reduce the
range of common-mode voltage applied to A1, for a given over-
all range at the inputs. By offsetting the range of voltage applied
to the compensator, the input common-mode range is also offset
to include voltages more negative than the power supply. Ampli-
fier A3 detects the common-mode signal applied to A1 and
adjusts the voltage on the matched RCM resistors to reduce the
common-mode voltage range at the A1 inputs. By adjusting the
common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.
The preamp incorporates a dynamic bridge (subtractor) circuit.
Identical networks (within the shaded areas), consisting of RA,
RB, RC, and RG, attenuate input signals applied to Pins 1 and 8.
Note that when equal amplitude signals are asserted at inputs 1
and 8, and the output of A1 is equal to the common potential
(i.e., zero), the two attenuators form a balanced-bridge network.
When the bridge is balanced, the differential input voltage at A1
and thus its output will be zero.
Any common-mode voltage applied to both inputs will keep the
bridge balanced and the A1 output at zero. Because the resistor
networks are carefully matched, the common-mode signal rejec-
tion approaches this ideal state.
The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for low-
pass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio-trimmed for high accuracy.
However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive RB, by way of RG, to adjust the voltage at its inverting
input until it matches the voltage at its noninverting input.
The output of the preamp drives a gain-of-two buffer-amplifier
A2, implemented with carefully matched feedback resistors RF.
By attenuating voltages at Pins 1 and 8, the amplifier inputs are
held within the power supply range, even if Pin 1 and Pin 8 input
levels exceed the supply, or fall below common (ground.) The
input network also attenuates normal (differential) mode volt-
ages. RC and RG form an attenuator that scales A1 feedback,
forcing large output signals to balance relatively small differen-
tial inputs. The resistor ratios establish the preamp gain at 10.
The two-stage system architecture of the AD8200 enables the
user to incorporate a low-pass filter prior to the output buffer.
By separating the gain into two stages, a full-scale rail-to-rail
signal from the preamp can be filtered at Pin 3, and a half-scale
signal resulting from filtering can be restored to full scale by the
output buffer amp. The source resistance seen by the inverting
input of A2 is approximately 100 kΩ, to minimize the effects of
A2’s input bias current. However, this current is quite small and
errors resulting from applications that mismatch the resistance
are correspondingly small.
Because the differential input signal is attenuated, and then
amplified to yield an overall gain of 10, the amplifier A1 oper-
ates at a higher noise gain, multiplying deficiencies such as input
offset voltage and noise with respect to Pins 1 and 8.
APPLICATIONS
+IN
–IN
The AD8200 difference amplifier is intended for applications
where it is required to extract a small differential signal in the
presence of large common-mode voltages. The input resistance
is nominally 200 kΩ, and the device can tolerate common-mode
voltages higher than the supply voltage and lower than ground.
R
R
A
A
100kꢃ
A1
(TRIMMED)
A2
R
R
R
G
R
F
CM
CM
The open collector output stage will source current to within
20 mV of ground.
R
R
R
A3
B
B
C
F
R
R
R
AD8200
G
C
COM
Figure 3. Simplified Schematic
REV. A
–5–
AD8200
CURRENT SENSING
Gains Greater than 20
High Line, High Current Sensing
Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 6, will increase the
Basic automotive applications making use of the large common-
mode range are shown in Figures 1 and 2. The capability of the
device to operate as an amplifier in primary battery supply cir-
cuits is shown in Figure 1; Figure 2 illustrates the ability of the
device to withstand voltages below system ground.
gain. The gain is now multiplied by the factor REXT/(REXT
–
100 kΩ); for example, it is doubled for REXT = 200 kΩ. Overall
gains as high as 50 are achievable in this way. Note that the
accuracy of the gain becomes critically dependent on resistor
value at high gains. Also, the effective input offset voltage at
Pins 1 and 8 (about six times the actual offset of A1) limits the
part’s use in very high gain, dc-coupled applications.
Low Current Sensing
The AD8200 can also be used in low current sensing applica-
tions, such as a 4–20 mA current loop shown in Figure 4. In
such applications, the relatively large shunt resistor can degrade
the common-mode rejection. Adding a resistor of equal value in
the low impedance side of the input corrects for this error.
+V
S
OUT
+IN
NC
+V
S
OUT
5V
10ꢃ
OUTPUT
V
V
DIFF
2
10kꢃ
10kꢃ
20R
EXT
1%
GAIN =
R
– 100kꢃ
EXT
R
AD8200
EXT
+IN NC
OUT
+V
S
GAIN
GAIN – 20
DIFF
2
R
= 100kꢃ
V
100kꢃ
EXT
CM
+
10ꢃ
AD8200
1%
–IN GND
A1
A2
–IN GND A1 A2
NC = NO CONNECT
Figure 6. Adjusting for Gains Greater than 20
NC = NO CONNECT
GAIN TRIM
Figure 7 shows a method for incremental gain trimming using
a trimpot and external resistor REXT
Figure 4. 4–20 mA Current Loop Receiver
.
GAIN ADJUSTMENT
The following approximation is useful for small gain ranges:
The default gain of the preamplifier and buffer are ×10 and ×2,
respectively, resulting in a composite gain of ×20. With the
addition of external resistor(s) or trimmer(s), the gain may be
lowered, raised, or finely calibrated.
∆G ≈ (10 MΩ ÷ REXT) %
Thus, the adjustment range would be 2% for REXT = 5 MΩ;
10% for REXT = 1 MΩ, and so on.
Gains Less than 20
5V
See Figure 5. Since the preamplifier has an output resistance of
100 kΩ, an external resistor connected from Pins 3 and 4 to
GND will decrease the gain by a factor REXT/(100 kΩ + REXT).
OUT
V
DIFF
2
+IN NC
OUT
+V
S
+V
S
AD8200
OUT
V
DIFF
2
V
CM
A1
–IN GND
A2
R
+IN
NC
+V
S
OUT
GAIN TRIM
20kꢃ MIN
V
V
DIFF
2
10kꢃ
10kꢃ
20R
EXT
GAIN =
EXT
R
+ 100kꢃ
EXT
AD8200
GAIN
DIFF
2
R
= 100kꢃ
V
100kꢃ
EXT
CM
20 – GAIN
NC = NO CONNECT
–IN GND
A1
A2
Figure 7. Incremental Gain Trim
R
EXT
NC = NO CONNECT
Figure 5. Adjusting for Gains Less than 20
The overall bandwidth is unaffected by changes in gain using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer. In
many cases this can be ignored, but if desired, can be nulled by
inserting a resistor equal to 100 kΩ minus the parallel sum of REXT
and 100 kΩ, in series with Pin 4. For example, with REXT = 100 kΩ
(yielding a composite gain of ×10), the optional offset nulling
resistor is 50 kΩ (see Figure 11.)
–6–
REV. A
AD8200
5V
+V
Internal Signal Overload Considerations
OUT
When configuring gain for values other than 20, the maximum
input voltage with respect to the supply voltage and ground
must be considered, since either the preamplifier or the output
buffer will reach its full-scale output (approximately VS – 0.2 V)
with large differential input voltages. The input of the AD8200
is limited to (VS – 0.2) ÷ 10, for overall gains ≤10, since the
preamplifier, with its fixed gain of ×10, reaches its full-scale
output before the output buffer. For gains greater than 10, the
swing at the buffer output reaches its full scale first and limits
the AD8200 input to (VS – 0.2) ÷ G, where G is the overall gain.
V
V
DIFF
2
+IN NC
OUT
S
C
AD8200
DIFF
2
V
CM
–IN GND A1 A2
255kꢃ
F
= 1Hz – ꢂF
C
C
NC = NO CONNECT
LOW-PASS FILTERING
Figure 9. 2-Pole Low-Pass Filter
In many transducer applications it is necessary to filter the sig-
nal to remove spurious high frequency components, including
noise, or to extract the mean value of a fluctuating signal with a
peak-to-average ratio (PAR) greater than unity. For example, a
full-wave rectified sinusoid has a PAR of 1.57, a raised cosine
has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14.
Signals having large spikes may have PARs of 10 or more.
A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented
using the connections shown in Figure 9. This is a Sallen-Key
form based on a ×2 amplifier. It is useful to remember that a 2-pole
filter with a corner frequency f2 and a 1-pole filter with a corner
2
at f1 have the same attenuation at the frequency (f2 /f1). The
attenuation at that frequency is 40 Log (f2/f1). This is illustrated
in Figure 10. Using the standard resistor value shown and equal
capacitors (Figure 9), the corner frequency is conveniently scaled at
1 Hz-µF (0.05 µF for a 20 Hz corner). A maximally flat response
occurs when the resistor is lowered to 196 kΩ and the scaling is
then 1.145 Hz-µF. The output offset is raised by about 5 mV
(equivalent to 250 V at the input pins).
When implementing a filter, the PAR should be considered so
the output of the AD8200 preamplifier (A1) does not clip before
A2, since this nonlinearity would be averaged and appear as an
error at the output. To avoid this error, both amplifiers should
be made to clip at the same time. This condition is achieved
when the PAR is no greater than the gain of the second ampli-
fier (2 for the default configuration). For example, if a PAR of 5
is expected, the gain of A2 should be increased to 5.
FREQUENCY
Low-pass filters can be implemented in several ways using the
features provided by the AD8200. In the simplest case, a single-
pole filter (20 dB/decade) is formed when the output of A1 is
connected to the input of A2 via the internal 100 kΩ resistor by
strapping Pins 3 and 4 and a capacitor added from this node to
ground, as shown in Figure 8. If a resistor is added across the
capacitor to lower the gain, the corner frequency will increase; it
should be calculated using the parallel sum of the resistor and
100 kΩ.
40dB/DECADE
20dB/DECADE
40LOG (f /f )
2
1
A 1-POLE FILTER, CORNER f , AND
1
5V
A 2-POLE FILTER, CORNER f , HAVE
2
OUT
THE SAME ATTENUATION –40LOG (f /f )
2
1
2
AT FREQUENCY
f /f
2 1
V
DIFF
2
+IN NC
OUT
+VS
1
2
F
=
f
f
f /f
2 1
C
1
2
5
2ꢄC10
AD8200
V
DIFF
2
C IN FARADS
V
Figure 10. Comparative Responses of 1- and 2-Pole
Low-Pass Filters
CM
–IN GND A1 A2
C
NC = NO CONNECT
Figure 8. A Single-Pole, Low-Pass Filter Using the
Internal 100 kΩ Resistor
If the gain is raised using a resistor, as shown in Figure 8, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled) the corner frequency is now 0.796 Hz-µF,
(0.039 µF for a 20 Hz corner frequency.)
REV. A
–7–
AD8200
HIGH LINE CURRENT SENSING WITH LPF AND GAIN
ADJUSTMENT
DRIVING CHARGE REDISTRIBUTION A/D
CONVERTERS
Figure 11 is another refinement of Figure 1, including gain
adjustment and low-pass filtering.
When driving CMOS ADCs, such as those embedded in popular
microcontrollers, the charge injection (⌬Q) can cause a signifi-
cant deflection in the output voltage of the AD8200. Though
generally of short duration, this deflection may persist until after
the sample period of the ADC has expired, due to the relatively
high open-loop output impedance of the AD8200. Including an
R-C network in the output can significantly reduce the effect.
The capacitor helps to absorb the transient charge, effectively
lowering the high frequency output impedance of the AD8200.
For these applications, the output signal should be taken from the
midpoint of the RLAG–CLAG combination as shown in Figure 13.
INDUCTIVE
LOAD
5V
OUTPUT
4V/AMP
CLAMP
DIODE
+IN NC +V OUT
S
BATTERY
14V
191kꢃ
4 TERM
SHUNT
AD8200
20kꢃ
–IN GND A1 A2
POWER
DEVICE
V
Since the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8200 will appear to be
low. The transient response will, therefore, have a time constant
OS/IB
NULL
C
governed by the product of the two LAG components, CLAG
LAG. For the values shown in Figure 13, this time constant is
programmed at approximately 10 µs. Therefore, if samples are
taken at several tens of microseconds or more, there will be
negligible charge “stack-up.”
×
5% CALIBRATION RANGE
= 0.796Hz – ꢂF
(0.22ꢂF FOR f = 3.6 Hz)
NC = NO CONNECT
COMMON
R
F
C
Figure 11. High-Line Current Sensor Interface. Gain = ×40,
Single-Pole, Low-Pass Filter
A power device that is either ‘ON’ or ‘OFF’ controls the current
in the load. The average current is proportional to the duty cycle
of the input pulse, and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value will be higher by an amount that depends
on the inductance of the load and the control frequency. The
common-mode voltage, on the other hand, extends from roughly
1 V above ground, when the switch is ‘ON,’ to about 1.5 V
above the battery voltage, when the device is ‘OFF,’ and the
clamp diode conducts. If the maximum battery voltage spikes
up to 20 V, the common-mode voltage at the input can be as
high as 21.5 V.
5V
AD8200
+IN
R
LAG
1kꢃ
A2
ꢂPROCESSOR
A/D
C
LAG
0.01ꢂF
–IN
10kꢃ
10kꢃ
To produce a full-scale output of 4 V, a gain ×40 is used, adjust-
able by 5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
by a single-pole, low-pass filter, here set with a corner frequency
= 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz.
A higher rate of attenuation can be obtained using a two-pole
filter having fC = 20 Hz, as shown in Figure 12. Although this
circuit uses two separate capacitors, the total capacitance is less
than half that needed for the single-pole filter.
Figure 13. Recommended Circuit for Driving CMOS A/D
INDUCTIVE
LOAD
5V
CLAMP
DIODE
OUTPUT
+IN NC +VS OUT
BATTERY
14V
432kꢃ
4 TERM
SHUNT
AD8200
C
50kꢃ
–IN
A1 A2
GND
POWER
DEVICE
127kꢃ
C
F
= 1Hz – ꢂF
NC = NO CONNECT
COMMON
C
(0.05ꢂF FOR f = 20Hz)
C
Figure 12. Illustration of 2-Pole Low-Pass Filtering
–8–
REV. A
AD8200
OUTLINE DIMENSIONS
Dimensions shown in inches and (millimeters)
8-Lead SOIC Package
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
ꢅ 45ꢀ
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8ꢀ
0ꢀ
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
REV. A
–9–
AD8200
Revision History
Location
Page
6/02—Change from REV. 0 to REV. A.
CHANGE to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
–10–
REV. A
–11–
–12–
相关型号：
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