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AD8220WARMZ-RL [ADI]

JFET Input Instrumentation Amplifier with Rail-to-Rail Output in MSOP Package; JFET输入仪表放大器具有轨到轨输出，采用MSOP封装
AD8220WARMZ-RL
型号： AD8220WARMZ-RL
厂家： ADI    ADI
描述：

JFET Input Instrumentation Amplifier with Rail-to-Rail Output in MSOP Package
JFET输入仪表放大器具有轨到轨输出，采用MSOP封装

仪表放大器 放大器电路 光电二极管 PC
文件： 总28页 (文件大小：510K)
中文：  中文翻译
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JFET Input Instrumentation Amplifier with  
Rail-to-Rail Output in MSOP Package  
AD8220  
FEATURES  
PIN CONFIGURATION  
Low input currents  
AD8220  
1
2
3
4
8
7
6
5
–IN  
+V  
S
10 pA maximum input bias current (B grade)  
0.6 pA maximum input offset current (B grade)  
High CMRR  
100 dB CMRR (minimum), G = 10 (B grade)  
80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade)  
Excellent ac specifications and low power  
1.5 MHz bandwidth (G = 1)  
R
R
V
OUT  
G
G
REF  
–V  
+IN  
S
TOP VIEW  
(Not to Scale)  
Figure 1.  
14 nV/√Hz input noise (1 kHz)  
Slew rate: 2 V/μs  
750 μA quiescent supply current (maximum)  
Versatile  
MSOP package  
10n  
1n  
I
BIAS  
Rail-to-rail output  
Input voltage range to below negative supply rail  
4 kV ESD protection  
4.5 V to 36 V single supply  
100p  
10p  
1p  
I
2.25 V to 18 V dual supply  
OS  
Gain set with single resistor (G = 1 to 1000)  
Qualified for automotive applications  
0.1p  
APPLICATIONS  
–50  
–25  
0
25  
50  
75  
100  
125  
150  
Medical instrumentation  
Precision data acquisition  
Transducer interfaces  
TEMPERATURE (°C)  
Figure 2. Input Bias Current and Offset Current vs. Temperature  
GENERAL DESCRIPTION  
The AD8220 is the first single-supply, JFET input instrumentation  
amplifier available in an MSOP package. Designed to meet the  
needs of high performance, portable instrumentation, the AD8220  
has a minimum common-mode rejection ratio (CMRR) of 86 dB  
at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maxi-  
mum input bias current is 10 pA and typically remains below  
300 pA over the entire industrial temperature range. Despite the  
JFET inputs, the AD8220 typically has a noise corner of only 10 Hz.  
Gain is set from 1 to 1000 with a single resistor. Increasing the  
gain increases the common-mode rejection. Measurements that  
need higher CMRR when reading small signals benefit when  
the AD8220 is set for large gains.  
A reference pin allows the user to offset the output voltage. This  
feature is useful when interfacing with analog-to-digital converters.  
The AD8220 is available in an MSOP that takes roughly half the  
board area of an SOIC. Performance for the A and B grade is  
specified over the industrial temperature range of −40°C to +85°C,  
and the W grade is specified over the automotive temperature  
range of −40°C to +125°C.  
With the proliferation of mixed-signal processing, the number  
of power supplies required in each system has grown. The AD8220  
is designed to alleviate this problem. The AD8220 can operate  
on a 18 ꢀ dual supply, as well as on a single +5 ꢀ supply. Its  
rail-to-rail output stage maximizes dynamic range on the low  
voltage supplies common in portable applications. Its ability to  
run on a single 5 ꢀ supply eliminates the need to use higher  
voltage, dual supplies. The AD8220 draws a maximum of 750 μA  
of quiescent current, making it ideal for battery powered devices.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.  
 
 
 
 
AD8220  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Power Supply Regulation and Bypassing ................................ 21  
Input Bias Current Return Path ............................................... 21  
Input Protection ......................................................................... 21  
RF Interference ........................................................................... 22  
Common-Mode Input ꢀoltage Range..................................... 22  
Driving an ADC ......................................................................... 22  
Applications Information.............................................................. 23  
AC-Coupled Instrumentation Amplifier................................ 23  
Differential Output .................................................................... 23  
Electrocardiogram Signal Conditioning................................. 25  
Outline Dimensions....................................................................... 26  
Ordering Guide .......................................................................... 26  
Automotive Products................................................................. 26  
Applications....................................................................................... 1  
Pin Configuration............................................................................. 1  
General Description......................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Absolute Maximum Ratings............................................................ 8  
ESD Caution.................................................................................. 8  
Pin Configuration and Function Descriptions............................. 9  
Typical Performance Characteristics ........................................... 10  
Theory of Operation ...................................................................... 19  
Gain Selection............................................................................. 20  
Layout........................................................................................... 20  
Reference Terminal .................................................................... 21  
REVISION HISTORY  
5/10—Rev. A to Rev. B  
5/07—Rev. 0 to Rev. A  
Added W Grade..................................................................Universal  
Changes to Features Section and General Description Section. 1  
Changes to Specifications Section and Table 1............................. 3  
Changes to Table 2............................................................................ 5  
Updated Outline Dimensions....................................................... 26  
Changes to Ordering Guide .......................................................... 26  
Added Automotive Products Section .......................................... 26  
Changes to Table 1.............................................................................3  
Changes to Table 2.............................................................................5  
Changes to Table 3.............................................................................8  
Changes to Figure 6 and Figure 7................................................. 10  
Changes to Figure 23 and Figure 24............................................. 13  
Changes to Theory of Operation.................................................. 19  
Changes to Layout.......................................................................... 20  
Changes to Ordering Guide.......................................................... 26  
4/06—Revision 0: Initial Version  
Rev. B | Page 2 of 28  
 
AD8220  
SPECIFICATIONS  
ꢀS+ = 15 ꢀ, ꢀS− = −15 ꢀ, ꢀREF = 0 ꢀ, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade,  
G = 1, RL = 2 kΩ1, unless otherwise noted.  
Table 1.  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
Test Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
COMMON-MODE  
TA for A, B grades,  
REJECTION RATIO (CMRR) TOPR for W grade  
CMRR DC to 60 Hz with  
1 kΩ Source Imbalance  
VCM  
=
10 V  
G = 1  
G = 10  
G = 100  
G = 1000  
CMRR at 5 kHz  
G = 1  
G = 10  
G = 100  
G = 1000  
78  
94  
94  
94  
86  
77  
92  
92  
92  
dB  
dB  
dB  
dB  
100  
100  
100  
VCM  
=
10 V  
74  
84  
84  
84  
80  
90  
90  
90  
72  
80  
80  
80  
dB  
dB  
dB  
dB  
NOISE  
RTI noise =  
√(eni2 + (eno/G)2), TA  
Voltage Noise, 1 kHz  
Input Voltage Noise, eni  
Output Voltage Noise, eno  
RTI, 0.1 Hz to 10 Hz  
G = 1  
VIN+, VIN− = 0 V  
VIN+, VIN− = 0 V  
14  
90  
14  
90  
17  
100  
14  
90  
nV/√Hz  
nV/√Hz  
5
0.8  
1
5
0.8  
1
5
0.8  
1
μV p-p  
μV p-p  
fA/√Hz  
G = 1000  
Current Noise  
f = 1 kHz  
VOLTAGE OFFSET  
Input Offset, VOSI  
Average TC  
Output Offset, VOSO  
Average TC  
VOS = VOSI + VOSO/G  
TA  
TOPR  
TA  
TOPR  
−250  
−10  
−750  
−10  
+250  
+10  
+750  
+10  
−125  
−5  
−500  
−5  
+125  
+5  
+500  
+5  
−250  
−10  
−750  
−10  
+250  
+10  
+750  
+10  
μV  
μV/°C  
μV  
μV/°C  
Offset RTI vs. Supply  
(PSR)  
VS = 5 V to 15 V,  
TA for A, B grades,  
TOPR for W grade  
G = 1  
G = 10  
G = 100  
G = 1000  
86  
96  
96  
96  
86  
80  
92  
92  
92  
dB  
dB  
dB  
dB  
100  
100  
100  
INPUT CURRENT  
Input Bias Current  
Over Temperature  
Input Offset Current  
Over Temperature  
DYNAMIC RESPONSE  
TA  
TOPR  
TA  
25  
2
10  
25  
100  
2
pA  
nA  
pA  
nA  
0.3  
0.3  
0.6  
TOPR  
0.005  
0.005  
10  
Small Signal Bandwidth,  
−3 dB  
TA  
G = 1  
1500  
800  
120  
14  
1500  
800  
120  
14  
1500  
800  
120  
14  
kHz  
kHz  
kHz  
kHz  
G = 10  
G = 100  
G = 1000  
Rev. B | Page 3 of 28  
 
AD8220  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
Settling Time 0.01%  
G = 1  
G = 10  
G = 100  
G = 1000  
Settling Time 0.001%  
G = 1  
G = 10  
G = 100  
G = 1000  
Slew Rate  
G = 1 to 100  
GAIN  
Test Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
10 V step, TA  
5
5
5
μs  
μs  
μs  
μs  
4.3  
8.1  
58  
4.3  
8.1  
58  
4.3  
8.1  
58  
10 V step, TA  
6
6
6
μs  
μs  
μs  
μs  
4.6  
9.6  
74  
4.6  
9.6  
74  
4.6  
9.6  
74  
TA  
2
1
2
1
2
1
V/μs  
G = 1 + (49.4 kΩ/RG),  
TA for A, B grades,  
TOPR for W grade  
Gain Range  
Gain Error  
G = 1  
G = 10  
G = 100  
1000  
1000  
1000  
V/V  
VOUT  
=
10 V  
−0.06  
−0.3  
−0.3  
−0.3  
+0.06  
+0.3  
+0.3  
+0.3  
−0.04  
−0.2  
−0.2  
−0.2  
+0.04  
+0.2  
+0.2  
+0.2  
−0.1  
−0.8  
−0.8  
−0.8  
+0.1  
+0.8  
+0.8  
+0.8  
%
%
%
%
G = 1000  
Gain Nonlinearity  
VOUT  
=
−10 V to +10 V, TA  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 2 kΩ  
G = 1  
G = 10  
G = 100  
G = 1000  
G = 1  
10  
5
15  
10  
60  
500  
15  
15  
75  
10  
5
15  
10  
60  
500  
15  
15  
75  
10  
5
15  
10  
60  
500  
15  
15  
75  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
30  
400  
10  
10  
50  
30  
400  
10  
10  
50  
30  
400  
10  
10  
50  
G = 10  
RL = 2 kΩ  
RL = 2 kΩ  
G = 100  
Gain vs. Temperature  
G = 1  
3
10  
−50  
2
5
−50  
3
10  
−50  
ppm/°C  
ppm/°C  
G > 10  
INPUT  
Impedance (Pin to  
Ground)2  
TA  
104||5  
104||5  
104||5  
GΩ||pF  
Input Operating Voltage VS = 2.25 V to 18 V −VS −  
+VS −  
2
+VS −  
2.1  
−VS −  
0.1  
−VS −  
0.1  
+VS −  
2
+VS −  
2.1  
−VS −  
0.1  
−VS −  
0.1  
+VS − 2  
V
V
Range3  
for dual supplies  
0.1  
Over Temperature  
TOPR  
−VS −  
0.1  
+VS −  
2.2  
OUTPUT  
Output Swing  
Over Temperature  
Short-Circuit Current  
REFERENCE INPUT  
RIN  
RL = 10 kΩ, TA  
TOPR  
TA  
−14.7  
−14.6  
+14.7  
+14.6  
−14.7  
−14.6  
+14.7  
+14.6  
−14.7  
−14.3  
+14.7  
+14.3  
V
V
15  
40  
15  
40  
15  
40  
mA  
kΩ  
μA  
V
V/V  
V/V  
TA  
IIN  
VIN+, VIN− = 0 V  
TA  
70  
+VS  
70  
+VS  
70  
+VS  
1
Voltage Range  
Gain to Output  
−VS  
−VS  
1
1
0.0001  
0.0001  
0.0001  
Rev. B | Page 4 of 28  
AD8220  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
Test Conditions  
Min  
2.254  
Max  
Min  
2.254  
Max  
Min  
2.254  
Max  
Unit  
V
μA  
μA  
μA  
POWER SUPPLY  
Operating Range  
Quiescent Current  
Over Temperature  
TEMPERATURE RANGE  
18  
750  
850  
18  
750  
850  
18  
750  
1000  
TA  
TOPR  
For Specified  
Performance  
TOPR  
−40  
+85  
−40  
+85  
−40  
+125  
°C  
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.  
2 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.  
3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum  
allowable voltage where the input bias current is within the specification.  
4 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.  
ꢀS + = 5 ꢀ, ꢀS− = 0 ꢀ, ꢀREF = 2.5 ꢀ, TA = 25°C, TOPR = −40°C to +85°C for A and B grades. TOPR = −40°C to +125°C for W grade, G = 1,  
RL = 2 kΩ1, unless otherwise noted.  
Table 2.  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
Test Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
COMMON-MODE REJECTION TA for A, B grades,  
RATIO (CMRR)  
CMRR DC to 60 Hz with  
1 kΩ Source Imbalance  
TOPR for W grade  
VCM = 0 to 2.5 V  
G = 1  
G = 10  
G = 100  
G = 1000  
CMRR at 5 kHz  
G = 1  
G = 10  
G = 100  
G = 1000  
78  
94  
94  
94  
86  
77  
92  
92  
92  
dB  
dB  
dB  
dB  
100  
100  
100  
VCM = 0 to 2.5 V  
74  
84  
84  
84  
80  
90  
90  
90  
72  
80  
80  
80  
dB  
dB  
dB  
dB  
2
NOISE  
RTI noise = √(eni  
+
(eno/G)2), TA  
VS = 2.5 V  
Voltage Noise, 1 kHz  
Input Voltage Noise, eni  
VIN+, VIN− = 0 V, VREF  
0 V  
VIN+, VIN− = 0 V, VREF  
0 V  
=
=
14  
90  
14  
90  
17  
14  
90  
nV/√Hz  
nV/√Hz  
Output Voltage Noise, eno  
100  
RTI, 0.1 Hz to 10 Hz  
G = 1  
G = 1000  
Current Noise  
VOLTAGE OFFSET  
Input Offset, VOSI  
Average TC  
Output Offset, VOSO  
Average TC  
5
0.8  
1
5
0.8  
1
5
0.8  
1
μV p-p  
μV p-p  
fA/√Hz  
f = 1 kHz  
VOS = VOSI + VOSO/G  
TA  
TOPR  
TA  
TOPR  
−300  
−10  
−800  
−10  
+300  
+10  
+800  
+10  
−200  
−5  
−600  
−5  
+200  
+5  
+600  
+5  
−300  
−10  
−800  
−10  
+300  
10  
+800  
+10  
μV  
μV/°C  
μV  
μV/°C  
Offset RTI vs. Supply (PSR)  
TA for A, B grades,  
TOPR for W grade  
G = 1  
86  
96  
96  
96  
86  
80  
92  
92  
92  
dB  
dB  
dB  
dB  
G = 10  
G = 100  
G = 1000  
100  
100  
100  
Rev. B | Page 5 of 28  
AD8220  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
Test Conditions  
Min  
Max  
25  
Min  
Max  
10  
Min  
Max  
Unit  
INPUT CURRENT  
Input Bias Current  
Over Temperature  
Input Offset Current  
Over Temperature  
DYNAMIC RESPONSE  
TA  
TOPR  
TA  
TOPR  
TA  
25  
100  
2
pA  
nA  
pA  
nA  
0.3  
0.3  
2
0.6  
0.005  
0.005  
10  
Small Signal Bandwidth,  
−3 dB  
G = 1  
G = 10  
G = 100  
G = 1000  
Settling Time 0.01%  
G = 1  
G = 10  
G = 100  
G = 1000  
Settling Time 0.001%  
G = 1  
G = 10  
G = 100  
G = 1000  
Slew Rate  
G = 1 to 100  
GAIN  
1500  
800  
120  
14  
1500  
800  
120  
14  
1500  
800  
120  
14  
kHz  
kHz  
kHz  
kHz  
TA  
3 V step  
4 V step  
4 V step  
4 V step  
TA  
3 V step  
4 V step  
4 V step  
4 V step  
2.5  
2.5  
7.5  
30  
2.5  
2.5  
7.5  
30  
2.5  
2.5  
7.5  
30  
μs  
μs  
μs  
μs  
3.5  
3.5  
8.5  
37  
3.5  
3.5  
8.5  
37  
3.5  
3.5  
8.5  
37  
μs  
μs  
μs  
μs  
TA  
2
1
2
1
2
1
V/μs  
G = 1 + (49.4 kΩ/RG),  
TA for A, B grades,  
TOPR for W grade  
Gain Range  
Gain Error  
1000  
1000  
1000  
V/V  
VOUT = 0.3 V to 2.9 V for  
G = 1, VOUT = 0.3 V to  
3.8 V for G > 1  
G = 1  
G = 10  
G = 100  
G = 1000  
Nonlinearity  
−0.06  
−0.3  
−0.3  
−0.3  
+0.06 −0.04  
+0.04 −0.1  
+0.1  
+0.8  
+0.8  
+0.8  
%
%
%
%
+0.3  
+0.3  
+0.3  
−0.2  
−0.2  
−0.2  
+0.2  
+0.2  
+0.2  
−0.8  
−0.8  
−0.8  
VOUT = 0.3 V to 2.9 V for  
G = 1, VOUT = 0.3 V to  
3.8 V for G > 1, TA  
G = 1  
G = 10  
G = 100  
G = 1000  
G = 1  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 10 kΩ  
RL = 2 kΩ  
RL = 2 kΩ  
RL = 2 kΩ  
35  
35  
50  
650  
35  
35  
50  
50  
50  
75  
750  
50  
50  
75  
35  
35  
50  
650  
35  
35  
50  
50  
50  
75  
750  
50  
50  
75  
50  
50  
75  
750  
50  
50  
75  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
G = 10  
G = 100  
Gain vs. Temperature  
G = 1  
3
10  
−50  
2
5
−50  
3
10  
−50  
ppm/°C  
ppm/°C  
G > 10  
INPUT  
Impedance (Pin to  
TA  
104||6  
104||6  
104||6  
GΩ||pF  
Ground)2  
Input Voltage Range3  
Over Temperature  
TA  
−0.1  
−0.1  
+VS −  
2
+VS −  
2.1  
−0.1  
−0.1  
+VS −  
2
+VS −  
2.1  
V
V
TOPR  
−0.1  
+VS −  
2.2  
Rev. B | Page 6 of 28  
 
AD8220  
A Grade  
Typ  
B Grade  
Typ  
W Grade  
Typ  
Parameter  
OUTPUT  
Test Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Output Swing  
Over Temperature  
RL = 10 kΩ  
TOPR  
0.15  
0.2  
4.85  
4.80  
0.15  
0.2  
4.85  
4.80  
0.15  
0.3  
4.85  
4.70  
V
V
Short-Circuit Current  
REFERENCE INPUT  
RIN  
15  
40  
15  
40  
15  
40  
mA  
TA  
kΩ  
μA  
V
VIN+, VIN− = 0 V  
TA  
IIN  
70  
+VS  
70  
+VS  
70  
+VS  
Voltage Range  
Gain to Output  
−VS  
4.5  
−VS  
4.5  
−VS  
4.5  
1
1
1
V/V  
0.0001  
0.0001  
0.0001  
POWER SUPPLY  
Operating Range  
Quiescent Current  
Over Temperature  
TEMPERATURE RANGE  
36  
750  
850  
36  
750  
850  
36  
750  
1000  
V
μA  
μA  
TA  
TOPR  
TOPR, For Specified  
Performance  
TOPR  
−40  
+85  
−40  
+85  
−40  
+125  
°C  
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.  
2 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.  
3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum  
allowable voltage where the input bias current is within the specification.  
Rev. B | Page 7 of 28  
AD8220  
ABSOLUTE MAXIMUM RATINGS  
Table 3.  
Parameter  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rating  
18 V  
See Figure 3  
Indefinite1  
Vs  
Supply Voltage  
Power Dissipation  
Output Short-Circuit Current  
Input Voltage (Common Mode)  
Differential Input Voltage  
Storage Temperature Range  
Operating Temperature Range2  
Lead Temperature (Soldering 10 sec)  
Junction Temperature  
Vs  
−65°C to +125°C  
−40°C to +125°C  
300°C  
Figure 3 shows the maximum safe power dissipation in the  
package vs. the ambient temperature for the MSOP on a 4-layer  
JEDEC standard board. θJA values are approximations.  
140°C  
θJA (4-Layer JEDEC Standard Board)  
Package Glass Transition Temperature  
ESD (Human Body Model)  
ESD (Charge Device Model)  
ESD (Machine Model)  
135°C/W  
140°C  
4 kV  
1 kV  
0.4 kV  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
1 Assumes the load is referenced to midsupply.  
2 Temperature for specified performance is −40°C to +85°C. For performance  
to 125°C, see the Typical Performance Characteristics section.  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
AMBIENT TEMPERATURE (°C)  
Figure 3. Maximum Power Dissipation vs. Ambient Temperature  
ESD CAUTION  
Rev. B | Page 8 of 28  
 
 
 
 
 
AD8220  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
AD8220  
1
2
3
4
8
7
6
5
–IN  
+V  
S
R
R
V
OUT  
G
G
REF  
–V  
+IN  
S
TOP VIEW  
(Not to Scale)  
Figure 4. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
2, 3  
4
5
6
−IN  
RG  
Negative Input Terminal (True Differential Input)  
Gain Setting Terminals (Place Resistor Across the RG Pins)  
Positive Input Terminal (True Differential Input)  
Negative Power Supply Terminal  
Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output)  
Output Terminal  
+IN  
−VS  
REF  
VOUT  
+VS  
7
8
Positive Power Supply Terminal  
Rev. B | Page 9 of 28  
 
AD8220  
TYPICAL PERFORMANCE CHARACTERISTICS  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
1200  
1000  
800  
600  
400  
200  
0
–40  
–20  
0
20  
40  
0
1
2
3
4
5
CMRR (µV/V)  
I
(pA)  
BIAS  
Figure 5. Typical Distribution of CMRR (G = 1)  
Figure 8. Typical Distribution of Input Bias Current  
1200  
1000  
800  
600  
400  
200  
0
1000  
800  
600  
400  
200  
0
–200  
–100  
0
100  
200  
–0.2  
–0.1  
0
0.1  
0.2  
V
(µV)  
I
(pA)  
OSI  
OS  
Figure 6. Typical Distribution of Input Offset Voltage  
Figure 9. Typical Distribution of Input Offset Current  
1000  
100  
10  
1000  
800  
600  
400  
200  
0
GAIN = 100 BANDWIDTH ROLL-OFF  
GAIN = 1  
GAIN = 10  
GAIN = 100/GAIN = 1000  
GAIN = 1000 BANDWIDTH ROLL-OFF  
1
1
10  
100  
1k  
10k  
100k  
–1000  
–500  
0
500  
1000  
FREQUENCY (Hz)  
V
(µV)  
OSO  
Figure 10. Voltage Spectral Density vs. Frequency  
Figure 7. Typical Distribution of Output Offset Voltage  
Rev. B | Page 10 of 28  
 
AD8220  
XX  
150  
130  
110  
90  
GAIN = 1000  
BANDWIDTH  
LIMITED  
GAIN = 100  
GAIN = 10  
GAIN = 1  
70  
50  
30  
5µV/DIV  
1s/DIV  
XX  
XX  
10  
XX  
1
10  
100  
1k  
10k  
100k  
1M  
XXX (X)  
FREQUENCY (Hz)  
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)  
Figure 14. Positive PSRR vs. Frequency, RTI  
XX  
150  
130  
110  
90  
GAIN = 1000  
GAIN = 1  
70  
GAIN = 10  
50  
GAIN = 100  
30  
1µV/DIV  
1s/DIV  
XX  
XX  
10  
XX  
1
10  
100  
1k  
10k  
100k  
1M  
XXX (X)  
FREQUENCY (Hz)  
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)  
Figure 15. Negative PSRR vs. Frequency, RTI  
8
7
6
5
4
3
2
1
0
0.3  
INPUT OFFSET  
CURRENT ±15  
9
7
0.2  
INPUT OFFSET  
CURRENT ±5  
0.1  
0
5
–15.1V  
–5.1V  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
3
INPUT BIAS  
INPUT BIAS  
CURRENT ±5  
CURRENT ±15  
1
–1  
–16  
0.1  
1
10  
100  
1k  
–12  
–8  
–4  
0
4
8
12  
16  
TIME (s)  
COMMON-MODE VOLTAGE (V)  
Figure 13. Change in Input Offset Voltage vs. Warmup Time  
Figure 16. Input Bias Current and Input Offset Current vs.  
Common-Mode Voltage  
Rev. B | Page 11 of 28  
AD8220  
160  
140  
120  
100  
80  
10n  
1n  
GAIN = 1000  
GAIN = 100  
I
BIAS  
100p  
10p  
1p  
BANDWIDTH  
LIMITED  
GAIN = 1  
I
GAIN = 10  
OS  
60  
0.1p  
40  
–50  
–25  
0
25  
50  
75  
100  
125  
150  
1
10  
100  
1k  
10k  
100k  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
Figure 17. Input Bias Current and Offset Current vs. Temperature,  
VS = 15 V, VREF = 0 V  
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance  
10  
8
6
10n  
1n  
4
I
BIAS  
2
100p  
10p  
1p  
0
–2  
–4  
–6  
–8  
–10  
I
OS  
0.1p  
–50  
–25  
0
25  
50  
75  
100  
125  
150  
–50  
–30  
–10  
10  
30  
50  
70  
90  
110  
130  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 18. Input Bias Current and Offset Current vs. Temperature,  
VS = +5 V, VREF = 2.5 V  
Figure 21. Change in CMRR vs. Temperature, G = 1  
160  
70  
60  
GAIN = 1000  
GAIN = 1000  
140  
50  
40  
GAIN = 100  
120  
GAIN = 100  
GAIN = 10  
GAIN = 1  
30  
GAIN = 10  
20  
BANDWIDTH  
LIMITED  
100  
10  
GAIN = 1  
80  
0
–10  
–20  
–30  
–40  
60  
40  
10  
100  
1k  
10k  
100k  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 19. CMRR vs. Frequency  
Figure 22. Gain vs. Frequency  
Rev. B | Page 12 of 28  
AD8220  
R
= 2kΩ  
LOAD  
R
= 10kΩ  
LOAD  
R
= 2kΩ  
LOAD  
R
= 10kΩ  
LOAD  
V
= ±15V  
–8  
V
= ±15V  
–8  
S
S
–10  
–6  
–4  
–2  
0
2
4
6
8
10  
–10  
–6  
–4  
–2  
0
2
4
6
8
10  
OUTPUT VOLTAGE (V)  
OUTPUT VOLTAGE (V)  
Figure 23. Gain Nonlinearity, G = 1  
Figure 26. Gain Nonlinearity, G = 1000  
18  
+13V  
12  
6
±15V SUPPLIES  
–14.8V, +5.5V  
–4.8V, +0.6V  
+3V  
+14.9V, +5.5V  
+4.95V, +0.6V  
R
= 2kΩ  
LOAD  
0
±5V SUPPLIES  
–4.8V, –3.3V  
–14.8V, –8.3V  
+4.95V, –3.3V  
+14.9V, –8.3V  
R
= 10kΩ  
LOAD  
–6  
–12  
–18  
–5.3V  
V
= ±15V  
–8  
–15.3V  
S
–16  
–12  
–8  
–4  
0
4
8
12  
16  
–10  
–6  
–4  
–2  
0
2
4
6
8
10  
OUTPUT VOLTAGE (V)  
OUTPUT VOLTAGE (V)  
Figure 24. Gain Nonlinearity, G = 10  
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,  
G = 1, VREF = 0 V  
4
+3V  
3
R
= 2kΩ  
LOAD  
2
+0.1V, +1.7V  
+0.1V, +0.5V  
+4.9V, +1.7V  
+4.9V, +0.5V  
R
= 10kΩ  
LOAD  
+5V SINGLE SUPPLY,  
V
= +2.5V  
REF  
1
0
–0.3V  
V
= ±15V  
–8  
S
–1  
–1  
0
1
2
3
4
5
6
–10  
–6  
–4  
–2  
0
2
4
6
8
10  
OUTPUT VOLTAGE (V)  
OUTPUT VOLTAGE (V)  
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage,  
G = 1, VS = +5 V, VREF = 2.5 V  
Figure 25. Gain Nonlinearity, G = 100  
Rev. B | Page 13 of 28  
 
AD8220  
18  
12  
6
V +  
S
–1  
–2  
–3  
–4  
+13V  
+85°C  
–40°C  
±15V SUPPLIES  
+25°C  
+125°C  
–14.9V, +5.4V  
+3V  
+14.9V, +5.4V  
+4.9V, +0.5V  
–4.9V, +0.4V  
–4.9V, –4.1V  
0
±5V SUPPLIES  
–5.3V  
+4  
+3  
+2  
+1  
+4.9V, –4.1V  
+14.9V, –9V  
–6  
–12  
–14.8V, –9V  
+125°C  
–40°C  
16  
+85°C  
+25°C  
14  
–15.3V  
–18  
–16  
V –  
S
–12  
–8  
–4  
0
4
8
12  
16  
2
4
6
8
10  
12  
18  
OUTPUT VOLTAGE (V)  
DUAL SUPPLY VOLTAGE (±V)  
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage,  
G = 100, VREF = 0 V  
Figure 32. Output Voltage Swing vs. Supply Voltage, RLOAD = 2 kΩ, G = 10,  
VREF = 0 V  
4
V +  
S
–0.2  
–0.4  
+125°C  
+3V  
+85°C  
3
+25°C  
–40°C  
2
+0.1V, +1.7V  
+4.9V, +1.7V  
+5V SINGLE SUPPLY,  
= +2.5V  
1
0
V
REF  
+0.4  
+0.2  
+125°C  
+85°C  
–40°C  
10  
+25°C  
8
+0.1V, –0.5V  
1
+4.9V, –0.5V  
4
–0.3V  
–1  
–1  
V
–
S
0
2
3
5
6
2
4
6
12  
14  
16  
18  
OUTPUT VOLTAGE (V)  
DUAL SUPPLY VOLTAGE (±V)  
Figure 30. Input Common-Mode Voltage Range vs. Output Voltage,  
G = 100, VS = +5 V, VREF = 2.5 V  
Figure 33. Output Voltage Swing vs. Supply Voltage, RLOAD = 10 kΩ, G = 10,  
VREF = 0 V  
V +  
S
15  
–1  
–2  
–40°C  
10  
+125°C  
+85°C  
–40°C  
+25°C  
+25°C  
+85°C  
5
+125°C  
NOTES  
1. THE AD8220 CAN OPERATE UP TO A V BELOW  
THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT  
WILL INCREASE SHARPLY.  
BE  
0
+125°C  
–5  
–10  
–15  
+1  
+85°C  
–40°C +25°C  
+85°C  
+125°C  
+25°C  
–40°C  
V –  
S
–1  
2
4
6
8
10  
12  
14  
16  
18  
100  
1k  
10k  
SUPPLY VOLTAGE (V)  
R
(Ω)  
LOAD  
Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V  
Figure 34. Output Voltage Swing vs. Load Resistance VS = 15 V, VREF = 0 V  
Rev. B | Page 14 of 28  
 
AD8220  
5
4
3
2
1
0
XX  
47pF  
–40°C  
NO LOAD  
+85°C  
100pF  
+25°C  
+125°C  
+125°C  
–40°C  
+25°C  
+85°C  
1k  
20mV/DIV  
XX  
5µs/DIV  
XX  
100  
10k  
XX  
R
(Ω)  
XXX (X)  
LOAD  
Figure 38. Small Signal Pulse Response for Various Capacitive Loads,  
VS = 15 V, VREF = 0 V  
Figure 35. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V  
V +  
S
XX  
–40°C  
47pF  
–1  
–2  
–3  
–4  
100pF  
NO LOAD  
+125°C  
+85°C  
+25°C  
+4  
+3  
+2  
+1  
+85°C +25°C  
+125°C  
10  
–40°C  
14 16  
20mV/DIV  
XX  
5µs/DIV  
V –  
S
XX  
0
2
4
6
8
12  
XX  
I
(mA)  
OUT  
XXX (X)  
Figure 36. Output Voltage Swing vs. Output Current, VS = 15 V, VREF = 0 V  
Figure 39. Small Signal Pulse Response for Various Capacitive Loads,  
VS = 5 V, VREF = 2.5 V  
V +  
S
35  
GAIN = 10, 100, 1000  
30  
–1  
–2  
+2  
+1  
+25°C  
GAIN = 1  
25  
+85°C  
+125°C  
20  
15  
10  
5
+25°C  
+85°C  
+125°C  
–40°C  
V –  
0
100  
S
0
2
4
6
8
10  
12  
14  
16  
1k  
10k  
100k  
1M  
10M  
I
(mA)  
FREQUENCY (Hz)  
OUT  
Figure 40. Output Voltage Swing vs. Large Signal Frequency Response  
Figure 37. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V  
Rev. B | Page 15 of 28  
AD8220  
XX  
XX  
5V/DIV  
5V/DIV  
5µs TO 0.01%  
6µs TO 0.001%  
58μs TO 0.01%  
74μs TO 0.001%  
0.002%/DIV  
0.002%/DIV  
200µs/DIV  
20µs/DIV  
XX  
XX  
XX  
XX  
XX  
XX  
XXX (X)  
XXX (X)  
Figure 41. Large Signal Pulse Response and Settle Time, G = 1,  
RLOAD = 10 kΩ, VS = 15 V, VREF = 0 V  
Figure 44. Large Signal Pulse Response and Settle Time, G = 1000,  
RLOAD = 10 kΩ, VS = 15 V, VREF = 0 V  
XX  
5V/DIV  
4.3μs TO 0.01%  
4.6μs TO 0.001%  
0.002%/DIV  
20mV/DIV  
20µs/DIV  
XX  
XX  
4µs/DIV  
XX  
XXX  
XXX (X)  
Figure 45. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 15 V, VREF = 0 V  
Figure 42. Large Signal Pulse Response and Settle Time, G = 10,  
RLOAD = 10 kΩ, VS = 15 V, VREF = 0 V  
XX  
5V/DIV  
8.1μs TO 0.01%  
9.6μs TO 0.001%  
0.002%/DIV  
20mV/DIV  
20µs/DIV  
XX  
XX  
4µs/DIV  
XX  
XXX  
XXX (X)  
Figure 46. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 15 V, VREF = 0 V  
Figure 43. Large Signal Pulse Response and Settle Time, G = 100,  
RLOAD = 10 kΩ, VS = 15 V, VREF = 0 V  
Rev. B | Page 16 of 28  
AD8220  
20mV/DIV  
20mV/DIV  
4µs/DIV  
4µs/DIV  
XXX  
XXX  
Figure 47 Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 15 V, VREF =0 V  
Figure 50. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 5 V, VREF = 2.5 V  
20mV/DIV  
20mV/DIV  
4µs/DIV  
40µs/DIV  
XXX  
XXX  
Figure 51. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 5 V, VREF = 2.5 V  
Figure 48. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ,  
CLOAD = 100 pF, VS = 15 V, VREF = 0 V  
20mV/DIV  
20mV/DIV  
40µs/DIV  
4µs/DIV  
XXX  
XXX  
Figure 52. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ,  
Figure 49. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF,  
VS = 5 V, VREF = 2.5 V  
C
LOAD = 100 pF, VS = 5 V, VREF = 2.5 V  
Rev. B | Page 17 of 28  
AD8220  
15  
100  
10  
1
10  
SETTLED TO 0.001%  
SETTLED TO 0.001%  
SETTLED TO 0.01%  
5
SETTLED TO 0.01%  
0
0
5
10  
15  
20  
1
10  
100  
1000  
OUTPUT VOLTAGE STEP SIZE (V)  
GAIN (V/V)  
Figure 53. Settling Time vs. Output Voltage Step Size (G = 1) 15 V, VREF = 0 V  
Figure 54. Settling Time vs. Gain for a 10 V Step, VS = 15 V, VREF = 0 V  
Rev. B | Page 18 of 28  
AD8220  
THEORY OF OPERATION  
+V  
+V  
+V  
–V  
+V  
S
S
S
S
R
NODE A  
NODE B  
G
20kꢀ  
NODE F  
R2  
24.7kꢀ  
+V  
–V  
R1  
24.7kꢀ  
S
20kꢀ  
20kꢀ  
–V  
S
S
OUTPUT  
A3  
+V  
–V  
+V  
–V  
S
S
S
S
NODE E  
+V  
–V  
NODE C  
NODE D  
S
+IN  
J1  
V
Q2  
V
J2  
–IN  
Q1  
C1  
C2  
REF  
20kꢀ  
A1  
A2  
PINCH  
PINCH  
S
S
I
VB  
I
–V  
S
Figure 55. Simplified Schematic  
The AD8220 is a JFET input, monolithic instrumentation amplifier  
based on the classic 3-op amp topology (see Figure 55). Input  
Transistor J1 and Input Transistor J2 are biased at a fixed current so  
that any input signal forces the output voltages of A1 and A2 to  
change accordingly; the input signal creates a current through RG  
that flows in R1 and R2 such that the outputs of A1 and A2 provide  
the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2,  
and R2 can be viewed as precision current feedback amplifiers that  
have a gain bandwidth of 1.5 MHz. The common-mode voltage  
and amplified differential signal from A1 and A2 are applied to a  
difference amplifier that rejects the common-mode voltage but  
amplifies the differential signal. The difference amplifier employs  
20 kΩ laser-trimmed resistors that result in an in-amp with gain  
error less than 0.04%. New trim techniques were developed to  
ensure that CMRR exceeds 86 dB (G = 1).  
The AD8220 has extremely low load-induced nonlinearity. All  
amplifiers that comprise the AD8220 have rail-to-rail output  
capability for enhanced dynamic range. The input of the AD8220  
can amplify signals with wide common-mode voltages even  
slightly lower than the negative supply rail. The AD8220 operates  
over a wide supply voltage range. It can operate from either a  
single +4.5 ꢀ to +36 ꢀ supply or a dual 2.25 ꢀ to 18 ꢀ. The  
transfer function of the AD8220 is  
49.4 kΩ  
G 1  
RG  
Users can easily and accurately set the gain using a single,  
standard resistor. Because the input amplifiers employ a current  
feedback architecture, the AD8220 gain-bandwidth product  
increases with gain, resulting in a system that does not suffer as  
much bandwidth loss as voltage feedback architectures at higher  
gains. A unique pinout enables the AD8220 to meet a CMRR  
specification of 80 dB through 5 kHz (G = 1). The balanced  
pinout, shown in Figure 56, reduces parasitics that adversely  
affect CMRR performance. In addition, the new pinout  
simplifies board layout because associated traces are grouped  
together. For example, the gain setting resistor pins are adjacent  
to the inputs, and the reference pin is next to the output.  
Using JFET transistors, the AD8220 offers an extremely high  
input impedance, extremely low bias currents of 10 pA  
maximum, a low offset current of 0.6 pA maximum, and no  
input bias current noise. In addition, input offset is less than  
125 μꢀ and drift is less than 5 μꢀ/°C. Ease of use and robustness  
were considered. A common problem for instrumentation  
amplifiers is that at high gains, when the input is overdriven,1  
an excessive milliampere input bias current can result and the  
output can undergo phase reversal. The AD8220 has none of  
these problems; its input bias current is limited to less than  
10 μA, and the output does not phase reverse under overdrive  
fault conditions.  
AD8220  
1
2
3
4
8
7
6
5
–IN  
+V  
S
R
R
V
OUT  
G
G
REF  
–V  
+IN  
1 Overdriving the input at high gains refers to when the input signal is within  
the supply voltages but the amplifier cannot output the gained signal. For  
example, at a gain of 100, driving the amplifier with 10 V on 15 V constitutes  
overdriving the inputs since the amplifier cannot output 100 V.  
S
TOP VIEW  
(Not to Scale)  
Figure 56. Pin Configuration  
Rev. B | Page 19 of 28  
 
 
 
AD8220  
gain setting resistor to the RG pins should be kept as short as  
possible to minimize parasitic inductance. An example layout is  
shown in Figure 57 and Figure 58. To ensure the most accurate  
output, the trace from the REF pin should either be connected to  
the AD8220 local ground (see Figure 59) or connected to a  
voltage that is referenced to the AD8220 local ground.  
GAIN SELECTION  
Placing a resistor across the RG terminals sets the AD8220 gain,  
which can be calculated by referring to Table 5 or by using the  
gain equation  
49.4 kΩ  
RG   
G 1  
Common-Mode Rejection Ratio (CMRR)  
Table 5. Gains Achieved Using 1% Resistors  
The AD8220 has high CMRR over frequency giving it greater  
immunity to disturbances, such as line noise and its associated  
harmonics, in contrast to typical in-amps whose CMRR falls off  
around 200 Hz. These in-amps often need common-mode  
filters at the inputs to compensate for this shortcoming. The  
AD8220 is able to reject CMRR over a greater frequency range,  
reducing the need for input common-mode filtering.  
1% Standard Table Value of RG (Ω)  
Calculated Gain  
49.9 k  
12.4 k  
5.49 k  
2.61 k  
1.00 k  
499  
1.990  
4.984  
9.998  
19.93  
50.40  
100.0  
A well-implemented layout helps to maintain the high CMRR  
over frequency of the AD8220. Input source impedance and  
capacitance should be closely matched. In addition, source  
resistance and capacitance should be placed as close to the  
inputs as possible.  
249  
199.4  
100  
495.0  
49.9  
991.0  
The AD8220 defaults to G = 1 when no gain resistor is used.  
Gain accuracy is determined by the absolute tolerance of RG.  
The TC of the external gain resistor increases the gain drift of  
the instrumentation amplifier. Gain error and gain drift are kept  
to a minimum when the gain resistor is not used.  
Grounding  
The output voltage of the AD8220 is developed with respect to  
the potential on the reference terminal. Care should be taken to  
tie REF to the appropriate local ground (see Figure 59).  
In mixed-signal environments, low level analog signals need to  
be isolated from the noisy digital environment. Many ADCs  
have separate analog and digital ground pins. Although it is  
convenient to tie both grounds to a single ground plane, the  
current traveling through the ground wires and PC board can  
cause a large error. Therefore, separate analog and digital  
ground returns should be used to minimize the current flow  
from sensitive points to the system ground.  
LAYOUT  
Careful board layout maximizes system performance. In  
applications that need to take advantage of the low input bias  
current of the AD8220, avoid placing metal under the input path  
to minimize leakage current. To maintain high CMRR over  
frequency, lay out the input traces symmetrically and lay out the  
traces of the RG resistor symmetrically. Ensure that the traces  
maintain resistive and capacitive balance; this holds for additional  
PCB metal layers under the input and RG pins. Traces from the  
Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board  
Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board  
Rev. B | Page 20 of 28  
 
 
 
 
 
AD8220  
REFERENCE TERMINAL  
INPUT BIAS CURRENT RETURN PATH  
The reference terminal, REF, is at one end of a 20 kΩ resistor  
(see Figure 55). The output of the instrumentation amplifier is  
referenced to the voltage on the REF terminal; this is useful  
when the output signal needs to be offset to voltages other than  
common. For example, a voltage source can be tied to the REF  
pin to level-shift the output so that the AD8220 can interface  
with an ADC. The allowable reference voltage range is a function of  
the gain, common-mode input, and supply voltages. The REF  
pin should not exceed either +ꢀS or −ꢀS by more than 0.5 ꢀ.  
The AD8220 input bias current is extremely small at less than  
10 pA. Nonetheless, the input bias current must have a return  
path to common. When the source, such as a transformer,  
cannot provide a return current path, one should be created  
(see Figure 60).  
+V  
S
For best performance, especially in cases where the output is  
not measured with respect to the REF terminal, source impedance  
to the REF terminal should be kept low, because parasitic  
resistance can adversely affect CMRR and gain accuracy.  
AD8220  
REF  
–V  
S
POWER SUPPLY REGULATION AND BYPASSING  
TRANSFORMER  
The AD8220 has high PSRR. However, for optimal  
performance, a stable dc voltage should be used to power  
the instrumentation amplifier. Noise on the supply pins can  
adversely affect performance. As in all linear circuits, bypass  
capacitors must be used to decouple the amplifier.  
+V  
S
C
C
A 0.1 μF capacitor should be placed close to each supply pin.  
A 10 μF tantalum capacitor can be used further away from the  
part (see Figure 59). In most cases, it can be shared by other  
precision integrated circuits.  
R
R
1
fHIGH-PASS  
=
2πRC  
AD8220  
REF  
+V  
S
–V  
S
0.1µF  
10µF  
AC-COUPLED  
Figure 60. Creating an IBIAS Path  
+IN  
–IN  
INPUT PROTECTION  
V
OUT  
AD8220  
All terminals of the AD8220 are protected against ESD.  
(ESD protection is guaranteed to 4 kꢀ, human body model.) In  
addition, the input structure allows for dc overload conditions  
a diode drop above the positive supply and a diode drop below  
the negative supply. ꢀoltages beyond a diode drop of the supplies  
cause the ESD diodes to conduct and enable current to flow  
through the diode. Therefore, an external resistor should be  
used in series with each of the inputs to limit current for  
voltages above +ꢀs. In either scenario, the AD8220 safely  
handles a continuous 6 mA current at room temperature.  
LOAD  
REF  
0.1µF  
10µF  
–V  
S
Figure 59. Supply Decoupling, REF and Output Referred to Ground  
For applications where the AD8220 encounters extreme  
overload voltages, as in cardiac defibrillators, external series  
resistors and low leakage diode clamps, such as BAꢀ199Ls,  
FJH1100s, or SP720s, should be used.  
Rev. B | Page 21 of 28  
 
 
 
 
 
 
AD8220  
+15V  
RF INTERFERENCE  
RF rectification is often a problem in applications where there are  
large RF signals. The problem appears as a small dc offset voltage.  
The AD8220 by its nature has a 5 pF gate capacitance, CG, at its  
inputs. Matched series resistors form a natural low-pass filter that  
reduces rectification at high frequency (see Figure 61). The  
relationship between external, matched series resistors and the  
internal gate capacitance is expressed as follows:  
0.1µF  
+IN  
10µF  
C
C
C
1nF  
C
D
C
R
4.02kꢀ  
V
OUT  
10nF  
1nF  
AD8220  
R
REF  
–IN  
4.02kꢀ  
1
FilterFreqDIFF  
2πRCG  
0.1µF  
10µF  
1
–15V  
FilterFreqCM  
2πRCG  
Figure 62. RFI Suppression  
+15V  
COMMON-MODE INPUT VOLTAGE RANGE  
The common-mode input voltage range is a function of the  
input range and the outputs of Internal Amplifier A1, Internal  
Amplifier A2, and Internal Amplifier A3, the reference voltage,  
and the gain. Figure 27 to Figure 30 show common-mode  
voltage ranges for various supply voltages and gains.  
0.1µF  
10µF  
+IN  
R
R
C
G
DRIVING AN ADC  
V
OUT  
AD8220  
–V  
An instrumentation amplifier is often used in front of an ADC  
to provide CMRR and additional conditioning, such as a voltage  
level shift and gain (see Figure 63). In this example, a 2.7 nF  
capacitor and a 1 kΩ resistor create an antialiasing filter for the  
AD7685. The 2.7 nF capacitor also serves to store and deliver  
the necessary charge to the switched capacitor input of the  
ADC. The 1 kΩ series resistor reduces the burden of the 2.7 nF  
load from the amplifier. However, large source impedance in  
front of the ADC can degrade THD.  
S
C
G
REF  
–V  
S
–IN  
0.1µF  
10µF  
–15V  
Figure 61. RFI Filtering Without External Capacitors  
The example shown in Figure 63 is for sub-60 kHz applications.  
For higher bandwidth applications where THD is important,  
the series resistor needs to be small. At worst, a small series  
resistor can load the AD8220, potentially causing the output to  
overshoot or ring. In such cases, a buffer amplifier, such as the  
AD8615, should be used after the AD8220 to drive the ADC.  
+5V  
To eliminate high frequency common-mode signals while using  
smaller source resistors, a low-pass RC network can be placed at  
the input of the instrumentation amplifier (see Figure 62). The  
filter limits the input signal bandwidth according to the following  
relationship:  
1
FilterFreqDIFF  
10µF  
0.1µF  
2πR(2 CD CC CG )  
ADR435  
+5V  
4.7µF  
1
FilterFreqCM  
+IN  
2πR(CC CG )  
1kꢀ  
±50mV  
1.07kꢀ  
AD8220  
Mismatched CC capacitors result in mismatched low-pass filters.  
The imbalance causes the AD8220 to treat what would have  
been a common-mode signal as a differential signal. To reduce  
the effect of mismatched external CC capacitors, select a value of  
CD greater than 10 times CC. This sets the differential filter  
frequency lower than the common-mode frequency.  
AD7685  
REF  
2.7nF  
–IN  
+2.5V  
Figure 63. Driving an ADC in a Low Frequency Application  
Rev. B | Page 22 of 28  
 
 
 
 
 
 
AD8220  
APPLICATIONS INFORMATION  
AC-COUPLED INSTRUMENTATION AMPLIFIER  
DIFFERENTIAL OUTPUT  
Measuring small signals that are in the noise or offset of the  
amplifier can be a challenge. Figure 64 shows a circuit that  
can improve the resolution of small ac signals. The large gain  
reduces the referred input noise of the amplifier to 14 nꢀ/√Hz.  
Therefore, smaller signals can be measured because the noise  
floor is lower. DC offsets that would have been gained by 100  
are eliminated from the AD8220 output by the integrator  
feedback network.  
In certain applications, it is necessary to create a differential  
signal. New high resolution ADCs often require a differential  
input. In other cases, transmission over a long distance can  
require differential processing for better immunity to  
interference.  
Figure 65 shows how to configure the AD8220 to output a  
differential signal. An OP1177 op amp is used to create a  
differential voltage. Errors from the op amp are common to  
both outputs and are thus common mode. Likewise, errors from  
using mismatched resistors cause a common-mode dc offset  
error. Such errors are rejected in differential signal processing  
by differential input ADCs or instrumentation amplifiers.  
At low frequencies, the OP1177 forces the AD8220 output to  
0 ꢀ. Once a signal exceeds fHIGH-PASS, the AD8220 outputs the  
amplified input signal.  
+V  
S
When using this circuit to drive a differential ADC, ꢀREF can be  
set using a resistor divider from the reference of the ADC to  
make the output ratiometric with the ADC as shown in Figure 66.  
0.1µF  
+IN  
R
1
fHIGH-PASS  
=
2πRC  
AD8220  
499ꢀ  
R
REF  
15.8kꢀ  
–IN  
C
1µF  
+V  
S
0.1µF  
0.1µF  
–V  
S
OP1177  
+V  
–V  
S
S
V
REF  
0.1µF  
–V  
10µF  
10µF  
S
Figure 64. AC-Coupled Circuit  
Rev. B | Page 23 of 28  
 
 
 
 
AD8220  
+15V  
AMPLITUDE  
0.1µF  
+IN  
+5V  
–5V  
TIME  
V
A = +V + V  
IN  
OUT  
REF  
2
AD8220  
±5V  
AMPLITUDE  
REF  
4.99kꢀ  
+5.0V  
+2.5V  
+0V  
–IN  
TIME  
TIME  
0.1µF  
AMPLITUDE  
+5.0V  
REF  
2.5V  
–15V  
+15V  
0.1µF  
–15V  
OP1177  
+5V  
4.99kꢀ  
V
+2.5V  
+0V  
0.1µF  
10µF  
V
B = –V + V  
IN  
OUT  
REF  
2
Figure 65. Differential Output with Level Shift  
+15V  
0.1µF  
+IN  
TIME  
V
A = +V + V  
IN  
OUT  
REF  
2
±5V  
AD8220  
+5V FROM REFERENCE  
TO 0V TO +5V ADC  
+5V FROM REFERENCE  
REF  
4.99kꢀ  
–IN  
REF  
V
2.5V  
4.99kꢀ  
4.99kꢀ  
REF  
+AIN  
0.1µF  
–AIN  
10nF  
–15V  
+15V  
–15V  
OP1177  
+5V  
4.99kꢀ  
0.1µF  
0.1µF  
10µF  
TO 0V TO +5V ADC  
V
B = –V + V  
IN  
OUT  
REF  
2
Figure 66. Configuring the AD8220 to Output A Ratiometric, Differential Signal  
Rev. B | Page 24 of 28  
 
 
AD8220  
In addition, the AD8220 JFET inputs have ultralow input  
ELECTROCARDIOGRAM SIGNAL CONDITIONING  
bias current and no current noise, making it useful for ECG  
applications where there are often large impedances. The MSOP  
and the optimal pinout of the AD8220 allow smaller footprints  
and more efficient layout, paving the way for next-generation  
portable ECGs.  
The AD8220 makes an excellent input amplifier for next  
generation ECGs. Its small size, high CMRR over frequency,  
rail-to-rail output, and JFET inputs are well suited for this  
application. Potentials measured on the skin range from 0.2 mꢀ  
to 2 mꢀ. The AD8220 solves many of the typical challenges of  
measuring these body surface potentials. The high CMRR of  
the AD8220 helps reject common-mode signals that come in  
the form of line noise or high frequency EMI from equipment  
in the operating room. Its rail-to-rail output offers a wide  
dynamic range allowing for higher gains than would be possible  
using other instrumentation amplifiers. JFET inputs offer a  
large input capacitance of 5 pF. A natural RC filter is formed  
reducing high frequency noise when series input resistors are  
used in front of the AD8220 (see the RF Interference section).  
Figure 67 shows an example ECG schematic. Following the  
AD8220 is a 0.033 Hz high-pass filter, formed by the 4.7 μF  
capacitor and the 1 MΩ resistor, which removes the dc offset  
that develops between the electrodes. An additional gain of 50,  
provided by the AD8618, makes use of the 0 ꢀ to 5 ꢀ input  
range of the ADC. An active, fifth-order, low-pass Bessel filter  
removes signals greater than approximately 160 Hz. An OP2177  
buffers, inverts, and gains the common-mode voltage taken at  
the midpoint of the AD8220 gain setting resistors. This right-  
leg drive circuit helps cancel common-mode signals by  
inverting the common-mode signal and driving it back into the  
body. A 499 kΩ series resistor at the output of the OP2177  
limits the current driven into the body.  
G = +50  
1.18kꢀ 57.6kꢀ 14kꢀ  
LOW-PASS FIFTH ORDER FILTER AT 157Hz  
INSTRUMENTATION  
AMPLIFIER  
33nF  
68nF  
19.3kꢀ  
14.5kꢀ  
14kꢀ  
G = +14  
+5V  
–5V  
2.5V  
47nF  
2.2pF  
HIGH-PASS FILTER 0.033Hz  
+5V  
AD8220  
AD8618  
AD8618  
+5V  
15kꢀ  
AD7685  
ADC  
+5V  
AD8618  
+5V  
+5V  
A
B
10kꢀ  
500ꢀ  
24.9kꢀ  
19.3kꢀ  
14.5kꢀ  
4.12kꢀ  
10pF  
2.7nF  
+5V  
–5V  
24.9kꢀ  
4.7µF  
4.7µF  
AD8618  
REF  
+5V  
1.15kꢀ  
4.99kꢀ  
10kꢀ  
220pF  
–5V  
1Mꢀ  
33nF  
22nF  
2.5V  
2.2pF  
+5V  
REFERENCE  
ADR435  
2.5V  
2.5V  
2.5V  
OP2177  
C
–5V  
OP AMPS  
12.7kꢀ  
68pF  
866kꢀ  
+5V  
499kꢀ  
OP2177  
–5V  
Figure 67. Example ECG Schematic  
Rev. B | Page 25 of 28  
 
 
AD8220  
OUTLINE DIMENSIONS  
3.20  
3.00  
2.80  
8
1
5
4
5.15  
4.90  
4.65  
3.20  
3.00  
2.80  
PIN 1  
IDENTIFIER  
0.65 BSC  
0.95  
0.85  
0.75  
15° MAX  
1.10 MAX  
0.80  
0.55  
0.40  
0.15  
0.05  
0.23  
0.09  
6°  
0°  
0.40  
0.25  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-187-AA  
Figure 68. 8-Lead Mini Small Outline Package [MSOP]  
(RM-8)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1, 2  
Temperature Range3  
Package Description  
Package Option  
RM-8  
RM-8  
RM-8  
RM-8  
RM-8  
RM-8  
RM-8  
RM-8  
Branding  
H01  
H01  
H01  
H0P  
H0P  
H0P  
Y2D  
Y2D  
AD8220ARMZ  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
8-Lead MSOP  
AD8220ARMZ-RL  
AD8220ARMZ-R7  
AD8220BRMZ  
AD8220BRMZ-RL  
AD8220BRMZ-R7  
AD8220WARMZ  
AD8220WARMZ-RL  
AD8220WARMZ-R7  
8-Lead MSOP, 13" Tape and Reel  
8-Lead MSOP, 7" Tape and Reel  
8-Lead MSOP  
8-Lead MSOP, 13" Tape and Reel  
8-Lead MSOP, 7" Tape and Reel  
8-Lead MSOP  
8-Lead MSOP, 13" Tape and Reel  
8-Lead MSOP, 7" Tape and Reel  
RM-8  
Y2D  
1 Z = RoHS Compliant Part.  
2 W = Qualified for Automotive Applications.  
3 See the Typical Performance Characteristics section for expected operation from 85°C to 125°C.  
AUTOMOTIVE PRODUCTS  
The AD8220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive  
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers  
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in  
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to  
obtain the specific Automotive Reliability reports for these models.  
Rev. B | Page 26 of 28  
 
 
 
AD8220  
NOTES  
Rev. B | Page 27 of 28  
AD8220  
NOTES  
©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D03579-0-5/10(B)  
Rev. B | Page 28 of 28  

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