AD8222HACPZ-RL [ADI]
Precision, Dual-Channel Instrumentation Amplifier; 精密，双通道仪表放大器
| 型号： | AD8222HACPZ-RL |
| 厂家： | 
ADI |
| 描述： | Precision, Dual-Channel Instrumentation Amplifier |
| 文件： | 总24页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, Dual-Channel
Instrumentation Amplifier
AD8222
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two channels in small 4 mm × 4 mm LFCSP
Gain set with 1 resistor per amplifier (G = 1 to 10,000)
Low noise
16 15 14 13
8 nV/√Hz at 1 kHz
0.25 μV p-p (0.1 Hz to 10 Hz)
AD8222
1
2
3
4
12
11
10
9
–IN1
RG1
RG1
+IN1
–IN2
RG2
RG2
+IN2
High accuracy dc performance (B grade)
60 μV maximum input offset voltage
0.3 μV/°C maximum input offset drift
1.0 nA maximum input bias current
126 dB minimum CMRR (G = 100)
Excellent ac performance
5
6
7
8
140 kHz bandwidth (G = 100)
13 μs settling time to 0.001%
Differential output option (single channel)
Fully specified
Adjustable common-mode output
Supply range: 2.3 V to 18 V
Figure 1. 4 mm × 4 mm LFCSP
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
AD8231
AD8290
AD8293
AD8553
AD8556
AD8557
AD620
AD621
AD524
AD526
AD624
AD8235
AD8236
AD627
AD8250
AD8251
AD8253
APPLICATIONS
Multichannel data acquisition for
ECG and medical instrumentation
Industrial process controls
Wheatstone bridge sensors
Differential drives for
AD623
AD8223
AD8226
AD8227
1 See www.analog.com for the latest selection of instrumentation amplifiers.
High resolution input ADCs
Remote sensors
GENERAL DESCRIPTION
The AD8222 maintains a minimum CMRR of 80 dB to 4 kHz
for all grades at G = 1. High CMRR over frequency allows the
AD8222 to reject wideband interference and line harmonics,
greatly simplifying filter requirements. The AD8222 also has a
typical CMRR drift over temperature of just 0.07 μV/V/°C at G = 1.
The AD8222 is a dual-channel, high performance instrumentation
amplifier that requires only one external resistor per amplifier
to set gains of 1 to 10,000.
The AD8222 is the first dual-instrumentation amplifier in the
small 4 mm × 4mm LFCSP. It requires the same board area as a
typical single instrumentation amplifier. The smaller package
allows a 2× increase in channel density and a lower cost per
channel, all with no compromise in performance.
The AD8222 operates on both single and dual supplies and only
requires 2.2 mA maximum supply current for both amplifiers.
It is specified over the industrial temperature range of −40°C to
+85°C and is fully RoHS compliant.
The AD8222 can also be configured as a single-channel, differen-
tial output instrumentation amplifier. Differential outputs provide
high noise immunity, which can be useful when the output
signal must travel through a noisy environment, such as with
remote sensors. The configuration can also be used to drive
differential input ADCs.
For a single-channel version, see the AD8221.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.
AD8222
TABLE OF CONTENTS
Features .............................................................................................. 1
Package Considerations............................................................. 16
Layout .......................................................................................... 16
Input Bias Current Return Path ............................................... 17
Input Protection ......................................................................... 18
RF Interference ........................................................................... 18
Common-Mode Input Voltage Range..................................... 18
Applications Information.............................................................. 19
Differential Output .................................................................... 19
Driving a Differential Input ADC............................................ 20
Precision Strain Gage................................................................. 20
Driving Cabling.......................................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Amplifier Architecture .............................................................. 15
Gain Selection............................................................................. 15
Reference Terminal .................................................................... 16
REVISION HISTORY
2/10—Rev. 0 to Rev. A
Changes to Reference Terminal Section, Figure 45, and Package
Considerations Section.................................................................. 16
Deleted Thermal Pad Section ....................................................... 16
Added Package Without Thermal Pad and Package with
Thermal Pad Sections .................................................................... 16
Changes to Figure 46...................................................................... 17
Deleted Solder Wash Section........................................................ 17
Changes to RFI and Antialising Filter Section ........................... 20
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide.......................................................... 23
Added LFCSP_VQ, CP-16-13 Package............................Universal
Changes to Features Section and Table 1 ...................................... 1
Changed VIN+ to V+IN, VIN− to V−IN, and T to TA Throughout..... 3
Change to Reference Input Parameter, Table 2............................. 4
Changed Output Short-Circuit Current to Output Short-Circuit
Duration, Table 5 .............................................................................. 6
Changes to Thermal Resistance Section and Table 6................... 6
Changes to Figure 2.......................................................................... 7
Changes to Figure 19...................................................................... 10
Changes to Figure 43...................................................................... 14
7/06—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8222
SPECIFICATIONS
VS = 15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Single-Ended and Differential1 Output Configuration
A Grade
Typ
B Grade
Typ
Parameter
Conditions
CM = –10 V to +10 V
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION
RATIO (CMRR)
V
CMRR DC to 60 Hz
G = 1
G = 10
G = 100
G = 1000
1 kΩ source imbalance
80
86
dB
dB
dB
dB
100
120
130
106
126
140
CMRR at 4 kHz
G = 1
80
80
dB
G = 10
G = 100
G = 1000
90
100
100
100
110
110
dB
dB
dB
CMRR Drift
NOISE
TA = −40°C to +85°C, G = 1
0.07
0.07
μV/V/°C
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
RTI noise = √(eNI2 + (eNO/G)2)
V+IN, V−IN, VREF = 0 V
V+IN, V−IN, VREF = 0 V
8
75
8
75
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
2
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
0.25
40
6
0.5
0.25
40
6
f = 1 kHz
f = 0.1 Hz to 10 Hz
RTI VOS = (VOSI) + (VOSO/G)
VS = 5 V to 15 V
TA = −40°C to +85°C
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
120
150
0.4
500
0.8
9
60
80
0.3
350
0.5
5
μV
μV
μV/°C
μV
mV
VS = 5 V to 15 V
TA = −40°C to +85°C
μV/°C
Offset RTI vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
VS = 2.3 V to 18 V
90
110
120
130
140
94
110
130
140
150
dB
dB
dB
dB
110
124
130
114
130
140
INPUT CURRENT (PER CHANNEL)
Input Bias Current, IBIAS
Over Temperature
Average TC
Input Offset Current, IOFFSET
Over Temperature
Average TC
0.5
2.0
3.0
0.2
1.0
1.5
nA
nA
pA/°C
nA
nA
TA = −40°C to +85°C
TA = −40°C to +85°C
1
0.2
1
0.1
1
1.5
0.5
0.6
2
1
0.5
pA/°C
Rev. A | Page 3 of 24
AD8222
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
−VS
1
Max
Min
−VS
1
Max
Unit
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
GAIN
20
50
20
50
kΩ
μA
V
V/V
%
V+IN, V−IN, VREF = 0 V
60
+VS
60
+VS
1
0.01
1
0.01
G = 1 + (49.4 kΩ/RG)
VOUT 10 V
Gain Range
Gain Error
10000
10000
V/V
G = 1
G = 10
G = 100
G = 1000
0.05
0.3
0.3
0.02
0.15
0.15
0.15
%
%
%
%
0.3
Gain Nonlinearity
G = 1
G = 10
VOUT = –10 V to +10 V
3
7
7
10
20
20
1
7
7
5
20
20
ppm
ppm
ppm
G = 100
Gain vs. Temperature
G = 1
G > 12
3
10
−50
2
5
−50
ppm/°C
ppm/°C
INPUT
Input Impedance
Differential
100||2
100||2
100||2
100||2
GΩ||pF
GΩ||pF
V
V
V
V
Common Mode
Input Operating Voltage Range3
Over Temperature
Input Operating Voltage Range3
Over Temperature
OUTPUT
VS = 2.3 V to 5 V
TA = −40°C to +85°C
VS = 5 V to 18 V
TA = −40°C to +85°C
RL = 10 kΩ
−VS + 1.9
−VS + 2.0
−VS + 1.9
−VS + 2.0
+VS − 1.1 −VS + 1.9
+VS − 1.2 −VS + 2.0
+VS − 1.2 −VS + 1.9
+VS − 1.2 −VS + 2.0
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current (per Amplifier)
Over Temperature
TEMPERATURE RANGE
Specified Performance
Operational4
VS = 2.3 V to 5 V
TA = −40°C to +85°C
VS = 5 V to 18 V
TA = −40°C to +85°C
−VS + 1.1
−VS + 1.4
−VS + 1.2
−VS + 1.6
+VS − 1.2 −VS + 1.1
+VS − 1.3 −VS + 1.4
+VS − 1.4 −VS + 1.2
+VS − 1.5 −VS + 1.6
+VS − 1.2
+VS − 1.3
+VS − 1.4
+VS − 1.5
V
V
V
V
18
18
mA
VS = 2.3 V to 18 V
TA = −40°C to +85°C
2.3
18
1.1
2.3
18
1.1
1.2
V
mA
mA
0.9
1
0.9
1
1.2
−40
−40
+85
+125
−40
−40
+85
+125
°C
°C
1 Refers to differential configuration shown in Figure 49.
2 Does not include the effects of external resistor, RG.
3 One input grounded. G = 1.
4 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C.
Rev. A | Page 4 of 24
AD8222
VS = 15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, unless otherwise noted.
Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers)
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
1200
750
140
15
1200
750
140
15
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
Settling Time 0.01%
G = 1 to 100
G = 1000
Settling Time 0.001%
G = 1 to 100
G = 1000
10 V step
10 V step
10
80
10
80
μs
μs
13
110
2
13
110
2
μs
μs
Slew Rate
G = 1
G = 5 to 1000
1.5
2
1.5
2
V/μs
V/μs
2.5
2.5
Table 4. Differential Output Configuration1—Dynamic Performance
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
1000
650
140
15
1000
650
140
15
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1 to 100
G = 1000
Settling Time 0.001%
G = 1 to 100
G = 1000
10 V step
10 V step
15
80
15
80
μs
μs
18
110
2
18
110
2
μs
μs
Slew Rate
G = 1
G = 5 to 1000
1.5
2
1.5
2
V/μs
V/μs
2.5
2.5
1 Refers to differential configuration shown in Figure 49.
Rev. A | Page 5 of 24
AD8222
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
Parameter
Rating
Table 6.
Package
Supply Voltage
18 V
Indefinite
VS
VS
−65°C to +130°C
−40°C to +125°C
130°C
θJA
86
48
Unit
°C/W
°C/W
Output Short-Circuit Current Duration
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range
Operational Temperature Range
Package Glass Transition Temperature (TG)
ESD
CP-16-19: LFCSP Without Thermal Pad
CP-16-13: LFCSP with Thermal Pad
The θJA values in Table 6 assume a 4-layer JEDEC standard
board. For the LFCSP with thermal pad, it is assumed that the
thermal pad is soldered to a landing on the PCB board, with the
landing thermally connected to a heat dissipating power plane.
θJC at the exposed pad is 4.4°C/W.
Human Body Model
Charge Device Model
1 kV
1 kV
Maximum Power Dissipation
The maximum safe power dissipation for the AD8222 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
ESD CAUTION
Rev. A | Page 6 of 24
AD8222
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
12
11
10
9
–IN1 1
RG1 2
RG1 3
+IN1 4
–IN2
RG2
RG2
+IN2
INDICATOR
AD8222
TOP VIEW
NOTES
1. THE AD8222 COMES IN TWO PACKAGE TYPES—EACH A 16 LEAD
4mm × 4mm LFCSP. ONE PACKAGE TYPE HAS AN EXPOSED
THERMAL PAD, WHICH IS CONNECTED TO –V . THE OTHER
S
PACKAGE TYPE DOES NOT EXPOSE THE THERMAL PAD. SEE THE
PACKAGE CONSIDERATIONS SECTION FOR MORE INFORMATION.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No
Mnemonic
−IN1
RG1
RG1
+IN1
+VS
Description
1
2
3
4
Negative Input In-Amp 1
Gain Resistor In-Amp 1
Gain Resistor In-Amp 1
Positive Input In-Amp 1
Positive Supply
5
6
7
8
REF1
REF2
−VS
Reference Adjust In-Amp 1
Reference Adjust In-Amp 2
Negative Supply
9
+IN2
RG2
RG2
−IN2
−VS
OUT2
OUT1
+VS
Positive Input In-Amp 2
Gain Resistor In-Amp 2
Gain Resistor In-Amp 2
Negative Input In-Amp 2
Negative Supply
Output In-Amp 2
Output In-Amp 1
Positive Supply
10
11
12
13
14
15
16
Rev. A | Page 7 of 24
AD8222
TYPICAL PERFORMANCE CHARACTERISTICS
N = 1713
500
800
600
400
200
0
400
300
200
100
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
CMRR (µV/V)
I
(nA)
OFFSET
Figure 6. Typical Distribution of Input Offset Current
Figure 3. Typical Distribution for CMRR (G = 1)
15
10
5
N = 1713
300
250
200
150
100
10
V
= ±15V
S
0
V
= ±5V
S
–5
–10
–15
0
–100 80
60
40
20
0
20
40
60
80
100
–15
–10
–5
0
5
10
15
V
(µV)
OSI
OUTPUT VOLTAGE (V)
Figure 4. Typical Distribution of Input Offset Voltage
Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1
15
10
N = 1713
700
600
500
400
300
200
100
0
V
= ±15V
S
5
0
V
= ±5V
S
–5
–10
–15
–15
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–10
–5
0
5
10
15
I
(nA)
BIAS
OUTPUT VOLTAGE (V)
Figure 5. Typical Distribution of Input Bias Current
Figure 8. Input Common-Mode Range vs. Output Voltage, G = 100
Rev. A | Page 8 of 24
AD8222
200
150
100
50
160
150
140
130
120
110
100
90
BANDWIDTH
LIMITED
V
= ±15V
= ±5V
S
GAIN = 1000
0
80
GAIN = 100
GAIN = 10
GAIN = 1
V
70
S
–50
–100
–150
–200
60
50
40
30
20
10
0
–15
–10
–5
0
5
10
15
0.1
1
10
100
1k
10k
100k
1M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 12. Positive PSRR vs. Frequency, RTI (G = 1 to 1000)
Figure 9. IBIAS vs. Common-Mode Voltage
160
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
150
140
130
120
110
100
90
GAIN = 1000
GAIN = 100
80
70
60
50
40
GAIN = 10
GAIN = 1
30
20
10
0
0.1
1
10
100
1k
10k
100k
1M
0
2
4
6
8
10
FREQUENCY (Hz)
WARM-UP TIME (Minutes)
Figure 10. Change in Input Offset Voltage vs. Warm-Up Time
Figure 13. Negative PSRR vs. Frequency, RTI (G = 1 to 1000)
1000
10k
800
600
NEGATIVE
1k
100
10
400
GAIN = 1
GAIN = 10 GAIN = 100
200
POSITIVE
0
OFFSET CURRENT
–200
–400
–600
–800
–1000
GAIN = 1000
1
–55
–35
–15
5
25
45
65
85
105
125
1
10
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
SOURCE RESISTANCE (Ω)
Figure 11. Input Bias Current and Offset Current vs. Temperature
Figure 14. Total Drift vs. Source Resistance
Rev. A | Page 9 of 24
AD8222
70
20
15
GAIN = 1000
60
50
GAIN = 100
GAIN = 10
GAIN = 1
10
40
30
5
EXAMPLE PART 1
EXAMPLE PART 2
20
0
10
–5
0
–10
–20
–30
–40
–10
–15
–20
100
1k
10k
100k
1M
10M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Gain vs. Frequency
Figure 18. ΔCMR vs. Temperature, G = 1
160
150
140
130
120
110
100
90
+V –0
S
GAIN = 1000
GAIN = 100
–0.4
–0.8
–1.2
–1.6
–2.0
FROM +V
S
GAIN = 10
GAIN = 1
BANDWIDTH
LIMITED
+2.0
+1.6
+1.2
+0.8
+0.4
FROM –V
S
80
70
60
50
–V +0
S
40
0.1
2
6
10
SUPPLY VOLTAGE (V)
14
18
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 16. CMRR vs. Frequency, RTI
Figure 19. Input Voltage Limit vs. Supply Voltage, G = 1
160
150
140
130
120
110
100
90
+V –0
S
GAIN = 1000
–0.4
–0.8
–1.2
–1.6
R
L
= 10kΩ
GAIN = 100
GAIN = 10
R
R
= 2kΩ
= 2kΩ
L
BANDWIDTH
LIMITED
+1.6
+1.2
+0.8
+0.4
L
80
70
GAIN = 1
60
R
L
= 10kΩ
50
–V +0
S
40
0.1
2
6
10
14
18
1
10
100
1k
10k
100k
1M
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
Figure 17. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
Figure 20. Output Voltage Swing vs. Supply Voltage, G = 1
Rev. A | Page 10 of 24
AD8222
30
20
10
0
40
30
20
2kΩ LOAD
10
0
600Ω LOAD
–10
–20
–30
–40
10kΩ LOAD
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1k
10k
V
(V)
LOAD RESISTANCE (Ω)
OUT
Figure 24. Gain Nonlinearity, G = 100
Figure 21. Output Voltage Swing vs. Load Resistance
1k
100
10
+V –0
S
–1
–2
–3
SOURCING
GAIN = 1
GAIN = 10
GAIN = 100
+3
+2
+1
GAIN = 1000
SINKING
GAIN = 1000
BW LIMIT
1
–V +0
S
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (Hz)
OUTPUT CURRENT (mA)
Figure 25. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)
Figure 22. Output Voltage Swing vs. Output Current, G = 1
4
3
2
1
10kΩ LOAD
0
2kΩ LOAD
–1
600Ω LOAD
–2
–3
–4
2µV/DIV
1s/DIV
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
(V)
OUT
Figure 23. Gain Nonlinearity, G = 1
Figure 26. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Rev. A | Page 11 of 24
AD8222
30
25
20
15
10
5
GAIN = 10, 100, 1000
GAIN = 1
0
1k
0.1µV/DIV
1s/DIV
10k
100k
FREQUENCY (Hz)
1M
Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 30. Large Signal Frequency Response
1k
100
10
5V/DIV
7.4µs TO 0.01%
8.3µs TO 0.001%
0.002%/DIV
20µs/DIV
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 31. Large Signal Pulse Response and Settling Time (G = 1)
Figure 28. Current Noise Spectral Density vs. Frequency
5V/DIV
4.8µs TO 0.01%
6.6µs TO 0.001%
0.002%/DIV
20µs/DIV
5pA/DIV
1s/DIV
Figure 32. Large Signal Pulse Response and Settling (G = 10)
Figure 29. 0.1 Hz to 10 Hz Current Noise
Rev. A | Page 12 of 24
AD8222
5V/DIV
9.2µs TO 0.01%
16.2µs TO 0.001%
0.002%/DIV
20mV/DIV
4µs/DIV
20µs/DIV
Figure 33. Large Signal Pulse Response and Settling Time (G = 100)
Figure 36. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF
5V/DIV
83µs TO 0.01%
112µs TO 0.001%
0.002%/DIV
20mV/DIV
10µs/DIV
200µs/DIV
Figure 34. Large Signal Pulse Response and Settling Time (G = 1000)
Figure 37. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF
20mV/DIV
4µs/DIV
20mV/DIV
100µs/DIV
Figure 38. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF
Figure 35. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF
Rev. A | Page 13 of 24
AD8222
15
60
40
GAIN = 1000
GAIN = 100
10
20
SETTLED TO 0.001%
GAIN = 10
GAIN = 1
0
SETTLED TO 0.01%
5
–20
–40
0
0
5
10
15
20
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE STEP SIZE (V)
FREQUENCY (Hz)
Figure 39. Settling Time vs. Step Size (G = 1)
Figure 42. Differential Output Configuration: Gain vs. Frequency
1k
100
10
100
V
DIFF_OUT
OUTPUT BALANCE = 20 log
90
80
70
60
50
40
30
20
10
0
V
CM_OUT
LIMITED BY
MEASUREMENT
SYSTEM
SETTLED TO 0.001%
SETTLED TO 0.01%
1
1
10
100
1k
1
10
100
1k
10k
100k
1M
GAIN
FREQUENCY (Hz)
Figure 40. Settling Time vs. Gain for a 10 V Step
Figure 43. Differential Output Configuration:
Output Balance vs. Frequency
200
SOURCE
= 20V p-p
SOURCE V
OUT
SMALLER TO
V
OUT
AVOID SLEW
RATE LIMIT
180
160
140
120
100
80
GAIN = 1000
THERMAL CROSSTALK
VARIES WITH LOAD
GAIN = 1
60
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 41. Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1
Rev. A | Page 14 of 24
AD8222
THEORY OF OPERATION
V
I
I
B
A1
A2
I
COMPENSATION
I
COMPENSATION
B
B
10kΩ
C1
C2
+V
–V
S
10kΩ
10kΩ
OUTPUT
A3
+V
–V
S
+V
S
+V
–V
R1 24.7kΩ
R2 24.7kΩ
+V
S
S
400Ω
+V
400Ω
S
S
Q2
–IN
Q1
+IN
REF
10kΩ
R
G
–V
S
S
S
–V
–V
S
S
Figure 44. Simplified Schematic
AMPLIFIER ARCHITECTURE
GAIN SELECTION
The two instrumentation amplifiers of the AD8222 are based
on the classic 3-op-amp topology. Figure 44 shows a simplified
schematic of one of the amplifiers. The input transistors, Q1
and Q2, are biased at a fixed current. Any differential input
signal forces the output voltages of A1 and A2 to change so that
the differential voltage also appears across RG. The current that
flows through RG must also flow through R1 and R2, resulting
in a precisely amplified version of the differential input signal
between the outputs of A1 and A2. Topologically, Q1 + A1 + R1
and Q2 + A2 + R2 can be viewed as precision current feedback
amplifiers. The common-mode signal and the amplified differen-
tial signal are applied to a difference amplifier that rejects the
common-mode voltage. The difference amplifier employs innova-
tions that result in low output offset voltage as well as low output
offset voltage drift.
Placing a resistor across the RG terminals sets the gain of the
AD8222, which can be calculated by referring to Table 8 or by
using the following gain equation:
49.4 kꢀ
RG
G 1
Table 8. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
1.990
4.984
9.998
19.93
50.40
100.0
249
199.4
Because the input amplifiers employ a current feedback architec-
ture, the gain-bandwidth product of the AD8222 increases
with gain, resulting in a system that does not suffer from the
expected bandwidth loss of voltage feedback architectures at
higher gains.
100
49.9
495.0
991.0
The AD8222 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8222’s specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
The transfer function of the AD8222 is
V
OUT = G(V+IN − V−IN) + VREF
where:
49.4 kꢀ
G 1
RG
Rev. A | Page 15 of 24
AD8222
Outline Dimensions section. This metal is connected to −VS
through the part. Because of a possibility of a short, vias should
not be placed underneath this exposed metal.
REFERENCE TERMINAL
The output voltage of an AD8222 channel is developed with
respect to the potential on the corresponding reference terminal.
Typically the reference terminal is connected to ground, but it
can also be driven with a voltage to offset the output signal. For
example, connect a voltage to the reference terminal to level-
shift the output so that the AD8222 can drive a single-supply
ADC. Both REF1 and REF2 are protected with ESD diodes and
should not exceed either +VS or −VS by more than 0.3 V.
Package with Thermal Pad
This package is included primarily for legacy reasons. Because
the AD8222 dissipates so little power, there is little need for the
thermal pad.
The thermal pad is connected internally to −VS. The pad can
either be left unsoldered, soldered to an otherwise unconnected
PCB landing, or soldered to a landing connected to the negative
supply rail (−VS). If pin compatibility with the AD8224 is
desired, the pad should not be electrically connected to any net,
including −VS.
For best performance, source impedance to a reference terminal
should be kept below 1 ꢀ. As shown in Figure 44, the reference
terminal is at one end of a 10 kꢀ resistor. Additional impedance
at the reference terminal adds to this 10 kꢀ resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional RREF can be computed by
The solder process can leave flux and other contaminants on
the board. When these contaminants are between the AD8222
leads and thermal pad, they can create leakage paths that are
larger than the AD8222’s bias currents. A thorough washing
process removes these contaminants and restores the AD8222’s
excellent bias current performance.
2
10 kꢀ RREF
20 kꢀ RREF
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the amplifier’s
CMRR.
LAYOUT
INCORRECT
CORRECT
CORRECT
The AD8222 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout. The AD8222 pinout is arranged in a
logical manner to aid in this task.
AD8222
REF
AD8222
AD8222
REF
REF
V
V
Common-Mode Rejection Over Frequency
V
The AD8222 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances, such
as line noise and its associated harmonics. A well-implemented
layout is required to maintain this high performance. Input
source impedances should be matched closely. Source resistance
should be placed close to the inputs so that it interacts with as
little parasitic capacitance as possible.
+
+
AD8222
–
OP2177
–
Figure 45. Driving the Reference Pin
PACKAGE CONSIDERATIONS
The AD8222 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; the landing pattern may be different. Refer to
the Outline Dimensions section to verify that the PCB symbol
has the correct dimensions.
Parasitics at the RGx pins can also affect CMRR over frequency.
The PCB should be laid out so that the parasitic capacitances at
each pin match. Traces from the gain setting resistor to the RGx
pins should be kept short to minimize parasitic inductance.
Reference
The AD8222 comes in two package varieties, both with and
without a thermal pad.
Errors introduced at the reference terminal feed directly to the
output. Care should be taken to tie REF to the appropriate local
ground.
Package Without Thermal Pad
The AD8222 ships with a package that does not include a thermal
pad; it is the preferred package for the AD8222. Unlike chip
scale packages where the pad limits routing capability, the AD8222
package allows routes and vias directly underneath the chip, so
that the full space savings of the small LFCSP can be realized.
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
The AD8222 has two positive supply pins (Pin 5 and Pin 16)
and two negative supply pins (Pin 8 and Pin 13). Although the
part functions with only one pin from each supply pair connected,
Although the package has no metal in the center of the part, the
manufacturing process does leave a very small section of exposed
metal at each of the package corners, shown in Figure 55 in the
Rev. A | Page 16 of 24
AD8222
both pins should be connected for specified performance and
optimum reliability.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8222 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 47.
The AD8222 should be decoupled with 0.1 μF bypass capacitors,
one for each supply. The positive supply decoupling capacitor
should be placed near Pin 16, and the negative supply decoupl-
ing capacitor should be placed near Pin 8. Each supply should
also be decoupled with a 10 μF tantalum capacitor. The tantalum
capacitor can be placed further away from the AD8222 and can
generally be shared by other precision integrated circuits. Figure
46 shows an example layout.
INCORRECT
+V
CORRECT
+V
S
S
AD8222
AD8222
REF
REF
REF
REF
–V
–V
S
S
0.1µF
TRANSFORMER
TRANSFORMER
+V
+V
S
S
16
15
14
13
AD8222
12
11
10
9
AD8222
AD8222
1
2
3
4
REF
R
R
G2
G1
10MΩ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
+V
+V
S
S
5
6
7
8
C
C
C
R
R
1
fHIGH-PASS
=
AD8222
2πRC
AD8222
C
REF
0.1µF
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 46. Example Layout
Figure 47. Creating an IBIAS Path
Rev. A | Page 17 of 24
AD8222
+15V
INPUT PROTECTION
All terminals of the AD8222 are protected against ESD (1 kV,
human body model). In addition, the input structure allows for
dc overload conditions of about 2.5 V beyond the supplies.
0.1µF
10µF
C
1nF
C
R
+IN
R1
4.02kΩ
Input Voltages Beyond the Rails
V
C
D
10nF
OUT
AD8222
499Ω
For larger input voltages, an external resistor should be used in
series with each input to limit current during overload conditions.
The AD8222 can safely handle a continuous 6 mA current. The
limiting resistor can be computed from
R
REF
–IN
4.02kΩ
C
C
1nF
0.1µF
10µF
VIN VSUPPLY
RLIMIT
400 ꢀ
–15V
6 mA
Figure 48. RFI Suppression
For applications in which the AD8222 encounters extreme over-
load voltages, such as cardiac defibrillators, external series
resistors and low leakage diode clamps, such as the BAV199L,
the FJH1100, or the SP720, should be used.
Figure 48 shows an example where the differential filter fre-
quency is approximately 2 kHz, and the common-mode filter
frequency is approximately 40 kHz.
Values of R and CC should be chosen to minimize RFI. Mismatch
between the R × CC at the positive input and the R × CC at
negative input degrades the CMRR of the AD8222. By using a
value of CD 10× larger than the value of CC, the effect of the
mismatch is reduced and performance is improved.
Differential Input Voltages at High Gains
When operating at high gain, large differential input voltages
can cause more than 6 mA of current to flow into the inputs.
This condition occurs when the differential voltage exceeds
the following critical voltage:
COMMON-MODE INPUT VOLTAGE RANGE
VCRITICAL = (400 + RG) × (6 mA)
The 3-op-amp architecture of the AD8222 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8222 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual
input and output signals are not. Figure 7 and Figure 8 show the
allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.
This is true for differential voltages of either polarity.
The maximum allowed differential voltage can be increased by
adding an input protection resistor in series with each input.
The value of each protection resistor should be
R
PROTECT = (VDIFF_MAX − VCRITICAL)/6 mA
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the input
of the instrumentation amplifier, as shown in Figure 48. The
filter limits the input signal bandwidth according to the
following relationship:
1
FilterFreqDiff
2 R(2CD CC)
1
FilterFreqCM
2 RCC
where CD ≥ 10CC.
Rev. A | Page 18 of 24
AD8222
APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
Setting the Common-Mode Voltage
The output common-mode voltage is set by the average of +IN2
and REF2. The transfer function is
The differential configuration of the AD8222 has the same
excellent dc precision specifications as the single-ended output
configuration and is recommended for applications in the
frequency range of dc to 100 kHz.
V
CM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2
+IN2 and REF2 have different properties that allow the
reference voltage to be easily set for a wide variety of applications.
+IN2 has high impedance but cannot swing to the supply rails
of the part. REF2 must be driven with a low impedance but can
go 300 mV beyond the supply rails.
The circuit configuration is shown in Figure 49. The differential
output specifications in Table 2 and Table 4 refer to this configura-
tion only. The circuit includes an RC filter that maintains the
stability of the loop.
The transfer function for the differential output is:
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-mode
output voltage of half the ADC reference voltage.
VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G
49.4 kꢀ
where G 1
RG
2-Channel Differential Output Using a Dual Op Amp
+IN
R
+
Another differential output topology is shown in Figure 50.
Instead of a second in-amp, ½ of a dual OP2177 op amp creates
the inverted output. Because the OP2177 is packaged in an
MSOP, this configuration allows the creation of a dual channel,
precision differential output in-amp with little board area.
+OUT
AD8222
–
G
10kΩ
–IN
–
100pF
AD8222
+
+IN2
Errors from the op amp are common to both outputs and are
thus common mode. Errors from mismatched resistors also
create a common-mode dc offset. Because these errors are
common mode, they will likely be rejected by the next device
in the signal chain.
REF2
–OUT
Figure 49. Differential Circuit Schematic
+IN
+OUT
AD8222
–IN
4.99kΩ
REF
V
REF
–
+
4.99kΩ
OP2177
–OUT
Figure 50. Differential Output Using Op Amp
Rev. A | Page 19 of 24
AD8222
+12V
+
10µF
0.1µF
+5V
100pF
NPO
5%
0.1µF
1kΩ
+IN
–IN
1kΩ
1kΩ
VDD
+OUT
–OUT
IN+
IN–
AD8222
AD7688
GND REF
1000pF
(DIFF OUT)
1kΩ
2200pF
2200pF
REF2
+IN2
100pF
NPO
5%
10µF
X5R
+12V
+5V REF
–12V
0.1µF
10µF
0.1µF
+
V
IN
V
+5V REF
OUT
0.1µF
ADR435
GND
Figure 51. Driving a Differential ADC
The 1 kΩ resistors can also protect an ADC from overvoltages.
Because the AD8222 runs on wider supply voltages than a
typical ADC, there is a possibility of overdriving the ADC. This
is not an issue with a PulSAR® converter, such as the AD7688.
Its input can handle a 130 mA overdrive, which is much higher
than the short-circuit limit of the AD8222. However, other conver-
ters have less robust inputs and may need the added protection.
DRIVING A DIFFERENTIAL INPUT ADC
The AD8222 can be configured in differential output mode
to drive a differential analog-to-digital converter. Figure 51
illustrates several of the concepts.
RFI and Antialiasing Filter
The 1 kΩ resistors, 1000 pF capacitor, and 100 pF capacitors in
front of the in-amp form filter circuitry that performs many
functions. The 1 kꢀ and 100 pF capacitors form common-mode
filters that protect the amplifier from incoming radio frequency
signals. Without the filtering, these RFI signals can be rectified
in the in-amp. The 1 kꢀ resistors provide some overvoltage
protection. The 1 kꢀ resistors and 1000 pF capacitor form a
76 kHz antialiasing filter for the ADC.
Reference
The ADR435 supplies a reference voltage to both the ADC and
the AD8222. Because REF2 on the AD8222 is grounded, the
common-mode output voltage is precisely half the reference
voltage, exactly where it needs to be for the ADC.
PRECISION STRAIN GAGE
Note that the 100 pF capacitors are 5% COG/NPO types. These
capacitors match well over time and temperature, which keeps
the system CMRR high over frequency.
The low offset and high CMRR over frequency of the AD8222
make it an excellent candidate for both ac and dc bridge measure-
ments. As shown in Figure 52, the bridge can be connected to
the inputs of the amplifier directly.
Second Antialiasing Filter
5V
A 1 kΩ resistor and 2200 pF capacitor are placed between each
AD8222 output and ADC input. They create a 72 kHz low-pass
filter for another stage of antialiasing protection.
10µF
0.1µF
350Ω
350Ω
350Ω
350Ω
+IN
–IN
+
These four elements also improve distortion performance. The
2200 pF capacitor provides charge to the switched capacitor
front end of the ADC, and the 1 kΩ resistor shields the AD8222
from driving any sharp current changes. If the application
requires a lower frequency antialiasing filter and is distortion
sensitive, increase the value of the capacitor rather than the
resistor.
R
AD8222
G
–
2.5V
Figure 52. Precision Strain Gauge
Rev. A | Page 20 of 24
AD8222
DRIVING CABLING
AD8222
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the cable
may cause peaking in the AD8222’s output response. To reduce
the peaking, use a resistor between the AD8222 and the cable.
Because cable capacitance and desired output response vary
widely, this resistor is best determined empirically. A good
starting point is 50 Ω.
(DIFF OUT)
AD8222
(SINGLE OUT)
The AD8222 operates at a low enough frequency that
transmission line effects are rarely an issue; therefore, the
resistor need not match the characteristic impedance of
the cable.
Figure 53. Driving a Cable
Rev. A | Page 21 of 24
AD8222
OUTLINE DIMENSIONS
0.50
0.40
0.30
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
12
13
16
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
3.75
BSC SQ
EXPOSED
PAD
4
8
5
0.65
BSC
9
0.25 MIN
TOP VIEW
1.95 BCS
BOTTOM VIEW
12° MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions are shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
13
12
16
5
1
4
0.65
BSC
PIN 1
INDICATOR
3.75
BCS SQ
1.95 REF
SQ
9
8
0.75
0.60
0.50
TOP VIEW
BOTTOM VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.35
0.30
0.25
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-263-VBBC
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle
CP-16-19
Dimensions shown in millimeters
Rev. A | Page 22 of 24
AD8222
ORDERING GUIDE
Temperature
Package
Option
Model1
Range
Product Description
Package Description
AD8222ACPZ-R7
−40°C to +85°C
Standard Grade with Thermal Pad
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], 7“ Tape and Reel
AD8222ACPZ-RL
AD8222ACPZ-WP
AD8222BCPZ-R7
AD8222BCPZ-RL
AD8222BCPZ-WP
AD8222HACPZ-R7
AD8222HACPZ-RL
AD8222HACPZ-WP
AD8222HBCPZ-R7
AD8222HBCPZ-RL
AD8222HBCPZ-WP
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Standard Grade with Thermal Pad
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], 13“Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], Waffle Pack
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], 7“ Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], 13” Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-13
[LFCSP_VQ], Waffle Pack
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], 7” Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], 13” Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], Waffle Pack
Standard Grade with Thermal Pad
High Performance Grade with Thermal Pad
High Performance Grade with Thermal Pad
High Performance Grade with Thermal Pad
Standard Grade Without Thermal Pad
Standard Grade Without Thermal Pad
Standard Grade Without Thermal Pad
High Performance Grade Without Thermal Pad
High Performance Grade Without Thermal Pad
High Performance Grade Without Thermal Pad
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], 7” Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], 13” Tape and Reel
16-Lead Lead Frame Chip Scale Package CP-16-19
[LFCSP_VQ], Waffle Pack
AD8222-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
AD8222
NOTES
©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05947-0-2/10(A)
Rev. A | Page 24 of 24
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