AD82241 [ADI]
10 MHz, 20 V/レs, G = 1, 10, 100, 1000 i CMOS㈢ Programmable Gain Instrumentation Amplifier; 10兆赫， 20 V / μs的，G = 1 ， 10 ， 100 ， 1000我CMOS®可编程增益仪表放大器
| 型号： | AD82241 |
| 厂家： | 
ADI |
| 描述： | 10 MHz, 20 V/レs, G = 1, 10, 100, 1000 i CMOS㈢ Programmable Gain Instrumentation Amplifier |
| 文件： | 总10页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS®
Programmable Gain Instrumentation Amplifier
Preliminary Technical Data
AD8253
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DGD
Small package: 10-lead MSOP
WR
A1
A0
Programmable gains: 1, 10, 100, 1000
Digital or pin-programmable gain setting
Wide supply: 5 V to 15 V
Logic
-IN
Excellent dc performance
High CMRR 120 dB , G = 100
Low gain drift: 10 ppm/°C
Low offset drift: 1.2 μV/°C , G = 1000
Excellent ac performance
Fast settling time: 615 ns to 0.001%
High slew rate: 20 V/ꢀs
OUT
+IN
AD8253
+VS
-VS
REF
Low distortion:
Figure 1.
High CMRR over frequency: 80 dB to 50 kHz
Low noise: 8 nV/√Hz, G = 1000
Low power: 4 mA
Table 1. Instrumentation and Difference Amplifiers by
Category
APPLICATIONS
High
Low
High
Mil
Low
Digital
Gain
Data acquisition
Biomedical analysis
Test and measurement
Performance Cost
Voltage Grade Power
AD82201
AD8221
AD8222
AD82241
AD6231
AD85531
AD6271 AD82311
AD628
AD629
AD620
AD621
AD524
AD526
AD624
AD8250
GENERAL DESCRIPTION
AD8251
AD85551
AD85561
AD85571
The AD8253 is an instrumentation amplifier with digitally
programmable gains that has GΩ input impedance, low output
noise, and low distortion making it suitable for interfacing with
sensors and driving high sample rate analog-to-digital converters
(ADCs). It has high bandwidth of 10 MHz, low THD and fast
settling time of 615 ns to 0.001%. Offset drift and gain drift are
specified to 1.2 μV/°C and 10 ppm/°C, respectively for G = 1000.
In addition to its wide input common voltage range, it boasts a
high common-mode rejection of 80 dB at G = 1 from dc to
50 kHz. The combination of precision dc performance coupled
with high speed capabilities make the AD8253 an excellent
candidate for data acquisition. Furthermore, this monolithic
solution simplifies design and manufacturing, and boosts
performance of instrumentation by maintaining a tight match
of internal resistors and amplifiers.
1 Rail-to-rail output.
The AD8253 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.
The AD8253 user interface consists of a parallel port that allows
users to set the gain in one of two different ways (see Figure 1
for the functional block diagram). A 2-bit word sent via a bus
WR
can be latched using the
input. An alternative is to use
transparent gain mode where the state of logic levels at the gain
port determines the gain.
Rev. prA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8253
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Maximum Power Dissipation......................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Theory of Operation .........................................................................8
Gain Selection................................................................................8
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. prA | Page 2 of 10
Preliminary Technical Data
AD8253
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance
+IN = −IN = −10 V to +10 V
G = 1
G = 10
G = 100
G = 1000
80
dB
dB
dB
dB
100
120
120
CMRR to 50 kHz
G = 1
G = 10
G = 100
G = 1000
+IN = −IN = −10 V to +10 V
80
dB
dB
dB
dB
NOISE
Voltage Noise, 1 kHz, RTI
G = 1
G = 10
G = 100
G = 1000
40
9
8
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
8
0.1 Hz to 10 Hz, RTI
G = 1
G = 10
G = 100
G = 1000
Current Noise, 1 kHz
Current Noise, 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Offset RTI VOS
Over Temperature
Average TC
Offset Referred to the Input vs. Supply (PSR)
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
2.5
2.5
μV p-p
μV p-p
μV p-p
μV p-p
pA/√Hz
pA p-p
5
60
G = 1, 10, 100, 1000
T = −40°C to +85°C
T = −40°C to +85°C
VS = 5 V to 15 V
200 + 600/G
260 + 900/G
1.2 + 5/G
μV
μV
μV/°C
μV/V
6 + 20/G
5
5
30
40
400
30
30
nA
nA
pA/°C
nA
nA
T = −40°C to +85°C
T = −40°C to +85°C
Input Offset Current
Over Temperature
Average TC
160
pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
10
6
3
MHz
MHz
MHz
MHz
G = 10
G = 100
G = 1000
0.3
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
ΔOUT = 10 V step
585
648
ns
ns
ns
ns
Rev. prA | Page 3 of 10
AD8253
Preliminary Technical Data
Parameter
Settling Time 0.001%
G = 1
Conditions
Min
Typ
Max
Unit
ΔOUT = 10 V step
615
685
ns
ns
ns
ns
G = 10
G = 100
G = 1000
Slew Rate
G = 1
G = 10
G = 100
G = 1000
20
25
25
25
V/μs
V/μs
V/μs
V/μs
dB
Total Harmonic Distortion
GAIN
f = 1 kHz, RL = 10 kΩ, G = 1
Gain Range
Gain Error
G = 1, 10, 100, 1000
OUT = 10 V
1
1000
V/V
G = 1
G = 10
G = 100
G = 1000
0.03
0.04
%
%
%
%
Gain Nonlinearity
G = 1
G = 10
G = 100
G = 1000
OUT = −10 V to +10 V
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
All gains
6
10
ppm
ppm
ppm
ppm
Gain vs. Temperature
INPUT
10
ppm/°C
Input Impedance
Differential
Common Mode
Input Operating Voltage Range
Over Temperature
OUTPUT
1
GΩ||pF
1
GΩ||pF
V
V
VS = 5 V to 15 V
T = −40°C to +85°C
−VS + 1.0
−VS + 1.1
+VS − 1.1
+VS − 1.4
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
−13.5
−13.5
+13.5
+13.5
V
V
mA
T = −40°C to +85°C
+IN, −IN, REF = 0
37
20
kΩ
μA
V
IIN
1
+VS
Voltage Range
Gain to Output
−VS
V/V
1
0
0.0001
DIGITAL LOGIC
Digital Ground Voltage, DGND
Digital Input Voltage Low
Digital Input Voltage High
Digital Input Current
Gain Switching Time1
tSU
Referred to GND
Referred to GND
Referred to GND
−VS + 4.25
DGND
2.8
+VS − 2.7
2.1
+VS
V
V
V
μA
ns
ns
ns
ns
ns
1
325
See Figure 2 timing diagram
20
10
20
40
tHD
t WR -LOW
t WR -HIGH
Rev. prA | Page 4 of 10
Preliminary Technical Data
AD8253
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current, +IS
Quiescent Current, −IS
Over Temperature
TEMPERATURE RANGE
Specified Performance
5
15
4.5
4.5
4.5
V
4.1
3.7
mA
mA
mA
T = −40°C to +85°C
−40
+85
°C
1 Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
tWR-HIGH
tWR-LOW
WR
tSU
tHD
A0, A1
Figure 2. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. prA | Page 5 of 10
AD8253
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3.
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
Parameter
Rating
17 V
Supply Voltage
Power Dissipation
See Figure 3
Indefinite1
VS
VS
VS
Output Short-Circuit Current
Common-Mode Input Voltage
Differential Input Voltage
Digital Logic Inputs
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
Storage Temperature Range
Operating Temperature Range2
Lead Temperature (Soldering 10 sec)
Junction Temperature
–65°C to +125°C
–40°C to +85°C
300°C
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
PD =
(
VS ×IS
)
+
×
–
2
RL
140°C
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
θJA (4-Layer JEDEC Standard Board)
Package GlassTransitionTemperature
112°C/W
140°C
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA.
1 Assumes the load is referenced to mid supply.
2 Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Error! Reference source not found. section.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8253 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8253. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
TJ =TA +
PD × θJA
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
Rev. prA | Page 6 of 10
Preliminary Technical Data
AD8253
differential input.
Digital Ground.
Negative Supply Terminal.
Gain Setting Pin (LSB).
Gain Setting Pin (MSB).
Write Enable.
PIN CONFIGURATION AND FUNCTION
DESCRIPTIONS
2
3
4
5
DGND
−VS
A0
A1
WR
6
-IN
DGND
-VS
1
2
3
4
5
10 +IN
7
8
9
10
OUT
+VS
REF
+IN
Output Terminal.
Positive Supply Terminal.
Reference Voltage Terminal.
Noninverting Input Terminal. True
differential input.
9
8
7
6
VREF
AD8253
+VS
TOP VIEW
(Not to Scale)
A0
VOUT
WR
A1
NC = NO CONNECT
Figure 4. 10-Lead MSOP (RM-10) Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Name
Description
1
−IN
Inverting Input Terminal. True
Rev. prA | Page 7 of 10
AD8253
Preliminary Technical Data
THEORY OF OPERATION
+V
–V
+V
–V
S
S
A0
A1
2.2kΩ
+V
–V
S
S
S
2.2kΩ
–IN
10kΩ
10kΩ
A1
S
+V
S
DIGITAL
GAIN
CONTROL
OUTPUT
A3
–V
+V
S
S
+V
–V
S
10kΩ
10kΩ
A2
REF
+IN
2.2kΩ
–V
S
+V
–V
+V
S
S
S
2.2kΩ
DGND
WR
–V
S
S
Figure 5. Simplified Schematic
The AD8253 is a monolithic instrumentation amplifier based
on the classic, three op amp topology as shown in Figure 5.
It is fabricated on the Analog Devices, Inc. proprietary iCMOS
process that provides precision, linear performance ,and a robust
digital interface. A parallel interface allows users to digitally
program gains of 1, 10, 100, and 1000. Gain control is achieved
by switching resistors in an internal, precision, resistor array (as
shown in Figure 5). Although the AD8253 has a voltage feed-
back topology, gain bandwidth product increases for gains of 1,
10, and 100 because each gain has its own frequency
compensation. This results in maximum bandwidth at higher
gains.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 6
shows an example of this gain setting method, referred to through-
WR
out the data sheet as transparent gain mode. Tie
to the
negative supply to engage transparent gain mode. In this mode,
any change in voltage applied to A0 and A1 from logic low to
logic high, or vice versa, immediately results in a gain change.
Table 5 is the truth table for transparent gain mode and Figure 6
shows the AD8253 configured in transparent gain mode.
All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser trimmed
resistors allow for a maximum gain error of less than 0.03% for
G = 1, and minimum CMRR of 120 dB for G = 1000. A pinout
optimized for high CMRR over frequency enables the AD8253
to offer CMRR over frequency of 80 dB at 50 kHz (G = 1). The
balanced input reduces the parasitics that, in the past, had
adversely affected CMRR performance.
GAIN SELECTION
This section shows users how to configure the AD8253 for basic
operation. Logic low and Logic high voltage limits are listed in
the Specifications section. Typically, logic low is 0 V and
logic high is 5 V; both voltages are measured with respect
to DGND. Refer to the specifications table (Table 2) for
the permissible voltage range of DGND. The gain of the
AD8253 can be set using two methods.
Figure 6. Transparent Gain Mode, A0 and A1 = High, G = 1000
Rev. prA | Page 8 of 10
Preliminary Technical Data
AD8253
Table 5. Truth Table Logic Levels for Transparent Gain Mode
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
WR
A1
A0
Gain
−VS
−VS
−VS
−VS
Low
Low
High
High
Low
High
Low
High
1
10
100
1000
High to Low
High to Low
High to Low
High to Low
Low to Low
Low to High
High to High
Low
Low
High
High
X1
Low
High
Low
High
X1
Change to 1
Change to 10
Change to 100
Change to 1000
No Change
X1
X1
No Change
No Change
Latched Gain Mode
X1
X1
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using
allowing other devices to share A0 and A1. Figure 7 shows a
schematic using this method, known as latched gain mode. The
1 X = don’t care.
Upon power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 upon power-up.
WR
as a latch,
WR
AD8253 is in this mode when
low, typically 5 V and 0 V, respectively. The voltages on A0 and
WR
is held at logic high or logic
Timing for Latched Gain Mode
A1 are read on the downward edge of the
signal as it
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, tSU, before the downward edge of
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table listing in Table 6 for more on these gain changes.
WR
latches in the gain. Similarly, they must be held for a
WR
minimum hold time of tHD after the downward edge of
to
ensure that the gain is latched in correctly. After tHD, A0 and A1
may change logic levels but the gain does not change (until the
WR
WR
next downward edge of
can be held high is t WR-HIGH, and t WR-LOW is the minimum
). The minimum duration that
WR
duration that
can be held low. Digital timing specifications
are listed in Table 2. The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in Figure 8.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
Figure 7. Latched Gain Mode, G = 1000
tWR-HIGH
tWR-LOW
WR
tSU
tHD
A0, A1
Figure 8. Timing Diagram for Latched Gain Mode
Rev. prA | Page 9 of 10
AD8253
Preliminary Technical Data
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 9. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8253ARMZ1
AD8253ARMZ-RL1
AD8253ARMZ-R71
AD8253-EVALZ1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
RM-10
RM-10
RM-10
Branding
Y0K
Y0K
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
–40°C to +85°C
Y0K
1 Z = RoHS compliant part.
Rev. PrA | Page 10 of 10
PR06983-0-9/07(PrA)
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