AD822BRZ-REEL [ADI]
Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp; 单电源，轨到轨低功耗FET输入运算放大器
| 型号： | AD822BRZ-REEL |
| 厂家： | 
ADI |
| 描述： | Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp |
| 文件： | 总28页 (文件大小：597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply, Rail-to-Rail
Low Power FET-Input Op Amp
AD822
FEATURES
CONNECTION DIAGRAM
True single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 3 V to 36 V
Dual-supply capability from 1.ꢀ V to 18 V
High load drive
8
7
6
5
OUT1
–IN1
+IN1
1
2
3
4
V+
OUT2
–IN2
V–
+IN2
AD822
Figure 1. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix);
and 8-Lead SOIC (R Suffix)
Capacitive load drive of 3ꢀ0 pF, G = +1
Minimum output current of 1ꢀ mA
Excellent ac performance for low power
800 μA maximum quiescent current per amplifier
Unity gain bandwidth: 1.8 MHz
Slew rate of 3.0 V/ꢁs
GENERAL DESCRIPTION
The AD822 is a dual precision, low power FET input op amp
that can operate from a single supply of 3.0 V to 36 V or dual
supplies of ±±.ꢀ V to ±±8 V. It has true single-supply capability
with an input voltage range extending below the negative rail,
allowing the AD822 to accommodate input signals below
ground in the single-supply mode. Output voltage swing
extends to within ±0 mV of each rail, providing the maximum
output dynamic range.
Good dc performance
800 μV maximum input offset voltage
2 μV/°C typical offset voltage drift
2ꢀ pA maximum input bias current
Low noise
13 nV/√Hz @ 10 kHz
100
10
1
No phase inversion
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems
Medical instrumentation
Low power references and regulators
10
100
FREQUENCY (Hz)
10k
1k
Figure 2. Input Voltage Noise vs. Frequency
Offset voltage of 800 μV maximum, offset voltage drift of 2 μV/°C,
input bias currents below 2ꢀ pA, and low input voltage noise
provide dc precision with source impedances up to a gigaohm. The
±.8 MHz unity gain bandwidth, –93 dB THD at ±0 kHz, and 3 V/μs
slew rate are provided with a low supply current of 800 μA per
amplifier.
(continued on Page 3)
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD822
TABLE OF CONTENTS
Features .............................................................................................. ±
Applications....................................................................................... ±
Functional Block Diagram .............................................................. ±
General Description......................................................................... ±
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Absolute Maximum Ratings.......................................................... ±2
Maximum Power Dissipation ................................................... ±2
ESD Caution................................................................................ ±2
Typical Performance Characteristics ........................................... ±3
Application Notes ........................................................................... 20
Input Characteristics.................................................................. 20
Output Characteristics............................................................... 20
Applications..................................................................................... 22
Single-Supply Voltage-to-Frequency Converter .................... 22
Single-Supply Programmable Gain Instrumentation
Amplifier ..................................................................................... 22
3 V, Single-Supply Stereo Headphone Driver......................... 23
Low Dropout Bipolar Bridge Driver........................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide............................................................................... 2ꢀ
Edits to Ordering Guide ...................................................................6
Updated SOIC Package Outline ................................................... ±7
REVISION HISTORY
6/06—Rev. F to Rev. G
Changes to Features.......................................................................... ±
Changes to Table 4.......................................................................... ±0
Changes to Table ꢀ.......................................................................... ±2
Changes to Table 6.......................................................................... 22
8/02—Data sheet changed from Rev. B to Rev. C
All Figures Updated ................................................................Global
Edits to Features.................................................................................±
Updated All Package Outlines...................................................... ±7
10/05—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Outline Dimensions................................................... 24
Updated Ordering Guide............................................................... 24
7/01—Data sheet changed from Rev. A to Rev. B
All Figures Updated ................................................................Global
CERDIP References Removed.......................................±, 6, and ±8
Additions to Product Description...................................................±
8-Lead SOIC and 8-Lead MSOP Diagrams Added ......................±
Deletion of AD822S Column...........................................................2
Edits to Absolute Maximum Ratings and Ordering Guide .........6
Removed Metalization Photograph ................................................6
1/03—Data sheet changed from Rev. D to Rev. E
Edits to Specifications ...................................................................... 2
Edits to Figure ±0............................................................................ ±6
Updated Outline Dimensions....................................................... ±7
10/02—Data sheet changed from Rev. C to Rev. D
Edits to Features................................................................................ ±
Rev. G | Page 2 of 28
AD822
GENERAL DESCRIPTION
(continued from Page 1)
The AD822 drives up to 3ꢀ0 pF of direct capacitive load as a
follower and provides a minimum output current of ±ꢀ mA.
This allows the amplifier to handle a wide range of load
conditions. Its combination of ac and dc performance, plus the
outstanding load drive capability, results in an exceptionally
versatile amplifier for the single-supply user.
1V
. . . . . . . .
20µs
. . . . . . . . . . . .
1V
. . . .
. . . . . . . . . . . . . . . .
100
90
5V
.
V
OUT
The AD822 is available in two performance grades. The A grade
and B grade are rated over the industrial temperature range of
−40°C to +8ꢀ°C.
10
. . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . .
0%
0V
(GND)
1V
The AD822 is offered in three varieties of 8-lead packages:
PDIP, MSOP, and SOIC.
Figure 3. Gain-of-2 Amplifier; VS = 5, 0, VIN = 2.5 V Sine Centered at 1.25 V,
RL = 100 Ω
Rev. G | Page 3 of 28
AD822
SPECIFICATIONS
VS = 0, ꢀ V @ TA = 2ꢀ°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted.
Table 1.
AD822 A Grade
AD822 B Grade
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
DC PERFORMANCE
Initial Offset
0.1
0.5
2
2
0.5
2
0.8
1.2
0.1
0.5
2
2
0.5
2
0.4
0.9
mV
mV
μV/°C
pA
nA
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
VCM = 0 V to 4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VO = 0.2 V to 4 V
RL = 100 kΩ
500
400
80
80
15
1000
150
30
500
400
80
80
15
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
25
21
16
13
25
21
16
13
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ to 2.5 V
VO = 0.25 V to 4.75 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.8
210
3
1.8
210
3
MHz
kHz
V/μs
VO p-p = 4.5 V
Settling Time
to 0.1%
to 0.01%
VO = 0.2 V to 4.5 V
1.4
1.8
1.4
1.8
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
1.0
1.6
0.5
1.3
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
3
3
20
10
RL = 5 kΩ
−130
−93
–130
–93
INPUT CHARACTERISTICS
Input Voltage Range1
TMIN to TMAX
−0.2
−0.2
66
+4
+4
−0.2
−0.2
69
+4
+4
V
V
dB
dB
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
VCM = 0 V to 2 V
VCM = 0 V to 2 V
80
80
66
66
Rev. G | Page 4 of 28
AD822
AD822 A Grade
AD822 B Grade
Parameter
Input Impedance
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL – VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
15
12
15
12
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.24
80
1.6
1.24
80
1.6
mA
dB
dB
VS+ = 5 V to 15 V
66
66
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. G | Page 5 of 28
AD822
VS = ±ꢀ V @ TA = 2ꢀ°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 2.
AD822 A Grade
AD822 B Grade
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
DC PERFORMANCE
Initial Offset
0.1
0.5
2
2
0.5
2
0.8
1.5
0.1
0.5
2
2
0.5
2
0.4
1
mV
mV
μV/°C
pA
nA
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
VCM = −5 V to +4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VO = −4 V to +4 V
RL = 100 kΩ
400
400
80
80
20
1000
150
30
400
400
80
80
20
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
25
21
16
13
25
21
16
13
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VO = 4.5 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
105
3
1.9
105
3
MHz
kHz
V/μs
VO p-p = 9 V
Settling Time
to 0.1%
to 0.01%
VO = 0 V to 4.5 V
1.4
1.8
1.4
1.8
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
1.0
3
0.5
2
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
3
3
25
10
RL = 5 kΩ
−130
−93
−130
−93
INPUT CHARACTERISTICS
Input Voltage Range1
TMIN to TMAX
−5.2
−5.2
66
+4
+4
−5.2
−5.2
69
+4
+4
V
V
dB
dB
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
VCM = –5 V to +2 V
VCM = –5 V to +2 V
80
80
66
66
Input Impedance
Differential
Common Mode
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Rev. G | Page 6 of 28
AD822
AD822 A Grade
AD822 B Grade
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
15
12
15
12
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.3
80
1.6
1.3
80
1.6
mA
dB
dB
VS+ = 5 V to 15 V
66
66
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. G | Page 7 of 28
AD822
VS = ±±ꢀ V @ TA = 2ꢀ°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 3.
AD822 A Grade
Typ
AD822 B Grade
Parameter
Conditions
Min
Max
Min
Typ
Max
Unit
DC PERFORMANCE
Initial Offset
0.4
0.5
2
2
3
0.3
0.5
2
1.5
2.5
mV
mV
μV/°C
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
VCM = 0 V
2
25
2
12
VCM = −10 V
VCM = 0 V
40
0.5
2
40
0.5
2
pA
nA
pA
nA
at TMAX
Input Offset Current
at TMAX
5
20
2.5
12
0.5
0.5
Open-Loop Gain
VO = +10 V to −10 V
RL = 100 kΩ
500
500
100
100
30
2000
500
45
500
500
100
100
30
2000
500
45
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
20
20
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
25
21
16
13
25
21
16
13
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VO = 10 V
−85
−85
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
45
3
1.9
45
3
MHz
kHz
V/μs
VO p-p = 20 V
Settling Time
to 0.1%
to 0.01%
VO = 0 V to 10 V
4.1
4.5
4.1
4.5
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
3
4
2
2.5
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
Crosstalk @ f = 1 kHz
f = 100 kHz
3
3
25
12
RL = 5 kΩ
−130
−93
−130
−93
INPUT CHARACTERISTICS
Input Voltage Range1
TMIN to TMAX
−15.2
−15.2
70
+14
+14
−15.2
−15.2
74
+4
+4
V
V
dB
dB
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
VCM = −15 V to +12 V
VCM = −15 V to +12 V
80
90
70
74
Rev. G | Page 8 of 28
AD822
AD822 A Grade
Typ
AD822 B Grade
Parameter
Input Impedance
Conditions
Min
Max
Min
Typ
Max
Unit
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
20
15
20
15
Capacitive Load Drive
POWER SUPPLY
Quiescent Current TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.4
80
1.8
1.4
80
1.8
mA
dB
dB
VS+ = 5 V to 15 V
70
70
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. G | Page 9 of 28
AD822
VS = 0, 3 V @ TA = 2ꢀ°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted.
Table 4.
Parameter
Conditions
Typ
Unit
DC PERFORMANCE
Initial Offset
0.2
0.5
1
2
0.5
2
mV
mV
μV/°C
pA
nA
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
VCM = 0 V to 2 V
0.5
nA
Open-Loop Gain
TMIN to TMAX
TMIN to TMAX
VO = 0.2 V to 2 V
RL = 100 kΩ
RL = 10 kΩ
1000
150
30
V/mV
V/mV
V/mV
TMIN to TMAX
RL = 1 kΩ
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
2
ꢀV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ to 1.5 V
VO = 1.25 V
−92
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.5
240
3
MHz
kHz
V/μs
VO p-p = 2.5 V
Settling Time
to 0.1%
to 0.01%
VO = 0.2 V to 2.5 V
1
1.4
μs
μs
MATCHING CHARACTERISTICS
Offset Drift
2
μV/°C
dB
dB
Crosstalk @ f = 1 kHz
f = 100 kHz
RL = 5 kΩ
−130
−93
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
VCM = 0 V to 1 V
74
dB
Input Impedance
Differential
Common Mode
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Rev. G | Page 10 of 28
AD822
Parameter
Conditions
Typ
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage1
VOL − VEE
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
ISOURCE = 2 mA
ISINK = 10 mA
ISOURCE = 10 mA
5
10
40
80
200
500
350
mV
mV
mV
mV
mV
mV
pF
VCC − VOH
VOL − VEE
VCC − VOH
VOL − VEE
VCC − VOH
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
TMIN to TMAX
1.24
80
mA
dB
Power Supply Rejection
TMIN to TMAX
VS+ = 3 V to 15 V
1 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Specifications are TMIN to TMAX
.
Rev. G | Page 11 of 28
AD822
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
Internal Power Dissipation1
PDIP (N)
18 V
Observe derating curves
Observe derating curves
SOIC (R)
Input Voltage
(+VS + 0.2 V) to
−(20 V + VS)
Output Short Circuit Duration
Differential Input Voltage
Storage Temperature Range (N)
Storage Temperature Range (R, RM)
Operating Temperature Range
AD822 A Grade and B Grade
Indefinite
30 V
–65°C to +125°C
–65°C to +150°C
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD822 is limited by the associated rise in junction temperature.
For plastic packages, the maximum safe junction temperature is
±4ꢀ°C. If these maximums are exceeded momentarily, proper
circuit operation is restored as soon as the die temperature is
reduced. Leaving the device in the overheated condition for an
extended period can result in device burnout. To ensure proper
operation, it is important to observe the derating curves shown
in Figure 27.
–40°C to +85°C
260°C
Lead Temperature Range
(Soldering, 60 sec)
1 8-lead PDIP package: θJA = 90°C/W.
8-lead SOIC package: θJA = 160°C/W.
8-lead MSOP package: θJA = 190°C/W.
While the AD822 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditions. With power
supplies ±±2 V (or less) at an ambient temperature of 2ꢀ°C or
less, if the output node is shorted to a supply rail, then the
amplifier is not destroyed, even if this condition persists for an
extended period.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. G | Page 12 of 28
AD822
TYPICAL PERFORMANCE CHARACTERISTICS
70
5
V
= 0V, 5V
S
60
50
40
30
20
10
0
V
= 0V, +5V AND ±5V
S
V
= ±5V
S
0
–5
–5
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
OFFSET VOLTAGE (mV)
Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and
VS = 5 V
Figure 4. Typical Distribution of Offset Voltage (390 Units)
1k
100
10
16
14
12
10
8
V
V
= ±5V
= ±15V
S
S
6
1
4
2
0.1
–16
0
–12
–8
–4
0
4
8
12
16
–12 –10 –8
–6
–4
–2
0
2
4
6
8
10
COMMON-MODE VOLTAGE (V)
OFFSET VOLTAGE DRIFT (µV/°C)
Figure 5. Typical Distribution of Offset Voltage Drift (100 Units)
Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = 15 V
50
45
40
35
30
25
20
15
10
5
100k
10k
1k
100
10
1
0
0.1
20
0
1
2
3
4
5
6
7
8
9
10
40
60
80
100
120
140
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
Figure 6. Typical Distribution of Input Bias Current (213 Units)
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0
Rev. G | Page 13 of 28
AD822
10M
40
20
POS RAIL
NEG RAIL
R = 2kΩ
L
R
= 20kΩ
L
V
= ±15V
S
1M
V
= 0V, +5V
S
POS RAIL
0
POS
RAIL
V
= 0V, +3V
100k
S
–20
–40
NEG RAIL
NEG RAIL
R
= 100kΩ
L
10k
100
1k
10k
100k
0
60
120
180
240
300
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE FROM SUPPLY RAILS (mV)
Figure 10. Open-Loop Gain vs. Load Resistance
Figure 13. Input Effort Voltage with Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = 5 V
10M
1M
1k
100
10
R
= 100kΩ
L
V
= ±15V
S
V
= 0V, +5V
S
V
= ±15V
R
= 10kΩ
S
L
V
= 0V, +5V
S
100k
10k
V
= ±15V
S
R
= 600Ω
L
V
= 0V, +5V
S
1
–60 –40 –20
0
20
40
60
80
100 120 140
1
10
100
1k
10k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 11. Open-Loop Gain vs. Temperature
Figure 14. Input Voltage Noise vs. Frequency
300
200
100
–40
–50
R
A
= 10kΩ
L
= –1
CL
–60
R
= 10kΩ
L
R
= 100kΩ
V
= 0V, +3V; V = 2.5V p-p
OUT
L
S
–70
0
–100
–200
–80
V
= ±15V; V = 20V p-p
OUT
S
–90
V
= ±5V; V = 9V p-p
OUT
S
R
= 600Ω
L
–100
–110
V
= 0V, +5V; V = 4.5V p-p
OUT
S
–300
100
1k
10k
FREQUENCY (Hz)
100k
–16
–12
–8
–4
0
4
8
12
16
OUTPUT VOLTAGE (V)
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads
Figure 15. Total Harmonic Distortion (THD) vs. Frequency
Rev. G | Page 14 of 28
AD822
100
80
60
40
20
0
100
80
90
80
70
60
50
40
30
20
10
0
V
= ±15V
S
PHASE
60
V
= 0V, +5V
S
GAIN
V
= 0V, +3V
S
40
20
R
= 2kΩ
L
0
C
= 100pF
L
–20
10M
–20
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
Figure 19. Common-Mode Rejection vs. Frequency
1k
5
A
= +1
CL
= ±15V
V
S
NEGATIVE
RAIL
POSITIVE
RAIL
100
10
4
3
2
1
0
+25°C
–55°C
1
+125°C
0.1
0.01
–55°C
+125°C
100
1k
10k
100k
1M
10M
–1
0
1
2
3
FREQUENCY (Hz)
COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V)
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from
Figure 17. Output Impedance vs. Frequency
Supply Rails (VS − VCM
)
1000
100
10
16
12
8
1%
4
V
– V
OH
S
0.01%
ERROR
0.1%
0
0.01%
–4
–8
V
– V
OL S
1%
–12
–16
0
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
LOAD CURRENT (mA)
SETTLING TIME (µs)
Figure 18. Output Swing and Error vs. Settling Time
Figure 21. Output Saturation Voltage vs. Load Current
Rev. G | Page 15 of 28
AD822
1000
100
90
80
70
60
50
40
30
20
10
0
I
I
= 10mA
SOURCE
= 10mA
SINK
+PSRR
100
10
1
I
= 1mA
= 10µA
SOURCE
I
I
I
= 1mA
SINK
–PSRR
SOURCE
= 10µA
SINK
10
100
1k
10k
100k
1M
10M
10M
80
60
TEMPERATURE (°C)
–60 –40 –20
0
20
40
80
100 120 140
FREQUENCY (Hz)
Figure 22. Output Saturation Voltage vs. Temperature
Figure 25. Power Supply Rejection vs. Frequency
80
70
60
50
40
30
20
10
0
30
25
20
15
10
5
V
= ±15V
R
= 2kΩ
S
L
V
= ±15V
S
–OUT
+
V
= ±15V
S
V
= 0V, +5V
S
V
= 0V, +3V
S
–
–
V
= 0V, +5V
= 0V, +3V
+
+
S
V
= 0V, +5V
S
0
V
= 0V, +3V
S
V
S
0
10k
100k
FREQUENCY (Hz)
1M
–60 –40 –20
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 23. Short Circuit Current Limit vs. Temperature
Figure 26. Large Signal Frequency Response
2.4
2.2
1600
1400
1200
1000
800
600
400
200
0
T = +125°C
T = +25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
8-LEAD PDIP
8-LEAD SOIC
T = –55°C
8-LEAD MSOP
0
4
8
12
16
20
24
28
32
36
–60
–40
–20
0
20
40
60
TOTAL SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Figure 27. Maximum Power Dissipation vs. Temperature for Packages
Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature
Rev. G | Page 16 of 28
AD822
–70
–80
5V
5µs
100
90
–90
–100
–110
–120
10
0%
–130
–140
300
1k
3k
10k
30k
100k
300k
1M
Figure 32. Large Signal Response Unity Gain Follower; VS = 15 V, RL = 10 kΩ
FREQUENCY (Hz)
Figure 28. Crosstalk vs. Frequency
10mV
500ns
+V
S
0.01µF
100
90
8
+
1/2
V
IN
AD822
–
V
OUT
100pF
R
L
0.01µF
4
10
Figure 29. Unity Gain Follower
0%
5V
10µs
Figure 33. Small Signal Response Unity Gain Follower; VS = 15 V, RL = 10 kΩ
100
90
1V
2µs
100
90
10
0%
10
0%
GND
Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity Gain Follower; VS = 15 V,
RL = 600 Ω
V
OUT
Figure 34. VS = 5 V, 0 V; Unity Gain Follower Response to 0 V to 4 V Step
+V
s
20kΩ
2.2kΩ
+V
8
S
0.1µF
1
1µF
0.01µF
8
2
3
–
–
6
5
1/2
AD822
1/2
AD822
7
5kΩ
V
+
IN
1/2
AD822
20V p-p
+
+
5kΩ
V
OUT
100pF
R
L
–
4
V
IN
0.1µF
1µF
V
OUT
CROSS TALK = 20 log
Figure 35. Unity Gain Follower
10V
IN
–V
s
Figure 31. Crosstalk Test Circuit
Rev. G | Page 17 of 28
AD822
10kΩ
20kΩ
V
IN
10mV
2µs
V
+V
8
OUT
S
0.01µF
100
90
–
1/2
AD822
+
100pF
R
L
4
10
Figure 36. Gain-of-T2 Inverter
0%
GND
1V
2µs
Figure 39. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step,
Centered 20 mV below Ground, RL = 10 kΩ
100
90
1V
2µs
100
90
10
0%
GND
10
Figure 37. VS = 5 V, 0 V; Unity Gain Follower Response to 0 V to 5 V Step
0%
GND
Figure 40. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V below Ground, RL = 10 kΩ
10mV
2µs
100
90
500mV
10µs
100
90
10
0%
GND
10
0%
Figure 38. VS = 5 V, 0 V; Unity Gain Follower Response to 40 mV Step,
Centered 40 mV above Ground, RL = 10 kΩ
GND
Figure 41. VS = 3 V, 0 V; Gain-of-2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave
Centered at −0.75 V, RL = 600 Ω
Rev. G | Page 18 of 28
AD822
1V
10µs
. . . .
. . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
100
90
10
. . . . . . . .
. . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
0%
GND
1V
(a)
10µs
1V
1V
. . . . . . . . . . .
. . .
. . . . . . . . . . . .
. . . .
100 . . . .
. . . .
+V
s
90
10
. . . .
0% . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
. . . .
GND
1V
(b)
5V
R
P
V
IN
V
OUT
Figure 42. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to +VS + 200 mV
V
OUT = 0 to + VS
RP = 49.9 kΩ
Rev. G | Page 19 of 28
AD822
APPLICATION NOTES
100k
10k
1k
INPUT CHARACTERISTICS
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
In the AD822, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below −VS to ± V
less than +VS. Driving the input voltage closer to the positive
rail causes a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figure 34 and
Figure 37) and increased common-mode voltage error as
illustrated in Figure 20.
1kHz
RESISTOR JOHNSON
NOISE
100
10
10Hz
1
The AD822 does not exhibit phase reversal for input voltages up
to and including +VS. Figure 42 shows the response of an
AD822 voltage follower to a 0 V to ꢀ V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output waveform.
For input voltages greater than +VS, a resistor in series with the
AD822’s noninverting input prevents phase reversal, at the
expense of greater input voltage noise. This is illustrated in
Figure 42.
AMPLIFIER-GENERATED
NOISE
0.1
10k
100k
10M
100M
1G
10G
1M
SOURCE IMPEDANCE (Ω)
Figure 43. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD822’s unique bipolar rail-to-rail output stage swings within
ꢀ mV of the negative supply and ±0 mV of the positive supply with
no external resistive load. The AD822’s approximate output
saturation resistance is 40 Ω sourcing and 20 Ω sinking. This can be
used to estimate output saturation voltage when driving heavier
current loads. For instance, when sourcing ꢀ mA, the saturation
voltage to the positive supply rail is 200 mV; when sinking ꢀ mA,
the saturation voltage to the negative rail is ±00 mV.
Since the input stage uses n-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS – 0.4 V, then the input current reverses direction as
internal device junctions become forward biased. This is
illustrated in Figure 7.
The amplifier’s open-loop gain characteristic changes as a
function of resistive load, as shown in Figure ±0 to Figure ±3.
For load resistances over 20 kΩ, the AD822’s input error voltage
is virtually unchanged until the output voltage is driven to
±80 mV of either supply.
A current limiting resistor should be used in series with the
input of the AD822 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage is applied to the AD822 when ±VS = 0. The
amplifier is damaged if left in that condition for more than
±0 seconds. A ± kΩ resistor allows the amplifier to withstand up
to ±0 V of continuous overvoltage and increases the input
voltage noise by a negligible amount.
If the AD822’s output is overdriven so as to saturate either of
the output devices, the amplifier recovers within 2 ꢁs of its
input returning to the amplifier’s linear operating region.
Direct capacitive loads interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 44 shows the AD822’s pulse
response as a unity gain follower driving 3ꢀ0 pF. This amount of
overshoot indicates approximately 20° of phase margin—the
system is stable, but nearing the edge. Configurations with less
loop gain, and as a result less loop bandwidth, are much less
sensitive to capacitance load effects.
Input voltages less than –VS are a completely different story. The
amplifier can safely withstand input voltages 20 V below the
negative supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In
addition, the input stage typically maintains picoampere (pA)
level input currents across that input voltage range.
The AD822 is designed for ±3 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure ±4). This noise performance, along with the
AD822’s low input current and current noise, means that the
AD822 contributes negligible noise for applications with source
resistances greater than ±0 kΩ and signal bandwidths greater
than ± kHz. This is illustrated in Figure 43.
Rev. G | Page 20 of 28
AD822
Figure 46 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
values, the circuit drives ꢀ000 pF with a ±0% overshoot.
20mV
. . . . . . . .
2µs
. . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
100
90
+V
S
0.01µF
8
+
1/2
100Ω
V
IN
AD822
V
OUT
–
0.01µF
20pF
C
10
4
L
. . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . .
0%
–V
S
20kΩ
Figure 44. Small Signal Response of AD822 as
Unity Gain Follower Driving 350 pF
Figure 46. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Figure 4ꢀ is a plot of capacitive load that results in a 20° phase
margin vs. noise gain for the AD822. Noise gain is the inverse of
the feedback attenuation factor provided by the feedback
network in use.
5
4
3
2
1
300
1k
3k
10k
30k
CAPACITIVE LOAD FOR 20° PHASE MARGIN (pF)
C
L
R
F
R1
Figure 45. Capacitive Load Tolerance vs. Noise Gain
Rev. G | Page 21 of 28
AD822
APPLICATIONS
SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY
CONVERTER
Table 6. In-Amp Performance
Parameters
VS = 3 V, 0 V
VS = 5 V
CMRR
74 dB
80 dB
The circuit shown in Figure 47 uses the AD822 to drive a low
power timer that produces a stable pulse of width t1. The
positive going output pulse is integrated by R1 − C1 and used as
one input to the AD822 that is connected as a differential
integrator. The other input (nonloading) is the unknown
voltage, VIN. The AD822 output drives the timer trigger input,
closing the overall feedback loop.
Common-Mode Voltage
Range
3 dB BW, G = 10
G = 100
−0.2 V to +2 V
180 kHz
18 kHz
−5.2 V to +4 V
180 kHz
18 kHz
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = 5 V)
Noise @ f = 1 kHz, G = 10
G = 100
2 μs
5 μs
10V
270 nV/√Hz
2.2 μV/√Hz
1.10 mA
270 nV/√Hz
2.2 μV/√Hz
1.15 mA
U4
REF02
= 5V
C5
0.1µF
ISUPPLY (Total)
V
REF
2
4
6
5
CMOS
74HCO4
OUT2
OUT1
R
**
C3
0.1µF
3
SCALE
10kΩ
U3A
2
U3B
5µs
3
1
4
U2
CMOS 555
100 . . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . .
. . .
R2
499kΩ
1%
0.01µF, 2%
C1
90
8
4
R3*
116kΩ
U1
R
V+
6
3
THR
+
OUT
CV
R1
1/2
2
7
499kΩ
1%
TR
AD822B
5
V
–
DIS
IN
GND
C2
0.01µF
2%
1
10
C4
0.01µF
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
. . . .
. . . . . . . .
0%
0V TO 2.5V
FULL SCALE
1V
NOTES
1. f
= V /(V × t ), t = 1.1 × R3 × C6.
IN REF 1 1
OUT
= 25kHz F AS SHOWN.
= 1% METAL FILM <50ppm/°C TC.
= 10% 20T FILM <100ppm/°C TC.
S
Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal; VS = 5 V,
0 V; Gain = 0
2. *
3. **
4. t
= 33µF FOR f
= 20kHz @ V = 2.0V.
1
OUT
IN
Figure 47. Single-Supply Voltage-to-Frequency Converter
OHMTEK
PART # 1043
R1
90kΩ
R2
9kΩ
R3
1kΩ
R4
1kΩ
R5
9kΩ
R6
90kΩ
+
–
V
Typical AD822 bias currents of 2 pA allow MΩ range source
impedances with negligible dc errors. Linearity errors on the
order of 0.01% full scale can be achieved with this circuit. This
performance is obtained with a 5 V single supply that delivers
less than 1 mA to the entire circuit.
REF
G = 10
G = 100
G = 100
G = 10
+V
S
0.1µF
1
2
3
6
5
–
–
SINGLE-SUPPLY PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
1/2
AD822
1/2
7
+
–
R
P
AD822
1kΩ
+
+
V
OUT
V
V
IN1
4
R
P
1kΩ
The AD822 can be configured as a single-supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to 15 V. Using only one AD822
rather than three separate op amps, this circuit is cost and
power efficient. The AD822 FET inputs’ 2 pA bias currents
minimize offset errors caused by high unbalanced source
impedances.
IN2
R6
(G = 10) V
OUT
= (V
– V
IN2
)
+V
1+
IN1
REF
(
)
)
R4 + R5
R5 + R6
R4
(G = 100) V
OUT
= (V
IN1
– V
IN2
)
+V
REF
1+
(
Figure 49. A Single-Supply Programmable Instrumentation Amplifier
An array of precision thin film resistors sets the in amp gain to be
either 10 or 100. These resistors are laser trimmed to ratio match to
0.01% and have a maximum differential TC of 5 ppm/°C.
Rev. G | Page 22 of 28
AD822
that all signals in the audio frequency range (20 Hz to 20 kHz) are
delivered to the headphones.
3 V, SINGLE-SUPPLY STEREO HEADPHONE
DRIVER
The AD822 exhibits good current drive and THD + N
performance, even at 3 V single supplies. At ± kHz, total
harmonic distortion plus noise (THD + N) equals –62 dB
(0.079%) for a 300 mV p-p output signal. This is comparable to
other single-supply op amps that consume more power and
cannot run on 3 V power supplies.
LOW DROPOUT BIPOLAR BRIDGE DRIVER
The AD822 can be used for driving a 3ꢀ0 Ω Wheatstone bridge.
Figure ꢀ± shows one-half of the AD822 being used to buffer the
ADꢀ89, a ±.23ꢀ V low power reference. The output of 4.ꢀ V can
be used to drive an ADC converter front end. The other half of
the AD822 is configured as a unity gain inverter and generates
the other bridge input of −4.ꢀ V. Resistor R± and Resistor R2
provide a constant current for bridge excitation. The AD620 low
power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620 is
programmed using an external resistor RG and determined by
3V
+
1µF
MYLAR
0.1µF
0.1µF
95.3kΩ
47.5kΩ
8
3
2
CHANNEL 1
+
1/2
AD822
1
500µF
–
4.99kΩ
49.9 kΩ
G =
+±
L
RG
95.3kΩ
10kΩ
HEADPHONES
32Ω IMPEDANCE
+V
S
10kΩ
49.9kΩ
8
R
R1
20Ω
4.99kΩ
+1.235V
3
2
+
1/2
AD822
+
1
TO A/D CONVERTER
REFERENCE INPUT
–
6
5
AD589
–
1/2
1µF
MYLAR
–
7
47.5kΩ
AD822
+V
S
+
25.4kΩ 1%
500µF
CHANNEL 2
10kΩ 1%
4
350Ω
7
350Ω
350Ω
3
–
6
Figure 50. 3 V Single-Supply Stereo Headphone Driver
R
AD820
350Ω
G
+
5
2
In Figure ꢀ0, each channel’s input signal is coupled via a ± μF
Mylar capacitor. Resistor dividers set the dc voltage at the non-
inverting inputs so that the output voltage is midway between the
power supplies (±.ꢀ V). The gain is ±.ꢀ. Each half of the AD822
can then be used to drive a headphone channel. A ꢀ Hz high-pass
filter is realized by the ꢀ00 μF capacitors and the headphones that
can be modeled as 32 Ω load resistors to ground. This ensures
4
10kΩ 1%
V
REF
–V
S
6
5
–
1/2
7
10kΩ 1%
+V
S
+5V
–5V
–4.5V
+
+
+
AD822
0.1µF
GND
0.1µF
1µF
1µF
+
4
R2
20Ω
+
–V
S
–V
S
Figure 51. Low Dropout Bipolar Bridge Driver
Rev. G | Page 23 of 28
AD822
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
1
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 52. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
PIN 1
0.25 (0.0098)
0.65 BSC
0.10 (0.0040)
0.95
0.85
0.75
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
1.10 MAX
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
SEATING
PLANE
COPLANARITY
0.10
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 54. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. G | Page 24 of 28
AD822
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
Package Option
Branding
AD822AN
AD822ANZ1
AD822AR
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
AD822AR-REEL
AD822AR-REEL7
AD822ARZ1
AD822ARZ-REEL1
AD822ARZ-REEL71
AD822ARM-R2
AD822ARM-REEL
AD822ARMZ-R21
AD822ARMZ-REEL1
AD822BR
AD822BR-REEL
AD822BR-REEL7
AD822BRZ1
AD822BRZ-REEL1
AD822BRZ-REEL71
B4A
B4A
#B4A
#B4A
R-8
1 Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
SPICE model is available at www.analog.com.
Rev. G | Page 25 of 28
AD822
NOTES
Rev. G | Page 26 of 28
AD822
NOTES
Rev. G | Page 27 of 28
AD822
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00874-0-6/06(G)
Rev. G | Page 28 of 28
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