首页 |元器件品牌

AD822 [ADI]

Single Supply, Rail-to-Rail Low Power FET-Input Op Amp; 单电源，轨到轨低功耗FET输入运算放大器
AD822
型号： AD822
厂家： ADI    ADI
描述：

Single Supply, Rail-to-Rail Low Power FET-Input Op Amp
单电源，轨到轨低功耗FET输入运算放大器

晶体 运算放大器 晶体管
文件： 总16页 (文件大小：322K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Single Supply, Rail-to-Rail  
Low Power FET-Input Op Amp  
a
AD822  
CO NNECTIO N D IAGRAM  
FEATURES  
TRUE SINGLE SUPPLY OPERATION  
Output Sw ings Rail to Rail  
8-P in P lastic D IP , Cerdip and SO IC  
Input Voltage Range Extends Below Ground  
Single Supply Capability from +3 V to +36 V  
Dual Supply Capability from ؎1.5 V to ؎18 V  
HIGH LOAD DRIVE  
Capacitive Load Drive of 350 pF, G = 1  
Minim um Output Current of 15 m A  
EXCELLENT AC PERFORMANCE FOR LOW POWER  
800 ␮A Max Quiescent Current per Am plifier  
Unity Gain Bandw idth: 1.8 MHz  
Slew Rate of 3.0 V/ ␮s  
OUT1  
–IN1  
+IN1  
V–  
1
2
3
4
8
7
6
5
V+  
OUT2  
–IN2  
+IN2  
AD822  
capability with an input voltage range extending below the  
negative rail, allowing the AD822 to accommodate input signals  
below ground in the single supply mode. Output voltage swing  
extends to within 10 mV of each rail providing the maximum  
output dynamic range.  
GOOD DC PERFORMANCE  
800 ␮V Max Input Offset Voltage  
2 ␮V/ ؇C Typ Offset Voltage Drift  
25 pA Max Input Bias Current  
LOW NOISE  
13 nV/ √Hz @ 10 kHz  
NO PHASE INVERSION  
Offset voltage of 800 µV max, offset voltage drift of 2 µV/°C,  
input bias currents below 25 pA and low input voltage noise  
provide dc precision with source impedances up to a Gigaohm.  
1.8 MHz unity gain bandwidth, –93 dB T HD at 10 kHz and  
3 V/µs slew rate are provided with a low supply current of  
800 µA per amplifier. T he AD822 drives up to 350 pF of direct  
capacitive load as a follower, and provides a minimum output  
current of 15 mA. T his allows the amplifier to handle a wide  
range of load conditions. T his combination of ac and dc  
performance, plus the outstanding load drive capability, results  
in an exceptionally versatile amplifier for the single supply user.  
APPLICATIONS  
Battery Pow ered Precision Instrum entation  
Photodiode Pream ps  
Active Filters  
12- to 14-Bit Data Acquisition System s  
Medical Instrum entation  
Low Pow er References and Regulators  
T he AD822 is available in four performance grades. T he A and  
B grades are rated over the industrial temperature range of  
–40°C to +85°C. T here is also a 3 volt grade—the AD822A-3V,  
rated over the industrial temperature range. T he mil grade is  
rated over the military temperature range of –55°C to +125°C  
and is available processed on standard military drawing.  
P RO D UCT D ESCRIP TIO N  
T he AD822 is a dual precision, low power FET input op  
amp that can operate from a single supply of +3.0 V to 36 V,  
or dual supplies of ±1.5 V to ±18 V. It has true single supply  
100  
10  
1
T he AD822 is offered in three varieties of 8-pin package: plastic  
DIP, hermetic cerdip and surface mount (SOIC) as well as die  
form.  
1V  
1V  
20µ  
s
100  
90  
5V  
V
OUT  
10  
0%  
0V  
(GND)  
1V  
10  
100  
FREQUENCY – Hz  
1k  
10k  
Input Voltage Noise vs. Frequency  
Gain of +2 Am plifier; VS = +5, 0, VIN = 2.5 V Sine Centered  
at 1.25 Volts, RL = 100 kΩ  
REV. A  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 617/ 329-4700  
Fax: 617/ 326-8703  
AD822–SPECIFICATIONS (V = 0, 5 volts @ T = +25؇C, V = 0 V, V = 0.2 V unless otherwise noted)  
S
A
CM  
OUT  
AD 822A  
Typ  
AD 822B  
Typ  
AD 822S1  
Typ  
P ar am eter  
Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
DC PERFORMANCE  
Initial Offset  
Max Offset over T emperature  
Offset Drift  
Input Bias Current  
at T MAX  
Input Offset Current  
at T MAX  
0.1  
0.5  
2
2
0.5  
2
0.8  
1.2  
0.1  
0.5  
2
2
0.5  
2
0.4  
0.9  
0.1  
0.5  
2
2
0.5  
2
0.8  
mV  
mV  
µV/°C  
pA  
nA  
pA  
VCM = 0 V to 4 V  
25  
5
20  
10  
2.5  
10  
25  
20  
0.5  
0.5  
1.5  
nA  
Open-Loop Gain  
VO = 0.2 V to 4 V  
RL = 100 k  
500  
400  
80  
80  
15  
1000  
150  
30  
500  
400  
80  
80  
15  
1000  
150  
30  
500  
80  
1000  
150  
30  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
T MIN to T MAX  
T MIN to T MAX  
T MIN to T MAX  
RL = 10 k  
RL = 1 k  
15  
10  
10  
NOISE/HARMONIC PERFORMANCE  
Input Voltage Noise  
0.1 Hz to 10 Hz  
f = 10 Hz  
2
2
2
µV p-p  
25  
21  
16  
13  
25  
21  
16  
13  
25  
21  
16  
13  
nV/√Hz  
nV/√Hz  
nV/√Hz  
nV/√Hz  
f = 100 Hz  
f = 1 kHz  
f = 10 kHz  
Input Current Noise  
0.1 Hz to 10 Hz  
f = 1 kHz  
18  
0.8  
18  
0.8  
18  
0.8  
fA p-p  
fA/√Hz  
Harmonic Distortion  
f = 10 kHz  
RL = 10 k to 2.5 V  
VO = 0.25 V to 4.75 V  
–93  
–93  
–93  
dB  
DYNAMIC PERFORMANCE  
Unity Gain Frequency  
Full Power Response  
Slew Rate  
1.8  
210  
3
1.8  
210  
3
1.8  
210  
3
MHz  
kHz  
V/µs  
VO p-p = 4.5 V  
Settling T ime  
to 0.1%  
to 0.01%  
VO = 0.2 V to 4.5 V  
1.4  
1.8  
1.4  
1.8  
1.4  
1.8  
µs  
µs  
MAT CHING CHARACT ERIST ICS  
Initial Offset  
Max Offset Over T emperature  
Offset Drift  
1.0  
1.6  
0.5  
1.3  
1.6  
20  
mV  
mV  
µV/°C  
pA  
3
3
Input Bias Current  
20  
10  
Crosstalk @ f = 1 kHz  
f = 100 kHz  
RL = 5 kΩ  
–130  
–93  
–130  
–93  
–130  
–93  
dB  
dB  
INPUT CHARACT ERIST ICS  
Common-Mode Voltage Range2  
T MIN to T MAX  
CMRR  
T MIN to T MAX  
–0.2  
–0.2  
66  
4
4
–0.2  
–0.2  
69  
4
4
–0.2  
66  
4
V
V
dB  
dB  
VCM = 0 V to +2 V  
80  
80  
80  
66  
66  
Input Impedance  
Differential  
Common Mode  
1013||0.5  
1013||2.8  
1013||0.5  
1013||0.5  
1013||2.8  
Ω||pF  
Ω||pF  
1013||2.8  
OUT PUT CHARACT ERIST ICS  
Output Saturation Voltage3  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
Operating Output Current  
T MIN to T MAX  
ISINK = 20 µA  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
ISOURCE = 20 µA  
ISINK = 2 mA  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
14  
55  
ISOURCE = 2 mA  
ISINK = 15 mA  
ISOURCE = 15 mA  
110  
500  
1500 mV  
mV  
mA  
mA  
pF  
15  
12  
15  
12  
15  
70  
Capacitive Load Drive  
350  
350  
350  
POWER SUPPLY  
Quiescent Current T MIN to T MAX  
Power Supply Rejection  
T MIN to T MAX  
1.24  
80  
1.6  
1.24  
80  
1.6  
1.24  
80  
mA  
dB  
dB  
VS+ = 5 V to 15 V  
70  
70  
66  
66  
–2–  
REV. A  
AD822  
(V = ؎5 volts @ T = +25؇C, V = 0 V, V = 0 V unless otherwise noted)  
S
A
CM  
OUT  
AD 822A  
Typ  
AD 822B  
Typ  
AD 822S1  
Typ  
P ar am eter  
Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
DC PERFORMANCE  
Initial Offset  
Max Offset over T emperature  
Offset Drift  
Input Bias Current  
at T MAX  
Input Offset Current  
at T MAX  
0.1  
0.5  
2
2
0.5  
2
0.8  
1.5  
0.1  
0.5  
2
2
0.5  
2
0.4  
1
0.1  
0.5  
2
2
0.5  
2
mV  
mV  
µV/°C  
pA  
nA  
pA  
VCM = –5 V to 4 V  
25  
5
20  
10  
2.5  
10  
25  
0.5  
0.5  
1.5  
nA  
Open-Loop Gain  
VO = –4 V to 4 V  
RL = 100 k  
400  
400  
80  
80  
20  
1000  
150  
30  
400  
400  
80  
80  
20  
1000  
150  
30  
400  
80  
1000  
150  
30  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
T MIN to T MAX  
T MIN to T MAX  
T MIN to T MAX  
RL = 10 k  
RL = 1 k  
20  
10  
10  
NOISE/HARMONIC PERFORMANCE  
Input Voltage Noise  
0.1 Hz to 10 Hz  
f = 10 Hz  
2
2
2
µV p-p  
25  
21  
16  
13  
25  
21  
16  
13  
25  
21  
16  
13  
nV/√Hz  
nV/√Hz  
nV/√Hz  
nV/√Hz  
f = 100 Hz  
f = 1 kHz  
f = 10 kHz  
Input Current Noise  
0.1 Hz to 10 Hz  
f = 1 kHz  
18  
0.8  
18  
0.8  
18  
0.8  
fA p-p  
fA/√Hz  
Harmonic Distortion  
f = 10 kHz  
RL = 10 k  
VO = ±4.5 V  
–93  
–93  
–93  
dB  
DYNAMIC PERFORMANCE  
Unity Gain Frequency  
Full Power Response  
Slew Rate  
1.9  
105  
3
1.9  
105  
3
1.9  
105  
3
MHz  
kHz  
V/µs  
VO p-p = 9 V  
Settling T ime  
to 0.1%  
to 0.01%  
VO = 0 V to ±4.5 V  
1.4  
1.8  
1.4  
1.8  
1.4  
1.8  
µs  
µs  
MAT CHING CHARACT ERIST ICS  
Initial Offset  
Max Offset Over T emperature  
Offset Drift  
1.0  
3
0.5  
2
1.6  
2
mV  
mV  
µV/°C  
pA  
3
3
Input Bias Current  
25  
10  
25  
Crosstalk @ f = 1 kHz  
f = 100 kHz  
RL = 5 kΩ  
–130  
–93  
–130  
–93  
–130  
–93  
dB  
dB  
INPUT CHARACT ERIST ICS  
Common-Mode Voltage Range2  
T MIN to T MAX  
CMRR  
T MIN to T MAX  
–5.2  
–5.2  
66  
4
4
–5.2  
–5.2  
69  
4
4
–5.2  
66  
4
V
V
dB  
dB  
VCM = –5 V to +2 V  
80  
80  
80  
66  
66  
Input Impedance  
Differential  
Common Mode  
1013||0.5  
1013||2.8  
1013||0.5  
1013||0.5  
1013||2.8  
Ω||pF  
Ω||pF  
1013||2.8  
OUT PUT CHARACT ERIST ICS  
Output Saturation Voltage3  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
Operating Output Current  
T MIN to T MAX  
ISINK = 20 µA  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
ISOURCE = 20 µA  
ISINK = 2 mA  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
14  
55  
ISOURCE = 2 mA  
ISINK = 15 mA  
ISOURCE = 15 mA  
110  
500  
1500 mV  
mV  
mA  
mA  
pF  
15  
12  
15  
12  
15  
70  
Capacitive Load Drive  
350  
350  
350  
POWER SUPPLY  
Quiescent Current TMIN to TMAX  
Power Supply Rejection  
T MIN to T MAX  
1.3  
80  
1.6  
1.3  
80  
1.6  
1.3  
80  
mA  
dB  
dB  
VS+ = 5 V to 15 V  
70  
70  
66  
66  
REV. A  
–3–  
AD822–SPECIFICATIONS(V = ؎15 volts @ T = +25؇C, V = 0 V, V = 0 V unless otherwise noted)  
S
A
CM  
OUT  
AD 822A  
Typ  
AD 822B  
Typ  
AD 822S1  
Typ  
P ar am eter  
Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
DC PERFORMANCE  
Initial Offset  
Max Offset over T emperature  
Offset Drift  
0.4  
0.5  
2
2
3
0.3  
0.5  
2
1.5  
2.5  
0.4  
0.5  
2
2.0  
mV  
mV  
µV/°C  
pA  
pA  
nA  
Input Bias Current  
VCM = 0 V  
VCM = –10 V  
VCM = 0 V  
2
25  
2
12  
2
25  
20  
40  
0.5  
2
40  
0.5  
2
40  
0.5  
2
at T MAX  
Input Offset Current  
at T MAX  
5
20  
2.5  
12  
pA  
nA  
0.5  
0.5  
1.5  
Open-Loop Gain  
VO = +10 V to –10 V  
RL = 100 k  
500  
500  
100  
100  
30  
2000  
500  
45  
500  
500  
100  
100  
30  
2000  
500  
45  
500  
150  
30  
2000  
400  
45  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
T MIN to T MAX  
T MIN to T MAX  
T MIN to T MAX  
RL = 10 k  
RL = 1 k  
20  
20  
NOISE/HARMONIC PERFORMANCE  
Input Voltage Noise  
0.1 Hz to 10 Hz  
f = 10 Hz  
2
2
2
µV p-p  
25  
21  
16  
13  
25  
21  
16  
13  
25  
21  
16  
13  
nV/√Hz  
nV/√Hz  
nV/√Hz  
nV/√Hz  
f = 100 Hz  
f = 1 kHz  
f = 10 kHz  
Input Current Noise  
0.1 Hz to 10 Hz  
f = 1 kHz  
18  
0.8  
18  
0.8  
18  
0.8  
fA p-p  
fA/√Hz  
Harmonic Distortion  
f = 10 kHz  
RL = 10 k  
VO = ±10 V  
–85  
–85  
–85  
dB  
DYNAMIC PERFORMANCE  
Unity Gain Frequency  
Full Power Response  
Slew Rate  
1.9  
45  
3
1.9  
45  
3
1.9  
45  
3
MHz  
kHz  
V/µs  
VO p-p = 20 V  
Settling T ime  
to 0.1%  
to 0.01%  
VO = 0 V to ±10 V  
4.1  
4.5  
4.1  
4.5  
4.1  
4.5  
µs  
µs  
MAT CHING CHARACT ERIST ICS  
Initial Offset  
Max Offset Over T emperature  
Offset Drift  
3
4
2
2.5  
0.8  
1.0  
mV  
mV  
µV/°C  
pA  
3
3
Input Bias Current  
25  
12  
25  
Crosstalk @ f = 1 kHz  
f = 100 kHz  
RL = 5 kΩ  
–130  
–93  
–130  
–93  
–130  
–93  
dB  
dB  
INPUT CHARACT ERIST ICS  
Common-Mode Voltage Range2  
T MIN to T MAX  
CMRR  
T MIN to T MAX  
–15.2  
–15.2  
70  
14  
14  
–15.2  
–15.2  
74  
14  
14  
–15.2  
70  
14  
V
V
dB  
dB  
VCM = –15 V to 12 V  
80  
90  
90  
70  
74  
Input Impedance  
Differential  
Common Mode  
1013||0.5  
1013||2.8  
1013||0.5  
1013||0.5  
1013||2.8  
Ω||pF  
Ω||pF  
1013||2.8  
OUT PUT CHARACT ERIST ICS  
Output Saturation Voltage3  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
Operating Output Current  
T MIN to T MAX  
ISINK = 20 µA  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
10  
14  
20  
55  
80  
110  
160  
500  
1000  
1500  
1900  
5
7
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
ISOURCE = 20 µA  
ISINK = 2 mA  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
10  
40  
80  
300  
800  
14  
55  
ISOURCE = 2 mA  
ISINK = 15 mA  
ISOURCE = 15 mA  
110  
500  
1500 mV  
mV  
mA  
mA  
pF  
20  
15  
20  
15  
20  
70  
Capacitive Load Drive  
350  
350  
350  
POWER SUPPLY  
Quiescent Current TMIN to TMAX  
Power Supply Rejection  
T MIN to T MAX  
1.4  
80  
1.8  
1.4  
80  
1.8  
1.4  
80  
mA  
dB  
dB  
VS+ = 5 V to 15 V  
70  
70  
70  
70  
REV. A  
–4–  
AD822  
(V = 0, 3 volts @ T = +25؇C, V = 0 V, V = 0.2 V unless otherwise noted)  
S
A
CM  
OUT  
AD 822A-3 V  
Typ  
P ar am eter  
Conditions  
Min  
Max  
Units  
DC PERFORMANCE  
Initial Offset  
Max Offset over T emperature  
Offset Drift  
Input Bias Current  
at T MAX  
Input Offset Current  
at T MAX  
0.2  
0.5  
1
2
0.5  
2
1
1.5  
mV  
mV  
µV/°C  
pA  
nA  
pA  
VCM = 0 V to +2 V  
25  
5
20  
0.5  
nA  
Open-Loop Gain  
VO = 0.2 V to 2 V  
RL = 100 k  
300  
300  
60  
60  
10  
8
1000  
150  
30  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
V/mV  
T MIN to T MAX  
T MIN to T MAX  
T MIN to T MAX  
RL = 10 k  
RL = 1 k  
NOISE/HARMONIC PERFORMANCE  
Input Voltage Noise  
0.1 Hz to 10 Hz  
f = 10 Hz  
2
µV p-p  
25  
21  
16  
13  
nV/√Hz  
nV/√Hz  
nV/√Hz  
nV/√Hz  
f = 100 Hz  
f = 1 kHz  
f = 10 kHz  
Input Current Noise  
0.1 Hz to 10 Hz  
f = 1 kHz  
18  
0.8  
fA p-p  
fA/√Hz  
Harmonic Distortion  
f = 10 kHz  
RL = 10 k to 1.5 V  
VO = ±1.25 V  
–92  
dB  
DYNAMIC PERFORMANCE  
Unity Gain Frequency  
Full Power Response  
Slew Rate  
1.5  
240  
3
MHz  
kHz  
V/µs  
VO p-p = 2.5 V  
Settling T ime  
to 0.1%  
to 0.01%  
VO = 0.2 V to 2.5 V  
1
1.4  
µs  
µs  
MAT CHING CHARACT ERIST ICS  
Initial Offset  
Max Offset Over T emperature  
Offset Drift  
1
2
mV  
mV  
µV/°C  
pA  
2
Input Bias Current  
10  
Crosstalk @ f = 1 kHz  
f = 100 kHz  
RL = 5 kΩ  
–130  
–93  
dB  
dB  
INPUT CHARACT ERIST ICS  
Common-Mode Voltage Range2  
T MIN to T MAX  
CMRR  
T MIN to T MAX  
–0.2  
–0.2  
60  
2
2
V
V
dB  
dB  
VCM = 0 V to +1 V  
74  
60  
Input Impedance  
Differential  
Common Mode  
1013||0.5  
1013||2.8  
Ω||pF  
Ω||pF  
OUT PUT CHARACT ERIST ICS  
Output Saturation Voltage3  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
VOL–VEE  
T MIN to T MAX  
VCC–VOH  
T MIN to T MAX  
Operating Output Current  
T MIN to T MAX  
ISINK = 20 µA  
5
7
10  
14  
20  
55  
80  
110  
160  
400  
400  
1000  
1000  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mA  
mA  
pF  
ISOURCE = 20 µA  
ISINK = 2 mA  
10  
40  
80  
200  
500  
ISOURCE = 2 mA  
ISINK = 10 mA  
ISOURCE = 10 mA  
15  
12  
Capacitive Load Drive  
350  
POWER SUPPLY  
Quiescent Current T MIN to T MAX  
Power Supply Rejection  
T MIN to T MAX  
1.24  
80  
1.6  
mA  
dB  
dB  
VS+ = 3 V to 15 V  
70  
70  
REV. A  
–5–  
AD822–SPECIFICATIONS  
NOT ES  
1See standard military drawing for 883B specifications.  
2T his is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+V S – 1 V) to +VS.  
Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply.  
3VOL–VEE is defined as the difference between the lowest possible output voltage (VOL) and the minus voltage supply rail (VEE).  
VCC–VOH is defined as the difference between the highest possible output voltage (VOH ) and the positive supply voltage (VCC).  
Specifications subject to change without notice.  
CAUTIO N  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD822 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
ABSO LUTE MAXIMUM RATINGS1  
operation will be restored as soon as the die temperature is  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V  
Internal Power Dissipation  
reduced. Leaving the device in the “overheated” condition for  
an extended period can result in device burnout. T o ensure  
proper operation, it is important to observe the derating curves  
shown in Figure 24.  
Plastic DIP (N) . . . . . . . . . . . . . . Observe Derating Curves  
Cerdip (Q) . . . . . . . . . . . . . . . . . . Observe Derating Curves  
SOIC (R) . . . . . . . . . . . . . . . . . . . Observe Derating Curves  
Input Voltage . . . . . . . . . . . . . . (+VS + 0.2 V) to –(20 V + VS)  
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite  
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V  
Storage T emperature Range (N) . . . . . . . . . –65°C to +125°C  
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C  
Storage T emperature Range (R) . . . . . . . . . –65°C to +150°C  
Operating T emperature Range  
While the AD822 is internally short circuit protected, this may not  
be sufficient to guarantee that the maximum junction temperature  
is not exceeded under all conditions. With power supplies ±12  
volts (or less) at an ambient temperature of +25°C or less, if the  
output node is shorted to a supply rail, then the amplifier will not  
be destroyed, even if this condition persists for an extended period.  
O RD ERING GUID E  
AD822A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C  
AD822S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C  
Lead T emperature Range (Soldering 60 sec) . . . . . . . +260°C  
Tem perature  
Range  
P ackage  
D escription  
P ackage  
O ption  
M
odel1  
NOT ES  
AD822AN  
AD822BN  
–40°C to +85°C  
–40°C to +85°C  
8-Pin Plastic  
Mini-DIP  
8-Pin Plastic  
Mini-DIP  
8-Pin SOIC  
8-Pin SOIC  
8-Pin SOIC  
8-Pin Plastic  
Mini-DIP  
Die  
N-8  
N-8  
1Stresses above those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. T his is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
28-Pin Plastic DIP Package: θJA = 90°C/Watt  
AD822AR  
AD822BR  
AD822AR-3V  
AD822AN-3V  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
R-8  
R-8  
R-8  
N-8  
8-Pin Cerdip Package: θJA = 110°C/Watt  
8-Pin SOIC Package: θJA = 160°C/Watt  
MAXIMUM P O WER D ISSIP ATIO N  
AD822A Chips  
Standard Military  
Drawing2  
–40°C to +85°C  
T he maximum power that can be safely dissipated by the AD822 is  
limited by the associated rise in junction temperature. For plastic  
packages, the maximum safe junction temperature is 145°C. For  
the cerdip packages, the maximum junction temperature is 175°C.  
If these maximums are exceeded momentarily, proper circuit  
–55°C to +125°C 8-Pin Cerdip Q-8  
NOT ES  
1Spice model is available on ADI Model Disc.  
2Contact factory for availability.  
METALIZATIO N P H O TO GRAP H  
Contact factory for latest dimensions.  
D imensions shown in inches and (mm ).  
REV. A  
–6–  
Typical Characteristics–AD822  
5
70  
60  
50  
40  
30  
20  
V
= 0V, 5V  
S
0
V
= 0V, +5V AND ±5V  
S
V
= ±5V  
S
10  
–5  
0
–5  
–4  
–3  
–2  
–1  
0
1
2
3
4
5
–0.5 –0.4 –0.3 –0.2 –0.1  
0
0.1  
0.2  
0.3  
0.4  
0.5  
COMMON-MODE VOLTAGE – V  
OFFSET VOLTAGE – mV  
Figure 4. Input Bias Current vs. Com m on-Mode Voltage;  
Figure 1. Typical Distribution of Offset Voltage (390 Units)  
VS = +5 V, 0 V and VS = ±5 V  
1k  
100  
10  
16  
V
V
= ±5V  
14  
12  
10  
8
S
S
= ±15V  
6
1
4
2
0.1  
0
–16  
–12  
–8  
–4  
0
4
8
12  
16  
–12 –10 –8  
–6  
–4  
–2  
0
2
4
6
8
10  
COMMON-MODE VOLTAGE – V  
OFFSET VOLTAGE DRIFT – µV/°C  
Figure 5. Input Bias Current vs. Com m on-Mode Voltage;  
VS = ±15 V  
Figure 2. Typical Distribution of Offset Voltage Drift  
(100 Units)  
100k  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
10k  
1k  
100  
10  
1
0.1  
0
0
1
2
3
4
5
6
7
8
9
10  
20  
40  
60  
80  
100  
120  
140  
INPUT BIAS CURRENT – pA  
TEMPERATURE – °C  
Figure 3. Typical Distribution of Input Bias Current  
(213 Units)  
Figure 6. Input Bias Current vs. Tem perature; VS = 5 V,  
VCM = 0  
REV. A  
–7–  
AD822–Typical Characteristics  
10M  
40  
20  
POS RAIL  
NEG RAIL  
RL = 2kΩ  
VS = ±15V  
RL = 20kΩ  
1M  
VS = 0V, 5V  
0
POS RAIL  
POS  
RAIL  
VS = 0V, 3V  
100k  
–20  
–40  
NEG RAIL  
NEG RAIL  
RL = 100kΩ  
10k  
100  
1k  
10k  
100k  
60  
120  
180  
240  
300  
0
LOAD RESISTANCE – Ω  
OUTPUT VOLTAGE FROM SUPPLY RAILS – mV  
Figure 7. Open-Loop Gain vs. Load Resistance  
Figure 10. Input Error Voltage with Output Voltage within  
300 m V of Either Supply Rail for Various Resistive Loads;  
VS = ±5 V  
1k  
100  
10  
10M  
V
V
= ±15V  
R
= 100kΩ  
= 10kΩ  
S
S
L
1M  
100k  
10k  
= 0V, 5V  
V
V
= ±15V  
R
S
S
L
= 0V, 5V  
V
V
= ±15V  
S
S
R
= 600Ω  
L
= 0V, 5V  
1
1
10  
100  
1k  
10k  
–60 –40 –20  
0
20  
40  
60  
80  
100 120 140  
TEMPERATURE – °C  
FREQUENCY – Hz  
Figure 11. Input Voltage Noise vs. Frequency  
Figure 8. Open-Loop Gain vs. Tem perature  
–40  
300  
R
A
= 10kΩ  
L
–50  
–60  
= –1  
200  
100  
CL  
R
= 10kΩ  
L
R
= 100kΩ  
V
= 0V, 3V; V  
= 20Vp-p  
= 2.5Vp-p  
OUT  
L
S
–70  
0
–100  
–200  
–300  
–80  
V
= ±15V; V  
= ±5V; V  
S
OUT  
–90  
V
= 9Vp-p  
OUT  
S
R
= 600Ω  
–100  
L
V
= 0V, 5V; V  
= 4.5Vp-p  
OUT  
S
–110  
100  
1k  
10k  
FREQUENCY – Hz  
100k  
–16  
–12  
–8  
–4  
0
4
8
12  
16  
OUTPUT VOLTAGE – V  
Figure 12. Total Harm onic Distortion vs. Frequency  
Figure 9. Input Error Voltage vs. Output Voltage for  
Resistive Loads  
–8–  
REV. A  
AD822  
90  
80  
70  
60  
50  
40  
30  
20  
10  
100  
100  
80  
60  
40  
20  
0
80  
60  
40  
20  
0
PHASE  
V
= 0V, 3V  
V
= ±15V  
S
S
GAIN  
V
= 0V, 5V  
S
RL = 2kΩ  
CL = 100pF  
–20  
–20  
0
10  
100  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY – Hz  
FREQUENCY – Hz  
Figure 13. Open-Loop Gain and Phase Margin vs.  
Frequency  
Figure 16. Com m on-Mode Rejection vs. Frequency  
1k  
5
4
A
V
= +1  
CL  
= ±15V  
S
100  
10  
NEGATIVE  
RAIL  
POSITIVE  
RAIL  
3
2
1
0
+25°C  
–55°C  
1
+125°C  
0.1  
–55°C  
+125°C  
0.01  
100  
1k  
10k  
100k  
1M  
10M  
–1  
0
1
2
3
FREQUENCY – Hz  
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – Volts  
Figure 14. Output Im pedance vs. Frequency  
Figure 17. Absolute Com m on-Mode Error vs. Com m on-  
Mode Voltage from Supply Rails (VS – VCM  
)
+16  
+12  
1000  
1%  
+8  
100  
+4  
VS – VOH  
0.1%  
0.01%  
ERROR  
0
–4  
VOL – VS  
10  
–8  
1%  
–12  
–16  
0
0.001  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
0.01  
0.1  
1
10  
100  
SETTLING TIME – µs  
LOAD CURRENT – mA  
Figure 15. Output Swing and Error vs. Settling Tim e  
Figure 18. Output Saturation Voltage vs. Load Current  
REV. A  
–9–  
AD822–Typical Characteristics  
1000  
100  
90  
ISOURCE = 10mA  
80  
70  
60  
50  
ISINK = 10mA  
100  
ISOURCE = 1mA  
ISINK = 1mA  
+PSRR  
40  
30  
20  
10  
ISOURCE = 10µA  
ISINK = 10µA  
–PSRR  
10  
0
1
–60 –40 –20  
0
20  
40  
60  
80  
100 120 140  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY – Hz  
TEMPERATURE – °C  
Figure 19. Output Saturation Voltage vs. Tem perature  
Figure 22. Power Supply Rejection vs. Frequency  
80  
70  
30  
RL = 2k  
25  
V
= ±15V  
S
60  
50  
40  
30  
20  
10  
0
V
= ±15V  
S
20  
15  
10  
5
–OUT  
+
V
= ±15V  
S
V
V
= 0V, 5V  
= 0V, 3V  
S
S
–
–
V
= 0V, 5V  
= 0V ,3V  
+
+
S
V
= 0V, 3V  
V
= 0V, 5V  
S
S
V
S
0
–60 –40 –20  
0
20  
40  
60  
80  
100 120 140  
10k  
100k  
1M  
10M  
TEMPERATURE – °C  
FREQUENCY – Hz  
Figure 20. Short Circuit Current Lim it vs. Tem perature  
Figure 23. Large Signal Frequency Response  
1600  
2.4  
T = +125°C  
(PLASTIC) T  
(HERMETIC) T  
= 145°C  
2.2  
2.0  
1.8  
1.6  
JMAX  
1400  
= 175°C  
JMAX  
T = +25°C  
1200  
T = –55°C  
1000  
800  
600  
400  
200  
0
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
8-PIN MINI-DIP  
(PLASTIC)  
8-PIN CERDIP  
(HERMETIC)  
8-PIN SOIC  
(PLASTIC)  
–60 –40 –20  
0
20  
40  
60  
80  
100 120 140  
0
4
8
12  
16  
20  
24  
28  
30  
36  
AMBIENT TEMPERATURE –  
°
C
TOTAL SUPPLY VOLTAGE – Volts  
Figure 21. Quiescent Current vs. Supply Voltage vs.  
Tem perature  
Figure 24. Maxim um Power Dissipation vs. Tem perature  
for Plastic and Herm etic Packages  
–10–  
REV. A  
AD822  
–70  
–80  
V
OUT  
20kΩ  
2.2kΩ  
+V  
S
0.1µF  
1µF  
5kΩ  
2
3
6
5
8
–90  
1/2  
AD822  
1
7
5kΩ  
1/2  
20V p-p  
AD822  
–100  
–110  
–120  
–130  
–140  
V
IN  
0.1µF  
1µF  
V
OUT  
CROSSTALK = 20 LOG  
10V  
IN  
–V  
S
Figure 28. Crosstalk Test Circuit  
300  
1k  
3k  
10k  
30k  
100k  
300k  
1M  
FREQUENCY – Hz  
Figure 25. Crosstalk vs. Frequency  
5V  
5µs  
100  
90  
+V  
S
0.01µF  
8
1/2  
AD822  
V
IN  
V
OUT  
4
R
100pF  
L
0.01µF  
10  
–V  
S
0%  
Figure 26. Unity-Gain Follower  
Figure 29. Large Signal Response Unity Gain Follower;  
VS = ±15 V, RL = 10 kΩ  
5V  
10µs  
10mV  
500ns  
100  
90  
100  
90  
10  
10  
0%  
0%  
Figure 27. 20 V p-p, 25 kHz Sine Wave Input; Unity Gain  
Figure 30. Sm all Signal Response Unity Gain Follower;  
Follower; RL = 600 Ω, VS = ±15 V  
VS = ±15 V, RL = 10 kΩ  
REV. A  
–11–  
AD822  
1V  
2µs  
1V  
2µs  
100  
90  
100  
90  
10  
10  
GND  
0%  
0%  
GND  
Figure 31. VS = +5 V, 0 V; Unity Gain Follower Response  
to 0 V to 4 V Step  
Figure 34. VS = +5 V, 0 V; Unity Gain Follower Response  
to 0 V to 5 V Step  
10mV  
2µs  
100  
90  
+VS  
0.01µF  
8
VIN  
1/2  
AD822  
VOUT  
RL  
100pF  
4
10  
GND  
0%  
Figure 35. VS = +5 V, 0 V; Unity Gain Follower Response,  
Figure 32. Unity Gain Follower  
to 40 m V Step Centered 40 m V Above Ground, RL = 10 kΩ  
2µs  
10mV  
10k  
20k  
100  
90  
VIN  
VOUT  
+VS  
0.01µF  
8
1/2  
AD822  
RL  
100pF  
4
10  
0%  
GND  
Figure 36. VS = +5 V, 0 V; Gain of Two Inverter Response  
Figure 33. Gain of Two Inverter  
to 20 m V Step, Centered 20 m V Below Ground, RL = 10 kΩ  
REV. A  
–12–  
AD822  
2µs  
1V  
1V  
2µs  
100  
90  
100  
90  
10  
0%  
GND  
1V  
1V  
10  
0%  
GND  
a
1V  
10µs  
100  
90  
+V  
S
Figure 37. VS = +5 V, 0 V; Gain of Two Inverter Response  
to 2.5 V Step Centered –1.25 V Below Ground, RL = 10 kΩ  
10  
GND  
0%  
1V  
500mV  
10µs  
b.  
+5V  
100  
90  
R
P
V
IN  
V
OUT  
10  
0%  
GND  
Figure 39. (a) Response with RP = 0; VIN from 0 to +VS  
(b) VIN = 0 to +VS + 200 m V  
VOUT = 0 to +VS  
RP = 49.9 kΩ  
Figure 38. VS = 3 V, 0 V; Gain of Two Inverter, VIN = 1.25 V,  
25 kHz, Sine Wave Centered at –0.75 V, RL = 600 Ω  
Since the input stage uses n-channel JFET s, input current  
during normal operation is negative; the current flows out from  
the input terminals. If the input voltage is driven more positive  
than +VS – 0.4 V, the input current will reverse direction as  
internal device junctions become forward biased. T his is  
illustrated in Figure 4.  
AP P LICATIO N NO TES  
INP UT CH ARACTERISTICS  
In the AD822, n-channel JFET s are used to provide a low  
offset, low noise, high impedance input stage. Minimum input  
common-mode voltage extends from 0.2 V below –VS to 1 V  
less than +VS. Driving the input voltage closer to the positive  
rail will cause a loss of amplifier bandwidth (as can be seen by  
comparing the large signal responses shown in Figures 31 and  
34) and increased common-mode voltage error as illustrated in  
Figure 17.  
A current limiting resistor should be used in series with the  
input of the AD822 if there is a possibility of the input voltage  
exceeding the positive supply by more than 300 mV, or if an  
input voltage will be applied to the AD822 when ±VS = 0. T he  
amplifier will be damaged if left in that condition for more than  
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up  
to 10 volts of continuous overvoltage, and increases the input  
voltage noise by a negligible amount.  
T he AD822 does not exhibit phase reversal for input voltages  
up to and including +VS. Figure 39a shows the response of an  
AD822 voltage follower to a 0 V to +5 V (+VS) square wave  
input. T he input and output arc superimposed. T he output  
tracks the input up to +VS without phase reversal. T he reduced  
bandwidth above a 4 V input causes the rounding of the output  
wave form. For input voltages greater than +VS, a resistor in  
series with the AD822’s noninverting input will prevent phase  
reversal, at the expense of greater input voltage noise. T his is  
illustrated in Figure 39b.  
Input voltages less than –VS are a completely different story.  
T he amplifier can safely withstand input voltages 20 volts below  
the minus supply voltage as long as the total voltage from the  
positive supply to the input terminal is less than 36 volts. In  
addition, the input stage typically maintains picoamp level input  
currents across that input voltage range.  
REV. A  
–13–  
AD822  
T he AD822 is designed for 13 nV/√Hz wideband input voltage  
noise and maintains low noise performance to low frequencies  
(refer to Figure 11). T his noise performance, along with the  
AD822’s low input current and current noise means that the  
AD822 contributes negligible noise for applications with source  
resistances greater than 10 kΩ and signal bandwidths greater  
than 1 kHz. T his is illustrated in Figure 40.  
20mV  
2µ s  
100  
90  
10  
100k  
0%  
WHENEVER JOHNSON NOISE IS GREATER THAN  
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE  
CONSIDERED NEGLIGIBLE FOR APPLICATION.  
10k  
1k  
1kHz  
Figure 41. Sm all Signal Response of AD822 as Unity Gain  
Follower Driving 350 pF Capacitive Load  
RESISTOR JOHNSON  
NOISE  
100  
10  
5
10Hz  
4
3
1
AMPLIFIER GENERATED  
NOISE  
0.1  
10k  
100k  
1M  
10M  
100M  
1G  
10G  
SOURCE IMPEDANCE – Ω  
Figure 40. Total Noise vs. Source Im pedance  
2
1
O UTP UT CH ARACTERISTICS  
T he AD822 s unique bipolar rail-to-rail output stage swings  
within 5 mV of the minus supply and 10 mV of the positive  
supply with no external resistive load. T he AD822’s  
approximate output saturation resistance is 40 Ω sourcing and  
20 Ω sinking. T his can be used to estimate output saturation  
voltage when driving heavier current loads. For instance, when  
sourcing 5 mA, the saturation voltage to the positive supply rail  
will be 200 mV, when sinking 5 mA, the saturation voltage to  
the minus rail will be 100 mV.  
300  
1k  
3k  
10k  
30k  
CAPACITIVE LOAD FOR 20  
°
PHASE MARGIN – pF  
R
F
C
L
R
I
T he amplifier’s open-loop gain characteristic will change as a  
function of resistive load, as shown in Figures 7 through 10. For  
load resistances over 20 kΩ, the AD822’s input error voltage is  
virtually unchanged until the output voltage is driven to 180 mV  
of either supply.  
Figure 42. Capacitive Load Tolerance vs. Noise Gain  
Figure 43 shows a method for extending capacitance load drive  
capability for a unity gain follower. With these component  
values, the circuit will drive 5,000 pF with a 10% overshoot.  
If the AD822’s output is overdriven so as to saturate either of  
the output devices, the amplifier will recover within 2 µs of its  
input returning to the amplifier’s linear operating region.  
+V  
S
0.01µF  
8
100Ω  
Direct capacitive loads will interact with the amplifier’s effective  
output impedance to form an additional pole in the amplifier’s  
feedback loop, which can cause excessive peaking on the pulse  
response or loss of stability. Worst case is when the amplifier is  
used as a unity gain follower. Figure 41 shows the AD822’s  
pulse response as a unity gain follower driving 350 pF. T his  
amount of overshoot indicates approximately 20 degrees of  
phase margin—the system is stable, but is nearing the edge.  
Configurations with less loop gain, and as a result less loop  
bandwidth, will be much less sensitive to capacitance load  
effects. Figure 42 is a plot of capacitive load that will result in a  
20 degree phase margin versus noise gain for the AD822. Noise  
gain is the inverse of the feedback attenuation factor provided  
by the feedback network in use.  
1/2  
V
IN  
AD822  
V
0.01µF  
OUT  
4
C
L
–V  
S
20pF  
20kΩ  
Figure 43. Extending Unity Gain Follower Capacitive Load  
Capability Beyond 350 pF  
REV. A  
–14–  
AD822  
AP P LICATIO NS  
Table I. AD 822 In Am p P erform ance  
Single Supply Voltage-to-Fr equency Conver ter  
T he circuit shown in Figure 44 uses the AD822 to drive a low  
power timer, which produces a stable pulse of width t1. T he  
positive going output pulse is integrated by R1-C1 and used as  
one input to the AD822, which is connected as a differential  
integrator. T he other input (nonloading) is the unknown  
voltage, VIN. T he AD822 output drives the timer trigger input,  
closing the overall feedback loop.  
P aram eters  
VS = 3 V, 0 V  
VS = ؎5 V  
CMRR  
74 dB  
80 dB  
Common-Mode  
Voltage Range  
3 dB BW, G = 10  
G = 100  
–0.2 V to +2 V –5.2 V to +4 V  
180 kHz  
18 kHz  
180 kHz  
18 kHz  
tSET T LING  
2 V Step (VS = 0 V, 3 V)  
5 V (VS = ±5 V)  
Noise @ f = 1 kHz, G = 10  
2 µs  
+10V  
5 µs  
U4  
C5  
270 nV/√Hz  
270 nV/√Hz  
2.2 µV/√Hz  
1.15 mA  
REF-02  
0.1µF  
2
VREF = 5V  
6
G = 100 2.2 µV/√Hz  
CMOS  
ISUPPLY (T otal)  
1.10 mA  
3
5
RSCALE **  
10k  
OUT2  
OUT1  
74HCO4  
C3  
0.1µF  
U3A  
2
4
U3B  
4
3
1
5µs  
U2  
CMOS 555  
0.01µF, 2%  
100  
90  
4
8
R2  
R3*  
499k, 1%  
U1  
116k  
R
V+  
C1  
6
3
THR  
OUT  
1/2  
2
7
TR  
R1  
AD822B  
5
VIN  
CV  
DIS  
499k, 1%  
GND  
C6  
0V TO 2.5V  
FULL SCALE  
390pF  
1
C2  
5%  
C4  
0.01µF  
0.01µF, 2%  
10  
(NPO)  
0%  
NOTES:  
1V  
fOUT = VIN /(VREF*t1), t1 = 1.1*R3*C6  
= 25kHz fS AS SHOWN.  
* = 1% METAL FILM, <50ppm/°C TC  
** = 10%, 20T FILM, <100ppm/°C TC  
Figure 45a. Pulse Response of In Am p to a 500 m V p-p  
Input Signal; VS = +5 V, 0 V; Gain = 10  
t1 = 33µs FOR fOUT = 20kHz @ VIN = 2.0V  
R1  
R2  
9k  
R3  
1k  
R4  
1k  
R5  
9k  
R6  
Figure 44. Single Supply Voltage-to-Frequency Converter  
OHMTEK  
PART # 1043  
VREF  
90k  
90k  
T ypical AD822 bias currents of 2 pA allow megaohm-range  
source impedances with negligible dc errors. Linearity errors on  
the order of 0.01% full scale can be achieved with this circuit.  
T his performance is obtained with a 5 volt single supply which  
delivers less than 1 mA to the entire circuit.  
G =10  
G =100  
G =100  
G =10  
+VS  
1/2  
0.1µF  
Single Supply P rogram m able Gain Instrum entation Am plifier  
T he AD822 can be configured as a single supply instrumenta-  
tion amplifier that is able to operate from single supplies down  
to 3 V, or dual supplies up to ±15 V. Using only one AD822  
rather than three separate op amps, this circuit is cost and power  
efficient. AD822 FET inputs’ 2 pA bias currents minimize offset  
errors caused by high unbalanced source impedances.  
6
2
1
7
1/2  
AD822  
RP  
AD822  
5
3
VOUT  
VIN1  
VIN2  
4
1kΩ  
RP  
1kΩ  
R6  
R4 + R5  
(G =10) VOUT = (VIN1 –VIN2) (1+  
(G =100) VOUT = (VIN1 –VIN2) (1+  
) +VREF  
) +VREF  
R5 + R6  
R4  
An array of precision thin-film resistors sets the in amp gain to  
be either 10 or 100. T hese resistors are laser-trimmed to ratio  
match to 0.01%, and have a maximum differential T C of  
5 ppm/°C.  
FOR R1 = R6, R2 = R5, AND R3 = R4  
Figure 45b. A Single Supply Program m able  
Instrum entation Am plifier  
REV. A  
–15–  
AD822  
+3V  
3
Low D r opout Bipolar Br idge D r iver  
T he AD822 can be used for driving a 350 ohm Wheatstone  
bridge. Figure 47 shows one half of the AD822 being used to  
buffer the AD589—a 1.235 V low power reference. T he output  
of +4.5 V can be used to drive an A/D converter front end. T he  
other half of the AD822 is configured as a unity-gain inverter,  
and generates the other bridge input of –4.5 V. Resistors R1 and  
R2 provide a constant current for bridge excitation. T he AD620  
low power instrumentation amplifier is used to condition the  
differential output voltage of the bridge. T he gain of the AD620  
is programmed using an external resistor RG, and determined  
by:  
0.1µF  
0.1µF  
95.3k  
47.5k  
1µF  
8
CHANNEL 1  
1/2  
AD822  
1
MYLAR  
500µF  
2
L
4.99k  
95.3k  
10k  
10k  
HEADPHONES  
32Ω IMPEDANCE  
R
4.99k  
7
49.4 kΩ  
6
G =  
+1  
1/2  
47.5k  
1µF  
AD822  
RG  
500µF  
CHANNEL 2  
5
4
MYLAR  
+V  
S
49.9k  
Figure 46. 3 Volt Single Supply Stereo Headphone Driver  
R1  
20Ω  
+1.235V  
8
3
2
3 Volt, Single Supply Ster eo H eadphone D r iver  
T he AD822 exhibits good current drive and T HD+N perfor-  
mance, even at 3 V single supplies. At 1 kHz, total harmonic  
distortion plus noise (T HD+N) equals –62 dB (0.079%) for a  
300 mV p-p output signal. T his is comparable to other single  
supply op amps which consume more power and cannot run on  
3 V power supplies.  
1/2  
AD822  
TO A/D CONVERTER  
REFERENCE INPUT  
1
AD589  
26.4k, 1%  
350Ω  
10k  
1%  
+V  
S
350Ω  
7
3
2
AD620  
R
6
G
350Ω  
350Ω  
5
4
In Figure 46, each channel s input signal is coupled via a 1 µF  
Mylar capacitor. Resistor dividers set the dc voltage at the non-  
inverting inputs so that the output voltage is midway between  
the power supplies (+1.5 V). T he gain is 1.5. Each half of the  
AD822 can then be used to drive a headphone channel. A 5 Hz  
high-pass filter is realized by the 500 µF capacitors and the head-  
phones, which can be modeled as 32 ohm load resistors to  
ground. T his ensures that all signals in the audio frequency  
range (20 Hz–20 kHz) are delivered to the headphones.  
10k  
1%  
V
REF  
–V  
S
10k  
1%  
6
5
1/2  
AD822  
+V  
S
+5V  
–5V  
–4.5V  
7
1µF  
1µF  
0.1µF  
4
R2  
20Ω  
GND  
0.1µF  
+V  
S
–V  
S
Figure 47. Low Dropout Bipolar Bridge Driver  
O UTLINE D IMENSIO NS  
D imensions shown in inches and (mm).  
Mini-D IP (N) P ackage  
Cer dip (Q ) P ackage  
SO IC (R) P ackage  
0.005 (0.13) MIN  
0.055 (1.35) MAX  
0.150 (3.81)  
8
5
0.25  
(6.35)  
8
5
0.31  
8
1
5
4
PIN 1  
0.310 (7.87)  
0.244 (6.20)  
0.228 (5.79)  
(7.87)  
0.157 (3.99)  
0.150 (3.81)  
0.220 (5.59)  
1
4
1
4
PIN 1  
0.070 (1.78)  
0.030 (0.76)  
0.39 (9.91) MAX  
0.035±0.01  
(0.89±0.25)  
0.405 (10.29) MAX  
0.165±0.01  
(4.19±0.25)  
0.200  
0.060 (1.52)  
0.015 (0.38)  
0.197 (5.01)  
0.189 (4.80)  
(5.08)  
MAX  
0.18±0.03  
(4.57±0.76)  
0.125  
(3.18)  
MIN  
0.102 (2.59)  
0.094 (2.39)  
0.150  
(3.81)  
MIN  
0.010 (0.25)  
0.004 (0.10)  
0.200 (5.08)  
0.125 (3.18)  
0.10  
(2.54)  
0.018±0.003  
(0.46±0.08)  
0.033  
(0.84)  
NOM  
0.019 (0.48)  
0.014 (0.36)  
0.050  
(1.27)  
BSC  
SEATING  
PLANE  
SEATING  
PLANE  
0.023 (0.58)  
0.014 (0.36)  
0.100 (2.54)  
BSC  
BSC  
0.30 (7.62)  
REF  
0.320 (8.13)  
0.020 (0.051) x 45  
CHAMF  
°
0.290 (7.37)  
0.190 (4.82)  
0.170 (4.32)  
8
0
°
°
0.090  
(2.29)  
0.011±0.003  
(0.28±0.08)  
10  
°
0.015 (0.38)  
0.008 (0.20)  
0°  
0.030 (0.76)  
0.018 (0.46)  
0.098 (0.2482)  
0.075 (0.1905)  
15  
°
0
°
0°-15°  
REV. A  
–16–  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明