AD8231ACPZ-R7 [ADI]
Zero Drift, Digitally Programmable Instrumentation Amplifier; 零漂移，数字可编程仪表放大器
| 型号： | AD8231ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Zero Drift, Digitally Programmable Instrumentation Amplifier |
| 文件： | 总20页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Zero Drift, Digitally Programmable
Instrumentation Amplifier
AD8231
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Digitally/pin programmable gain
G = 1, 2, 4, 8, 16, 32, 64, 128
Specified from −40°C to +125°C
50 nV/°C maximum input offset drift
10 ppm/°C maximum gain drift
Excellent dc performance
80 dB minimum CMR, G = 1
15 μV maximum input offset voltage
500 pA maximum bias current
0.7 μV p-p noise (0.1 Hz to 10 Hz)
Good ac performance
1
2
3
4
12
11
10
9
NC
–INA
+INA
NC
+V
–V
S
LOGIC
S
IN-AMP
OUTA
REF
OP
AMP
AD8231
2.7 MHz bandwidth, G = 1
1.1 V/ꢀs slew rate
Rail-to-rail input and output
Shutdown/multiplex
Extra op amp
Figure 1.
Single supply range: 3 V to 6 V
Dual supply range: 1.5 V to 3 V
Table 1. Instrumentation/Difference Amplifiers by Category
High
Low
Cost
High
Voltage
Mil
Grade
Low
Power
Digital
Gain
Performance
AD6231
AD85531
AD628
AD629
AD620
AD621
AD524
AD526
AD624
AD6271
AD82311
AD8250
AD8251
AD85551
AD85561
AD85571
APPLICATIONS
AD8221
AD82201
AD8222
AD82241
Pressure and strain transducers
Thermocouples and RTDs
Programmable instrumentation
Industrial controls
Weigh scales
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8231 also includes an uncommitted op amp that can be
used for additional gain, differential signal driving or filtering.
Like the in-amp, the op amp has an auto-zero architecture, rail-
to-rail input, and rail-to-rail output.
The AD8231 is a low drift, rail-to-rail, instrumentation ampli-
fier with software programmable gains of 1, 2, 4, 8, 16, 32, 64, or
128. The gains are programmed via digital logic or pin
strapping.
The AD8231 includes a shutdown feature that reduces current
to a maximum of 1 μA. In shutdown, both amplifiers also have
a high output impedance. This allows easy multiplexing of
multiple amplifiers without additional switches.
The AD8231 is ideal for applications that require precision
performance over a wide temperature range, such as industrial
temperature sensing and data logging. Because the gain setting
resistors are internal, maximum gain drift is only 10 ppm/°C.
Because of the auto-zero input stage, maximum input offset is
15 μV and maximum input offset drift is just 50 nV/°C. CMRR
is also guaranteed over temperature at 80 dB for G = 1, increas-
ing to 110 dB at higher gains.
The AD8231 is specified over the extended industrial tempera-
ture range of −40°C to +125°C. It is available in a 4 mm × 4 mm
16-lead LFCSP (chip scale).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8231
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Amplifier Architecture .............................................................. 14
Gain Selection............................................................................. 14
Reference Terminal .................................................................... 14
Layout .......................................................................................... 15
Input Bias Current Return Path ............................................... 15
RF Interference ........................................................................... 15
Common-Mode Input Voltage Range..................................... 16
Applications Information.............................................................. 17
Differential Output .................................................................... 17
Multiplexing................................................................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Instrumentation Amplifier Performance Curves..................... 9
Operational Amplifier Performance Curves .......................... 12
Performance Curves Valid for Both Amplifiers ..................... 13
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8231
SPECIFICATIONS
VS = 5 V, VREF = 2.5 V, G = 1, RL = 10 kΩ, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
INSTRUMENTATION AMPLIFIER
OFFSET VOLTAGE
Input Offset, VOSI
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
INPUT CURRENTS
VOS RTI = VOSI + VOSO/G
TA = −40°C to +125°C
TA = −40°C to +125°C
4
15
μV
0.01
15
0.05
30
μV/°C
μV
0.05
0.5
μV/°C
Input Bias Current
250
20
500
5
100
0.5
pA
nA
pA
nA
TA = −40°C to +125°C
Input Offset Current
TA = −40°C to +125°C
1, 2, 4, 8, 16, 32, 64, 128
GAINS
Gain Error
G = 1
G = 2 to 128
Gain Drift
G = 1
0.05
0.8
%
%
3
3
10
10
ppm/°C
ppm/°C
G = 2 to 128
CMRR
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
NOISE
80
86
92
98
104
110
110
110
dB
dB
dB
dB
dB
dB
dB
dB
en = √(eni2 + (eno/G)2), VIN+, VIN− = 2.5 V
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz,
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
Input Voltage Noise, eni
32
27
39
0.7
58
50
70
1.1
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
Output Voltage Noise, eno
OTHER INPUT CHARACTERISTICS
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
REFERENCE INPUT
10||5
110
GΩ||pF
dB
V
100
0.05
4.95
+5.2
Input Impedance
Voltage Range
28
kΩ
V
−0.2
Rev. 0 | Page 3 of 20
AD8231
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Bandwidth
G = 1
G = 2
2.7
2.5
MHz
MHz
Gain Bandwidth Product
G = 4 to 128
Slew Rate
7
1.1
MHz
V/μs
OUTPUT CHARACTERISTICS
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
4.9
4.8
4.94
4.88
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
DIGITAL INTERFACE
Input Voltage Low
Input Voltage High
Setup Time to CS high
Hold Time after CS high
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
1.0
V
V
ns
ns
4.0
50
20
OPERATIONAL AMPLIFIER
INPUT CHARACTERISTICS
Offset Voltage, VOS
5
15
μV
Temperature Drift
Input Bias Current
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.01
250
0.06
500
5
100
0.5
4.95
uV/°C
pA
nA
pA
nA
Input Offset Current
20
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
0.05
100
100
100
V
120
120
115
20
V/mV
dB
dB
nV/√Hz
μV p-p
f = 0.1 Hz to 10 Hz
0.4
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
1
0.5
MHz
V/μs
OUTPUT CHARACTERISTICS
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
4.9
4.8
4.96
4.92
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
BOTH AMPLIFIERS
POWER SUPPLY
Quiescent Current
Quiescent Current (Shutdown)
4
0.01
5
1
mA
μA
Rev. 0 | Page 4 of 20
AD8231
VS = 3.0 V, VREF = 1.5 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
INSTRUMENTATION AMPLIFIER
OFFSET VOLTAGE
VOS RTI = VOSI + VOSO/G
Input Offset, VOSI
4
15
μV
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
INPUT CURRENTS
0.01
15
0.05
0.05
30
0.5
μV/°C
μV
μV/°C
Input Bias Current
250
20
500
5
100
0.5
pA
nA
pA
nA
TA = −40°C to +125°C
Input Offset Current
TA = −40°C to +125°C
1, 2, 4, 8, 16, 32, 64, 128
GAINS
Gain Error
G = 1
G = 2 to 128
Gain Drift
G = 1
0.05
0.8
%
%
3
3
10
10
ppm/°C
ppm/°C
G = 2 to 128
CMRR
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
G = 64
G = 128
NOISE
80
86
92
98
104
110
110
110
dB
dB
dB
dB
dB
dB
dB
dB
en = √(eni2 + (eno/G)2)
V
IN+, VIN− = 2.5 V, TA = 25°C
Input Voltage Noise, eni
f = 1 kHz
40
35
48
0.8
72
62
83
1.4
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
Output Voltage Noise, eno
OTHER INPUT CHARACTERISTICS
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
REFERENCE INPUT
10||5
110
GΩ||pF
dB
V
100
0.05
2.95
+3.2
Input Impedance
Voltage Range
28
kΩ||pF
V
−0.2
Rev. 0 | Page 5 of 20
AD8231
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Bandwidth
G = 1
G = 2
2.7
2.5
MHz
MHz
Gain Bandwidth Product
G = 4 to 128
Slew Rate
7
1.1
MHz
V/μs
OUTPUT CHARACTERISTICS
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
2.9
2.8
2.94
2.88
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
DIGITAL INTERFACE
Input Voltage Low
Input Voltage High
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.7
V
V
ns
ns
2.3
60
20
CS
Setup Time to high
CS
Hold Time after high
OPERATIONAL AMPLIFIER
INPUT CHARACTERISTICS
Offset Voltage, VOS
5
15
μV
Temperature Drift
Input Bias Current
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
0.01
250
0.06
500
5
100
0.5
2.95
μV/°C
pA
nA
pA
nA
Input Offset Current
20
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
0.05
100
100
100
V
120
120
115
27
V/mV
dB
dB
nV/√Hz
μV p-p
f = 0.1 Hz to 10 Hz
0.6
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
1
0.5
MHz
V/μs
OUTPUT CHARACTERISTICS
Output Voltage High
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
2.9
2.8
2.96
2.82
60
80
70
V
V
mV
mV
mA
Output Voltage Low
100
200
Short-Circuit Current
BOTH AMPLIFIERS
POWER SUPPLY
Quiescent Current
Quiescent Current (Shutdown)
3.5
0.01
4.5
1
mA
μA
Rev. 0 | Page 6 of 20
AD8231
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
Table 5.
Parameter
Rating
Supply Voltage
6 V
Thermal Pad
θJA
54
96
Unit
°C/W
°C/W
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature Range
Operational Temperature Range
Indefinite1
Soldered to Board
Not Soldered to Board
−VS − 0.3 V to +VS + 0.3 V
−VS − 0.3 V to +VS + 0.3 V
–65°C to +150°C
–40°C to +125°C
The θJA values in Table 5 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, then it is
also assumed it is connected to a plane. θJC at the exposed pad
is 6.3°C/W.
Package Glass Transition Temperature 130°C
ESD (Human Body Model)
ESD (Charged Device Model)
ESD (Machine Model)
1 For junction temperatures between 105°C and 130°C, short-circuit operation
beyond 1000 hours may impact part reliability.
1.5 kV
1.5 kV
0.2 kV
Maximum Power Dissipation
The maximum safe power dissipation for the AD8231 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 7 of 20
AD8231
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 +V
11 –V
NC
(IN-AMP –IN) –INA
(IN-AMP +IN) +INA
NC
1
2
3
4
S
S
AD8231
TOP VIEW
(Not to Scale)
10 OUTA (IN-AMP OUT)
REF
9
NC = NO CONNECT
Figure 2. 16-Lead LFCSP (Chip Scale)
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1
2
3
4
5
6
7
8
9
NC
No Connect.
−INA
+INA
NC
In-Amp Negative Input.
In-Amp Positive Input.
No Connect.
SDN
Shutdown.
+INB
−INB
OUTB
REF
Op Amp Positive Input.
Op Amp Negative Input.
Op Amp Output.
In-Amp Reference Pin. It should be driven with a low impedance. Output is referred to
this pin.
10
11
12
13
14
15
16
OUTA
−VS
+VS
CS
In-Amp Output.
Negative Power Supply. Connect to ground in single supply applications.
Positive Power Supply.
Chip Select. Enables digital logic interface.
Gain Setting Bit (LSB).
Gain Setting Bit.
Gain Setting Bit (MSB).
A0
A1
A2
Rev. 0 | Page 8 of 20
AD8231
TYPICAL PERFORMANCE CHARACTERISTICS
INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES
6
50
40
G = +128
0V, 4.96V
G = +64
G = +32
G = +16
G = +8
G = +4
G = +2
G = +1
5
4
30
20
10
5V SINGLE SUPPLY
4.92V, 2.5V
3
0
0V, 2.96V
2
–10
–20
–30
–40
3V SINGLE SUPPLY
1
2.92V, 1.5V
4
0V, 0.04V
1
0
0
2
3
5
6
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 3. Input Common-Mode Range vs. Output Voltage, VREF = 0 V
Figure 6. Gain vs. Frequency
6
140
120
100
80
G = +128
1.5V, 4.96V
5
0.02V, 4.22V
G = +8
G = +1
4
5V SINGLE SUPPLY
1.5V, 2.96V
4.98V, 3.22V
4.98V, 1.78V
3
2
1
0
0.02V, 2.22V
0.02V, 0.78V
2.98V, 2.22V
3V SINGLE SUPPLY
60
2.98V, 0.78V
1.5V, 0.04V
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
100
1k
10k
100k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 4. Input Common-Mode Range vs. Output Voltage, VREF = 1.5 V
Figure 7. CMRR vs. Frequency
6
2.5V, 4.96V
5
G = +128, 0.4µV/DIV
G = +1, 1µV/DIV
5V SINGLE SUPPLY
4
4.98V, 3.72V
0.02V, 3.72V
3
2
1
0
2.98V, 2.72V
2.5V, 2.96V
0.02V, 1.72V
0.02V, 1.28V
3V SINGLE
SUPPLY
4.98V,1.28V
2.5V, 0.04V
1s/DIV
2.98V, 0.28V
3.0 3.5 4.0
OUTPUT VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
4.5
5.0
Figure 8. 0.1 Hz to 10 Hz Noise
Figure 5. Input Common-Mode Range vs. Output Voltage, VREF = 2.5 V
Rev. 0 | Page 9 of 20
AD8231
100
90
80
70
60
50
40
30
20
10
1.0
0.8
G = +1
G = +8
G = +128
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
+V = +1.5V
S
–V = –1.5V
S
V
= 0V
REF
0
1
10
100
FREQUENCY (Hz)
1k
–1.5 –1.2 –0.9 –0.6 –0.3
0
0.3
0.6
0.9
1.2
1.5
V
(V)
CM
Figure 9. Voltage Noise Spectral Density vs. Frequency, 5 V, 1 Hz to 1000 Hz
Figure 12. Bias Current vs. Common-Mode Voltage, 3 V
1000
G = +1
G = +8
G = +128
900
800
700
600
500
400
300
200
100
0
20mV/DIV
5µs/DIV
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 13. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 500 pF
Figure 10. Voltage Noise Spectral Density vs. Frequency, 5V, 1 Hz to 1 MHz
2.0
1.5
1.0
0.5
0
500pF
800pF
300pF
NO
LOAD
–0.5
–1.0
+V = +2.5V
S
–1.5
–2.0
–V = –2.5V
S
20mV/DIV
4µs/DIV
V
= 0V
REF
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
V
(V)
CM
Figure 14. Small Signal Pulse Response for Various Capacitive Loads, G = 1
Figure 11. Bias Current vs. Common-Mode Voltage, 5 V
Rev. 0 | Page 10 of 20
AD8231
G = +8
G = +32
G = +128
2V/DIV
17.6µs TO 0.01%
21.4µs TO 0.001%
0.001%/DIV
100µs/DIV
20mV/DIV
10µs/DIV
Figure 15. Small Signal Pulse Response, G = 8, 32, 128, RL = 2 kΩ, CL = 500 pF
Figure 18. Large Signal Pulse Response, G = 128, VS = 5 V
25
20
15
10
5
0.001%
2V/DIV
0.01%
3.95µs TO 0.01%
4µs TO 0.001%
0.001%/DIV
10µs/DIV
0
1
10
100
1k
GAIN (V/V)
Figure 16. Large Signal Pulse Response, G = 1, VS = 5 V
Figure 19. Settling Time vs. Gain for a 4 V p-p Step, VS = 5 V
25
0.001%
20
15
10
5
2V/DIV
0.01%
3.75µs TO 0.01%
3.8µs TO 0.001%
0.001%/DIV
10µs/DIV
0
1
10
100
1k
GAIN (V/V)
Figure 17. Large Signal Pulse Response, G = 8, VS = 5 V
Figure 20. Settling Time vs. Gain for a 2 V p-p Step, VS = 3 V
Rev. 0 | Page 11 of 20
AD8231
OPERATIONAL AMPLIFIER PERFORMANCE CURVES
100
80
60
40
20
0
–90
NO
LOAD
–100
–110
–120
–130
–140
–150
300pF
76° PHASE
MARGIN
800pF
1nF
1.5nF
R
C
= 10kΩ
= 200pF
L
L
20mV/DIV
5µs/DIV
–20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 21. Open Loop Gain and Phase vs. Frequency, VS = 5 V
Figure 24. Small Signal Response for Various Capacitive Loads, VS = 3 V
100
80
60
40
20
0
–90
NO
LOAD
–100
–110
–120
1nF║2kΩ
1.5nF║2kΩ
72° PHASE
MARGIN
–130
–140
R
C
= 10kΩ
= 200pF
L
L
–20
–150
10M
10
100
1k
10k
100k
1M
TIME (5µs/DIV)
FREQUENCY (Hz)
Figure 22. Open Loop Gain and Phase vs. Frequency, VS = 3 V
Figure 25. Large Signal Transient Response, VS = 5 V
NO
LOAD
1nF
2nF
800pF
NO
LOAD
1nF║2kΩ
1.5nF║2kΩ
1.5nF
20mV/DIV
5µs/DIV
TIME (5µs/DIV)
Figure 26. Large Signal Transient Response, VS = 3 V
Figure 23. Small Signal Response for Various Capacitive Loads, VS = 5 V
Rev. 0 | Page 12 of 20
AD8231
PERFORMANCE CURVES VALID FOR BOTH AMPLIFIERS
7
5
4
3
2
1
0
+125°C
+85°C
6
–40°C SOURCE
+25°C SOURCE
+85°C SOURCE
+125°C SOURCE
5
+25°C
–40°C
4
–40°C SINK
+25°C SINK
+85°C SINK
+125°C SINK
3
2
1
0
2.7
3.1
3.5
3.9
4.3
4.7
(V)
5.1
5.5
5.9
0
5
10
15
20
25
V
OUTPUT CURRENT (mA)
SUPPLY
Figure 29. Output Voltage Swing vs. Output Current, VS = 5 V
Figure 27. Supply Current vs. Supply Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
–40°C SOURCE
+25°C SOURCE
+85°C SOURCE
+125°C SOURCE
–40°C SINK
+25°C SINK
+85°C SINK
+125°C SINK
0
5
10
15
20
25
OUTPUT CURRENT (mA)
Figure 28. Output voltage Swing vs. Output Current, VS = 3 V
Rev. 0 | Page 13 of 20
AD8231
THEORY OF OPERATION
CS A0 A1 A2
SDN
A4
OUTB
–INA
14kΩ
14kΩ
14kΩ
–INB
+INB
OUTA
A1
A2
A3
14kΩ
+INA
AD8231
+V
–V
REF
S
S
Figure 30. Simplified Schematic
Table 7. Truth Table for AD8231 Gain Settings
AMPLIFIER ARCHITECTURE
CS
A2
A1
A0
Gain
The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage. Figure 30 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of A3 and four 14 kꢀ
resistors. Amplifier A1, Amplifier A2, and Amplifier A3 are all
zero drift, rail-to-rail input, rail-to rail-output amplifiers.
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
High
High
High
High
X
Low
Low
High
High
Low
Low
High
High
X
Low
High
Low
High
Low
High
Low
High
X
1
2
4
8
16
32
64
128
No change
The AD8231 design makes it extremely robust over tempera-
ture. The AD8231 uses an internal thin film resistor to set the
gain. Since all of the resistors are on the same die, gain
temperature drift performance and CMRR drift performance
are better than can be achieved with topologies using external
resistors. The AD8231 also uses an auto-zero topology to null
the offsets of all its internal amplifiers. Since this topology
continually corrects for any offset errors, offset temperature
drift is nearly nonexistent.
REFERENCE TERMINAL
The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 30, the reference
terminal, REF, is at one end of a 14 kꢀ resistor. Additional
impedance at the REF terminal adds to this 14 kꢀ resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.
GAIN SELECTION
The AD8231’s gain is set by voltages applied to the A0, A1,
CS
and A2 pins. To change the gain, the
pin must be driven
CS
low. When the
pin is driven high, the gain is latched, and
voltages at the A0 to A2 pins have no effect. Table 7 shows the
different gain settings.
The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to Figure 16
through Figure 20 to determine the settling time for different
gains.
Rev. 0 | Page 14 of 20
AD8231
INCORRECT
CORRECT
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8231 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 32.
AD8231
AD8231
IN-AMP
IN-AMP
V
REF
V
REF
INCORRECT
CORRECT
+
+V
+V
S
S
AD8231
OP AMP
–
Figure 31. Driving the Reference Pin
AD8231
AD8231
REF
REF
REF
REF
LAYOUT
The AD8231 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout. The AD8231 pinout is arranged in
a logical manner to aid in this task.
–V
S
–V
S
TRANSFORMER
TRANSFORMER
+V
+V
S
S
Power Supplies
The AD8231 should be decoupled with a 0.1 μF bypass capacitor
between the two supplies. This capacitor should be placed as close
as possible to Pin 11 and Pin 12, either directly next to the pins or
beneath the pins on the backside of the board. The AD8231’s auto-
zero architecture requires a low ac impedance between the supplies.
Long trace lengths to the bypass capacitor increase this impedance,
which results in a larger input offset voltage.
AD8231
AD8231
REF
10MΩ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
+V
+V
S
S
C
C
C
R
R
Package Considerations
1
fHIGH-PASS
=
AD8231
2πRC
AD8231
C
The AD8231 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; it may not have the same thermal pad size and
leads. Refer to the Outline Dimensions section to verify that the
PCB symbol has the correct dimensions. Space between the
leads and thermal pad should be kept as wide as possible for the
best bias current performance.
REF
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 32. Creating an IBIAS Path
RF INTERFERENCE
Thermal Pad
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the input
of the instrumentation amplifier, as shown in Figure 33. The
filter limits the input signal bandwidth according to the
following relationship:
The AD8231 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to −VS. The pad can either be
left unconnected or connected to the negative supply rail. For
high vibration applications, a landing is recommended.
Because the AD8231 dissipates little power, heat dissipation is
rarely an issue. If improved heat dissipation is desired (for
example, when ambient temperatures are near 125°C or when
driving heavy loads), connect the thermal pad to the negative
supply rail. For the best heat dissipation performance, the
negative supply rail should be a plane in the board. See the
Thermal Resistance section for thermal coefficients with and
without the pad soldered.
1
FilterFreqDiff =
2π R(2CD + CC )
1
FilterFreqCM =
2π RCC
where CD ≥ 10CC.
Rev. 0 | Page 15 of 20
AD8231
+V
S
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8231 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8231 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal could
be limited, refer to Figure 3 through Figure 5 or use the following
formula:
0.1µF
+INA
10µF
C
1nF
C
R
4.02kΩ
V
C
D
10nF
OUT
AD8231
R
REF
–INA
4.02kΩ
C
C
1nF
VDIFF ×Gain
0.1µF
10µF
−VS + 0.04 V < VCM
±
<+VS − 0.04 V
2
–V
S
If more common mode range is required, the simplest solution is to
apply less gain in the instrumentation amplifier. The extra op amp
can be used to provide another gain stage after the in-amp. Because
the AD8231 has good offset and noise performance at low gains,
applying less gain in the instrumentation amplifier generally has a
limited impact on the overall system performance.
Figure 33. RFI Suppression
Figure 33 shows an example where the differential filter
frequency is approximately 2 kHz, and the common-mode filter
frequency is approximately 40 kHz.
Values of R and CC should be chosen to minimize RFI. Mismatch
between the R × CC at the positive input and the R × CC at
negative input degrades the CMRR of the AD8231. By using a
value of CD ten times larger than the value of CC, the effect of
the mismatch is reduced and performance is improved.
Rev. 0 | Page 16 of 20
AD8231
APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
MULTIPLEXING
SDN0
SDN1
SDN2
SDN3
Figure 34 shows how to create a differential output in-amp
using the AD8231 uncommitted op amp. Errors from the op
amp are common to both outputs and are thus common-mode.
Errors from mismatched resistors also create a common-mode
dc offset. Because these errors are common-mode, they will
likely be rejected by the next device in the signal chain.
3
+IN
10
IN-AMP
+OUT
REF
9
2
–IN
4.99kΩ
4.99kΩ
V
REF
7
6
–
+
OP AMP
8
Figure 35.
–OUT
Figure 34. Differential Output Using Op Amp
The outputs of both the AD8231 in-amp and op amp are high
impedance in the shutdown state. This feature allows several
AD8231s to be multiplexed together without any external
switches. Figure 35 shows an example of such a configuration.
All the outputs are connected together and only one amplifier is
turned on at a time. This feature is analogous to the high Z
mode of digital tristate logic. Because the output impedance in
shutdown is multiple megaohms, several thousand AD8231s
can theoretically be multiplexed in such a way.
The AD8231 can enter and leave shutdown mode very quickly.
However, when the amplifier wakes up and reconnects its input
circuitry, the voltage at its internal input nodes changes dramati-
cally. It will take time for the output of the amplifier to settle.
Refer to Figure 16 through Figure 20 to determine the settling
time for different gains. This settling time limits how quickly
SDN
the user can multiplex the AD8231 with the
pin.
Rev. 0 | Page 17 of 20
AD8231
OUTLINE DIMENSIONS
4.00
0.60 MAX
(BOTTOM VIEW)
BSC SQ
0.60 MAX
0.65 BSC
PIN 1
INDICATOR
13
16
1
12
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
3.75
BSC SQ
0.75
0.60
0.50
9
4
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8231ACPZ-R71
AD8231ACPZ-RL1
AD8231ACPZ-WP1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-16-4
CP-16-4
16-Lead LFCSP_VQ, 7”Tape and Reel
16-Lead LFCSP_VQ, 13”Tape and Reel
16-Lead LFCSP_VQ, Waffle Pack
CP-16-4
1 Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
AD8231
NOTES
Rev. 0 | Page 19 of 20
AD8231
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06586-0-5/07(0)
Rev. 0 | Page 20 of 20
相关型号：
AD8231ACPZ-WP
INSTRUMENTATION AMPLIFIER, 15 uV OFFSET-MAX, 1 MHz BAND WIDTH, QCC16, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGC, LFCSP-16
ROCHESTER
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