AD823ARZ-RL [ADI]
Dual, 16 MHz, Rail-to-Rail FET Input Amplifier; 双通道， 16 MHz的轨到轨FET输入放大器
| 型号： | AD823ARZ-RL |
| 厂家： | 
ADI |
| 描述： | Dual, 16 MHz, Rail-to-Rail FET Input Amplifier |
| 文件： | 总20页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 16 MHz, Rail-to-Rail
FET Input Amplifier
AD823
FEATURES
CONNECTION DIAGRAM
Single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 3 V to 36 V
High load drive
1
2
3
4
8
7
6
5
+V
S
OUT1
–IN1
OUT2
–IN2
+IN2
+IN1
–V
S
AD823
Figure 1. 8-Lead PDIP and SOIC
Capacitive load drive of 500 pF, G = +1
Output current of 15 mA, 0.5 V from supplies
Excellent ac performance on 2.6 mA/amplifier
−3 dB bandwidth of 16 MHz, G = +1
350 ns settling time to 0.01% (2 V step)
Slew rate of 22 V/μs
R
C
= 100kΩ
= 50pF
L
L
+V = +3V
G = +1
S
3V
Good dc performance
800 μV maximum input offset voltage
2 μV/°C offset voltage drift
25 pA maximum input bias current
Low distortion: −108 dBc worst harmonic @ 20 kHz
Low noise: 16 nV/√Hz @ 10 kHz
GND
No phase inversion with inputs to the supply rails
500mV
200µs
APPLICATIONS
Figure 2. Output Swing, +VS = +3 V, G = +1
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 16-bit data acquisition systems
Medical instrumentation
2
1
0
+V = +5V
S
G = +1
–1
–2
–3
–4
–5
–6
GENERAL DESCRIPTION
The AD823 is a dual precision, 16 MHz, JFET input op amp
that can operate from a single supply of 3.0 V to 36 V or from
dual supplies of 1.ꢀ V to 18 V. It has true single-supply
capability with an input voltage range extending below ground
in single-supply mode. Output voltage swing extends to within
ꢀ0 mV of each rail for IOUT ≤ 100 μA, providing outstanding
output dynamic range.
–7
–8
1k
10k
100k
1M
10M
FREQUENCY (Hz)
An offset voltage of 800 μV maximum, an offset voltage drift of
2 μV/°C, input bias currents below 2ꢀ pA, and low input voltage
noise provide dc precision with source impedances up to a
Gigaohm. It provides 16 MHz, −3 dB bandwidth, −108 dB THD
@ 20 kHz, and a 22 V/μs slew rate with a low supply current of
2.6 mA per amplifier. The AD823 drives up to ꢀ00 pF of direct
capacitive load as a follower and provides an output current of
1ꢀ mA, 0.ꢀ V from the supply rails. This allows the amplifier to
handle a wide range of load conditions.
Figure 3. Small Signal Bandwidth, G = +1
This combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile ampli-
fier for applications such as A/D drivers, high speed active
filters, and other low voltage, high dynamic range systems.
The AD823 is available over the industrial temperature range of
−40°C to +8ꢀ°C and is offered in both 8-lead PDIP and 8-lead
SOIC packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1995–2007 Analog Devices, Inc. All rights reserved.
AD823
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 13
Output Impedance ..................................................................... 14
Application Notes........................................................................... 15
Input Characteristics.................................................................. 15
Output Characteristics............................................................... 15
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
REVISION HISTORY
2/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to DC Performance .......................................................... 5
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide ......................................................... 19
5/04—Rev. 0 to Rev. A
Changes to Specifications................................................................ 2
Changes to Ordering Guide ......................................................... 17
Updated Outline Dimensions....................................................... 17
5/95—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD823
SPECIFICATIONS
At TA = 2ꢀ°C, +VS = +ꢀ V, RL = 2 kΩ to 2.ꢀ V, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
12
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
G = +1
VO = 2 V p-p
G = −1, VO = 4 V Step
16
3.5
22
MHz
MHz
V/μs
14
Settling Time
to 0.1%
to 0.01%
G = −1, VO = 2 V Step
G = −1, VO = 2 V Step
320
350
ns
ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 10 kHz
f = 1 kHz
16
1
−108
nV/√Hz
fA/√Hz
dBc
RL = 600 Ω to 2.5 V, VO = 2 V p-p, f = 20 kHz
f = 1 kHz
f = 1 MHz
RL = 5 kΩ
RL = 5 kΩ
−105
−63
dB
dB
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
0.2
0.3
2
3
0.5
2
0.8
2.0
mV
mV
μV/°C
pA
nA
pA
nA
V/mV
V/mV
VCM = 0 V to 4 V
VCM = 0 V to 4 V
25
5
20
0.5
45
Open-Loop Gain
TMIN to TMAX
VO = 0.2 V to 4 V, RL = 2 kΩ
20
20
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = 100 μA
−0.2 to +3
60
−0.2 to +3.8
V
Ω
pF
dB
1013
1.8
76
VCM = 0 V to 3 V
0.025 to 4.975
V
IL = 2 mA
0.08 to 4.92
V
IL = 10 mA
0.25 to 4.75
V
Output Current
Short-Circuit Current
VOUT = 0.5 V to 4.5 V
Sourcing to 2.5 V
Sinking to 2.5 V
G = +1
16
40
30
500
mA
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
36
V
Quiescent Current
Power Supply Rejection Ratio
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
5.2
80
5.6
mA
dB
70
Rev. B | Page 3 of 20
AD823
At TA = 2ꢀ°C, +VS = +3.3 V, RL = 2 kΩ to 1.6ꢀ V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
12
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
G = +1
VO = 2 V p-p
G = −1, VO = 2 V Step
15
3.2
20
MHz
MHz
V/μs
13
Settling Time
to 0.1%
to 0.01%
G = −1, VO = 2 V Step
G = −1, VO = 2 V Step
250
300
ns
ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 10 kHz
f = 1 kHz
RL = 100 Ω, VO = 2 V p-p, f = 20 kHz
16
1
−93
nV/√Hz
fA/√Hz
dBc
f = 1 kHz
f = 1 MHz
RL = 5 kΩ
RL = 5 kΩ
−105
−63
dB
dB
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
0.2
0.5
2
3
0.5
2
1.5
2.5
mV
mV
μV/°C
pA
nA
pA
nA
V/mV
V/mV
VCM = 0 V to 2 V
VCM = 0 V to 2 V
25
5
20
0.5
30
Open-Loop Gain
TMIN to TMAX
VO = 0.2 V to 2 V, RL = 2 kΩ
15
12
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = 100 μA
−0.2 to +1
54
−0.2 to +1.8
V
Ω
pF
dB
1013
1.8
70
VCM = 0 V to 1 V
0.025 to 3.275
V
IL = 2 mA
0.08 to 3.22
V
IL = 10 mA
0.25 to 3.05
V
Output Current
Short-Circuit Current
VOUT = 0.5 V to 2.5 V
Sourcing to 1.5 V
Sinking to 1.5 V
G = +1
15
40
30
500
mA
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
36
V
Quiescent Current
Power Supply Rejection Ratio
TMIN to TMAX, total
VS = 3.3 V to 15 V, TMIN to TMAX
5.0
80
5.7
mA
dB
70
Rev. B | Page 4 of 20
AD823
At TA = 2ꢀ°C, VS = 1ꢀ V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
12
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p
Full Power Response
Slew Rate
G = +1
VO = 2 V p-p
G = −1, VO = 10 V Step
16
4
25
MHz
MHz
V/μs
17
Settling Time
to 0.1%
to 0.01%
G = −1, VO = 10 V Step
G = −1, VO = 10 V Step
550
650
ns
ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise
Input Current Noise
Harmonic Distortion
Crosstalk
f = 10 kHz
f = 1 kHz
RL = 600 Ω, VO = 10 V p-p, f = 20 kHz
16
1
−90
nV/√Hz
fA/√Hz
dBc
f = 1 kHz
f = 1 MHz
RL= 5 kΩ
RL= 5 kΩ
−105
−63
dB
dB
DC PERFORMANCE
Initial Offset
Maximum Offset Over temperature
Offset Drift
0.7
1.0
2
3.5
7
mV
mV
μV/°C
pA
Input Bias Current
VCM = 0 V
5
30
VCM = −10 V
VCM = 0 V
60
0.5
2
0.5
60
pA
nA
pA
nA
V/mV
V/mV
at TMAX
Input Offset Current
at TMAX
Open-Loop Gain
TMIN to TMAX
5
20
VO = +10 V to −10 V, RL = 2 kΩ
30
30
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = 100 μA
−15.2 to +13
66
−15.2 to +13.8
V
Ω
pF
dB
1013
1.8
82
VCM = −15 V to +13 V
−14.95 to +14.95
V
IL = 2 mA
−14.92 to +14.92
V
IL = 10 mA
−14.75 to +14.75
V
Output Current
Short-Circuit Current
VOUT = −14.5 V to +14.5 V
Sourcing to 0 V
Sinking to 0 V
G = +1
17
80
60
500
mA
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
36
V
Quiescent Current
Power Supply Rejection Ratio
TMIN to TMAX, total
VS = 5 V to 15 V, TMIN to TMAX
7.0
80
8.4
mA
dB
70
Rev. B | Page 5 of 20
AD823
ABSOLUTE MAXIMUM RATINGS
Table 4
Parameter
Supply Voltage
Internal Power Dissipation
PDIP (N)
2.0
1.5
1.0
0.5
0
Rating
T
= 150°C
J
8-LEAD PDIP
36 V
1.3 W
0.9 W
VS
1.2 V
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
SOIC (R)
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range N, R
Operating Temperature Range
8-LEAD SOIC
Lead Temperature Range
(Soldering, 10 sec)
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Specification is for device in free air.
Table 5. Thermal Resistance
Package Type
8-Lead PDIP
8-Lead SOIC
θJA
90
160
Unit
°C/W
°C/W
ESD CAUTION
Rev. B | Page 6 of 20
AD823
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
+V = +5V
317 UNITS
σ = 0.4pA
+V = +5V
S
S
314 UNITS
70
σ = 40µV
80
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
–200 –150 –100
–50
0
50
100
150
200
0
1
2
3
4
5
6
7
8
9
10
INPUT OFFSET VOLTAGE (µV)
INPUT BIAS CURRENT (pA)
Figure 5. Typical Distribution of Input Offset Voltage
Figure 8. Typical Distribution of Input Bias Current
10000
22
20
18
16
14
12
+V = +5V
+V = +5V
–55°C TO +125°C
103 UNITS
S
S
V
= 0V
CM
1000
100
10
8
10
1
6
4
2
0
0.1
0
25
50
75
100
125
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 6. Typical Distribution of Input Offset Voltage Drift
Figure 9. Input Bias Current vs. Temperature
3
1000
100
10
+V = +5V
S
V
= ±15V
S
2
1
0
–1
–2
–3
–4
1
0.1
–5
–4
–3
–2
–1
0
1
2
3
4
5
–16
–12
–8
–4
0
4
8
12
16
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
Figure 7. Input Bias Current vs. Common-Mode Voltage
Figure 10. Input Bias Current vs. Common-Mode Voltage
Rev. B | Page 7 of 20
AD823
110
100
90
95
94
R
= 2kΩ
V
= ±2.5V
L
S
+V = +5V
S
93
92
91
90
89
88
80
70
87
86
60
100
–55
–25
5
35
65
95
125
1k
100k
500k
10k
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
Figure 11. Open-Loop Gain vs. Load Resistance
Figure 14. Open-Loop Gain vs. Temperature
1000
100
10
100
80
60
40
20
0
100
R
C
= 2kΩ
= 20pF
L
L
R
= 10kΩ
L
80
60
40
20
0
PHASE
R
= 1kΩ
L
GAIN
R
= 100Ω
L
1
0.1
–20
100M
–20
100
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0 1.5 2.0
2.5
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase Margin vs. Frequency
Figure 12. Open-Loop Gain vs. Output Voltage, VS = 2.5 V
–40
100
+V = +5V
S
–50
–60
+V = +3V
S
30
10
3
V
R
= 2V p-p
OUT
= 100Ω
ALL
–70
L
OTHERS
V
V
R
= ±2.5V
–80
S
= 2V p-p
OUT
= 1kΩ
+V = +3V
= 2V p-p
= 5kΩ
S
V
= ±15V
= 10V p-p
S
L
V
R
OUT
V
R
–90
OUT
= 600Ω
L
L
+V = +5V
S
–100
–110
V
R
= 2V p-p
OUT
= 5kΩ
L
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Total Harmonic Distortion vs. Frequency
Figure 16. Input Voltage Noise vs. Frequency
Rev. B | Page 8 of 20
AD823
5
4
3
2
90
80
70
60
50
40
30
20
V
= ±15V
C
= 20pF
S
L
L
R
= 2kΩ
G = +1
+V = +5V
S
1
0
–55°C
+27°C
–1
–2
–3
+125°C
–4
–5
0.30 3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00
FREQUENCY (MHz)
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 20. Common-Mode Rejection Ratio vs. Frequency
Figure 17. Closed-Loop Gain vs. Frequency
10
100
+V = +5V
S
+V = +5V
S
GAIN = +1
10
1
1
V
25°C
– V
OH
S
0.1
V
OL
25°C
0.1
0.01
0.01
0.1
1
10
100
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
LOAD CURRENT (mA)
Figure 21. Output Saturation Voltage vs. Load Current
Figure 18. Output Resistance vs. Frequency, +VS = +5 V, Gain = +1
10
10
8
V
C
= ±15V
= 20pF
S
8
6
L
1%
0.1%
0.01%
+125°C
+25°C
4
6
2
–55°C
0
–2
–4
–6
–8
–10
4
0.1%
400
1%
0.01%
2
0
0
5
10
15
20
100
200
300
500
600
700
SUPPLY VOLTAGE (±V)
SETTLING TIME (ns)
Figure 22. Quiescent Current vs. Supply Voltage
Figure 19. Output Step Size vs. Settling Time (Inverter)
Rev. B | Page 9 of 20
AD823
21
18
15
100
90
80
70
60
50
40
30
20
10
0
+V = +5V
S
+V = +5V
S
R
V
S
IN
C
L
+PSRR
12
9
–PSRR
Ф
= 45°
M
6
Ф
= 20°
M
3
0
0
1
2
3
4
5
6
7
8
9
10
100
1k
10k
FREQUENCY (Hz)
1M
10M
100k
CAPACITOR (pF × 1000)
Figure 26. Series Resistance vs. Capacitive Load
Figure 23. Power Supply Rejection vs. Frequency
–30
–40
30
20
10
0
+V = +5V
R
= 2kΩ
S
L
G = +1
–50
–60
–70
V
= ±15V
S
–80
–90
–100
–110
+V = +5V
S
–120
–130
+V = +3V
S
10k
100k
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 24. Large Signal Frequency Response
Figure 27. Crosstalk vs. Frequency
V
= 20V p-p
= ±15V
V
= 2.9V p-p
IN
IN
V
+V = +3V
G = –1
S
S
G = +1
5V
20µs
500mV
10µs
100kΩ
+15V
–15V
3V
100kΩ
50Ω
V
= 2.9V p-p
IN
20kHz, 20V p-p
V
OUT
50pF
604Ω
50pF
100kΩ
Figure 25. Output Swing, +VS = +3 V, G = −1
Figure 28. Output Swing, VS = 15 V, G = +1
Rev. B | Page 10 of 20
AD823
5V
R
C
= 100kΩ
= 50pF
R
C
R
= 300Ω
= 50pF
L
L
L
L
F
= R = 2kΩ
+V = +3V
G = +1
G
S
+V = +5V
G = –1
S
3V
GND
500mV
200µs
500mV
200µs
GND
Figure 29. Output Swing, +VS = +5 V, G = −1
Figure 32. Output Swing, +VS = +3 V, G = +1
5V
V
= 100mV STEP
R
C
= 2kΩ
= 50pF
IN
L
L
+V = +3V
S
G = +1
+V = +5V
S
G = +1
1.55V
1.45V
25mV
50ns
500mV
100ns
GND
Figure 30. Pulse Response, +VS = +3 V, G = +1
Figure 33. Pulse Response, +VS = +5 V, G = +1
5V
R
C
= 2kΩ
= 50pF
L
R
= 2kΩ
L
L
C
= 470pF
L
+V = +5V
G = +2
S
+V = +5V
G = +1
S
500mV
100ns
500mV
200ns
GND
Figure 31. Pulse Response, +VS = +5 V, G = +2
Figure 34. Pulse Response, +VS = +5 V, G = +1, CL = 470 pF
Rev. B | Page 11 of 20
AD823
R
C
V
= 100kΩ
= 50pF
= ±15V
L
L
S
G = +1
+10V
–10V
5V
500ns
Figure 35. Pulse Response, VS = 15 V, G = +1
Rev. B | Page 12 of 20
AD823
THEORY OF OPERATION
The AD823 is fabricated on the Analog Devices, Inc. proprietary
complementary bipolar (CB) process that enables the construction
of PNP and NPN transistors with similar fT’s in the 600 MHz to
800 MHz region. In addition, the process also features N-Channel
JFETs that are used in the input stage of the AD823. These
process features allow the construction of high frequency, low
distortion op amps with picoamp input currents. This design
uses a differential output input stage to maximize bandwidth
and headroom (see Figure 36). The smaller signal swings
required on the S1P/S1N outputs reduce the effect of the
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic
distortion of better than −91 dB @ 20 kHz into 600 ꢁ with
A nested integrator topology is used in the AD823 (see Figure 37).
The output stage can be modeled as an ideal op amp with a
single-pole response and a unity-gain frequency set by
transconductance gm2 and Capacitor C2. R1 is the output
impedance of the input stage; gm is the input transconductance.
C1 and Cꢀ provide Miller compensation for the overall op amp.
The unity-gain frequency occurs at gm/Cꢀ. Solving the node
equations for this circuit yields
VOUT
Vi
A0
+1
=
g
C2
⎛
⎞
⎡
⎤
m2
(
sR1
[
C1
(
A2 +1
)]
)
× s
+1
⎜
⎟
⎟
⎜
⎝
⎢
⎣
⎥
⎦
⎠
where:
VOUT = 4 V p-p on a single ꢀ V supply is achieved. The
A0 = gmgm2 R2R1 (open-loop gain of op amp)
A2 = gm2 R2 (open-loop gain of output stage).
complementary common emitter design of the output stage
provides excellent load drive without the need for emitter
followers, thereby improving the output range of the device
considerably with respect to conventional op amps. The
AD823 can drive 20 mA with the outputs within 0.6 V of the
supply rails. The AD823 also offers outstanding precision for a
high speed op amp. Input offset voltages of 1 mV maximum
and offset drift of 2 μV/°C are achieved through the use of the
Analog Devices advanced thin film trimming techniques.
The first pole in the denominator is the dominant pole of the
amplifier and occurs at ~18 Hz. This equals the input stage
output impedance R1 multiplied by the Miller-multiplied value
of C1. The second pole occurs at the unity-gain bandwidth of
the output stage, which is 23 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard 2-stage architecture would allow.
V
CC
Q44
A = 1
Q43
Q58
Q55
Q49
I6
R42
R37
V
+ 0.3V V1
Q61
I5
BE
Q57
A = 19
Q72
Q18
C2
Q46
J1
J6
V
INP
R44
R28
V
Q54
OUT
Q21
V
INN
S1P
S1N
Q62
Q60
V
C1
CC
Q48
V
B
Q53
Q35
Q17
A = 19
C6
I2
R33
R43
I1
Q59
A = 1
I4
I3
Q56
Q52
V
EE
Figure 36. Simplified Schematic
Rev. B | Page 13 of 20
AD823
OUTPUT IMPEDANCE
C1
S1N
S1P
The low frequency open-loop output impedance of the common-
emitter output stage used in this design is approximately 30 kΩ.
Although this is significantly higher than a typical emitter
follower output stage, when it is connected with feedback, the
output impedance is reduced by the open-loop gain of the op
amp. With 109 dB of open-loop gain, the output impedance is
reduced to <0.2 Ω. At higher frequencies, the output impedance
rises as the open-loop gain of the op amp drops; however, the
output also becomes capacitive due to the integrator capacitors
C1 and C2. This prevents the output impedance from ever
g
g
VI
VI
R1
R1
m
V
OUT
C2
R2
C5
m
g
m2
Figure 37. Small Signal Schematic
becoming excessively high (see Figure 18), which can cause
stability problems when driving capacitive loads. In fact, the AD823
has excellent cap-load drive capability for a high frequency op
amp. Figure 34 shows the AD823 connected as a follower while
driving 470 pF direct capacitive load. Under these conditions,
the phase margin is approximately 20°. If greater phase margin
is desired, a small resistor can be used in series with the output
to decouple the effect of the load capacitance from the op amp
(see Figure 26). In addition, running the part at higher gains
also improves the capacitive load drive capability of the op amp.
Rev. B | Page 14 of 20
AD823
APPLICATION NOTES
Because the input stage uses N-Channel JFETs, input current
INPUT CHARACTERISTICS
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 7.
In the AD823, N-Channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input common-
mode voltage extends from 0.2 V below −VS to 1 V < +VS. Driving
the input voltage closer to the positive rail causes a loss of amplifier
bandwidth and increased common-mode voltage error.
A current limiting resistor should be used in series with the
input of the AD823 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage is applied to the AD823 when VS = 0. The
amplifier becomes damaged if left in that condition for more
than 10 seconds. A 1 kΩ resistor allows the amplifier to
withstand up to 10 V of continuous overvoltage and increases
the input voltage noise by a negligible amount.
The AD823 does not exhibit phase reversal for input voltages up
to and including +VS. Figure 38 shows the response of an
AD823 voltage follower to a 0 V to ꢀ V (+VS) square wave input.
The input and output are superimposed. The output polarity
tracks the input polarity up to +VS, with no phase reversal. The
reduced bandwidth above a 4 V input causes the rounding of
the output wave form. For input voltages greater than +VS, a
resistor in series with the AD823’s noninverting input prevents
phase reversal, at the expense of greater input voltage noise.
This is illustrated in Figure 39.
Input voltages less than −VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
−VS as long as the total voltage from the positive supply to the
input terminal is less than 36 V. In addition, the input stage
typically maintains picoamp level input currents across that
input voltage range.
1V
2µs
100
90
The AD823 is designed for 16 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(see Figure 16). This noise performance, along with the AD823’s
low input current and current noise, means that the AD823
contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz.
10
GND 0%
1V
OUTPUT CHARACTERISTICS
Figure 38. AD823 Input Response: RP = 0, VIN = 0 to +VS
The AD823’s unique bipolar rail-to-rail output stage swings
within 2ꢀ mV of the supplies with no external resistive load.
The AD823’s approximate output saturation resistance is 2ꢀ Ω
sourcing and sinking. This can be used to estimate the output
saturation voltage when driving heavier current loads. For
instance, when driving ꢀ mA, the saturation voltage to the rails
is approximately 12ꢀ mV.
1V
10µs
100
90
+V
S
If the AD823’s output is driven hard against the output
saturation voltage, it recovers within 2ꢀ0 ns of the input
returning to the amplifier’s linear operating region.
GND
10
A/D Driver
0%
The rail-to-rail output of the AD823 makes it useful as an A/D
driver in a single-supply system. Because it is a dual op amp, it
can be used to drive both the analog input of the A/D as well as
its reference input. The high impedance FET input of the
AD823 is well suited for minimal loading of high output
impedance devices.
1V
5V
R
P
V
IN
AD823
V
OUT
Figure 39. AD823 Input Response:
IN = 0 to +VS + 200 mV, VOUT = 0 to +VS, RP = 49.9 kΩ
V
Rev. B | Page 15 of 20
AD823
Figure 40 shows a schematic of an AD823 being used to drive
both the input and reference input of an AD1672, a 12-bit,
3-MSPS, single-supply ADC. One amplifier is configured as a
unity-gain follower to drive the analog input of the AD1672,
which is configured to accept an input voltage that ranges from
0 V to 2.ꢀ V.
The distortion analysis is important for systems requiring good
frequency domain performance. Other systems may require
good time domain performance. The noise and settling time
performance of the AD823 provides the necessary information
for its applicability for these systems.
1
V
= 2.15V p-p
IN
The other amplifier is configured as a gain of 2 to drive the
reference input from a 1.2ꢀ V reference. Although the AD1672
has its own internal reference, there are systems that require
greater accuracy than the internal reference provides. On the other
hand, if the AD1672 internal reference is used, the second AD823
amplifier can be used to buffer the reference voltage for driving
other circuitry while minimally loading the reference source.
+5VA +5VD
G = +1
FI = 490kHz
2
4
9
7
6
5
8
3
0.1µF
10µF
0.1µF
10µF
+5VA
8
28 19
0.1µF
+5VD
10µF
Figure 41. FFT of AD1672 Output Driven by AD823
2
3
20
21
22
0.1µF
OTR
REFOUT
AIN1
AIN2
1
15
3 V, Single-Supply Stereo Headphone Driver
49.9Ω
V
IN
13
14
12
11
10
9
BIT1 (MSB)
The AD823 exhibits good current drive and total harmonic
distortion plus noise (THD+N) performance, even at 3 V
single supplies. At 20 kHz, THD+N equals −62 dB (0.079%) for
a 300 mV p-p output signal. This is comparable to other single-
supply op amps that consume more power and cannot run on
3 V power supplies.
AD823
AD1672
BIT2
BIT3
BIT4
BIT5
BIT6
5
V
7
REF
(1.25V)
23
24
25
26
REFIN
8
6
REFCOM
NCOMP2
NCOMP1
4
7
6
5
4
3
2
1
BIT7
BIT8
BIT9
BIT10
BIT11
1kΩ
1kΩ
In Figure 42, each channel’s input signal is coupled via a 1 μF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway
between the power supplies (+1.ꢀ V). The gain is 1.ꢀ. Each half
of the AD823 can then be used to drive a headphone channel. A
ꢀ Hz high-pass filter is realized by the ꢀ00 μF capacitors and the
headphones that can be modeled as 32 Ω load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz to 20 kHz) are delivered to the headphones.
3V
27
16
ACOM
REF
BIT12 (LSB)
CLOCK
19
18
Figure 40. AD823 Driving Input and Reference of the
AD1672, a 12-Bit, 3-MSPS ADC
The circuit was tested with a ꢀ00 kHz sine wave input that was
heavily low-pass filtered (60 dB) to minimize the harmonic content
at the input to the AD823. The digital output of the AD1672 was
analyzed by performing a fast Fourier transform (FFT).
+
0.1µF
0.1µF
95.3kΩ
95.3kΩ
47.5kΩ
8
3
CHANNEL 1
During the testing, it was observed that at ꢀ00 kHz, the output
of the AD823 cannot go below ~3ꢀ0 mV (operating with
negative supply at ground) without seriously degrading the
second harmonic distortion. Another test was performed with a
200 Ω pull-down resistor to ground that allowed the output to
go as low as 200 mV without seriously affecting the second
harmonic distortion. There was, however, a slight increase in
the third harmonic term with the resistor added, but it was still
less than the second harmonic.
+
1/2
1µF
MYLAR
1
2 AD823
500µF
L
4.99kΩ
95.3kΩ
10kΩ
10kΩ
HEADPHONES
32Ω IMPEDANCE
R
4.99kΩ
6
500µF
+
1/2
47.5kΩ
7
1µF
AD823
5
Figure 41 is an FFT plot of the results of driving the AD1672
with the AD823 with no pull-down resistor. The input
amplitude was 2.1ꢀ V p-p and the lower voltage excursion was
3ꢀ0 mV. The input frequency was 490 kHz, which was chosen
to spread the location of the harmonics.
4
CHANNEL 2
MYLAR
Figure 42. 3 V Single-Supply Stereo Headphone Driver
Rev. B | Page 16 of 20
AD823
Second-Order Low-Pass Filter
Single-Supply Half-Wave and Full-Wave Rectifiers
Figure 43 depicts the AD823 configured as a second-order
Butterworth low-pass filter. With the values as shown, the
corner frequency equals 200 kHz. Component selection is
shown in the following equations:
An AD823 configured as a unity-gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD823 inputs maintain picoamp level input currents even
when driven well below the minus supply. The rectifier puts
that behavior to good use, maintaining an input impedance of
over 1011 Ω for input voltages from within 1 V of the positive
supply to 20 V below the negative supply.
R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ)
1.414
2πfcutoff × R1
C1
(
farads =
)
The full-wave and half-wave rectifier shown in Figure 4ꢀ
operates as follows: when VIN is above ground, R1 is boot-
strapped through the unity-gain follower A1 and the loop of
Amplifier A2. This forces the inputs of A2 to be equal, thus no
current flows through R1 or R2, and the circuit output tracks
the input. When VIN is below ground, the output of A1 is forced
to ground. The noninverting input of Amplifier A2 sees the
ground level output of A1; therefore, A2 operates as a unity-
gain inverter. The output at Node C is then a full-wave rectified
version of the input. Node B is a buffered half-wave rectified
version of the input. Input voltage supply to 18 V can be
rectified, depending on the voltage supply used.
0.707
2πfcutoff × R1
C2 =
+5V
1/2
C2
56pF
C3
0.1µF
R1
R2
20kΩ
20kΩ
V
IN
C1
28pF
V
AD823
OUT
50pF
R1
100kΩ
R2
100kΩ
C4
0.1µF
–5V
+V
8
S
0.01µF
Figure 43. Second-Order Low-Pass Filter
6
5
A
7
3
2
C
A plot of the filter is shown in Figure 44; better than ꢀ0 dB of
high frequency rejection is provided.
A2
1
V
FULL-WAVE
RECTIFIED OUTPUT
A1
1/2
AD823
IN
1/2
0
4 AD823
B
–10
HALF-WAVE
RECTIFIED OUTPUT
V
– V
OUT
DB
–20
–30
–40
Figure 45. Full-Wave and Half-Wave Rectifier
2V
200µs
–50
–60
100
90
A
1k
10k
100k
FREQUENCY (Hz)
10M
100M
1M
Figure 44. Frequency Response of Filter
B
C
10
0%
2V
Figure 46. Single-Supply Half-Wave and Full-Wave Rectifier
Rev. B | Page 17 of 20
AD823
OUTLINE DIMENSIONS
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015
(0.38)
0.180
(4.57)
MAX
MIN
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 18 of 20
AD823
ORDERING GUIDE
Models
AD823AN
AD823ANZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
Package Option
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
AD823AR
8-Lead SOIC_N
AD823AR-REEL
AD823AR-REEL7
AD823ARZ1
AD823ARZ-RL1
AD823ARZ-R71
8-Lead SOIC_N, 13”Reel
8-Lead SOIC_N, 7”Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13”Reel
8-Lead SOIC_N, 7”Reel
1 Z = RoHS Compliant Part.
Rev. B | Page 19 of 20
AD823
NOTES
©1995–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00901-0-2/07(B)
Rev. B | Page 20 of 20
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