AD824 [ADI]
Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp; 单电源，轨到轨，低功耗， FET输入运算放大器
| 型号： | AD824 |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp |
| 文件： | 总16页 (文件大小：553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail-to-Rail
a
Low Power, FET-Input Op Amp
AD824
FEATURES
PIN CONFIGURATIONS
Single Supply Operation: 3 V to 30 V
Very Low Input Bias Current: 2 pA
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 500 A/Amp
Wide Bandwidth: 2 MHz
Slew Rate: 2 V/s
14-Lead Epoxy DIP
(N Suffix)
14-Lead Epoxy SO
(R Suffix)
OUT A
1
2
3
4
5
6
7
14 OUT D
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
–IN A
+IN A
V+
13 –IN D
12 +IN D
11 V–
No Phase Reversal
AD824
TOP VIEW
AD824
APPLICATIONS
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
+INB
–INB
OUTB
+IN C
–IN C
OUT C
Photo Diode Preamplifier
Battery Powered Instrumentation
Power Supply Control and Protection
Medical Instrumentation
Remote Sensors
9
8
–IN C
OUT C
8
TOP VIEW
Low Voltage Strain Gage Amplifiers
DAC Output Amplifier
16-Lead Epoxy SO
(R Suffix)
GENERAL DESCRIPTION
OUT D
OUT A
–IN A
16
15 –IN D
14
1
2
3
4
5
6
7
8
The AD824 is a quad, FET input, single supply amplifier, fea-
turing rail-to-rail outputs. The combination of FET inputs and
rail-to-rail outputs makes the AD824 useful in a wide variety of
low voltage applications where low input current is a primary
consideration.
+IN A
V+
+IN D
13 V–
AD824
+IN B
–IN B
OUT B
12 +IN C
11 –IN C
The AD824 is guaranteed to operate from a 3 V single supply
up to ±15 volt dual supplies.
OUT C
NC
10
9
NC
Fabricated on ADI’s complementary bipolar process, the AD824
has a unique input stage that allows the input voltage to safely
extend beyond the negative supply and to the positive supply
without any phase inversion or latchup. The output voltage
swings to within 15 millivolts of the supplies. Capacitive loads
to 350 pF can be handled without oscillation.
NC = NO CONNECT
Applications for the AD824 include portable medical equipment,
photo diode preamplifiers and high impedance transducer
amplifiers.
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets be-
low 300 µV. This enables high accuracy designs even with high
source impedances. Precision is combined with low noise,
making the AD824 ideal for use in battery powered medical
equipment.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
The AD824 is specified over the extended industrial (–40°C to
+85°C) temperature range and is available in 14-pin DIP and
narrow 14-pin and 16-pin SO packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
AD824–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
(@ VS = +5.0 V, VCM = 0 V, VOUT = 0.2 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
VOS
IB
0.1
1.0
1.5
300
900
12
mV
mV
µV
T
T
T
T
MIN to TMAX
MIN to TMAX
MIN to TMAX
MIN to TMAX
Offset Voltage AD824B
Input Bias Current
µV
2
300
2
pA
pA
pA
pA
V
dB
dB
dB
ΩʈpF
4000
10
Input Offset Current
IOS
300
Input Voltage Range
Common-Mode Rejection Ratio
–0.2
66
60
3.0
CMRR
AVO
V
V
CM = 0 V to 2 V
CM = 0 V to 3 V
80
74
TMIN to TMAX
60
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
VO = 0.2 V to 4.0 V
RL = 2 kΩ
RL = 10 kΩ
20
50
250
180
40
V/mV
V/mV
V/mV
V/mV
µV/°C
100
1000
400
2
RL = 100 kΩ
TMIN to TMAX, RL = 100 kΩ
Offset Voltage Drift
∆VOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 µA
TMIN to TMAX
ISOURCE = 2.5 mA
4.975
4.97
4.80
4.75
4.988
4.985
4.85
4.82
15
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
T
MIN to TMAX
Output Voltage Low
VOL
ISINK = 20 µA
TMIN to TMAX
25
30
150
200
20
I
SINK = 2.5 mA
120
140
±12
±10
100
TMIN to TMAX
Sink/Source
Short Circuit Limit
ISC
T
MIN to TMAX
Open-Loop Impedance
ZOUT
f = 1 MHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 12 V
TMIN to TMAX
TMIN to TMAX
70
66
80
dB
dB
µA
Supply Current/Amplifier
500
600
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
φo
CS
RL = 10 kΩ, AV = 1
1% Distortion, VO = 4 V p-p
VOUT = 0.2 V to 4.5 V, to 0.01%
2
V/µs
kHz
µs
MHz
Degrees
dB
150
2.5
2
50
–123
No Load
f = 1 kHz, RL = 2 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
2
16
0.8
0.005
µV p-p
nV/√Hz
fA/√Hz
%
THD
f = 10 kHz, RL = 0, AV = +1
REV. A
–2–
AD824
ELECTRICAL SPECIFICATIONS (@ VS = ؎15.0 V, VOUT = 0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
VOS
IB
0.5
0.6
0.5
0.6
4
500
25
3
2.5
4.0
1.5
2.5
35
mV
mV
mV
mV
pA
pA
pA
pA
pA
V
T
MIN to TMAX
MIN to TMAX
Offset Voltage AD824B
Input Bias Current
T
VCM = 0 V
MIN to TMAX
VCM = –10 V
T
4000
Input Bias Current
Input Offset Current
IB
IOS
20
13
TMIN to TMAX
500
Input Voltage Range
Common-Mode Rejection Ratio
–15
70
66
CMRR
AVO
V
T
CM = –15 V to 13 V
MIN to TMAX
80
dB
dB
ΩʈpF
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
Vo = –10 V to +10 V;
RL = 2 kΩ
RL = 10 kΩ
12
50
300
200
50
V/mV
V/mV
V/mV
V/mV
µV/°C
200
2000
1000
2
RL = 100 kΩ
TMIN to TMAX, RL = 100 kΩ
Offset Voltage Drift
∆VOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 µA
MIN to TMAX
SOURCE = 2.5 mA
MIN to TMAX
ISINK = 20 µA
MIN to TMAX
SINK = 2.5 mA
MIN to TMAX
14.975
14.970
14.80
14.988
14.985
14.85
14.82
–14.985 –14.975
–14.98
–14.88
–14.86
±20
V
V
V
V
V
V
V
V
T
I
T
14.75
Output Voltage Low
VOL
T
I
T
–14.97
–14.85
–14.8
Short Circuit Limit
Open-Loop Impedance
ISC
ZOUT
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
±8
mA
Ω
100
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 15 V
70
68
80
dB
dB
µA
µA
TMIN to TMAX
Supply Current/Amplifier
VO = 0 V
TMIN to TMAX
560
625
675
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
SR
BWP
tS
RL = 10 kΩ, AV = 1
1% Distortion, VO = 20 V p-p
VOUT = 0 V to 10 V, to 0.01%
2
33
6
V/µs
kHz
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
GBP
φo
CS
2
50
–123
MHz
Degrees
dB
f = 1 kHz, RL =2 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f =10 kHz, VO = 3 V rms,
RL = 10 kΩ
2
16
1.1
µV p-p
nV/√Hz
fA/√Hz
THD
0.005
%
–3–
REV. A
AD824–SPECIFICATIONS
(@ VS = +3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = +25؇C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A -3 V
VOS
IB
0.2
1.0
1.5
12
4000
10
mV
mV
pA
pA
pA
pA
V
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Input Bias Current
Input Offset Current
2
250
2
IOS
250
Input Voltage Range
0
1
Common-Mode Rejection Ratio
CMRR
AVO
V
T
CM = 0 V to 1 V
MIN to TMAX
58
56
74
dB
dB
ΩʈpF
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
VO = 0.2 V to 2.0 V
RL = 2 kΩ
RL = 10 kΩ
RL = 100 kΩ
T
10
30
180
90
20
65
500
250
2
V/mV
V/mV
V/mV
V/mV
µV/°C
MIN to TMAX, RL = 100 kΩ
Offset Voltage Drift
∆VOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 µA
MIN to TMAX
SOURCE = 2.5 mA
MIN to TMAX
ISINK = 20 µA
MIN to TMAX
SINK = 2.5 mA
MIN to TMAX
2.975
2.97
2.8
2.988
2.985
2.85
2.82
15
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
T
I
T
2.75
Output Voltage Low
VOL
25
30
150
200
T
I
T
20
120
140
±8
±6
100
Short Circuit Limit
Short Circuit Limit
Open-Loop Impedance
ISC
ISC
ZOUT
Sink/Source
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 12 V,
70
66
dB
dB
µA
TMIN to TMAX
Supply Current/Amplifier
VO = 0.2 V, TMIN to TMAX
500
600
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
SR
BWP
tS
RL =10 kΩ, AV = 1
1% Distortion, VO = 2 V p-p
VOUT = 0.2 V to 2.5 V, to 0.01%
2
300
2
V/µs
kHz
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
GBP
φo
CS
2
50
–123
MHz
Degrees
dB
f = 1 kHz, RL = 2 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
2
16
0.8
0.01
µV p-p
nV/√Hz
fA/√Hz
%
THD
f = 10 kHz, RL = 0, AV = +1
–4–
REV. A
AD824
(@ V = +5.0 V, VCM = 0 V, TA = +25؇C unless otherwise noted)
WAFER TEST LIMITS
S
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Input Bias Current
Input Offset Current
VOS
IB
IOS
1.0
12
20
mV max
pA max
pA
Input Voltage Range
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
–0.2 to 3.0
66
70
15
4.975
25
600
V min
dB min
µV/V
V/mV min
V min
mV max
µA max
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
V
CM = 0 V to 2 V
V = + 2.7 V to +12 V
RL = 2 kΩ
ISOURCE = 20 µA
ISINK = 20 µA
Supply Current/Amplifier
VO = 0 V, RL = ∞
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly
methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice
lot qualifications through sample lot assembly and testing.
DICE CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils.
Substrate (Die Backside) Is Connected to V+. Transistor
Count, 143.
2
Package Type
θJA
θJC
Units
14-Pin Plastic DIP (N)
14-Pin SOIC (R)
16-Pin SOIC (R)
76
120
92
33
36
27
°C/W
°C/W
°C/W
V
CC
I5
I6
Q18
Q29
R1
R2
R9
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
Q21 Q27
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC
package.
Q4
Q6
C3
Q5
J1
J2
Q20
Q19
Q22
+IN
Q7
R7
ORDERING GUIDE
Temperature
C4
R13
–IN
Q23
V
OUT
C2
R15
Model
Range
Package Option
Q24 Q25
AD824AN
AD824BN
AD824AR
AD824AR-3V
AD824AN-3V
AD824AR-14
AD824AR-14-3V
AD824AR-16
AD824AChips
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
+25°C
14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
14-Pin Plastic DIP
14-Pin SOIC
14-Pin SOIC
16-Pin SOIC
DICE
Q8
C1
Q2
Q3
Q31
Q28
R14
I2
R12
I1
Q26
R17
I4
I3
V
EE
Figure 1. Simplified Schematic of 1/4 AD824
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD824 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
AD824–Typical Characteristics
V
= +5V
S
V
= ±15V
80
60
40
20
0
80
60
40
20
0
S
NO LOAD
NO LOAD
45
45
90
90
135
180
135
180
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
Figure 4. Open-Loop Gain/Phase and Small Signal
Response, VS = +5 V, No Load
Figure 2. Open-Loop Gain/Phase and Small Signal
Response, VS = ±15 V, No Load
V
= +5V
60
40
20
S
V
= ±15V
80
60
40
20
0
S
C
= 220pF
L
C
= 100pF
L
45
90
135
180
45
0
90
135
180
–20
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
Figure 5. Open-Loop Gain/Phase and Small Signal
Response, VS = +5 V, CL = 220 pF
Figure 3. Open-Loop Gain/Phase and Small Signal
Response, VS = ±15 V, CL = 100 pF
–6–
REV. A
AD824
t
60
40
20
9.950µs
V
= +3V
S
NO LOAD
100
90
45
90
10
135
180
0%
0
5V
2µs
–20
t
10.810 µs
1k
10k
100k
1M
10M
100
90
100
90
10
0%
5V
2µs
10
Figure 8. Slew Rate, RL = 10k
0%
50mV
1µs
Figure 6. Open-Loop Gain/Phase and Small Signal
Response, VS = +3 V, No Load
100
90
V
OUT
V
= +3V
S
10
60
40
20
0%
C
= 220pF
L
100µs
5V
45
90
Figure 9. Phase Reversal with Inputs Exceeding Supply by
1 Volt
135
180
0
0.8
0.7
0.6
–20
1k
10k
100k
1M
10M
0.5
SOURCE
0.4
0.3
0.2
100
90
SINK
0.1
0
10
1µ
5µ
10µ
50µ 100µ
500µ
1m
5m
10m
0%
LOAD CURRENT – A
50mV
1µs
Figure 10. Output Voltage to Supply Rail vs. Sink and
Source Load Currents
Figure 7. Open-Loop Gain/Phase and Small Signal
Response, VS = +3 V, CL = 220 pF
–7–
REV. A
AD824–Typical Characteristics
14
12
10
8
COUNT = 60
+3V ≤ V ≤ ±15V
S
60
40
20
6
4
2
5
10
15
20
FREQUENCY – kHz
0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0 1.5
2.0
2.5
OFFSET VOLTAGE DRIFT
Figure 14. TC VOS Distribution, –55°C to +125°C, VS = 5, 0
Figure 11. Voltage Noise Density
150
V
= 5, 0
0.1
S
125
100
75
R
A
= 0
= +1
L
V
V
V
= +3
= +5
S
S
0.010
0.001
50
25
V
= ±15
S
0
0.0001
20
100
1k
FREQUENCY – Hz
10k 20k
–25
–60 –40 –20
0
20
40
60
80 100 120
140
TEMPERATURE – °C
Figure 12. Total Harmonic Distortion
Figure 15. Input Offset Current vs. Temperature
100k
280
240
200
160
120
80
V
= 5, 0
COUNT = 860
S
10k
1k
100
10
1
40
0
20
40
60
80
100
120
140
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
TEMPERATURE –
°C
OFFSET VOLTAGE – mV
Figure 16. Input Bias Current vs. Temperature
Figure 13. Input Offset Distribution, VS = 5, 0
REV. A
–8–
AD824
.
.
120
100
80
60
40
20
0
1k
100
10
10
100
1k
10k
100k
1M
10M
1
1
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20. Input Voltage Noise Spectral Density vs.
Frequency
Figure 17. Common-Mode Rejection vs. Frequency
120
100
80
60
40
20
0
–40
–60
–80
–100
–120
10
100
1k
10k
100k
1M
10M
100
1k
10k
FREQUENCY – Hz
100k
FREQUENCY – Hz
Figure 21. Power Supply Rejection vs. Frequency
Figure 18. THD vs. Frequency, 3 V rms
30
25
20
15
10
5
100
80
60
40
20
0
100
80
60
40
20
0
±15V
+3, 0V
0
1k
–20
10
–20
10M
3k
10k
30k
100k
300k
1M
100
1k
10k
100k
1M
INPUT FREQUENCY – Hz
FREQUENCY – Hz
Figure 22. Large Signal Frequency Response
Figure 19. Open-Loop Gain and Phase vs. Frequency
REV. A
–9–
AD824
–80
5V
5µs
–90
–100
–110
–120
–130
–140
100
90
1 TO 4
1 TO 2
10
1 TO 3
0%
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 23. Crosstalk vs. Frequency
Figure 26. Large Signal Response
10k
1k
100
10
1
2750
2500
2250
2000
1750
1500
1250
1000
V
= ±15V
S
V
= 3, 0
S
.1
.01
10
100
1k
10k
100k
1M
10M
–60 –40 –20
0
20
40
60
80 100 120
140
FREQUENCY – Hz
TEMPERATURE – °C
Figure 24. Output Impedance vs. Frequency, Gain = +1
Figure 27. Supply Current vs. Temperature
1000
V
V
= ±15V
S
20mV
500ns
= 3, 0
S
100
90
100
10
0
V
– V
S
OL
V
– V
OH
S
10
0%
0.01
0.10
1.0
10.0
LOAD CURRENT – mA
Figure 25. Small Signal Response, Unity Gain Follower,
10kʈ100 pF Load
Figure 28. Output Saturation Voltage
–10–
REV. A
AD824
APPLICATION NOTES
A current-limiting resistor should be used in series with the in-
put of the AD824 if there is a possibility of the input voltage ex-
ceeding the positive supply by more than 300 mV or if an input
voltage will be applied to the AD824 when ±VS = 0. The ampli-
fier will be damaged if left in that condition for more than 10
seconds. A 1 kΩ resistor allows the amplifier to withstand up to
10 volts of continuous overvoltage and increases the input volt-
age noise by a negligible amount.
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V less
than +VS. Driving the input voltage closer to the positive rail will
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages up
to and including +VS. Figure 29a shows the response of an
AD824 voltage follower to a 0 V to +5 V (+VS) square wave in-
put. The input and output are superimposed. The output tracks
the input up to +VS without phase reversal. The reduced band-
width above a 4 V input causes the rounding of the output wave
form. For input voltages greater than +VS, a resistor in series
with the AD824’s noninverting input will prevent phase reversal
at the expense of greater input voltage noise. This is illustrated
in Figure 29b.
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In ad-
dition, the input stage typically maintains picoamp level input
currents across that input voltage range.
OUTPUT CHARACTERISTICS
The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100 Ω for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 volts from either
supply with a 5 mA current load.
1V
2µs
100
90
For load resistances over 20 kΩ, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
10
GND
0%
If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 µs of its
input returning to the amplifier’s linear operating region.
1V
1V
(a)
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figures 5 and 7 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configu-
rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
10µs
1V
100
90
+V
S
10
GND
0%
1V
Figure 30 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val-
ues, the circuit will drive 5,000 pF with a 10% overshoot.
(b)
+5V
R
P
+V
S
V
IN
0.01µF
V
OUT
8
100Ω
1/4
AD824
V
N
I
V
0.01µF
OUT
4
C
Figure 29. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to + VS + 200 m V
VOUT = 0 to + VS
L
–V
S
20pF
RP = 49.9 kΩ
20kΩ
Since the input stage uses n-channel JFETs, input current dur-
ing normal operation is positive; the current flows out from the
input terminals. If the input voltage is driven more positive than
+VS – 0.4 V, the input current will reverse direction as internal
device junctions become forward biased. This is illustrated in
Figure 9.
Figure 30. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
REV. A
–11–
AD824
APPLICATIONS
Table I. AD824 In Amp Performance
Single Supply Voltage-to-Frequency Converter
The circuit shown in Figure 31 uses the AD824 to drive a low
power timer, which produces a stable pulse of width t1. The
positive going output pulse is integrated by R1-C1 and used as
one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown volt-
age, VIN. The AD824 output drives the timer trigger input, clos-
ing the overall feedback loop.
Parameters
VS = 3 V, 0 V VS = ؎5 V
74 dB 80 dB
CMRR
Common-Mode
Voltage Range
3 dB BW, G = 10
G = 100
–0.2 V to +2 V –5.2 V to +4 V
180 kHz
18 kHz
180 kHz
18 kHz
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = ±5 V)
Noise @ f = 1 kHz, G = 10
2 µs
+10V
5 µs
270 nV/√Hz
2.2 µV/√Hz
U4
C5
REF02
270 nV/√Hz
0.1µF
2
V
= 5V
REF
6
5
G = 100 2.2 µV/√Hz
CMOS
3
R
10k
SCALE**
OUT2
OUT1
74HCO4
C3
0.1µF
U3A
2
4
U3B
5µs
4
3
1
100
90
U2
0.01µF, 2%
CMOS 555
4
8
R2
R3*
U1
C1
499k, 1%
116k
R
V+
6
3
THR
OUT
1/4
AD824B
2
7
TR
5
R1
10
CV
V
0%
DIS
IN
GND
C6
499k, 1%
1V
390pF
0V TO 2.5V
1
5%
C4
0.01µF
FULL SCALE
C2
(NPO)
0.01µF, 2%
Figure 32a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; VS = +5 V, 0 V; Gain = 10
NOTES:
=V /(VREF*t ), t = 1.1*R3*C6
f
OUT
IN
1
1
= 25kHz f AS SHOWN.
S
* = 1% METAL FILM, <50ppm/°C TC
** = 10%, 20T FILM, <100ppm/°C TC
R1
R2
9k
R3
1k
R4
1k
R5
9k
R6
OHMTEK
PART # 1043
V
t
= 33µs FOR f
= 20kHz @
= 2.0V
IN
V
REF
1
OUT
90k
90k
Figure 31. Single Supply Voltage-to-Frequency Converter
G =10
G =100
G =100
G =10
Typical AD824 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 volt single supply, which
delivers less than 3 mA to the entire circuit.
+V
S
0.1µF
6
5
2
3
1/4
AD824
1
7
1/4
AD824
R
P
V
V
V
OUT
IN1
IN2
11
Single Supply Programmable Gain Instrumentation Amplifier
The AD824 can be configured as a single supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to ±15 V. AD824 FET inputs’ 2 pA
bias currents minimize offset errors caused by high unbalanced
source impedances.
1kΩ
R
P
1kΩ
R6
R4 + R5
(G =10)
V
= (V
– V ) (1+
) +V
REF
OUT
IN1
IN2
R5 + R6
R4
(G =100)
V
= (V
– V ) (1+
) +V
REF
OUT
IN1
IN2
FOR R1 = R6, R2 = R5 AND R3 = R4
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of
5 ppm/°C.
Figure 32b. A Single Supply Programmable
Instrumentation Amplifier
–12–
REV. A
AD824
3 Volt, Single Supply Stereo Headphone Driver
The AD824 exhibits good current drive and THD+N perfor-
mance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps that consume more power and cannot run on 3
V power supplies.
of +4.5 V can be used to drive an A/D converter front end. The
other half of the AD824 is configured as a unity-gain inverter
and generates the other bridge input of –4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor RG and determined by:
In Figure 33, each channel’s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway be-
tween the power supplies (+1.5 V). The gain is 1.5. Each half of
the AD824 can then be used to drive a headphone channel. A
5 Hz high-pass filter is realized by the 500 µF capacitors and the
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz–20 kHz) are delivered to the headphones.
49.4 kΩ
RG
G =
+ 1
A 3.3 Volt/5 Volt Precision Sample-and-Hold Amplifier
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit
shown in Figure 35, illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain
high signal-to-noise ratios (SNRs) in a low supply voltage appli-
cation requires the use of rail-to-rail, input/output operational
amplifiers. This design highlights the ability of the AD824 to oper-
ate rail-to-rail from a single +3 V/+5 V supply, with the advantages
of high input impedance. The AD824, a quad JFET-input op
amp, is well suited to S/H circuits due to its low input bias cur-
rents (3 pA, typical) and high input impedances (3 × 1013 Ω,
typical). The AD824 also exhibits very low supply currents so
the total supply current in this circuit is less than 2.5 mA.
+3V
0.1µF
0.1µF
95.3k
47.5k
1µF
CHANNEL 1
1/4
AD824
MYLAR
500µF
95.3k
L
4.99k
10k
HEADPHONES
32Ω IMPEDANCE
10k
3.3/5V
3.3/5V
0.1µF
R
R1 AD824A
4.99k
50k
3
2
4
1/4
AD824
1
47.5k
1µF
A1
FALSE GROUND (FG)
500µF
R2
50k
CHANNEL 2
11
R4
2kΩ
MYLAR
3.3/5V
13
Figure 33. 3 Volt Single Supply Stereo Headphone Driver
ADG513
15
14
Low Dropout Bipolar Bridge Driver
R5
2kΩ
16
9
10
11
The AD824 can be used for driving a 350 ohm Wheatstone
bridge. Figure 34 shows one half of the AD824 being used to
buffer the AD589—a 1.235 V low power reference. The output
AD824B
A2
C
H
FG
5
500pF
2
3
7
6
1
8
+V
S
10
9
8
A3
+
–
49.9k
V
R1
20Ω
OUT
6
5
7
4
+1.235V
AD824C
1/4
AD824
TO A/D CONVERTER
REFERENCE INPUT
C
AD589
AD824D
12
500pF
FG
14
26.4k, 1%
350Ω
10k
1%
+V
S
SAMPLE/
A4
13
FG
350Ω
350Ω
HOLD
3
7
6
AD620
R
G
350Ω
5
2
Figure 35. 3.3 V/5.5 V Precision Sample and Hold
4
10k
1%
V
REF
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the sup-
ply voltage symmetrically, creating the false ground voltage at
one-half the supply. Amplifier A1 then buffers this voltage cre-
ating a low impedance output drive. The S/H circuit is config-
ured in an inverting topology centered around this false ground
level.
–V
S
10k
1%
+V
1/4
AD824
S
+5V
–5V
–4.5V
1µF
1µF
0.1µF
R2
20Ω
GND
0.1µF
–V
–V
S
S
Figure 34. Low Dropout Bipolar Bridge Driver
REV. A
–13–
AD824
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 µV/µs in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be poly-
styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi-
tionally, 1% metal film resistors were used throughout the design.
appear at VOUT. The pedestal error for this circuit is less than 2
mV over the entire 0 V to 3.3 V/5 V signal range. Another
method of reducing pedestal error is to reduce the pulse ampli-
tude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and 0.8 V
for the “OFF” state. If possible, use an input control signal
whose amplitude ranges from 0.8 V to 2.4 V instead of a full
range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3 µs to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
In the sample mode, SW1 and SW4 are closed, and the output
is VOUT = –VIN. The purpose of SW4, which operates in paral-
lel with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This cre-
ates a common-mode voltage across the inputs of A3 and is then
rejected by the CMR of A3; otherwise, the charge injection from
SW1 would create a differential voltage step error that would
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normally-open and normally-closed pre-
cision CMOS switches on a dielectrically isolated process. SW2
is not required in this circuit; however, it was used in parallel
with SW3 to provide a lower RON analog switch.
–14–
REV. A
AD824
* AD824 SPICE Macro-model
9/94, Rev. A *
ARG/ADI
FSY1
FSY2
DC1
DC2
*
99
0
25
50
0
VP 1
VN 1
DX
50
99
25
*
* Copyright 1994 by Analog Devices, Inc.
*
DX
* Refer to “README.DOC” file for License Statement.
Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *
* Node assignments
* MODELS USED
*
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
.MODEL DX D(IS=1E-15)
*
*
*
noninverting input
| inverting input
| | positive supply
*
*
*
| |
| |
| |
|
|
|
negative supply
|
|
output
|
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824
.SUBCKT AD824
*
1 2 99 50 25
* INPUT STAGE & POLE AT 3.1 MHz
*
R3
R4
CIN
C2
I1
IOS
EOS
J1
5
6
1
5
4
1
7
4
4
99
99
2
6
50
2
1
2
7
1.193E3
1.193E3
4E-12
19.229E-12
108E-6
1E-12
POLY(1) (12,98) 100E-6 1
5
6
JX
JX
J2
*
* GAIN STAGE & DOMINANT POLE
*
EREF
R5
C3
G1
V1
98
9
9
98
8
98
9
0
(30,0) 1
2.205E6
54E-12
(6,5) 0.838E-3
-1
-1
DX
98
25
9
98
10
10
9
V2
D1
D2
*
8
DX
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *
R21
R22
C14
E13
*
11
12
11
11
12
98
12
98
1E6
100
159E-12
POLY(2) (2,98) (1,98) 0 0.5 0.5
* POLE AT 10 MHz
*
R23
C15
G15
*
18
18
98
98
98
18
1E6
15.9E-15
(9,98) 1E-6
* OUTPUT STAGE
*
ES
26
26
98
23
21
98
20
24
97
20
24
24
25
25
96
51
96
52
30
30
98
22
21
98
98
23
25
25
20
21
23
51
20
24
97
52
0
(18,98) 1
500
2.404E-3
2.404E-3
DY
RS
IB1
IB2
D10
D11
C16
C17
DQ1
Q2
DY
2E-12
2E-12
DQ
22 NPN
22 PNP
DQ
97 PNP 20
51 NPN 20
0
Q3
DQ2
Q5
Q6
VP
VN
EP
0
(99,0) 1
(50,0) 1
5E6
EN
R25
R26
0
99
50
5E6
REV. A
–15–
AD824
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Pin Plastic (N) Package
(N-14)
14
1
8
0.280 (7.11)
0.240 (6.10)
PIN 1
7
0.325 (8.25)
0.300 (7.62)
0.795 (20.19)
0.725 (18.42)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
14-Pin SOIC (R) Package
(R-14)
14
1
8
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
7
0.3444 (8.75)
0.3367 (8.55)
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.0688 (1.75)
0.0532 (1.35)
8
0
°
°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
16-Pin SOIC Package
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
PIN 1
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0125 (0.32)
0.0091 (0.23)
SEATING
PLANE
0.0138 (0.35)
–16–
REV. A
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