AD824AR-14-3V-REEL [ADI]
Single Supply, Rail-to-Rail Low Power, FET-Input Quad Op Amp;
| 型号： | AD824AR-14-3V-REEL |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail-to-Rail Low Power, FET-Input Quad Op Amp 放大器 光电二极管 |
| 文件： | 总17页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail-to-Rail
Low Power, FET-Input Op Amp
Data Sheet
AD824
FEATURES
PIN CONFIGURATION
Single supply operation: 3 V to 30 V
Very low input bias current: 2 pA
Wide input voltage range
Rail-to-rail output swing
Low supply current per amplifier: 500 µA
Wide bandwidth: 2 MHz
1
2
3
4
5
6
7
OUT D
–IN D
+IN D
V–
OUT A
–IN A
+IN A
V+
14
13
12
11
10
9
AD824
TOP VIEW
(Not to Scale)
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
Slew rate: 2 V/µs
8
No phase reversal
Figure 1. 14-Lead SOIC (R Suffix)
APPLICATIONS
Photo diode preamplifier
Battery powered instrumentation
Power supply control and protection
Medical instrumentation
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifier
GENERAL DESCRIPTION
The AD824 is a quad, FET input, single supply amplifier,
featuring rail-to-rail outputs. The combination of FET inputs
and rail-to-rail outputs makes the AD824 useful in a wide
variety of low voltage applications where low input current is
a primary consideration.
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets
below 1 mV. This enables high accuracy designs even with high
source impedances. Precision is combined with low noise,
making the AD824 ideal for use in battery powered medical
equipment.
The AD824 is guaranteed to operate from a 3 V single supply
up to 15 V dual supplies. AD824AR-3V parametric
performance at 3 V is fully guaranteed.
Applications for the AD824 include portable medical
equipment, photo diode preamplifiers, and high impedance
transducer amplifiers.
Fabricated on Analog Devices, Inc., complementary bipolar
process, the AD824 has a unique input stage that allows the
input voltage to safely extend beyond the negative supply and
to the positive supply without any phase inversion or latch-up.
The output voltage swings to within 15 mV of the supplies.
Capacitive loads to 350 pF can be handled without oscillation.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
The AD824 is specified over the extended industrial (−40°C to
+85°C) temperature range and is available in narrow 14-lead
SOIC package.
Rev. E
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AD824* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• AD824 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-106: A Collection of Amp Applications
• AN-253: Find Op Amp Noise with Spreadsheet
• AN-357: Operational Integrators
DISCUSSIONS
View all AD824 EngineerZone Discussions.
• AN-649: Using the Analog Devices Active Filter Design
Tool
SAMPLE AND BUY
Data Sheet
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• AD824: Single Supply, Rail-to-Rail Low Power, FET-Input
Op Amp Data Sheet
TECHNICAL SUPPORT
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number.
TOOLS AND SIMULATIONS
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• AD824 SPICE Macro-Model
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AD824
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Characteristics.................................................................. 12
Output Characteristics............................................................... 12
Applications Information .............................................................. 13
Single Supply Voltage-to-Frequency Converter..................... 13
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
Single Supply Programmable Gain Instrumentation
Amplifier ..................................................................................... 13
3 V, Single Supply Stereo Headphone Driver ......................... 14
Low Dropout Bipolar Bridge Driver........................................ 14
A 3.3 V/5 V Precision Sample-and-Hold Amplifier.............. 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/15—Rev. D to Rev. E
Change to Figure 1 Caption ............................................................ 1
5/14—Rev. C to Rev. D
Updated Format..................................................................Universal
Removed 16-Lead SOIC Package (Throughout).......................... 1
Deleted Wafer Test Limits Section ................................................. 5
Deleted AD824 SPICE Macro-model Section............................ 15
Changes to Ordering Guide .......................................................... 16
2/03—Rev. B to Rev. C
Deleted N Package..............................................................Universal
Edits to General Description........................................................... 1
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Edits to Figure 4.............................................................................. 12
Edits to Figure 8.............................................................................. 13
Updated Outline Dimensions....................................................... 16
1/02—Rev. A to Rev. B
Edits to Electrical Specifications................................................. 2, 3
Edits to Absolute Maximum Ratings ............................................. 5
Edits to Ordering Guide .................................................................. 5
Deleted Dice Characteristics........................................................... 5
Rev. E | Page 2 of 16
Data Sheet
AD824
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
At VS = 5.0 V, VCM = 0 V, V OUT = 0.2 V, TA = 25°C; unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A)
VOS
IB
0.1
1.0
1.5
12
4000 pA
10
mV
mV
pA
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Input Bias Current
2
300
2
Input Offset Current
IOS
pA
pA
V
dB
dB
dB
Ω||pF
300
Input Voltage Range
Common-Mode Rejection Ratio
−0.2
66
60
+3.0
CMRR
AVO
VCM = 0 V to 2 V
VCM = 0 V to 3 V
TMIN to TMAX
80
74
60
Input Impedance
Large Signal Voltage Gain
1013||3.3
VO = 0.2 V to 4.0 V
RL = 2 kΩ
RL = 10 kΩ
RL = 100 kΩ
TMIN to TMAX, RL = 100 kΩ
20
50
250
180
40
V/mV
V/mV
V/mV
V/mV
µV/°C
100
1000
400
2
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
ΔVOS/ΔT
VOH
ISOURCE = 20 µA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 µA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
4.975 4.988
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
4.97
4.80
4.75
4.985
4.85
4.82
15
Output Voltage Low
VOL
25
30
150
200
20
120
140
12
10
100
Short Circuit Limit
ISC
Sink/source
TMIN to TMAX
f = 1 MHz, AV = 1
Open-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
ZOUT
PSRR
ISY
VS = 2.7 V to 12 V
TMIN to TMAX
TMIN to TMAX
70
66
80
dB
dB
µA
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
500
600
SR
BWP
tS
GBP
φo
CS
RL = 10 kΩ, AV = 1
1% distortion, VO = 4 V p-p
VOUT = 0.2 V to 4.5 V, to 0.01%
2
V/µs
kHz
µs
MHz
Degrees
dB
150
2.5
2
50
–123
No load
f = 1 kHz, RL = 2 kΩ
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
2
16
0.8
0.005
µV p-p
nV/√Hz
fA/√Hz
%
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
THD
f = 10 kHz, RL = ∞, AV = +1
Rev. E | Page 3 of 16
AD824
Data Sheet
At VS = 15.0 V, VOUT = 0 V, TA = 25°C; unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A)
VOS
IB
0.5
0.6
4
500
25
3
2.5
4.0
35
4000
mV
mV
pA
pA
pA
pA
pA
V
TMIN to TMAX
VCM = 0 V
TMIN to TMAX
VCM = −10 V
Input Bias Current
IB
IOS
Input Offset Current
20
TMIN to TMAX
500
Input Voltage Range
Common-Mode Rejection Ratio
−15
70
66
+13
CMRR
AVO
VCM = −15 V to 13 V
TMIN to TMAX
80
dB
dB
Ω||pF
Input Impedance
Large Signal Voltage Gain
1013||3.3
VO = −10 V to +10 V;
RL = 2 kΩ
RL = 10 kΩ
12
50
300
50
200
2000
V/mV
V/mV
V/mV
RL = 100 kΩ
TMIN to TMAX, RL = 100 kΩ
200
1000
2
V/mV
µV/°C
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
ΔVOS/ΔT
VOH
ISOURCE = 20 µA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 µA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
Sink/source, TMIN to TMAX
f = 1 MHz, AV = 1
14.975
14.970
14.80
14.988
14.985
14.85
14.82
–14.985
–14.98
–14.88
–14.86
20
V
V
V
V
V
V
V
V
14.75
Output Voltage Low
VOL
–14.975
–14.97
–14.85
–14.8
Short Circuit Limit
Open-Loop Impedance
POWER SUPPLY
ISC
ZOUT
8
mA
Ω
100
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 15 V
TMIN to TMAX
VO = 0 V
70
68
80
dB
dB
µA
µA
Supply Current/Amplifier
560
625
675
TMIN to TMAX
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
SR
BWP
tS
RL = 10 kΩ, AV = 1
1% distortion, VO = 20 V p-p
VOUT = 0 V to 10 V, to 0.01%
2
33
6
V/µs
kHz
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
GBP
φo
CS
2
50
–123
MHz
Degrees
dB
f = 1 kHz, RL = 2 kΩ
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f =10 kHz, VO = 3 V rms, RL = 10 kΩ
2
16
1.1
0.005
µV p-p
nV/√Hz
fA/√Hz
%
THD
Rev. E | Page 4 of 16
Data Sheet
AD824
At VS = 3.0 V, VCM = 0 V, V OUT = 0.2 V, TA = 25°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (AD824A−3 V)
VOS
IB
0.2
1.0
1.5
12
4000
10
mV
mV
pA
pA
pA
pA
V
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Input Bias Current
2
250
2
Input Offset Current
IOS
250
Input Voltage Range
0
1
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 1 V
TMIN to TMAX
58
56
74
dB
dB
Ω||pF
Input Impedance
Large Signal Voltage Gain
1013||3.3
VO = 0.2 V to 2.0 V;
RL = 2 kΩ
RL = 10 kΩ
RL = 100 kΩ
TMIN to TMAX, RL = 100 kΩ
10
30
180
90
20
65
500
250
V/mV
V/mV
V/mV
V/mV
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
ΔVOS/ΔT
VOH
2
µV/°C
ISOURCE = 20 µA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 µA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
Sink/source
Sink/source, TMIN to TMAX
f = 1 MHz, AV = 1
2.975
2.97
2.8
2.988
2.985
2.85
2.82
15
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
2.75
Output Voltage Low
Short Circuit Limit
VOL
25
30
150
200
20
120
140
8
ISC
ISC
ZOUT
6
Open-Loop Impedance
POWER SUPPLY
100
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 12 V,
TMIN to TMAX
VO = 0.2 V, TMIN to TMAX
70
66
dB
dB
µA
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
500
600
SR
BWP
tS
RL =10 kΩ, AV = 1
1% distortion, VO = 2 V p-p
VOUT = 0.2 V to 2.5 V, to 0.01%
2
300
2
V/µs
kHz
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
GBP
φo
CS
2
50
–123
MHz
Degrees
dB
f = 1 kHz, RL = 2 kΩ
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
2
16
0.8
0.01
µV p-p
nV/√Hz
fA/√Hz
%
THD
f = 10 kHz, RL = ∞, AV = +1
Rev. E | Page 5 of 16
AD824
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter1
Rating
Table 5. Thermal Resistance
Package Type
1
Supply Voltage
18 V
θJA
120
θJC
Unit
Input Voltage
−VS − 0.2 V to +VS
30 V
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
14-Lead SOIC (R)
36
°C/W
Differential Input Voltage
Output Short Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range (Soldering 60 sec)
1 θJA is specified for the worst case conditions, that is, θJA is specified for device
soldered in circuit board for SOIC package.
ESD CAUTION
1 Absolute maximum ratings apply to packaged parts unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
V
CC
I5
I6
Q18
Q29
R1
J1
R2
R9
Q21 Q27
Q4
Q6
C3
Q5
J2
Q20
Q23
Q19
Q22
+IN
R7
Q7
C4
R13
–IN
R15
V
OUT
C2
Q24 Q25
Q8
C1
Q2
Q3
Q31
Q28
Q26
R12
I1
R14
I2
R17
I3
V
I4
EE
Figure 2. Simplified Schematic of 1/4 AD824
Rev. E | Page 6 of 16
Data Sheet
AD824
TYPICAL PERFORMANCE CHARACTERISTICS
V
= ±15V
V = 5V
S
S
NO LOAD
NO LOAD
80
60
40
20
0
80
60
40
20
0
45
45
90
90
135
180
135
180
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = 15 V,
No Load
Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
No Load
V
C
= ±15V
= 100pF
S
V
C
= 5V
= 220pF
S
L
80
60
40
20
0
L
60
40
45
90
20
45
135
180
90
0
135
180
–20
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = 15 V,
CL = 100 pF
Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V,
CL = 220 pF
Rev. E | Page 7 of 16
AD824
Data Sheet
V
= 3V
S
NO LOAD
60
40
20
0
t
9.950µs
45
100
90
90
135
180
10
0%
–20
1k
5V
2µs
10k
100k
1M
10M
FREQUENCY (Hz)
t
10.810µs
100
90
100
90
10
10
0%
0%
50mV
1µs
5V
2µs
Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V,
No Load
Figure 9. Slew Rate, RL = 10 kΩ
100
90
V
C
= 3V
= 220pF
S
L
60
40
V
OUT
45
10
0%
90
20
100µs
5V
135
180
Figure 10. Phase Reversal with Inputs Exceeding Supply by 1 V
0
0.8
–20
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100
90
SOURCE
SINK
10
0%
1µ
5µ
10µ
50µ
100µ
500µ
1m
5m
10m
50mV
1µs
LOAD CURRENT (A)
Figure 8. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V,
CL = 220 pF
Figure 11. Output Voltage to Supply Rail vs. Sink and Source Load Currents
Rev. E | Page 8 of 16
Data Sheet
AD824
14
12
10
8
COUNT = 60
3V ≤ V ≤ ±15V
S
60
40
20
6
4
2
0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
5
10
15
20
OFFSET VOLTAGE DRIFT (µV/°C)
FREQUENCY (kHz)
Figure 12. Voltage Noise Density
Figure 15. TC VOS Distribution, −55°C to +125°C, VS = 5 V, 0 V
0.1
150
125
100
75
R
A
= ∞
V
= 5V, 0V
L
V
S
= +1
V
V
= +3V
S
0.01
0.001
= +5V
S
50
V
= ±15V
S
25
0
0.0001
–25
20
100
1k
FREQUENCY (Hz)
10k 20k
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 13. Total Harmonic Distortion
Figure 16. Input Offset Current vs. Temperature
280
240
200
160
120
80
100k
10k
1k
V
= 5V, 0V
COUNT = 860
S
100
10
1
40
0
0.1
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
20
40
60
80
100
120
140
OFFSET VOLTAGE (mV)
TEMPERATURE (°C)
Figure 14. Input Offset Distribution, VS = 5 V, 0 V
Figure 17. Input Bias Current vs. Temperature
Rev. E | Page 9 of 16
AD824
Data Sheet
120
100
80
1k
100
10
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Common-Mode Rejection vs. Frequency
Figure 21. Input Voltage Noise Spectral Density vs. Frequency
–40
–60
120
100
80
60
40
20
0
–80
–100
–120
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. THD vs. Frequency, 3 V rms
Figure 22. Power Supply Rejection vs. Frequency
100
80
60
40
20
0
100
80
60
40
20
0
30
25
20
15
10
5
±15V
3V, 0V
–20
10
–20
10M
0
1k
100
1k
10k
100k
1M
3k
10k
30k
100k
300k
1M
FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
Figure 20. Open-Loop Gain and Phase vs. Frequency
Figure 23. Large Signal Frequency Response
Rev. E | Page 10 of 16
Data Sheet
AD824
–80
–90
–100
–110
–120
–130
5V
5µs
100
90
1 TO 4
1 TO 2
1 TO 3
10
0%
–140
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 24. Crosstalk vs. Frequency
Figure 27. Large Signal Response
10k
1k
2750
2500
2250
2000
1750
1500
1250
1000
V
= ±15V
S
100
10
V
= +3V, 0V
S
1
0.1
0.01
10
100
1k
10k
100k
1M
10M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 25. Output Impedance vs. Frequency, Gain = +1
Figure 28. Supply Current vs. Temperature
1k
100
10
V
V
= ±15V
= 3V, 0V
S
S
20mV
500ns
V
– V
S
OL
100
90
V
– V
OH
S
10
0%
1
0.01
0.1
1
10
LOAD CURRENT (mA)
Figure 26. Small Signal Response, Unity Gain Follower, 10 kΩ||100 pF Load
Figure 29. Output Saturation Voltage
Rev. E | Page 11 of 16
AD824
Data Sheet
THEORY OF OPERATION
positive supply by more than 300 mV or if an input voltage will
be applied to the AD824 when VS = 0 V. The amplifier will be
damaged if left in that condition for more than 10 seconds. A
1 kΩ resistor allows the amplifier to withstand up to 10 V of
continuous overvoltage and increases the input voltage noise by
a negligible amount.
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below −VS to 1 V
less than +VS. Driving the input voltage closer to the positive
rail causes a loss of amplifier bandwidth.
Input voltages less than −VS are a completely different story. The
amplifier can safely withstand input voltages 20 V below the
−VS as long as the total voltage from the +VS to the input termi-
nal is less than 36 V. In addition, the input stage typically maintains
picoamp level input currents across that input voltage range.
The AD824 does not exhibit phase reversal for input voltages up
to and including +VS. Figure 30a shows the response of an
AD824 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output waveform.
For input voltages greater than +VS, a resistor in series with the
noninverting input prevents phase reversal at the expense of
greater input voltage noise. This is illustrated in Figure 30b.
OUTPUT CHARACTERISTICS
The unique bipolar rail-to-rail output stage of the AD824
swings within 15 mV of the positive and negative supply
voltages. The approximate output saturation resistance of the
AD824 is 100 Ω for both sourcing and sinking. This can be used
to estimate output saturation voltage when driving heavier
current loads. For instance, the saturation voltage is 0.5 V from
either supply with a 5 mA current load.
1V
2µs
100
90
For load resistances over 20 kΩ, the input error voltage of the
AD824 is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
10
GND
0%
If the output of the AD824 is overdriven to saturate either of the
output devices, the amplifier will recover within 2 μs of its input
returning to the amplifier’s linear operating region.
1V
1V
(a)
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 6 and Figure 8 show the
pulse response of the AD824 as a unity gain follower driving
220 pF. Configurations with less loop gain, and as a result less
loop bandwidth, will be much less sensitive to capacitance load
effects. Noise gain is the inverse of the feedback attenuation
factor provided by the feedback network in use.
10µs
1V
100
90
+V
S
10
GND 0%
1V
(b)
5V
Figure 31 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
values, the circuit drives 5,000 pF with a 10% overshoot.
R
P
V
IN
V
OUT
+V
S
0.01µF
8
100Ω
Figure 30. (a) Response with RP = 0; VIN from 0 V to +VS;
(b) VIN = −200 V to + VS + 200 mV; VOUT = 0 V to + VS; RP = 49.9 kΩ
1/4
AD824
V
IN
V
OUT
0.01µF
4
Because the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 10.
C
L
–V
S
20pF
20kΩ
Figure 31. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Use a current-limiting resistor in series with the input of the
AD824 if there is a possibility of the input voltage exceeding the
Rev. E | Page 12 of 16
Data Sheet
AD824
APPLICATIONS INFORMATION
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY
CONVERTER
Table 6. AD824 In Amp Performance
Parameter
VS = 3 V, 0 V
VS = 5 V
80 dB
The circuit shown in Figure 32 uses the AD824 to drive a low
power timer, which produces a stable pulse of width, t1. The
positive going output pulse is integrated by R1 and C1 and used
as one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown
voltage, VIN. The AD824 output drives the timer trigger input,
closing the overall feedback loop.
CMRR
74 dB
Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V
3 dB BW
G = 10
G = 100
180 kHz
18 kHz
180 kHz
18 kHz
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = 5 V)
Noise @ f = 1 kHz
G = 10
2 μs
10V
5 μs
U4
REF02
C5
0.1µF
2
270 nV/√Hz
2.2 μV/√Hz
270 nV/√Hz
2.2 μV/√Hz
V
= 5V
REF
6
5
G = 100
CMOS
74HCO4
R
**
OUT2
OUT1
3
SCALE
10kΩ
C3
0.1µF
4
U3B
4
U3A
2
5µs
3
1
U2
CMOS 555
100
90
R2
4
8
V+
U1
R3*
C1
0.01µF
2%
499kΩ
R
116kΩ
1%
6
THR
3
5
OUT
CV
R1
1/4
2
7
499kΩ
TR
AD824
1%
10
DIS
C6
390pF
5%
0%
GND
0V TO 2.5V
FULL SCALE
1
1V
(NPO)
C4
C2
0.01µF
2%
0.1µF
Figure 33. Pulse Response of In Amp to a 500 mV p-p Input Signal;
VS = 5 V, 0 V; Gain = 10
NOTES
f
= V /(V × t ), t = 1.1 × R3 × C6 = 25kHz f AS SHOWN.
OUT
IN REF 1 1 S
R1
90kΩ
R2
9kΩ
R3
1kΩ
R4
1kΩ
R5
9kΩ
R6
90kΩ
OHMTEK
PART #1043
* = 1% METAL FILM, <50ppm/°C TC
** = 10%, 20T FILM, <100ppm/°C TC
t
V
REF
= 33µs FOR f
= 20kHz @ V = 2.0V
1
OUT
IN
Figure 32. Single Supply Voltage-to-Frequency Converter
G = 10
G = 100 G = 100
G = 10
Typical AD824 bias currents of 2 pA allow MΩ range source
impedances with negligible dc errors. Linearity errors of 0.01%
full scale can be achieved with this circuit. This performance is
obtained with a 5 V single supply, which delivers less than 3 mA
to the entire circuit.
+V
S
0.1µF
2
3
6
1/4
AD824
1/4
AD824
1
7
R
1kΩ
P
V
5
OUT
V
V
IN1
11
R
1kΩ
P
SINGLE SUPPLY PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
IN2
R6
(G = 10) V
(G = 10) V
= (V
= (V
– V )(1 +
IN2
) + V
REF
OUT
IN1
R4 + R5
The AD824 can be configured as a single supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 5 V or dual supplies up to 1 5 V. AD824 FET inputs bias
currents of 2 pA minimize offset errors caused by high
unbalanced source impedances.
R5 + R6
R4
– V )(1 +
IN2
) + V
REF
OUT
IN1
FOR R1 = R6, R2 = R5 AND R3 = R4
Figure 34. A Single Supply Programmable Instrumentation Amplifier
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of
5 ppm/°C.
Rev. E | Page 13 of 16
AD824
Data Sheet
3 V, SINGLE SUPPLY STEREO HEADPHONE DRIVER
LOW DROPOUT BIPOLAR BRIDGE DRIVER
The AD824 exhibits good current drive and THD + N
performance, even at 3 V single supplies. At 1 kHz, total
harmonic distortion plus noise (THD + N) equals −62 dB
(0.079%) for a 300 mV p-p output signal. This is comparable
to other single supply op amps that consume more power and
cannot run on 3 V power supplies.
The AD824 can be used for driving a 350 Ω Wheatstone bridge.
Figure 36 shows one half of the AD824 being used to buffer the
AD589—a 1.235 V low power reference. The output of 4.5 V
can be used to drive an ADC front end. The other half of the
AD824 is configured as a unity-gain inverter and generates the
other bridge input of –4.5 V. Resistors R1 and R2 provide a
constant current for bridge excitation. The AD620 low power
instrumentation amplifier is used to condition the differential
output voltage of the bridge. The gain of the AD620 is pro-
grammed using an external resistor RG and determined by:
In Figure 35, each channel’s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway
between the power supplies (1.5 V). The gain is 1.5. Each half of
the AD824 can then be used to drive a headphone channel. A
5 Hz high-pass filter is realized by the 500 µF capacitors and the
headphones, which can be modeled as 32 Ω load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz to 20 kHz) are delivered to the headphones.
3V
49.4 k Ω
G =
+1
RG
+V
S
49.9kΩ
R1
20Ω
+1.235V
1/4
AD824
TO ADC
REFERENCE INPUT
0.1µF
0.1µF
AD589
95.3kΩ
47.5kΩ
1µF
MYLAR
CHANNEL 1
26.4kΩ, 1%
350Ω
+V
S
1/4
AD824
10kΩ
1%
350Ω
500µF
3
7
6
R
AD824
350Ω
350Ω
95.3kΩ
G
L
4.99kΩ
5
10kΩ
2
10kΩ
1%
4
HEADPHONES
32Ω IMPEDANCE
V
REF
10kΩ
1%
10kΩ
–V
S
R
1/4
AD824
+V
S
+5V
–5V
–4.5V
4.99kΩ
1/4
0.1µF
GND
0.1µF
1µF
1µF
R2
20Ω
1µF
MYLAR
47.5kΩ
AD824
–V
S
500µF
CHANNEL 2
–V
S
Figure 36. Low Dropout Bipolar Bridge Driver
Figure 35. 3 Volt Single Supply Stereo Headphone Driver
Rev. E | Page 14 of 16
Data Sheet
AD824
A design consideration in sample-and-hold circuits is voltage
A 3.3 V/5 V PRECISION SAMPLE-AND-HOLD
AMPLIFIER
droop at the output caused by op amp bias and switch leakage
currents. By choosing an JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 µV/µs in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be
polystyrene, polypropylene or Teflon capacitors.
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit
shown in Figure 37 illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain
high signal-to-noise ratios (SNRs) in a low supply voltage
application requires the use of rail-to-rail, input/output
operational amplifiers. This design highlights the ability of the
AD824 to operate rail-to-rail from a single 3 V/5 V supply, with
the advantages of high input impedance. The AD824, a quad
JFET-input op amp, is well suited to sample-and-hold circuits
due to its low input bias currents (3 pA, typical) and high input
impedances (3 × 1013 Ω, typical). The AD824 also exhibits very
low supply currents so the total supply current in this circuit is
less than 2.5 mA.
These types of capacitors exhibit low leakage and low dielectric
absorption. Additionally, 1% metal film resistors were used
throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output is
V
OUT = −VIN. The purpose of SW4, which operates in parallel
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting
input of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 creates a differential voltage step error that appears at
3.3V/5V
3.3V/5V
V
OUT. The pedestal error for this circuit is less than 2 mV over
0.1µF
the entire 0 V to 3.3 V/5 V signal range. Another method of
reducing pedestal error is to reduce the pulse amplitude applied
to the control pins. To control the ADG513, only 2.4 V are
required for the on state and 0.8 V for the off state. If possible,
use an input control signal whose amplitude ranges from 0.8 V
to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum
pedestal error.
R1
50kΩ
AD824
3
4
1
A1
2
R2
50kΩ
FALSE GROUND (FG)
11
R4
2kΩ
3.3V/5V
13
ADG513
15
SW2
14
16
9
R5
2kΩ
Other circuit features include an acquisition time of less than
3 µs to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
11
10
SW3
AD824
5
FG
10
CH
500pF
7
2
3
A2
6
SW1
1
8
8
A3
+
9
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normally open and normally closed
precision CMOS switches on a dielectrically isolated process.
SW2 is not required in this circuit; however, it was used in
parallel with SW3 to provide a lower RON analog switch.
V
OUT
–
7
6
5
AD824
SW4
C2
500pF
AD824
12
4
FG
14
A4
13
SAMPLE/
HOLD
FG
Figure 37. 3.3 V/5.5 V Precision Sample-and-Hold Circuit
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The sample-and-hold
circuit is configured in an inverting topology centered around
this false ground level.
Rev. E | Page 15 of 16
AD824
Data Sheet
OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
R-14
R-14
R-14
R-14
R-14
R-14
R-14
R-14
AD824AR-14
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
AD824AR-14-3V
AD824AR-14-3V-REEL
AD824AR-14-REEL
AD824AR-14-REEL7
AD824ARZ-14
AD824ARZ-14-3V
AD824ARZ-14-3V-RL
AD824ARZ-14-REEL
AD824ARZ-14-REEL7
R-14
R-14
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00875-0-4/15(E)
Rev. E | Page 16 of 16
相关型号：
AD824AR-14-REEL7
QUAD OP-AMP, 4000uV OFFSET-MAX, 2MHz BAND WIDTH, PDSO14, PLASTIC, SOIC-14
ROCHESTER
AD824AR-16-REEL
IC QUAD OP-AMP, 4000 uV OFFSET-MAX, 2 MHz BAND WIDTH, PDSO16, PLASTIC, SOIC-16, Operational Amplifier
ADI
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