AD8285WBCPZ-RL [ADI]
Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC;
| 型号： | AD8285WBCPZ-RL |
| 厂家： | 
ADI |
| 描述： | Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC 电信 电信集成电路 |
| 文件： | 总28页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radar Receive Path AFE: 4-Channel
LNA/PGA/AAF with ADC
Data Sheet
AD8285
FEATURES
FUNCTIONAL BLOCK DIAGRAM
4-channel LNA, PGA, and AAF
1 direct to ADC channel
Programmable gain amplifier (PGA)
Includes low noise preamplifier (LNA)
Serial peripheral interface (SPI) programmable gain
16 dB to 34 dB in 6 dB steps
Antialiasing filter (AAF)
Programmable third order, low-pass elliptic filter (LPF)
from 1.0 MHz to 12.0 MHz
INA+
INA–
REFERENCE
LNA
LNA
LNA
LNA
PGA
PGA
PGA
PGA
AAF
AAF
AAF
INB+
INB–
DSYNC
D[0:11]
MUX
INC+
INC–
12-BIT
ADC
DRV
IND+
IND–
AAF
Analog-to-digital converter (ADC)
INADC+
INADC–
12 bits of accuracy up to 72 MSPS
Signal-to-noise ratio (SNR): 68.5 dB
Spurious-free dynamic range (SFDR): 68 dB at gain = 16 dB
Low power: 185 mW per channel at 12 bits and 72 MSPS
Low noise: 3.5 nV/√Hz maximum of input referred voltage noise
Power-down mode
72-lead, 10 mm × 10 mm LFCSP package
Specified from −40°C to +105°C
Qualified for automotive applications
SPI
AD8285
NOTES
1. AVDD18x = AVDD18, AVDD18ADC.
AVDD33x = AVDD33, AVDD33A, AVDD33B, AVDD33C, AVDD33D, AVDD33REF.
DVDD18x = DVDD18, DVDD18CLK. DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV.
Figure 1.
APPLICATIONS
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self parking
Electronic bumper
GENERAL DESCRIPTION
The AD8285 is designed for low cost, low power, compact size,
flexibility, and ease of use. It contains four channels of a low noise
preamplifier (LNA) with a programmable gain amplifier (PGA)
and an antialiasing filter (AAF) plus one direct to ADC channel, all
integrated with a single 12-bit analog-to-digital converter (ADC).
Fabricated in an advanced complementary metal oxide
semiconductor (CMOS) process, the AD8285 is available in a
10 mm × 10 mm, RoHS compliant, 72-lead LFCSP that is specified
over the automotive temperature range of −40°C to +105°C.
Table 1. Related Devices
Each channel features a gain range of 16 dB to 34 dB in 6 dB
increments and an ADC with a conversion rate of up to 72 MSPS.
The combined input referred noise voltage of the entire channel
is 3.5 nV/√Hz at maximum gain. The channel is optimized for
dynamic performance and low power in applications where a
small package size is critical.
Part No.
Description
AD8283
6-channel LNA/PGA/AAF, pseudo simultaneous
channel sampling with ADC
AD8284
4-channel LNA/PGA/AAF, sequential channel
sampling with ADC
ADA8282 4-channel LNA/PGA
Rev. B
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Last Content Update: 02/23/2017
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• AD8285: Radar Receive Path AFE: 4-Channel LNA/PGA/
AAF with ADC Data Sheet
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AD8285
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SDIO Pin...................................................................................... 17
SCLK Pin ..................................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Radar Receive Path AFE............................................................ 14
Channel Overview...................................................................... 15
ADC ............................................................................................. 16
Clock Input Considerations...................................................... 16
Clock Duty Cycle Considerations............................................ 17
Clock Jitter Considerations....................................................... 17
CS
Pin .......................................................................................... 17
RBIAS Pin.................................................................................... 17
Voltage Reference ....................................................................... 18
Power and Ground Recommendations................................... 18
Exposed Paddle Thermal Heat Slug Recommendations ...... 18
Serial Peripheral Interface (SPI)................................................... 19
Hardware Interface..................................................................... 19
Memory Map .................................................................................. 21
Reading the Memory Map Table.............................................. 21
Logic Levels................................................................................. 21
Reserved Locations .................................................................... 21
Default Values............................................................................. 21
Application Diagrams.................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Automotive Products................................................................. 27
REVISION HISTORY
9/15—Rev. A to Rev. B
Added Table 1; Renumbered Sequentially .................................... 1
10/14—Rev. 0 to Rev. A
Changes to Addr. (Hex) 0x15, Table 8 ......................................... 23
Changes to Ordering Guide .......................................................... 27
5/14—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
AD8285
SPECIFICATIONS
AC SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =
DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =
34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter2
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG CHANNEL CHARACTERISTICS
LNA, PGA, and AAF channels
Gain
Gain Range
Gain Error
16/22/28/34
18
dB
dB
dB
−1.25
+1.25
Input Voltage Range
Channel gain = 16 dB
Channel gain = 22 dB
Channel gain = 28 dB
Channel gain = 34 dB
200 Ω input impedance selected
200 kΩ input impedance selected
0.25
V p-p
V p-p
V p-p
V p-p
kΩ
0.125
0.0625
0.03125
0.230
200
Input Resistance
0.180
160
0.280
240
kΩ
Input Capacitance
22
pF
Input Referred Voltage Noise
Maximum gain at 1 MHz
Minimum gain at 1 MHz
Maximum gain, RS = 50 Ω, unterminated
Maximum gain, RS = RIN = 50 Ω
Gain = 16 dB
1.85
6.03
7.1
12.7
nV/√Hz
nV/√Hz
dB
Noise Figure
dB
Output Offset
−60
−250
+60
+250
LSB
LSB
MHz
%
Gain = 34 dB
AAF Low-Pass Filter Cutoff
Tolerance
AAF Attenuation in Stop Band
−3 dB, programmable
After filter autotune
Third-order elliptic filter
2× cutoff
1.0 to 12.0
5
−10
+10
30
dB
3× cutoff
40
dB
Group Delay Variation
Channel-to-Channel Phase Variation
Filter set at 2 MHz
400
0.5
ns
Frequencies up to −3 dB
¼ of −3 dB frequency
Frequencies up to −3 dB
¼ of −3 dB frequency
Relative to output
−5
−1
−0.5
−0.25
+5
+1
+0.5
+0.25
Degrees
Degrees
dB
dB
dBm
dBc
Channel-to-Channel Gain Matching
0.1
1 dB Compression
Crosstalk
9.8
−70
−55
POWER SUPPLY
AVDD18, AVDD18ADC
AVDD33, AVDD33x1, AVDD33REF
DVDD18, DVDD18CLK
DVDD33SPI, DVDD33CLK,
DVDD33DRV
1.7
3.1
1.7
3.1
1.8
3.3
1.8
3.3
1.9
3.5
1.9
3.5
V
V
V
V
IAVDD18
IAVDD33
IDVDD18
IDVDD33
Full channel mode
Full channel mode
130
130
22
2
185
mA
mA
mA
mA
mW
Total Power Dissipation Per Channel
Full channel mode, no signal, typical supply
voltage × maximum supply current; excludes
output current
Power-Down Dissipation
5
mW
Power Supply Rejection Ratio (PSRR)
1.6
mV/V
Rev. B | Page 3 of 27
AD8285
Data Sheet
Parameter2
Test Conditions/Comments
Min
Typ
Max
Unit
ADC
Resolution
Maximum Sample Rate
Signal-to-Noise Ratio (SNR)
Signal-to-Noise and Distortion
(SINAD)
12
72
68.5
66
Bits
MSPS
dB
fIN = 1 MHz
dB
Signal-to-Noise Ratio Full Scale
(SNRFS)
68
dB
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Effective Number of Bits (ENOB)
ADC OUTPUT CHARACTERISTICS
Maximum Capacitor Load
Guaranteed no missing codes
1
10
LSB
LSB
LSB
10.67
20
Per bit
pF
IDVDD33 Peak Current with Capacitor
Load
Peak current per bit when driving 20 pF load;
can be programmed via the SPI port, if required
40
25
mA
ADC REFERENCE
Output Voltage Error
Load Regulation
VREF = 1.024 V
At 1.0 mA, VREF = 1.024 V
mV
mV
kΩ
2
6
Input Resistance
FULL CHANNEL CHARACTERISTICS
SNRFS
LNA, PGA, AAF, and ADC channels
fIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
68
68
68
66
dB
dB
dB
dB
SINAD
fIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
67
68
67
66
dB
dB
dB
dB
Spurious-Free Dynamic Range
(SFDR)
fIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
68
74
74
73
dB
dB
dB
dB
Harmonic Distortion
Second Harmonic
fIN = 1 MHz at −10 dBFS, gain = 16 dB
fIN = 1 MHz at −10 dBFS, gain = 34 dB
fIN = 1 MHz at −10 dBFS, gain = 16 dB
fIN = 1 MHz at −10 dBFS, gain = 34 dB
fIN1 = 1 MHz, fIN2 = 1.1 MHz, −1 dBFS, gain = 34 dB
−70
−70
−66
−75
−69
600
200
dBc
dBc
dBc
dBc
dBc
ns
Third Harmonic
IM3 Distortion
Gain Response Time
Overdrive Recovery Time
ns
1 x stands for A, B, C, or D.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.
Rev. B | Page 4 of 27
Data Sheet
AD8285
DIGITAL SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =
DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =
34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 3.
Parameter2
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage3
Input Common-Mode Voltage
Differential Input Resistance
Input Capacitance
Full
Full
25°C
25°C
250
mV p-p
V
kΩ
pF
1.2
20
1.5
LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Full
Full
25°C
25°C
1.2
1.2
3.6
0.3
V
V
kΩ
pF
30
0.5
LOGIC INPUT (CS)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
3.6
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
70
0.5
kΩ
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
0
DVDD33x + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
30
2
kΩ
pF
LOGIC OUTPUT (SDIO)4
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
LOGIC OUTPUT (Dx, DSYNC)
Logic 1 Voltage (IOH = 2 mA)
Logic 0 Voltage (IOL = 2 mA)
Full
Full
3.0
3.0
V
V
0.3
Full
Full
V
V
0.05
1 x stands for A, B, C, or D.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.
3 Specified for LVDS and LVPECL only.
4 Specified for 13 SDIO pins sharing the same connection.
Rev. B | Page 5 of 27
AD8285
Data Sheet
SWITCHING SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =
DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =
34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 4.
Parameter2
CLOCK
Temperature
Min
Typ
Max
Unit
Clock Rate
Full
10
72
MSPS
ns
ns
ns
ns
Clock Pulse Width High (tEH) at 72 MSPS Full
Clock Pulse Width Low (tEL) at 72 MSPS Full
Clock Pulse Width High (tEH) at 40 MSPS Full
Clock Pulse Width Low (tEL) at 40 MSPS
OUTPUT PARAMETERS
6.94
6.94
12.5
12.5
Full
Propagation Delay (tPD) at 72 MSPS
Rise Time (tR)3
Full
Full
Full
Full
Full
Full
Full
Full
1.5
2.5
1.9
1.2
10.0
4.0
22.5
4.0
7
5.0
ns
ns
ns
ns
ns
ns
ns
Fall Time (tF)3
Data Set-Up Time (tDS) at 72 MSPS
Data Hold Time (tDH) at 72 MSPS
Data Set-Up Time (tDS) at 40 MSPS
Data Hold Time (tDH) at 40 MSPS
Pipeline Latency
9.0
1.5
21.5
1.5
11.0
5.0
23.5
5.0
Clock cycles
1 x stands for A, B, C, or D.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.
3 Not shown in Figure 2.
N
N –1
INAx
tEH
tEL
CLK–
CLK+
tDH
tDS
tPD
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
D[11:0]
Figure 2. Timing Definitions for Switching Specifications
Rev. B | Page 6 of 27
Data Sheet
AD8285
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Electrical
AVDD18x1 to GND
AVDD33x2 to GND
DVDD18x3 to GND
DVDD33x4 to GND
−0.3 V to +2.0 V
−0.3 V to +3.5 V
−0.3 V to +2.0 V
−0.3 V to +3.5 V
−0.3 V to +3.5 V
Analog Inputs
INx+, INx− to GND
ESD CAUTION
Auxiliary Inputs
INADC+, INADC− to GND
Digital Outputs
−0.3 V to +2.0 V
−0.3 V to +3.5 V
D[11:0], DSYNC, SDIO to GND
CLK+, CLK− to GND
PDWN, SCLK, CS, AUX, MUXA,
ZSEL to GND
−0.3 V to +3.9 V
−0.3 V to +3.9 V
RBIAS, VREF to GND
Environmental
−0.3 V to +2.0 V
Operating Temperature
Range (Ambient)
Storage Temperature
Range (Ambient)
Maximum Junction
Temperature
−40°C to +105°C
−65°C to +150°C
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
1 AVDD18x = AVDD18 and AVDD18ADC.
2 AVDD33x = AVDD33A, AVDD33B, AVDD33C, AVDD33D, and AVDD33REF.
3 DVDD18x = DVDD18, DVDD18CLK.
4 DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV.
Rev. B | Page 7 of 27
AD8285
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL 10
TEST1 11
TEST2 12
DVDD33SPI 13
AVDD18 14
AVDD33A 15
INA– 16
1
2
3
4
5
6
7
8
9
54 NC
PIN 1
INDICATOR
53 TEST4
52 DVDD18CLK
51 CLK+
50 CLK–
49 DVDD33CLK
48 AVDD33REF
47 VREF
46 RBIAS
45 BAND
44 APOUT
43 ANOUT
42 TEST3
41 AVDD18ADC
40 AVDD18
39 INADC+
38 INADC–
37 NC
AD8285
TOP VIEW
(Not to Scale)
INA+ 17
NC 18
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. TIE THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
1
2
3
EPAD
NC
DSYNC
PDWN
Exposed Pad. Tie the exposed pad on the bottom of the package to the analog/digital ground plane.
No Connect. Do not connect to this pin.
Data Output Synchronization.
Full Power Down. Logic high overrides the SPI and powers down the device. Logic low allows selection of
the power down option through the SPI.
4
5
6
7
8
DVDD18
SCLK
SDIO
CS
1.8 V Digital Supply.
Serial Clock.
Serial Data Input/Output.
Chip Select Bar.
AUX
Auxiliary. A logic high on AUX switches the AUX channel (INADC+/INADC−) to the ADC. The AUX pin has a
higher priority than the MUXA pin.
9
10
MUXA
ZSEL
Channel A Select. Logic high forces to Channel A unless AUX is asserted.
Input Impedance Select. Logic high overrides the SPI and sets the input impedance to 200 kΩ. Logic low
allows selection of the input impedance through the SPI.
11
12
13
14
15
16
17
18
19
20
21
22
23
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA−
INA+
NC
NC
NC
Test. Do not use the TEST1 pin; tie it to ground.
Test. Do not use the TEST2 pin; tie it to ground.
3.3 V Digital Supply for SPI Port.
1.8 V Analog Supply.
3.3 V Analog Supply for Channel A.
Negative LNA Analog Input for Channel A.
Positive LNA Analog Input for Channel A.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
3.3 V Analog Supply for Channel B.
AVDD33B
INB−
INB+
Negative LNA Analog Input for Channel B.
Positive LNA Analog Input for Channel B.
Rev. B | Page 8 of 27
Data Sheet
AD8285
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Mnemonic
AVDD33C
INC−
INC+
AVDD33D
IND−
IND+
AVDD33
NC
NC
AVDD33
NC
Description
3.3 V Analog Supply for Channel C.
Negative LNA Analog Input for Channel C.
Positive LNA Analog Input for Channel C.
3.3 V Analog Supply for Channel D.
Negative LNA Analog Input for Channel D.
Positive LNA Analog Input for Channel D.
3.3 V Analog Supply.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
3.3 V Analog Supply.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
Negative Analog Input for Alternate Channel D (ADC Only).
Positive Analog Input for Alternate Channel D (ADC Only).
1.8 V Analog Supply.
NC
NC
NC
INADC−
INADC+
AVDD18
AVDD18ADC
TEST3
ANOUT
APOUT
BAND
RBIAS
1.8 V Analog Supply for ADC.
Test. Do not use the TEST3 pin; tie it to ground.
Analog Outputs. The ANOUT pin is for debug purposes only. Leave this pin floating.
Analog Outputs. The APOUT pin is for debug purposes only. Leave this pin floating.
Band Gap Voltage. The BAND pin is for debug purposes only. Leave this pin floating.
External Resistor. The RBIAS pin sets the internal ADC core bias current.
Voltage Reference Input/Output.
3.3 V Analog Supply for References.
3.3 V Digital Supply for Clock.
Clock Input Complement.
Clock Input True.
VREF
AVDD33REF
DVDD33CLK
CLK−
CLK+
DVDD18CLK
TEST4
NC
1.8 V Digital Supply for Clock.
Test. Do not use the TEST4 pin; tie it to ground.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
NC
DVDD33DRV 3.3 V Digital Supply for Output Driver.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
ADC Data Output 11 (MSB).
ADC Data Output 10.
ADC Data Output 9.
ADC Data Output 8.
ADC Data Output 7.
ADC Data Output 6.
ADC Data Output 5.
ADC Data Output 4.
ADC Data Output 3.
ADC Data Output 2.
ADC Data Output 1.
ADC Data Output 0 (LSB).
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
DVDD33DRV 3.3 V Supply for Output Driver.
NC No Connect. Do not connect to this pin.
Rev. B | Page 9 of 27
AD8285
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33A = AVDD33B = AVDD33C = AVDD33D = AVDD33 = AVDD33REF = AVDD33CLK =
3.3 V, TA = 25°C, fS = 72 MSPS, RIN = 200 kꢀ, VREF = 1.024 V.
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
50
40
34dB
28dB
22dB
16dB
30
20
10
0
–10
–20
–30
–40
6
4
2
0
33.50
33.66
33.82
33.98
34.14
34.30
34.46
0.1
1
10
FREQUENCY (MHz)
100
33.58
33.74
33.90
34.06
34.22
34.38
GAIN ERROR (dB)
Figure 7. Gain Error Histogram (Gain = 34 dB)
Figure 4. Channel Gain vs. Frequency
20
1.0
0.8
34dB
19
18
17
16
15
14
13
12
11
10
9
28dB
22dB
16dB
0.6
0.4
0.2
0
8
7
6
5
4
3
2
1
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25
–40
–15
10
35
60
85
GAIN MATCHING (dB)
TEMPERATURE (°C)
Figure 5. Gain Error vs. Temperature at All Gains
Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB)
40
10
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
9
8
7
6
5
4
3
2
1
0
6
4
2
0
16.00
16.16
16.32
16.48
16.64
16.8
16.96
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25
16.08
16.24
16.4
16.56
16.72
16.88
GAIN ERROR (dB)
GAIN MATCHING (dB)
Figure 6. Gain Error Histogram (Gain = 16 dB)
Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB)
Rev. B | Page 10 of 27
Data Sheet
AD8285
12000
10000
8000
6000
4000
2000
0
70
65
60
55
50
45
40
SNR
SINAD
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
16
22
28
34
CODE
GAIN (dB)
Figure 10. Output Referred Noise Histogram (Gain = 16 dB)
Figure 13. SNR/SINAD vs. Gain
7000
20
10
6000
5000
4000
3000
2000
1000
0
0
–10
–20
–30
–40
–50
12MHz
8MHz
4MHz
2MHz
1MHz
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
0.1
1
10
100
CODE
FREQUENCY (Hz)
Figure 11. Output Referred Noise Histogram (Gain = 34 dB)
Figure 14. Filter Response
15
200
180
160
140
120
100
80
34dB
28dB
10
16dB
22dB
16dB
5
60
22dB
28dB
40
20
34dB
0
0.1
0
1
10
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Short-Circuit Input Referred Noise vs. Frequency
Figure 15. Short-Circuit Output Referred Noise vs. Frequency
Rev. B | Page 11 of 27
AD8285
Data Sheet
1000
900
800
700
600
500
400
300
200
100
1.5
1.0
1MHz
2MHz
4MHz
8MHz
12MHz
0.5
0
–0.5
–1.0
–1.5
0
0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1
10
FREQUENCY (MHz)
100
TIME (µs)
Figure 16. Group Delay vs. Frequency
Figure 19. Overdrive Recovery
–40
SECOND HARMONIC, –1dBFS
SECOND HARMONIC, –10dBFS
THIRD HARMONIC, –1dBFS
THIRD HARMONIC, –10dBFS
–45
–50
–55
–60
–65
–70
–75
–80
SDO
3
2
ANALOG
OUTPUT
CH2 500mV
ꢀ
M1µs 1.25GS/s
A CH2 560mV
800ps/pt
0
1
2
3
4
5
6
7
CH3 1V
INPUT FREQUENCY (MHz)
Figure 20. Gain Step Response
Figure 17. Harmonic Distortion vs. Input Frequency
30
500
200k
180k
160k
140k
120k
100k
80k
450
400
350
300
250
200
150
100
50
25
20
15
10
5
34dB, 50ꢀ TERMINATED
IMPEDANCE = 200ꢀ
34dB, UNTERMINATED
60k
40k
IMPEDANCE = 200kꢀ
20k
0
0.1
0
100
0
0.01
1
FREQUENCY (MHz)
10
0.1
1
10
FREQUENCY (MHz)
Figure 21. Noise Figure vs. Frequency
Figure 18. RIN vs. Frequency
Rev. B | Page 12 of 27
Data Sheet
AD8285
10
9
8
7
6
5
4
3
2
1
0
12
11
10
9
8
7
6
5
4
3
2
1
0
–200
–60
–44
–28
–12
4
20
36
52 60
–150
–100
–50
0
50
100
150
200
OUTPUT OFFSET (LSB)
OUTPUT OFFSET (LSB)
Figure 22. Channel Offset Distribution (Gain = 16 dB)
Figure 23. Channel Offset Distribution (Gain = 34 dB)
Rev. B | Page 13 of 27
AD8285
Data Sheet
THEORY OF OPERATION
The AD8285 includes a multiplexer (mux) in front of the ADC
as a cost saving alternative to having an ADC for each channel.
The mux automatically switches between each active channel
after each ADC sample. The DSYNC output indicates when
Channel A data is at the ADC output and when data for each
active channel follows sequentially with each clock cycle.
RADAR RECEIVE PATH AFE
The primary application for the AD8285 is a high speed ramp,
frequency modulated, continuous wave radar (HSR-FMCW radar).
Figure 24 shows a simplified block diagram of an HSR-FMCW
radar system. The signal chain requires multiple channels, each
including a LNA, a PGA, an AAF, and an ADC with a 12-bit
parallel output. The AD8285 provides all of these key components
in a single 10 × 10 LFCSP package.
The effective sample rate for each channel is reduced by a factor
equal to the number of active channels. The ADC resolution of
12 bits with up to 72 MSPS sampling satisfies the requirements
for most HSR-FMCW approaches.
The performance of each component is designed to meet the
demands of an HSR-FMCW radar system. Some examples of
these performance metrics are the LNA noise, PGA gain range,
AAF cutoff characteristics, and ADC sample rate and resolution.
SDIO
SCLK
AD8285
SPI
INTERFACE
MUX
CONTROLLER
DSYNC
200ꢀ/
200kꢀ
INx+
INx–
PIPELINE
ADC
PARALLEL
3.3V CMOS
MUX
D11 TO D0
LNA
22dB
PGA
AAF
–6dB,
0dB,
6dB,
12dB
THIRD-ORDER
ELLIPTICAL FILTER
12-BIT
72MSPS
Figure 24. Simplified Block Diagram of a Single Channel
REF.
OSCILLATOR
PA
VCO
CHIRP RAMP
GENERATOR
LNA
LNA
PGA
PGA
AAF
AAF
12-BIT
ADC
DSP
MUX
LNA
PGA
AAF
AD8285
ANTENNA
Figure 25. Radar System Overview
Rev. B | Page 14 of 27
Data Sheet
AD8285
Antialiasing Filter (AAF)
CHANNEL OVERVIEW
The filter that the signal reaches prior to the ADC is used to
band limit the signal for antialiasing.
Each channel contains an LNA, a PGA, and an AAF in the
signal path. The LNA input impedance can be either 200 Ω or
200 kΩ. The PGA has selectable gains that result in channel
gains ranging from 16 dB to 34 dB. The AAF has a three-pole
elliptical response with a selectable cutoff frequency. The mux is
synchronized with the ADC and automatically selects the next
active channel after the ADC acquires a sample.
The antialiasing filter uses a combination of poles and zeros to
create a third order elliptical filter. An elliptical filter is used to
achieve a sharp roll-off after the cutoff frequency. The filter uses
on-chip tuning to trim the capacitors to set the desired cutoff
frequency. This tuning method reduces variations in the cutoff
frequency due to standard IC process tolerances of resistors and
capacitors. The default −3 dB low-pass filter cutoff is 1/3 or 1/4
the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8,
0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI.
The signal path is fully differential throughout to maximize signal
swing and reduce even-order distortion including the LNA, which
is designed to be driven from a differential signal source.
Low Noise Amplifier (LNA)
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming the
filter cutoff scaling or ADC sample rate. Occasional retuning
during an idle time is recommended to compensate for
temperature drift.
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contributions on the following PGA and AAF. The input
impedance can be either 200 Ω or 200 kΩ and is selected through
the SPI port or using the ZSEL pin.
The LNA supports differential output voltages as high as 4.0 V p-p
with positive and negative excursions of 1.0 V from a common-
mode voltage of 1.5 V. With the output saturation level fixed, the
channel gain sets the maximum input signal before saturation.
A cutoff range of 1.0 MHz to 12.0 MHz is possible. An example
follows:
Four channels selected: A, B, C, and AUX
ADC clock: 30 MHz
Per channel sample rate: 30/4 = 7.5 MSPS
Default tuned cutoff frequency = 7.5/4 = 1.88 MHz
Low value feedback resistors and the current driving capability of
the output stage allow the LNA to achieve a low input referred
noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB. The use
of a fully differential topology and negative feedback minimizes
second-order distortion. Differential signaling enables smaller
swings at each output, further reducing third order distortion.
Mux and Mux Controller
The mux is designed to scan through each active channel
automatically. The mux remains on each channel for one clock
cycle, then switches to the next active channel. The mux switching
is synchronized to the ADC sampling so that the mux switching
and channel settling time do not interfere with ADC sampling.
Recommendation
To achieve the best possible noise performance, it is important
to match the impedances seen by the positive and negative inputs.
Matching the impedances ensures that any common-mode noise is
rejected by the signal path.
As shown in Table 9, Address 0x0C (FLEX_MUX_ CONTROL),
Channel A is usually the first converted input; the only exception
occurs when Channel AUX is the sole input (see Figure 26 for
the timing). Channel AUX is always the last converted input.
Unselected codes place the respective channels (LNA, PGA,
and filter) in power-down mode unless Address 0x0C, Bit 6 is
set to 1. Figure 26 shows the timing of the clock input and
data/DSYNC outputs.
Rev. B | Page 15 of 27
AD8285
Data Sheet
N
N + 1
INAx
CLK–
CLK+
XXXX
OUTA
tPD
OUTB
OUTC
OUTD
OUTA
OUTB
OUTC
OUTD
D[11:0]
N – 1
N
DSYNC
NOTES
tDS
tDH
1. FOR THIS CONFIGURATION, ADDRESS 0x0C, BITS [3:0] IS SET TO 0110 (CHANNEL A, B, C, AND D ENABLED).
2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE.
3. THERE IS A SEVEN-CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS.
Figure 26. Data and DSYNC Timing
If a low jitter clock is available, another option is to ac-couple a
differential PECL or LVDS signal to the sample clock input pins
as shown in Figure 28 and Figure 29. The AD9515/AD9520-0
device family of clock drivers offers excellent jitter performance.
ADC
The AD8285 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock. The output staging block aligns the data,
corrects errors, and passes the data to the output buffers.
3.3V
AD951x/AD952x
50ꢀ*
FAMILY
VFAC3
OUT
0.1µF
0.1µF
0.1µF
CLK
PECL DRIVER
CLK
CLK+
ADC
AD8285
100ꢀ
0.1µF
CLOCK INPUT CONSIDERATIONS
CLK–
240ꢀ
240ꢀ
For optimum performance, clock the AD8285 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or by using capacitors. These pins are biased
internally and require no additional bias.
*50ꢀ RESISTOR IS OPTIONAL.
Figure 28. Differential PECL Sample Clock
3.3V
AD951x/AD952x
FAMILY
50ꢀ*
Figure 27 shows the preferred method for clocking the AD8285.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50MHz, is converted from single ended to
differential using an RF transformer. The back to back Schottky
diodes across the secondary transformer limit clock excursions
into the AD8285 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD8285, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
VFAC3
OUT
0.1µF
0.1µF
0.1µF
CLK
CLK+
ADC
AD8285
100ꢀ
LVDS DRIVER
CLK
0.1µF
CLK–
*50ꢀ RESISTOR IS OPTIONAL.
Figure 29. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
drive CLK+ directly from a CMOS gate and bypass the CLK−
pin to ground with a 0.1 μF capacitor in parallel with a 39 kΩ
resistor (see Figure 30). Although the CLK+ input circuit supply
is AVDD18, this input is designed to withstand input voltages of
up to 3.3 V, making the selection of the drive logic voltage very
flexible. The AD9515/AD9520-0 device family can provide 3.3 V
inputs (see Figure 31). In this case, 39 kΩ resistor is not needed.
3.3V
®
MINI-CIRCUITS
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
OUT
CLK+
100ꢀ
ADC
AD8285
50ꢀ
0.1µF
VFAC3
CLK–
SCHOTTKY
DIODES:
0.1µF
HSM2812
Figure 27. Transformer Coupled Differential Clock
Rev. B | Page 16 of 27
Data Sheet
AD8285
3.3V
In this equation, the rms aperture jitter represents the root
AD951x/AD952x
FAMILY
0.1µF
mean square of all jitter sources, including the clock input, analog
input signal, and ADC aperture jitter. Intermediate frequency
undersampling applications are particularly sensitive to jitter.
VFAC3
CLK
OUT
OPTIONAL
100ꢀ
0.1µF
1.8V
50ꢀ*
CMOS DRIVER
CLK+
ADC
AD8285
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD8285. Separate power
supplies for clock drivers from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. Low jitter,
crystal-controlled oscillators make the best clock sources, such
as the Valpey Fisher VFAC3 series. If the clock is generated from
another type of source (by gating, dividing, or other methods),
retime it by the original clock during the last step.
CLK
0.1µF
CLK–
0.1µF
39kꢀ
*50ꢀ RESISTOR IS OPTIONAL.
Figure 30. Single-Ended 1.8 V CMOS Sample Clock
3.3V
AD951x/AD952x
FAMILY
0.1µF
VFAC3
OUT
CLK
OPTIONAL
0.1µF
Refer to the AN-501 Application Note and the AN-756 Application
Note for more in-depth information about how jitter performance
relates to ADCs.
3.3V
50ꢀ*
100ꢀ
CLK+
CMOS DRIVER
ADC
AD8285
CLK
0.1µF
0.1µF
CLK–
SDIO PIN
The SDIO pin is required to operate the SPI. It has an internal
30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
*50ꢀ RESISTOR IS OPTIONAL.
Figure 31. Single-Ended 3.3 V CMOS Sample Clock
CLOCK DUTY CYCLE CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD8285 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. The DCS allows a wide
range of clock input duty cycles without affecting the performance
of the AD8285.
SCLK PIN
The SCLK pin is required to operate the SPI port interface. It
has an internal 30 kΩ pull-down resistor that pulls this pin low
and is both 1.8 V and 3.3 V tolerant.
CS PIN
CS
The
pin is required to operate the SPI port interface. It has
an internal 70 kΩ pull-up resistor that pulls this pin high and is
both 1.8 V and 3.3 V tolerant.
When the DCS is on, noise and distortion performance are nearly
flat for a wide range of duty cycles. However, some applications
may require the DCS function to be off. If so, keep in mind that the
dynamic range performance can be affected when operating in this
mode. See Table 9 for more information about using this feature.
RBIAS PIN
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using
anything other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, it is imperative
that at least a 1.0% tolerance on this resistor be used to achieve
consistent performance.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create
the nonsampling edge. As a result, any changes to the sampling
frequency require approximately eight clock cycles to allow the
DLL to acquire and lock to the new rate.
CLOCK JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]
Rev. B | Page 17 of 27
AD8285
Data Sheet
Use several decoupling capacitors on all supplies to cover both
high and low frequencies. Locate these capacitors close to the
point of entry at the PCB level and close to the device, with
minimal trace lengths.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD8285. This is gained up internally by a factor of 2, setting
VREF to 1.024 V, which results in a full-scale differential input
span of 2.0 V p-p for the ADC. VREF is set internally by default,
but the VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, this device does not support
ADC full-scale ranges below 2.0 V p-p.
When using the AD8285, a single PCB ground plane is sufficient.
With proper decoupling and smart partitioning of the analog,
digital, and clock sections of the PCB, optimum performance
can be achieved easily.
When applying the decoupling capacitors to the VREF pin, use
ceramic low ESR capacitors. These capacitors must be close to
the reference pin and on the same layer of the printed circuit board
(PCB) as the AD8285. The VREF pin must have both a 0.1 μF
capacitor and a 1 μF capacitor connected in parallel to the analog
ground. These capacitor values are recommended for the ADC
to properly settle and acquire the next valid sample.
EXPOSED PADDLE THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed paddle on the underside of the
device be connected to a quiet analog ground to achieve the
best electrical and thermal performance of the AD8285. Mate
an exposed continuous copper plane on the PCB to the AD8285
exposed paddle, Pin 0. The copper plane must have several vias
to achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. Fill or plug
these vias with nonconductive epoxy.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD8285, it is recommended
that two separate 1.8 V supplies and two separate 3.3 V supplies
be used: one supply each for analog 1.8 V (AVDD18x), digital
1.8 V (DVDD18x), analog 3.3 V (AVDD33x), and digital 3.3 V
(DVDD33x). If only one supply is available for both analog and
digital, for example, AVDD18x and DVDD18x, route the supply
to the AVDD18x first and then tap off and isolate it with a ferrite
bead or a filter choke preceded by decoupling capacitors for the
DVDD18x. The same is true for the analog and digital 3.3 V
supplies.
To maximize the coverage and adhesion between the device and
the PCB, partition the continuous copper pad by overlaying a
silkscreen or solder mask to divide the copper pad into several
uniform sections. Dividing the copper pad ensures several tie
points between the PCB and the EPAD during the reflow process.
Using one continuous plane with no partitions only guarantees
one tie point between the AD8285 and the PCB. For more detailed
information on packaging, and for more PCB layout examples,
see the AN-772 Application Note.
Rev. B | Page 18 of 27
Data Sheet
AD8285
SERIAL PERIPHERAL INTERFACE (SPI)
The AD8285 serial peripheral interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. The SPI offers
added flexibility and customization depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields, as documented in the Memory
Map section. Detailed operational information can be found in
the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
CS
Regardless of the mode, if
is taken high in the middle of any
byte transfer, the SPI state machine is reset, and the device waits
for a new instruction.
In addition to the operation modes, the SPI port can be
configured to operate in different modes. For applications that
do not require a control port, the
high. This places the remainder of the SPI pins in their secondary
mode, as is defined in the SDIO Pin section and the SCLK Pin
pin can also be tied low to enable 2-wire mode.
is tied low, SCLK and SDIO are the only pins required
for communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the line.
CS
line can be tied and held
CS
section. The
CS
When
Three pins define the serial peripheral interface (SPI): SCLK,
CS
SDIO, and . The SCLK (serial clock) pin is used to synchronize
the read and write data presented to the device. The SDIO (serial
data input/output) pin is a dual purpose pin that allows data to
be sent to and read from the internal memory map registers of
CS
When operating in 2-wire mode, it is recommended to use a 1-,
2-, or 3-byte transfer exclusively. Without an active
streaming mode can be entered but not exited.
CS
line,
CS
the device. The
(chip select bar) pin is an active low control
that enables or disables the read and write cycles (see Table 7).
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Table 7. Serial Port Pins
Pin
Function
SCLK
Serial clock. The serial shift clock input. SCLK is used
to synchronize serial interface reads and writes.
SDIO
Serial data input/output. A dual-purpose pin. The
typical role for this pin is as an input or output,
depending on the instruction sent and the relative
position in the timing frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode is
the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
CS
Chip select bar (active low). This control gates the
read and write cycles.
CS
The falling edge of the
in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its
definitions can be found in Figure 32 and Table 8.
HARDWARE INTERFACE
The pins described in Table 7 constitute the physical interface
between the programming device of the user and the serial port
CS
of the AD8285. The SCLK and
pins function as inputs when
CS
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
In normal operation,
signals to the device that SPI
CS
commands are to be received and processed. When is brought
low, the device processes SCLK and SDIO to process instructions.
This interface is flexible enough to be controlled by either serial
PROMs or PIC microcontrollers. This flexibility provides the user
with an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
CS
Normally,
complete. However, if connected to a slow device,
brought high between bytes, allowing older microcontrollers
CS
remains low until the communication cycle is
CS
can be
enough time to transfer data into shift registers.
can be
If the user chooses not to use the SPI interface, these pins serve
a dual function and are associated with secondary functions
stalled when transferring one, two, or three bytes of data. When
W0 and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until
taken high to end the communication cycle. This allows
complete memory transfers without having to provide
additional instructions.
CS
when the
is strapped to AVDD33 during device power-up.
CS
is
See the SDIO Pin section and SCLK Pin section for details on
which pin strappable functions are supported on the SPI pins.
Rev. B | Page 19 of 27
AD8285
Data Sheet
tDS
tHI
tCLK
tH
tS
tDH
tLO
CS
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 32. Serial Timing Details
Table 8. Serial Timing Definitions
Parameter
Minimum Timing (ns)
Description
tDS
5
2
40
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
tDH
tCLK
tS
Setup time between CS and SCLK
tH
2
Hold time between CS and SCLK
tHI
tLO
tEN_SDIO
16
16
10
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 32)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 32)
Rev. B | Page 20 of 27
Data Sheet
AD8285
MEMORY MAP
Note that all registers except Register 0x00, Register 0x04,
READING THE MEMORY MAP TABLE
Register 0x05, and Register 0xFF are buffered with a master
slave latch and require writing to the transfer bit. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: the chip
configuration registers map (Address 0x00 and Address 0x01), the
device index and transfer registers map (Address 0x05 and
Address 0xFF), and the ADC channel functions registers map
(Address 0x04 and Address 0x08 to Address 0x2C).
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
The leftmost column of the memory map indicates the address
(hex) number, and the default value is shown in the second
rightmost column. The Bit 7 (MSB) column is the start of the
default hexadecimal value given. For example, Address 0x09,
the GLOBAL_CLOCK register, has a default value of 0x01,
meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This
setting is the default for the duty cycle stabilizer in the on condition.
By writing a 0 to Bit 0 of this address followed by a 0x01 to the
SW transfer bit in Register 0xFF, the duty cycle stabilizer turns
off. It is important to follow each writing sequence with a write
to the SW transfer bit to update the SPI registers.
RESERVED LOCATIONS
Do not write to undefined memory locations except when writing
the default values suggested in this data sheet. Consider addresses
marked as 0 as reserved, and these addresses must have a 0 written
into their registers during power-up.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with default
values. These values are indicated in Table 9, where an X refers
to an undefined feature.
Rev. B | Page 21 of 27
AD8285
Data Sheet
Table 9. Memory Map Register
Default
Addr.
Bit 7
Bit 0
Default Notes/
(Hex) Register Name
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Value
Comments
Chip Configuration Registers
0x00
CHIP_PORT_CONFIG
0
LSB first,
1 = on,
0 = off,
Soft
reset,
1 = on,
0 = off
(default)
1
1
Soft
reset,
1 = on,
0 = off
(default)
LSB first,
1 = on,
0 = off
0
0x18
Mirror the
nibbles so
that LSB- or
MSB-first
mode is set
correct
(default)
(default)
regardless of
shift mode.
0x01
CHIP_ID
Chip ID, Bits[7:0]
(AD8285 = 0xA2, default)
Read
only
The default
value is the
chip ID
assigned to
the AD8285.
This is a read-
only register.
Device Index and Transfer Registers
0x05
0xFF
DEVICE_INDEX
X
X
X
X
X
X
Data
Data
Data
Channel
B,
1 = on
(default), (default),
Data
Channel
A,
0x0F
0x00
Bits are set to
determine
which on-
chip device
receives the
next write
Chan-
nel D,
1 = on
(def-
ault),
0 = off
Chan-
nel C,
1 = on
(def-
ault),
0 = off
1 = on
0 = off
0 = off
command.
DEVICE_UPDATE
X
X
X
X
X
SW
Synchronously
transfers data
from the
master shift
register to the
slave.
transfer,
1 = on,
0 = off
(default)
Channel Functions Registers
0x04
0x08
FLEX_RES
X
X
X
X
X
X
X
X
X
X
Reserved Reserved 0x0F
Reserved. Bits
must be set
to 0x00.
GLOBAL_MODES
X
X
Internal power-
down mode,
00 = chip run
(default),
0x00
Determines
the power-
down mode
(global).
01 = full power-
down,
11 = reset
0x09
0x0C
GLOBAL_CLOCK
X
X
X
X
X
X
X
X
X
X
Duty
cycle
stabilizer,
1 = on
(default),
0 = off
0x01
0x00
Turns the
internal duty
cycle stabilizer
on and off
(global).
FLEX_MUX_CONTROL
Power-
down of
unused
channels,
0 = PD
(power-
down;
Mux input active channels,
0000 = A,
Selects the
mux input
channels to
use and
0001 = AUX,
0010 = A and B,
0011 = A and AUX,
0100 = A, B, and C,
0101 = A, B, and AUX,
0110 = A, B, C, and D,
0111 = A, B, C, and AUX
specifies
whether to
power down
unused
default),
1 =
channels.
power-on
Rev. B | Page 22 of 27
Data Sheet
AD8285
Default
Addr.
Bit 7
Bit 0
Default Notes/
(Hex) Register Name
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Value
Comments
0x0D
FLEX_TEST_IO
User test mode,
00 = off (default),
01 = on, single
alternate,
10 = on, single once,
11 = on, alternate
once
Reset
PN long
gen,
1 = on,
0 = off
(default) 0 = off
(default)
Reset
PN
short
gen,
Output test mode—see Table 10,
0000 = off (default,)
0x00
When this
register is set,
the test data
is placed on
the output
pins in place
of normal
data (local,
except for PN
sequence).
0001 = midscale short,
0010 = +full-scale short,
0011 = −full-scale short,
0100 = checkerboard output,
0101 = PN sequence long,
0110 = PN sequence short,
0111 = one-/zero-word toggle,
1000 = user input,
1 = on,
1001 = 1-bit/0-bit toggle,
1010 = 1× sync,
1011 = one bit high,
1100 = mixed bit frequency (format
determined by the OUTPUT_MODE register)
0x0F
FLEX_CHANNEL_INPU
T
Filter cutoff frequency control,
X
X
X
X
0x30
Low-pass
filter cutoff
(global).
0000 = 1.3 × 1/4 × fSAMPLECH
,
,
,
0001 = 1.2 × 1/4 × fSAMPLECH
0010 = 1.1 × 1/4 × fSAMPLECH
fSAMPLECH
=
0011 = 1.0 × 1/4 × fSAMPLECH (default),
ADC sample
rate/ number
of active
channels.
Note that the
absolute
0100 = 0.9 × 1/4 × fSAMPLECH
0101 = 0.8 × 1/4 × fSAMPLECH
0110 = 0.7 × 1/4 × fSAMPLECH
0111 = not applicable,
,
,
,
1000 = 1.3 × 1/3 × fSAMPLECH
1001 = 1.2 × 1/3 × fSAMPLECH
1010 = 1.1 × 1/3 × fSAMPLECH
1011 = 1.0 × 1/3 × fSAMPLECH
1100 = 0.9 × 1/3 × fSAMPLECH
1101 = 0.8 × 1/3 × fSAMPLECH
1110 = 0.7 × 1/3 × fSAMPLECH
1111 = not applicable
,
,
,
,
,
,
,
range is
limited to
1.0 MHz to
12.0 MHz.
0x10
FLEX_OFFSET
X
X
6-bit LNA offset adjustment,
00 0000 for LNA bias high,
0x20
LNA force
offset
01 1111 for LNA mid to high,
10 0000 for LNA mid to low (default),
10 0001 for LNA bias low
correction
(local).
0x11
0x12
FLEX_GAIN_1
X
X
X
X
X
X
X
X
X
X
010 = 16 dB (default),
011 = 22 dB,
0x02
0x09
Total LNA +
PGA gain
adjustment
(local)
100 = 28 dB,
101 = 34 dB
FLEX_BIAS_CURRENT
X
LNA bias,
00 = high,
LNA bias
current
01 = mid to high
(default),
adjustment
(global).
10 = mid to low,
11 = low
0x14
0x15
FLEX_OUTPUT_MODE
X
X
X
X
X
X
X
X
1 =
0 = offset binary
0x00
0x0F
Configures the
outputs and
the format of
the data.
output
invert
(local)
(default),
1 = twos
complement
(global)
FLEX_OUTPUT_
ADJUST
0 =
enable
Data
Bits[11:0],
1 =
disable
Data
Typical output rise
time and fall time,
respectively
00 = 2.6 ns, 3.4 ns
01 = 1.1 ns, 1.6 ns
10 = 0.7 ns, 0.9 ns
11 = 0.7 ns, 0.7 ns
(default)
Typical output drive
strength
Used to adjust
output rise
and fall times
and select
output drive
strength,
limiting the
noise added to
the channels
by output
00 = 45 mA
01 = 30 mA
10 = 60 mA
11 = 60 mA (default)
Bits[11:0]
switching.
Rev. B | Page 23 of 27
AD8285
Data Sheet
Default
Addr.
Bit 7
Bit 0
Default Notes/
(Hex) Register Name
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Value
Comments
0x18
FLEX_VREF
X
0 =
X
X
X
X
00 = 0.625 V,
01 = 0.750 V,
10 = 0.875 V,
11 = 1.024 V
(default)
0x03
Select internal
reference
(recom-
mended
default) or
external
internal
reference,
1 =
external
reference
reference
(global); adjust
internal
reference.
0x19
0x1A
0x1B
0x1C
0x2B
FLEX_USER_PATT1_
LSB
B7
B15
B7
B6
B5
B4
B3
B2
B1
B9
B1
B9
X
B0
B8
B0
B8
X
0x00
0x00
0x00
0x00
0x00
User-defined
Pattern 1, LSB
FLEX_USER_PATT1_
MSB
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
User-defined
Pattern 1, MSB
FLEX_USER_PATT2_
LSB
User-defined
Pattern 2, LSB
FLEX_USER_PATT2_
MSB
B15
X
B14
B13
X
B12
X
B11
X
B10
X
User-defined
Pattern 2, MSB
FLEX_FILTER
Enable
Refer to the
Antialiasing
Filter (AAF)
section.
automatic
low-pass
tuning,
1 = on
(self-
clearing)
0x2C
CH_IN_IMP
X
X
X
X
X
X
X
0 =
200 Ω
(default),
1 =
0x00
Input
impedance
adjustment
(global).
200 kΩ
Table 10. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Subject to Data
Format Select
Pattern Name
Digital Output Word 1
Not applicable
Digital Output Word 2
Not applicable
Same
Same
Same
0101 0101 0101
Not applicable
Not applicable
0000 0000 0000
Register 0x1B to Register 0x1C
Not applicable
Not applicable
Not applicable
Not applicable
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Off (default)
Midscale short
Not applicable
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
Not applicable
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
+Full-scale short
−Full-scale short
Checkerboard output
PN sequence long
PN sequence short
One-/zero-word toggle 1111 1111 1111
User input
1-bit/0-bit toggle
1× sync
One bit high
Mixed bit frequency
Not applicable
Register 0x19 to Register 0x1A
1010 1010 1010
0000 0011 1111
1000 0000 0000
1010 0011 0011
1100
Rev. B | Page 24 of 27
Data Sheet
AD8285
APPLICATION DIAGRAMS
The typical application diagrams for the AD8285 are shown in Figure 33 and Figure 34. As discussed in the Channel Overview section,
the maximum signal swing and the minimum third-order distortion can be achieved when the AD8285 is driven with a fully differential
source. The typical connections for this configuration are shown in Figure 33.
AVDD33REF
0.1µF
DVDD33SPI
0.1µF
DVDD18
0.1µF
AVDD18
0.1µF
3.3V
3.3V
1.8V
1.8V
AVDD33A
0.1µF
DVDD33CLK
0.1µF
AVDD18
0.1µF
DVDD18CLK
0.1µF
AVDD33B
0.1µF
DVDD33DRV
0.1µF
AVDD18ADC
0.1µF
AVDD33C
0.1µF
DVDD33DRV
0.1µF
AVDD33D
0.1µF
AVDD33
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
NC
NC
NC
TEST4
DVDD18CLK
CLK+
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
DSYNC
PDWN
CLK+
CLK–
SCLK
CLK–
10kꢀ
SDIO
DVDD33CLK
AVDD33REF
VREF
CS
AUX
MUXA
ZSEL
0.1µF
0.1µF
0.1µF
10kꢀ
AD8285
TOP VIEW
(Not to Scale)
RBIAS
BAND
APOUT
ANOUT
TEST3
1%
INADC+
AVDD18ADC
AVDD18
INADC+
INADC–
NC
INA–
0.1µF
0.1µF
INA+
NC
INADC–
0.1µF
INA+
INB–
0.1µF
IND+
0.1µF
INB+
0.1µF
INC–
0.1µF
INC+
0.1µF
IND–
0.1µF
NOTES
1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES MUST BE PLACED CLOSE TO THE DEVICE.
Figure 33. Differential Inputs Application Diagram
Rev. B | Page 25 of 27
AD8285
Data Sheet
The AD8285 can also be driven with a single-ended source, as shown in Figure 34. In this configuration, the negative analog input of each
channel is grounded through a resistor and a 0.1 μF capacitor. For optimal operation, this resistor must match the output impedance of
the input driver.
AVDD33REF
0.1µF
DVDD33SPI
0.1µF
DVDD18
0.1µF
AVDD18
0.1µF
3.3V
3.3V
1.8V
1.8V
AVDD33A
0.1µF
DVDD33CLK
0.1µF
AVDD18
0.1µF
DVDD18CLK
0.1µF
AVDD33B
0.1µF
DVDD33DRV
0.1µF
AVDD18ADC
0.1µF
AVDD33C
0.1µF
DVDD33DRV
0.1µF
AVDD33D
0.1µF
AVDD33
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
NC
NC
NC
TEST4
DVDD18CLK
CLK+
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
DSYNC
PDWN
CLK+
CLK–
SCLK
CLK–
10kꢀ
SDIO
CS
AUX
MUXA
ZSEL
DVDD33CLK
AVDD33REF
VREF
AD8285
TOP VIEW
(Not to Scale)
0.1µF
0.1µF
0.1µF
10kꢀ
RBIAS
BAND
APOUT
ANOUT
TEST3
1%
INADC+
AVDD18ADC
AVDD18
INADC+
INADC–
NC
INA+
NC
R
0.1µF
INADC–
0.1µF
INA
0.1µF
IND
0.1µF
INB
INC
0.1µF
0.1µF
NOTES
1. RESISTOR R (INx– INPUTS) MUST MATCH THE OUTPUT IMPEDANCE OF THE INPUT DRIVER.
2. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE DEVICE.
Figure 34. Single-Ended Inputs Application Diagram
Rev. B | Page 26 of 27
Data Sheet
AD8285
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.30
0.23
0.18
0.60
0.42
0.24
PIN 1
INDICATOR
55
54
72
1
PIN 1
INDICATOR
9.85
0.50
BSC
9.75 SQ
9.65
8.60
8.50 SQ
8.40
EXPOSED
PAD
0.50
0.40
0.30
18
19
37
36
0.25 MIN
TOP VIEW
BOTTOM VIEW
8.50 REF
0.70
0.65
0.60
12° MAX
0.90
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.01 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-72-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
AD8285WBCPZ-RL
AD8285WBCPZ
AD8285CP-EBZ
72-Lead LFCSP_VQ, 13”Tape and Reel
72-Lead LFCSP_VQ
Evaluation Board
CP-72-5
CP-72-5
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8285WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective owners.
D11952-0-9/15(B)
Rev. B | Page 27 of 27
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