AD828ARZ-REEL7 [ADI]
Dual, Low Power Video Op Amp;
| 型号： | AD828ARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Dual, Low Power Video Op Amp 放大器 光电二极管 |
| 文件： | 总13页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, Low Power
Video Op Amp
a
AD828
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Excellent Video Performance
Differential Gain and Phase Error of 0.01% and 0.05ꢀ
High Speed
130 MHz 3 dB Bandwidth (G = +2)
450 V/ꢁs Slew Rate
1
2
3
4
OUT1
–IN1
+IN1
V–
8
7
6
5
V+
OUT2
–IN2
+IN2
80 ns Settling Time to 0.01%
Low Power
15 mA Max Power Supply Current
High Output Drive Capability
50 mA Minimum Output Current per Amplifier
Ideal for Driving Back Terminated Cables
Flexible Power Supply
AD828
Specified for +5 V, ꢂ5 V, and ꢂ15 V Operation
ꢂ3.2 V Min Output Swing into a 150 ꢃ Load
(VS = ꢂ5 V)
Excellent DC Performance
2.0 mV Input Offset Voltage
Available in 8-Lead SOIC and 8-Lead Plastic Mini-DIP
GENERAL DESCRIPTION
The AD828 is fully specified for operation with a single 5 V
power supply and with dual supplies from 5 V to 15 V. This
power supply flexibility, coupled with a very low supply current
of 15 mA and excellent ac characteristics under all power supply
conditions, make the AD828 the ideal choice for many demand-
ing yet power-sensitive applications.
The AD828 is a low cost, dual video op amp optimized for use
in video applications that require gains of +2 or greater and
high output drive capability, such as cable driving. Due to its
low power and single-supply functionality, along with excellent
differential gain and phase errors, the AD828 is ideal for power-
sensitive applications such as video cameras and professional
video equipment.
The AD828 is a voltage feedback op amp that excels as a gain
stage (gains > +2) or active filter in high speed and video systems
and achieves a settling time of 45 ns to 0.1%, with a low input
offset voltage of 2 mV max.
With video specs like 0.1 dB flatness to 40 MHz and low
differential gain and phase errors of 0.01% and 0.05°, along
with 50 mA of output current per amplifier, the AD828 is an
excellent choice for any video application. The 130 MHz gain
bandwidth and 450 V/µs slew rate make the AD828 useful in
many high speed applications, including video monitors, CATV,
color copiers, image scanners, and fax machines.
The AD828 is available in low cost, small 8-lead plastic mini-DIP
and SOIC packages.
0.03
+V
0.1ꢁF
0.02
DIFF GAIN
R
75ꢃ
BT
75ꢃ
V
IN
0.01
0.07
1/2
R
75ꢃ
T
AD828
R
75ꢃ
T
0.1ꢁF
1kꢃ
0.06
DIFF PHASE
–V
1kꢃ
0.05
0.04
Figure 1. Video Line Driver
5
10
15
SUPPLY VOLTAGE – ꢂV
Figure 2. Differential Phase vs. Supply Voltage
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD828* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Product Selection Guide
• High Speed Amplifiers Selection Table
Tutorials
EVALUATION KITS
• Universal Evaluation Board for Dual High Speed
• MT-032: Ideal Voltage Feedback (VFB) Op Amp
• MT-033: Voltage Feedback Op Amp Gain and Bandwidth
• MT-047: Op Amp Noise
Operational Amplifiers
DOCUMENTATION
Application Notes
• MT-048: Op Amp Noise Relationships: 1/f Noise, RMS
Noise, and Equivalent Noise Bandwidth
• AN-356: User's Guide to Applying and Measuring
Operational Amplifier Specifications
• MT-049: Op Amp Total Output Noise Calculations for
Single-Pole System
• AN-358: Noise and Operational Amplifier Circuits
• MT-050: Op Amp Total Output Noise Calculations for
• AN-402: Replacing Output Clamping Op Amps with Input
Second-Order System
Clamping Amps
• MT-052: Op Amp Noise Figure: Don't Be Misled
• AN-417: Fast Rail-to-Rail Operational Amplifiers Ease
Design Constraints in Low Voltage High Speed Systems
• MT-053: Op Amp Distortion: HD, THD, THD + N, IMD,
SFDR, MTPR
• AN-581: Biasing and Decoupling Op Amps in Single
Supply Applications
• MT-056: High Speed Voltage Feedback Op Amps
• MT-058: Effects of Feedback Capacitance on VFB and CFB
Op Amps
• AN-649: Using the Analog Devices Active Filter Design
Tool
• MT-060: Choosing Between Voltage Feedback and
Current Feedback Op Amps
Data Sheet
• AD828: Dual, Low Power Video Op Amp Data Sheet
User Guides
DESIGN RESOURCES
• AD828 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• UG-128: Universal Evaluation Board for Dual High Speed
Op Amps in SOIC Packages
TOOLS AND SIMULATIONS
• Analog Filter Wizard
• Analog Photodiode Wizard
• Power Dissipation vs Die Temp
• VRMS/dBm/dBu/dBV calculators
• AD828 SPICE Macro-Model
DISCUSSIONS
View all AD828 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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(@ TA = 25ꢀC, unless otherwise noted.)
AD828–SPECIFICATIONS
Parameter
Conditions
Gain = +2
VS
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
5 V
60
100
30
35
60
20
30
30
10
15
30
10
85
130
45
55
90
35
43
40
18
25
50
19
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
15 V
0, +5 V
5 V
15 V
0, +5 V
5 V
15 V
0, +5 V
5 V
15 V
0, +5 V
Gain = –1
Gain = +2
Bandwidth for 0.1 dB Flatness
C
C = 1 pF
Gain = –1
C = 1 pF
C
Full Power Bandwidth
*
VOUT = 5 V p-p
RLOAD = 500 Ω
5 V
22.3
MHz
V
OUT = 20 V p-p
R
LOAD = 1 kΩ
15 V
5 V
15 V
0, +5 V
5 V
7.2
350
450
250
45
MHz
V/µs
V/µs
V/µs
ns
Slew Rate
RLOAD = 1 kΩ
Gain = –1
300
400
200
Settling Time to 0.1%
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
15 V
5 V
15 V
45
80
80
ns
ns
ns
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error
(RL = 150 Ω)
FC = 1 MHz
f = 10 kHz
f = 10 kHz
NTSC
15 V
5 V, 15 V
5 V, 15 V
15 V
5 V
0, +5 V
15 V
–78
10
1.5
0.01
0.02
0.08
0.05
0.07
0.1
dB
nV/√Hz
pA/√Hz
%
%
%
Degrees
Degrees
Degrees
0.02
0.03
Gain = +2
Differential Phase Error
(RL = 150 Ω)
NTSC
Gain = +2
0.09
0.1
5 V
0, +5 V
DC PERFORMANCE
Input Offset Voltage
5 V, 15 V
5 V, 15 V
5 V, 15 V
5 V
0.5
2
3
mV
mV
µV/°C
µA
T
MIN to TMAX
Offset Drift
Input Bias Current
10
3.3
6.6
10
4.4
300
500
TMIN
TMAX
µA
µA
nA
nA
nA/°C
Input Offset Current
25
0.3
5
T
MIN to TMAX
Offset Current Drift
Open-Loop Gain
VOUT
= 2.5 V
R
LOAD = 500 Ω
TMIN to TMAX
LOAD = 150 Ω
VOUT 10 V
RLOAD = 1 kΩ
MIN to TMAX
VOUT 7.5 V
RLOAD = 150 Ω (50 mA Output)
3
2
2
V/mV
V/mV
V/mV
R
4
=
15 V
15 V
5.5
2.5
9
V/mV
V/mV
T
=
3
5
V/mV
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
300
1.5
kΩ
pF
V
V
V
V
V
V
Input Common-Mode Voltage Range
5 V
+3.8
–2.7
+13
–12
+3.8
+1.2
82
+4.3
–3.4
+14.3
–13.4
+4.3
+0.9
100
15 V
0, +5 V
Common-Mode Rejection Ratio
V
CM = +2.5 V, TMIN to TMAX
VCM 12 V
TMIN to TMAX
5 V
15 V
15 V
dB
dB
dB
=
86
84
120
100
–2–
REV. C
AD828
Parameter
Conditions
LOAD = 500 Ω
VS
5 V
5 V
15 V
15 V
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
3.3
3.2
13.3
12.8
1.5
3.5
50
3.8
3.6
13.7
13.4
V
V
V
V
RLOAD = 150 Ω
R
R
LOAD = 1 kΩ
LOAD = 500 Ω
R
LOAD = 500 Ω
0, +5 V
15 V
5 V
0, +5 V
15 V
V
mA
mA
mA
mA
Ω
Output Current
40
30
Short Circuit Current
Output Resistance
90
8
Open-Loop
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
Skew Rate Match
f = 5 MHz
G = +1, f = 40 MHz
G = –1
15 V
15 V
15 V
–80
0.2
10
dB
dB
V/µs
DC
Input Offset Voltage Match
Input Bias Current Match
Open-Loop Gain Match
Common-Mode Rejection Ratio Match VCM
Power Supply Rejection Ratio Match
T
T
MIN to TMAX
MIN to TMAX
5 V, 15 V
5 V, 15 V
15 V
0.5
2
0.8
0.15
mV
µA
0.06
0.01
100
100
VO = 10 V, RL = 1 kΩ, TMIN to TMAX
mV/V
dB
=
12 V, TMIN to TMAX
15 V
80
80
5 V to 15 V, TMIN to TMAX
dB
POWER SUPPLY
Operating Range
Dual Supply
Single Supply
2.5
+5
18
+36
15
15
15
V
V
mA
mA
mA
dB
Quiescent Current
5 V
5 V
5 V
14.0
14.0
T
T
MIN to TMAX
MIN to TMAX
Power Supply Rejection Ratio
VS = 5 V to 15 V, TMIN to TMAX
80
90
*Full power bandwidth = slew rate/2 π VPEAK
Specifications subject to change without notice.
.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
ABSOLUTE MAXIMUM RATINGS1
AD828AN
AD828AR
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead Plastic SOIC SO-8
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2
AD828AR-REEL7 –40°C to +85°C 7" Tape and Reel
AD828AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
SO-8
Plastic DIP (N) . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Output Short Circuit Duration . . . . . . . . See Derating Curves
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
2.0
T
= 150ꢀC
J
8-LEAD MINI-DIP PACKAGE
1.5
1.0
0.5
0
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Specification is for device in free air:
8-LEAD SOIC PACKAGE
8-Lead Plastic DIP Package: θJA = 100°C/W
8-Lead SOIC Package: θJA = 155°C/W
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢀC
Figure 3. Maximum Power Dissipation vs.
Temperature for Different Package Types
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD828 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD828
—Typical Performance Characteristics
7.7
20
7.2
6.7
15
+V
CM
+85ꢀC
–40ꢀC
+25ꢀC
10
–V
CM
6.2
5.7
5
0
0
5
10
SUPPLY VOLTAGE – ꢂV
15
20
0
5
10
SUPPLY VOLTAGE – ꢂV
15
20
TPC 1. Common-Mode Voltage Range vs. Supply
Voltage
TPC 4. Quiescent Supply Current per Amp vs. Supply
Voltage for Various Temperatures
20
15
500
450
400
R
= 500ꢃ
L
10
5
R
= 150ꢃ
L
350
300
0
0
5
10
15
20
0
5
10
SUPPLY VOLTAGE – ꢂV
15
20
SUPPLY VOLTAGE – ꢂV
TPC 2. Output Voltage Swing vs. Supply Voltage
TPC 5. Slew Rate vs. Supply Voltage
30
25
100
V
= ꢂ15V
s
10
1
20
15
10
5
0.1
0.01
V
= ꢂ5V
s
0
10
100
1k
10k
1k
10k
100k
1M
100M
10M
LOAD RESISTANCE – ꢃ
FREQUENCY – Hz
TPC 6. Closed-Loop Output Impedance vs. Frequency
TPC 3. Output Voltage Swing vs. Load Resistance
–4–
REV. C
AD828
100
7
6
5
4
3
2
1
100
80
60
40
20
0
PHASE ꢂ5V OR
ꢂ15V SUPPLIES
80
60
ꢂ15V SUPPLIES
40
20
ꢂ5V SUPPLIES
0
R
= 1kꢃ
L
–20
1k
–60 –40 –20
0
20
40
60
80
100 120 140
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
TEMPERATURE –
ꢀC
TPC 7. Input Bias Current vs. Temperature
TPC 10. Open-Loop Gain and Phase Margin vs.
Frequency
9
130
ꢂ15V
8
110
90
70
50
30
SOURCE CURRENT
7
ꢂ5V
6
SINK CURRENT
5
4
3
100
1k
10k
–60 –40 –20
0
20
40
60
80
100 120 140
LOAD RESISTANCE – ꢃ
TEMPERATURE – ꢀC
TPC 8. Short Circuit Current vs. Temperature
TPC 11. Open-Loop Gain vs. Load Resistance
80
100
90
80
80
70
70
60
+SUPPLY
PHASE MARGIN
70
60
50
60
–SUPPLY
40
GAIN BANDWIDTH
50
50
40
30
20
10
40
100
1k
10k
100k
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY – Hz
TEMPERATURE – ꢀC
TPC 9. –3 dB Bandwidth and Phase Margin vs.
Temperature, Gain = +2
TPC 12. Power Supply Rejection vs. Frequency
REV. C
–5–
AD828
–40
–50
–60
–70
–80
–90
–100
140
V
= 1V p-p
IN
GAIN = +2
120
100
80
2ND HARMONIC
3RD HARMONIC
60
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 16. Harmonic Distortion vs. Frequency
TPC 13. Common-Mode Rejection vs. Frequency
50
40
30
20
10
0
30
R
= 1kꢃ
L
20
10
0
R
= 150ꢃ
L
0
10
100
1k
10k
100k
1M
10M
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 14. Large Signal Frequency Response
TPC 17. Input Voltage Noise Spectral Density vs.
Frequency
10
650
550
450
350
250
8
6
4
1%
1%
0.1%
0.01%
0.01%
2
0
ꢄ2
ꢄ4
ꢄ6
0.1%
ꢄ8
ꢄ10
0
20
40
60
80
100
120
140
160
–60 –40 –20
0
20
40
60
80
100 120 140
SETTLING TIME ꢄ ns
TEMPERATURE – ꢀC
TPC 18. Slew Rate vs. Temperature
TPC 15. Output Swing and Error vs. Settling Time
–6–
REV. C
AD828
10
8
5
4
1pF
1kꢃ
0.1dB
1pF
0.1dB
FLATNESS
ꢂ15V 50MHz
V
FLATNESS
ꢂ15V 40MHz
S
V
S
1kꢃ
6
4
3
2
1kꢃ
1kꢃ
AD828
150ꢃ
V
43MHz
18MHz
ꢂ5V
+5V
OUT
V
25MHz
19MHz
ꢂ5V
+5V
OUT
V
IN
AD828
150ꢃ
V
IN
V
= ꢂ15V
2
0
1
0
V = ꢂ15V
S
S
–2
–1
V
= +5V
S
–4
–6
–2
–3
–4
–5
V
S
= ꢂ5V
S
V
= ꢂ5V
S
V
= +5V
–8
–10
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 19. Closed-Loop Gain vs. Frequency
TPC 22. Closed-Loop Gain vs. Frequency, G = –1
0.03
0.02
1.0
0.8
0.6
0.4
0.2
DIFF GAIN
0.01
0.07
V
= ꢂ15V
S
0
–0.2
–0.4
–0.6
–0.8
–1.0
0.06
0.05
0.04
V
= ꢂ5V
S
DIFF PHASE
V
= ꢅ5V
S
5
10
15
100k
1M
10M
100M
SUPPLY VOLTAGE – ꢂV
FREQUENCY – Hz
TPC 23. Gain Flatness Matching vs. Supply, G = +2
TPC 20. Differential Gain and Phase vs. Supply Voltage
–30
–40
–50
–60
ꢅ5V
0.1ꢁF
V
OUT
1ꢁF
5
6
3
2
8
1/2
AD828
1/2
1
7
V
IN
AD828
–70
–80
R
= 150ꢃ
L
4
0.1ꢁF
1ꢁF
R
R
L
L
R
= 1kꢃ
–90
–100
–110
L
ꢄ5V
USE GROUND PLANE
10k
100k
1M
FREQUENCY – Hz
10M
100M
PINOUT SHOWN IS FOR MINI-DIP PACKAGE
TPC 21. Crosstalk vs. Frequency
TPC 24. Crosstalk Test Circuit
REV. C
–7–
AD828
C
F
5V
50ns
1kꢃ
100
90
+V
S
3.3ꢁF
0.01ꢁF
HP PULSE (LS)
OR FUNCTION (SS)
GENERATOR
V
1kꢃ
50ꢃ
IN
8
2
3
V
OUT
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
1/2
1
AD828
10
0.01ꢁF
4
0%
R
L
5V
3.3ꢁF
–V
S
TPC 25. Inverting Amplifier Connection
TPC 28. Inverter Large Signal Pulse Response ꢂ15 VS,
CF = 1 pF, RL = 1 kΩ
10ns
200mV
50ns
2V
100
90
100
90
10
10
0%
0%
200mV
2V
TPC 29. Inverter Small Signal Pulse Response ꢂ15 VS,
CF = 1 pF, RL = 1500 Ω
TPC 26. Inverter Large Signal Pulse Response ꢂ5 VS,
CF = 1 pF, RL = 1 kΩ
10ns
200mV
10ns
200mV
100
90
100
90
10
10
0%
0%
200mV
200mV
TPC 27. Inverter Small Signal Pulse Response ꢂ5 VS,
CF = 1 pF, RL = 150 Ω
TPC 30. Inverter Small Signal Pulse Response ꢂ5 VS,
CF = 0 pF, RL = 150 Ω
–8–
REV. C
AD828
C
F
50ns
5V
1kꢃ
1kꢃ
100
90
+V
S
3.3ꢁF
0.01ꢁF
8
2
3
V
OUT
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
1/2
R
100ꢃ
1
IN
HP PULSE (LS)
OR FUNCTION (SS)
GENERATOR
V
AD828
IN
10
0.01ꢁF
3.3ꢁF
4
0%
50ꢃ
R
L
5V
–V
S
TPC 31. Noninverting Amplifier Connection
TPC 34. Noninverting Large Signal Pulse Response
ꢂ15 VS, CF = 1 pF, RL = 1 kΩ
50ns
1V
100mV
10ns
100
90
100
90
10
10
0%
0%
2V
200mV
TPC 32. Noninverting Large Signal Pulse Response
ꢂ5 VS, CF = 1 pF, RL = 1 kΩ
TPC 35. Noninverting Small Signal Pulse Response
ꢂ15 VS, CF = 1 pF, RL = 150 Ω
100mV
10ns
100mV
10ns
100
90
100
90
10
10
0%
0%
200mV
200mV
TPC 33. Noninverting Small Signal Pulse Response
ꢂ5 VS, CF = 1 pF, RL = 150 Ω
TPC 36. Noninverting Small Signal Pulse Response
ꢂ5 VS, CF = 0 pF, RL = 150 Ω
REV. C
–9–
AD828
THEORY OF OPERATION
Circuit Board Layout
The AD828 is a low cost, dual video operational amplifier
designed to excel in high performance, high output current
video applications.
Input and output runs should be laid out so as to physically
isolate them from remaining runs. In addition, the feedback
resistor of each amplifier should be placed away from the feed-
back resistor of the other amplifier, since this greatly reduces
interamp coupling.
The AD828 consists of a degenerated NPN differential pair
driving matched PNPs in a folded-cascade gain stage (Figure 4).
The output buffer stage employs emitter followers in a class AB
amplifier that delivers the necessary current to the load while
maintaining low levels of distortion.
Choosing Feedback and Gain Resistors
To prevent the stray capacitance present at each amplifier’s
summing junction from limiting its performance, the feedback
resistors should be ≤ 1 kΩ. Since the summing junction capaci-
tance may cause peaking, a small capacitor (1 pF to 5 pF) may
be paralleled with RF to neutralize this effect. Finally, sockets
should be avoided, because of their tendency to increase interlead
capacitance.
The AD828 will drive terminated cables and capacitive loads of
10 pF or less. As the closed-loop gain is increased, the AD828
will drive heavier cap loads without oscillating.
+V
S
Power Supply Bypassing
Proper power supply decoupling is critical to preserve the
integrity of high frequency signals. In carefully laid out designs,
decoupling capacitors should be placed in close proximity to
the supply pins, while their lead lengths should be kept to a
minimum. These measures greatly reduce undesired inductive
effects on the amplifier’s response.
OUTPUT
–IN
+IN
Though two 0.1 µF capacitors will typically be effective in
decoupling the supplies, several capacitors of different values
can be paralleled to cover a wider frequency range.
PARALLEL AMPS PROVIDE 100 mA TO LOAD
–V
S
By taking advantage of the superior matching characteristics of the
AD828, enhanced performance can easily be achieved by employ-
ing the circuit in Figure 5. Here, two identical cells are paralleled
to obtain even higher load driving capability than that of a single
amplifier (100 mA min guaranteed). R1 and R2 are included to
limit current flow between amplifier outputs that would arise in
the presence of any residual mismatch.
Figure 4. Simplified Schematic
INPUT CONSIDERATIONS
An input protection resistor (RIN in TPC 31) is required in circuits
where the input to the AD828 will be subjected to transient or
continuous overload voltages exceeding the 6 V maximum dif-
ferential limit. This resistor provides protection for the input
transistors by limiting their maximum base current.
+V
1kꢃ
S
1ꢁF
For high performance circuits, the “balancing” resistor should be
used to reduce the offset errors caused by bias current flowing
through the input and feedback resistors. The balancing resistor
equals the parallel combination of RIN and RF and thus provides
a matched impedance at each input terminal. The offset voltage
error will then be reduced by more than an order of magnitude.
0.1ꢁF
1kꢃ
R1
5ꢃ
8
2
1/2
AD828
1
3
V
V
OUT
IN
APPLYING THE AD828
R2
5ꢃ
5
6
R
L
1/2
The AD828 is a breakthrough dual amp that delivers precision and
speed at low cost with low power consumption. The AD828 offers
excellent static and dynamic matching characteristics, combined
with the ability to drive heavy resistive loads.
7
AD828
1kꢃ
4
0.1ꢁF
1ꢁF
As with all high frequency circuits, care should be taken to main-
tain overall device performance as well as their matching. The
following items are presented as general design considerations.
1kꢃ
–V
S
Figure 5. Parallel Amp Configuration
–10–
REV. C
AD828
A
3
2
3
2
B
IN
IN
R
R
Z
Z
1/2
AD828
1/2
AD828
510ꢃ
510ꢃ
1
1
510ꢃ
510ꢃ
100FT
RG59A/U
R
= 75ꢃ
510ꢃ
Z
510ꢃ
536ꢃ
536ꢃ
6
5
6
5
1/2
AD828
1/2
AD828
B
A
7
OUT
7
OUT
Figure 6. Bidirectional Transmission CKT
Full-Duplex Transmission
clearly show that each input signal appears undisturbed at its out-
put, while the unwanted signal is eliminated at either receiver.
Superior load handling capability (50 mA min/amp), high
bandwidth, wide supply voltage range, and excellent crosstalk
rejection makes the AD828 an ideal choice for even the most
demanding high speed transmission applications.
The transmitters operate as followers, while the receivers’ gain
is chosen to take full advantage of the AD828’s unparalleled
CMRR. In practice, this gain is adjusted slightly from its
theoretical value to compensate for cable nonidealities and losses.
RZ is chosen to match the characteristic impedance of the
cable employed.
The schematic below shows a pair of AD828s configured to
drive 100 feet of coaxial cable in a full-duplex fashion.
Two different NTSC video signals are simultaneously applied at
A
IN and BIN and are recovered at AOUT and BOUT, respectively.
Finally, although a coaxial cable was used, the same topology
applies unmodified to a variety of cables (such as twisted pairs
often used in telephony).
This situation is illustrated in Figures 7 and 8. These pictures
500mV
500mV
100
90
100
90
B
A
IN
IN
B
OUT
A
OUT
10
10
0%
0%
500mV
10µs
500mV
10µs
Figure 7. A Transmission/B Reception
Figure 8. B Transmission/A Reception
+15V
A High Performance Video Line Driver
The buffer circuit shown in Figure 9 will drive a back-terminated
75 Ω video line to standard video levels (1 V p-p) with 0.1 dB
gain flatness to 40 MHz with only 0.05° and 0.01% differential
phase and gain at the 3.58 MHz NTSC subcarrier frequency.
This level of performance, which meets the requirements for
high definition video displays and test equipment, is achieved
using only 7 mA quiescent current/amplifier.
0.1ꢁF
1.0ꢁF
8
75ꢃ
V
3
2
IN
1/2
AD828
1
R
T
R
BT
R
T
75ꢃ
75ꢃ
4
75ꢃ
0.1ꢁF
1.0ꢁF
–15V
1kꢃ
1kꢃ
Figure 9. Video Line Driver
REV. C
–11–
AD828
LOW DISTORTION LINE DRIVER
1.1kꢃ
The AD828 can quickly be turned into a powerful, low distor-
tion line driver (see Figure 10). In this arrangement, the AD828
can comfortably drive a 75 Ω back-terminated cable with a
5 MHz, 2 V p-p input, while achieving the harmonic distortion
performance outlined in the following table.
+V
S
1kꢃ
1ꢁF
0.1ꢁF
2
3
8
1/2
AD828
1
Configuration
2nd Harmonic
R
7.5ꢃ
C
1. No Load
2. 150 Ω RL Only
3. 150 Ω RL 7.5 Ω RC
–78.5 dBm
–63.8 dBm
–70.4 dBm
1kꢃ
1kꢃ
R
6
5
L
75ꢃ
1/2
V
In this application, one half of the AD828 operates at a gain of +2.1
and supplies the current to the load, while the other provides the
overall system gain of +2. This is important for two reasons: the
first is to keep the bandwidth of both amplifiers the same, and
the second is to preserve the AD828’s ability to operate from low
supply voltage. RC varies with the load and must be chosen to
satisfy the following equation:
IN
7
AD828
4
75ꢃ
1ꢁF
75ꢃ
0.1ꢁF
–V
S
Figure 10. Low Distortion Amplifier
RC = MRL
where M is defined by [(M + 1) GS = GD] and GD = Driver’s
Gain, GS = System Gain.
OUTLINE DIMENSIONS
8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.4299 (10.92)
0.3480 (8.84)
5.00 (0.1968)
4.80 (0.1890)
8
5
4
8
1
5
4
0.2799 (7.11)
0.2402 (6.10)
6.20 (0.2440)
5.80 (0.2284)
0.1574 (4.00)
0.1497 (3.80)
1
PIN 1
PIN 1
0.3248 (8.25)
0.3000 (7.62)
0.1000 (2.54)
BSC
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢆ 45ꢀ
0.0598 (1.52)
0.0150 (0.38)
0.2098
(5.33)
MAX
1.75 (0.0688)
1.35 (0.0532)
COPLANARITY
0.25 (0.0098)
0.10 (0.0040)
0.1949 (4.95)
0.1154 (2.93)
8ꢀ
0.1299
(3.30)
MIN
0.1598 (4.06)
0.1154 (2.93)
0ꢀ 1.27 (0.0500)
0.51 (0.0201)
0.33 (0.0130)
0.0150 (0.38)
0.0079 (0.20)
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
0.0220 (0.56)
0.0142 (0.36)
SEATING
PLANE
0.0697 (1.77)
0.0453 (1.15)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012 AA
Revision History
Location
Page
6/02–Data Sheet changed from REV. B to REV. C.
Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Changes to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. C
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