AD8300AR-REEL [ADI]
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ADI |
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+3 Volt, Serial Input
Complete 12-Bit DAC
a
AD8300
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Complete 12-Bit DAC
No External Components
Single +3 Volt Operation
0.5 mV/Bit with 2.0475 V Full Scale
6 s Output Voltage Settling Time
Low Power: 3.6 mW
12-BIT
DAC
REF
V
OUT
12
V
DD
CLR
LD
DAC
REGISTER
12
GND
CS
CLK
SDI
EN
Compact SO-8 1.5 mm Height Package
SERIAL
REGISTER
APPLICATIONS
AD8300
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
GENERAL DESCRIPTION
A double buffered serial data interface offers high speed, three-
wire, DSP and microcontroller compatible inputs using data in
(SDI), clock (CLK) and load strobe (LD) pins. A chip select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, a CLR
input sets the output to zero scale at power on or upon user
demand.
The AD8300 is a complete 12-bit, voltage-output digital-to-
analog converter designed to operate from a single +3 volt sup-
ply. Built using a CBCMOS process, this monolithic DAC
offers the user low cost, and ease-of-use in single-supply +3 volt
systems. Operation is guaranteed over the supply voltage range
of +2.7 V to +5.5 V making this device ideal for battery oper-
ated applications.
The AD8300 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8300s are available in plastic
DIP, and low profile 1.5 mm height SO-8 surface mount packages.
The 2.0475 V full-scale voltage output is laser trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half-millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 5 mA.
3.0
1.00
V
= +2.7V
= –40؇C, +25؇C, +125؇C
DD
0.75
0.50
⌬VFS 1 LSB
T
A
2.8
2.6
2.4
2.2
2.0
DATA = FFF
H
T
A
= +25؇C
0.25
0.00
PROPER OPERATION
WHEN V SUPPLY
DD
–0.25
–0.50
–0.75
–1.00
VOLTAGE ABOVE
CURVE
= –40؇C
= +25؇C
= +125؇C
0
1024
2048
3072
4096
0.01
0.1
1.0
10
DIGITAL INPUT CODE – Decimal
OUTPUT LOAD CURRENT – mA
Figure 2. Linearity Error vs. Digital Code and Temperature
Figure 1. Minimum Supply Voltage vs. Load
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD8300–SPECIFICATIONS
+3 V OPERATION
(@ VDD = +5 V ؎ 10%, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
Parameter
Symbol
Condition
Min Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
[Note 1]
12
–2
–1
Bits
Relative Accuracy
Differential Nonlinearity2
Zero-Scale Error
INL
DNL
VZSE
VFS
±1/2
±1/2
+1/2
+2
+1
+3
LSB
LSB
mV
Volts
ppm/°C
Monotonic
Data = 000H
Data = FFFH
[Notes 3, 4]
Full-Scale Voltage3
Full-Scale Tempco
2.039 2.0475 2.056
16
TCVFS
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Load Regulation
Output Resistance to GND
Capacitive Load
IOUT
IOUT
LREG
ROUT
CL
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
RL = 200 Ω to ∞, Data = 800H
Data = 000H
5
2
5
mA
mA
LSB
Ω
1.5
30
500
No Oscillation4
pF
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
0.6
V
V
µA
pF
2.1
10
10
CIL
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
tCH
tCL
tLDW
tDS
40
40
50
15
15
40
15
40
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
Select
tDH
tCLRW
tLD1
tLD2
tCSS
tCSH
Deselect
AC CHARACTERISTICS4
Voltage Output Settling Time
tS
To ±0.2% of Full Scale
7
µs
µs
V/µs
nV/s
nV/s
To ±1 LSB of Final Value6
Data = 000H to FFFH to 000H
14
2.0
15
15
Output Slew Rate
DAC Glitch
Digital Feedthrough
SR
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
VDD RANGE
IDD
DNL < ±1 LSB
VDD = 3 V, VIL = 0 V, Data = 000H
2.7
5.5
1.7
3.0
5.1
V
1.2
1.9
3.6
mA
mA
mW
%/%
VDD = 3.6 V, VIH = 2.3 V, Data = FFFH
Power Dissipation
Power Supply Sensitivity
PDISS
PSS
VDD = 3 V, VIL = 0 V, Data = 000H
∆VDD = ±5%
0.001 0.005
NOTES
1LSB = 0.5 mV for 0 V to +2.0475 V output range.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
AD8300
+5 V OPERATION
(@ VDD = +5 V ؎ 10%, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
Parameter
Symbol
Condition
Min Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
[Note 1]
12
Bits
Relative Accuracy
Differential Nonlinearity2
Zero-Scale Error
INL
DNL
VZSE
VFS
–2
–1
±1/2
±1/2
+1/2
+2
+1
+3
LSB
LSB
mV
Volts
ppm/°C
Monotonic
Data = 000H
Data = FFFH
[Notes 3, 4]
Full-Scale Voltage3
Full-Scale Tempco
2.039 2.0475 2.056
16
TCVFS
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Load Regulation
Output Resistance to GND
Capacitive Load
IOUT
IOUT
LREG
ROUT
CL
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
RL = 200 Ω to ∞, Data = 800H
Data = 000H
5
2
5
mA
mA
LSB
Ω
1.5
30
500
No Oscillation4
pF
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
0.8
V
V
µA
pF
2.4
10
10
CIL
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
tCH
tCL
tLDW
tDS
tDH
tCLWR
tLD1
tLD2
tCSS
tCSH
30
30
30
15
15
30
15
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
Select
Deselect
AC CHARACTERISTICS4
Voltage Output Settling Time
tS
To ±0.2% of Full Scale
6
µs
µs
V/µs
nV/s
nV/s
To ±1 LSB of Final Value6
Data = 000H to FFFH to 000H
13
2.2
15
15
Output Slew Rate
DAC Glitch
Digital Feedthrough
SR
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
VDD RANGE
IDD
DNL < ±1 LSB
VDD = 5 V, VIL = 0 V, Data = 000H
2.7
5.5
1.7
4.0
5.1
V
1.2
2.8
6
mA
mA
mW
%/%
V
DD = 5.5 V, VIH = 2.3 V, Data = FFFH
Power Dissipation
Power Supply Sensitivity
PDISS
PSS
VDD = 5 V, VIL = 0 V, Data = 000H
∆VDD = ±10%
0.001 0.006
NOTES
11 LSB = 0.5 mV for 0 V to +2.0475 V output range.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
REV. A
–3–
AD8300
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
PIN CONFIGURATIONS
SO-8 Plastic DIP
1
4
8
1
2
3
4
8
7
6
5
V
OUT
V
DD
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
GND
CLR
LD
CS
AD8300
TOP VIEW
(Not to Scale)
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ Max – TA)/θJA
Thermal Resistance θJA
5
CLK
SDI
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
PIN DESCRIPTIONS
Function
Pin #
Name
1
VDD
Positive power supply input. Specified range
of operation +2.7 V to +5.5 V.
2
CS
Chip Select, active low input. Disables shift
register loading when high. Does not affect
LD operation.
Clock input, positive edge clocks data into
shift register.
Serial Data Input, input data loads directly
into the shift register, MSB first.
Load DAC register strobes, active low.
Transfers shift register data to DAC register.
See Truth Table I for operation. Asynchro-
nous active low input.
Resets DAC register to zero condition.
Asynchronous active low input.
Analog and Digital Ground.
DAC voltage output, 2.0475 V full scale
with 0.5 mV per bit. An internal tempera-
ture stabilized reference maintains a fixed
full-scale voltage independent of time, tem-
perature and power supply variations.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
3
4
5
CLK
SDI
LD
ORDERING GUIDE
Package
Description
Package
Options
Model
INL
Temp
AD8300AN
AD8300AR
±2
±2
XIND
XIND
8-Lead P-DIP
8-Lead SOIC
N-8
SO-8
6
CLR
NOTES
7
8
GND
VOUT
XIND = –40°C to +85°C.
The AD8300 contains 630 transistors. The die size measures 72 mil × 65 mil.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDI
CLK
CS
tCSS
tCSH
tLD1
tLD2
LD
SDI
tDS
tDH
tCL
CLK
tCH
tLDW
LD
tCLRW
tS
CLR
tS
FS
VOUT
ZS
؎1LSB
ERROR BAND
Figure 3. Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
Typical Performance Characteristics–
AD8300
2.5
2.0
1.5
1.0
0.5
0
80
60
POSITIVE
CURRENT
LIMIT
T
A
= –40 TO +85؇C
V
V
= +5V
= +3V
DD
40
DD
20
DATA = 800
H
0
R
TIED TO +1.024V
L
–20
–40
–60
–80
V
= +3V
= +5V
DD
NEGATIVE
CURRENT
LIMIT
V
DD
HORIZONTAL = 1s/DIV
0
1
2
3
4
5
6
0
1
2
V
DD
SUPPLY VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
Figure 5. Logic Input Threshold
Voltage vs. VDD
Figure 6. Detail Settling Time
Figure 4. IOUT vs. VOUT
50
45
V
DD
= +5V ؎10%
40
35
30
25
20
15
10
5
V
= +3V ؎10%
DD
T
= +25؇C
A
DATA = FFF
H
HORIZONTAL = 20s/DIV
TIME = 100s/DIV
0
10
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 9. Large Signal Settling Time
Figure 8. Power Supply Rejection
vs. Frequency
Figure 7. Broadband Noise
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
DD
= +3V
V
= +5V
DD
T
= +25؇C
A
DATA = FFF
H
0.5s/DIV
CODE 800 TO 7FF
H
H
0
1
2
3
4
5
LOGIC VOLTAGE – Volts
Figure 12. Digital Feedthrough vs.
Time
Figure 11. Midscale Transition
Performance
Figure 10. Supply Current vs. Logic
Input Voltage
REV. A
–5–
AD8300
3.0
2.6
2.2
1.8
1.4
1.0
1.5
1.0
60
50
40
30
20
10
0
V
= +5.5V
= +5.0V
DD
TUE = ⌺INL+ZS+FS
NO LOAD
ss = 300 UNITS
NORMALIZED TO +25؇C
ss = 300 UNITS
V
DD
= +3V
V
DD
T
A
= +25؇C
0.5
V
= +5V
DD
V
DD
= +4.5V
0
–0.5
–1.0
–1.5
V
DD
= +2.7, 3.0, 3.3V
V
= +2.7V
DD
DATA = FFF
H
V
= +2.4V
= 0V
IH
V
IL
–60
–20
20
60
100
140
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – ؇C
–1
0
1
2
3
4
5
6
TEMPERATURE – ؇C
TOTAL UNADJUSTED ERROR – mV
Figure 13. Total Unadjusted
Error Histogram
Figure 15. Supply Current vs.
Temperature
Figure 14. Zero-Scale Voltage Drift
vs. Temperature
70
1.5
10
NO LOAD
ss = 300 UNITS
NORMALIZED TO +25؇C
V
= +3V
60
50
40
30
20
10
0
V
= +3V
DD
DD
1.0
0.5
0
DATA = FFF
DATA FFF
H
H
T
A
= –40 TO +85؇C
1
V
DD
= +5.5V
–0.5
0.1
V
DD
= +2.7V
–1.0
–1.5
0.01
–50 –40 –30 –20 –10
TEMPERATURE COEFFICIENT – ppm/؇C
0
10 20 30 40
1
10
100
1k
10k
100k
–55 –35 –15
5
25 45 65 85 105 125
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 18. Full-Scale Output
Tempco Histogram
Figure 17. Output Voltage Noise
Density vs. Frequency
Figure 16. Full-Scale Voltage Drift
vs. Temperature
2.4
V
= +2.7V
DD
2.0
1.6
1.2
0.8
0.4
0
ss = 135 UNITS
FULL SCALE (DATA = FFF
)
H
ZERO SCALE (DATA = 000
)
H
600
0
100 200
300
400
500
HOURS OF OPERATION AT +150؇C
Figure 19. Long Term Drift
Accelerated by Burn-In
–6–
REV. A
AD8300
Table I. Control Logic Truth Table
Serial Shift Register Function
CS
CLK
CLR
LD
DAC Register Function
H
L
L
L
↑
H
H
H
H
X
L
H
↑
L
X
X
X
X
H
H
H
H
H
H
H
L
H
H
H
H
H
↓
L
X
H
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
↑
Latched All Zeros
NOTES
1. ↑ = Positive Logic Transition; ↓ = Negative Logic Transition; X = Don’t Care.
2. Do not clock in serial data while LD is LOW.
3. Data loads MSB first.
OPERATION
OUTPUT SECTION
The AD8300 is a complete ready to use 12-bit digital-to-analog
converter. Only one +3 V power supply is necessary for opera-
tion. It contains a 12-bit laser-trimmed digital-to-analog
converter, a curvature-corrected bandgap reference, rail-to-rail
output op amp, serial-input register, and DAC register. The
serial data interface consists of a serial-data-input (SDI) clock
(CLK), and load strobe pins (LD) with an active low CS strobe.
In addition an asynchronous CLR pin will set all DAC register
bits to zero causing the VOUT to become zero volts. This func-
tion is useful for power on reset or system failure recovery to a
known state.
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 21 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
V
DD
P-CH
N-CH
V
OUT
D/A CONVERTER SECTION
The internal DAC is a 12-bit device with an output that swings
from GND potential to 0.4 volt generated from the internal band-
gap voltage, see Figure 20. It uses a laser-trimmed segmented
R-2R ladder which is switched by N-channel MOSFETs. The
output voltage of the DAC has a constant resistance indepen-
dent of digital input code. The DAC output is internally con-
nected to the rail-to-rail output op amp.
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage achieves the minimum operating
supply voltage capability shown in Figure 2. The N-channel
output pull-down MOSFET shown in Figure 21 has a 35 Ω on
resistance which sets the sink current capability near ground. In
addition to resistive load driving capability, the amplifier has
also been carefully designed and characterized for up to 500 pF
capacitive load driving capability.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset volt-
age and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured
with a gain of approximately five in order to set the 2.0475 volt
full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent
circuit schematic of the analog section.
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output per-
formance of full-scale vs. temperature which is dominated by
the reference performance.
1.2V
BANDGAP
REF
0.4V
FS
POWER SUPPLY
12-BIT DAC
V
OUT
The very low power consumption of the AD8300 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
0.4V
2.047V
FS
R2
R1
Figure 20. Equivalent AD8300 Schematic of Analog Portion
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8300 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CLK, CS, LD, and CLR pins. Since these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving logic
The op amp has a 2 µs typical settling time to 0.4% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also negative transition settling time to
within the last 6 LSB of zero volts has an extended settling time.
See the oscilloscope photos in the typical performances section
of this data sheet.
REV. A
–7–
AD8300
Table II. Unipolar Code Table
VOH and VOL voltage levels. Consequently, for optimum dissipa-
tion use of CMOS logic versus TTL provides minimal dissipa-
tion in the static state. A VINL = 0 V on the logic input pins
provides the lowest standby dissipation of 1.2 mA with a +3.3 V
power supply.
Hexadecimal
Number in
DAC Register
Decimal
Number in
DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+2.0475
+1.0245
+1.0240
+1.0235
+0.0000
As with any analog system, it is recommended that the AD8300
power supply be bypassed on the same PC card that contains
the chip. Figure 8 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8300 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+2.7 V to +5.5 V. If reduced linearity and source current capa-
bility near full scale can be tolerated, operation of the AD8300
is possible down to +2.1 volts. The minimum operating supply
voltage versus load current plot in Figure 2 provides information
for operation below VDD = +2.7 V.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
TIMING AND CONTROL
8
1
5
4
The AD8300 has a separate serial-input register from the 12-bit
DAC register that allows preloading of a new data value MSB
first into the serial register without disturbing the present DAC
output voltage value. Data can only be loaded when the CS pin
is active low. After the new value is fully loaded in the serial-
input register, it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any new
data is loaded into the serial-input register. At any time the
contents of the DAC resister can be reset to zero by strobing the
CLR pin which causes the DAC output voltage to go to zero
volts. All of the timing requirements are detailed in Figure 3
along with Table I. Control Logic Truth Table.
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
8-Lead Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
All digital inputs are protected with a Zener type ESD protection
structure (Figure 22) that allows logic input voltages to exceed
the VDD supply voltage. This feature can be useful if the user is
loading one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8300 on a +3.3 V
power supply. If this mode of interface is used, make sure that
the VOL of the +5 V CMOS meets the VIL input requirement of
the AD8300 operating at 3 V. See Figure 5 for the effect on
digital logic input threshold versus operating VDD supply voltage.
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.015
(0.381)
TYP
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
15؇
0؇
V
DD
PLANE
LOGIC
IN
GND
Figure 22. Equivalent Digital Input ESD Protection
Unipolar Output Operation
This is the basic mode of operation for the AD8300. The
AD8300 has been designed to drive loads as low as 400 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table II.
APPLICATIONS INFORMATION
See DAC8512 data sheet for additional application circuit ideas.
–8–
REV. A
相关型号：
AD8300ARZ-REEL
SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.50 MM HEIGHT, LOW PROFILE, SOIC-8
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