AD8302-EVALZ_技术文档

LF–2.7 GHz

RF/IF Gain and Phase Detector

a

AD8302

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Measures Gain/Loss and Phase up to 2.7 GHz

Dual Demodulating Log Amps and Phase Detector

Input Range –60 dBm to 0 dBm in a 50 ⍀ System

Accurate Gain Measurement Scaling (30 mV/dB)

Typical Nonlinearity < 0.5 dB

Accurate Phase Measurement Scaling (10 mV/Degree)

Typical Nonlinearity < 1 Degree

Measurement/Controller/Level Comparator Modes

Operates from Supply Voltages of 2.7 V–5.5 V

Stable 1.8 V Reference Voltage Output

Small Signal Envelope Bandwidth from DC to 30 MHz

AD8302

MFLT

VIDEO OUTPUT – A

+

VMAG

–

INPA

60dB LOG AMPS

(7 DETECTORS)

OFSA

MSET

PSET

PHASE

COMM

DETECTOR

OFSB

INPB

–

APPLICATIONS

RF/IF PA Linearization

Precise RF Power Control

60dB LOG AMPS

(7 DETECTORS)

VPHS

PFLT

+

VIDEO OUTPUT – B

Remote System Monitoring and Diagnostics

Return Loss/VSWR Measurements

Log Ratio Function for AC Signals

1.8V

VPOS

BIAS

x3

VREF

PRODUCT DESCRIPTION

The signal inputs are single-ended, allowing them to be matched

and connected directly to a directional coupler. Their input

impedance is nominally 3 kΩ at low frequencies.

The AD8302 is a fully integrated system for measuring gain/loss

and phase in numerous receive, transmit, and instrumentation

applications. It requires few external components and a single

supply of 2.7 V–5.5 V. The ac-coupled input signals can range

from –60 dBm to 0 dBm in a 50 Ω system, from low frequencies

up to 2.7 GHz. The outputs provide an accurate measurement

of either gain or loss over a 30 dB range scaled to 30 mV/dB,

and of phase over a 0°–180° range scaled to 10 mV/degree.

Both subsystems have an output bandwidth of 30 MHz, which

may optionally be reduced by the addition of external filter

capacitors. The AD8302 can be used in controller mode to

force the gain and phase of a signal chain toward predetermined

setpoints.

The AD8302 includes a phase detector of the multiplier type,

but with precise phase balance driven by the fully limited signals

appearing at the outputs of the two logarithmic amplifiers.

Thus, the phase accuracy measurement is independent of signal

level over a wide range.

The phase and gain output voltages are simultaneously available

at loadable ground referenced outputs over the standard output

range of 0 V to 1.8 V. The output drivers can source or sink up

to 8 mA. A loadable, stable reference voltage of 1.8 V is avail-

able for precise repositioning of the output range by the user.

In controller applications, the connection between the gain

output pin VMAG and the setpoint control pin MSET is broken.

The desired setpoint is presented to MSET and the VMAG

control signal drives an appropriate external variable gain device.

Likewise, the feedback path between the phase output pin VPHS

and its setpoint control pin PSET may be broken to allow

operation as a phase controller.

The AD8302 comprises a closely matched pair of demodulating

logarithmic amplifiers, each having a 60 dB measurement range.

By taking the difference of their outputs, a measurement of

the magnitude ratio or gain between the two input signals is

available. These signals may even be at different frequencies,

allowing the measurement of conversion gain or loss. The AD8302

may be used to determine absolute signal level by applying the

unknown signal to one input and a calibrated ac reference signal

to the other. With the output stage feedback connection dis-

abled, a comparator may be realized, using the setpoint pins

MSET and PSET to program the thresholds.

The AD8302 is fabricated on Analog Devices’ proprietary, high

performance 25 GHz SOI complementary bipolar IC process. It is

available in a 14-lead TSSOP package and operates over a –40°C

to +85°C temperature range. An evaluation board is available.

REV. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

(T_A= 25؇C, V_S= 5 V, VMAG shorted to MSET, VPHS shorted to PSET, 52.3 ⍀ shunt

resistors connected to INPA and INPB, for Phase measurement P_INPA= P_INPB, unless otherwise noted.)

AD8302–SPECIFICATIONS

Parameter

Conditions

Min

Typ

Max

Unit

OVERALL FUNCTION

Input Frequency Range

Gain Measurement Range

Phase Measurement Range

Reference Voltage Output

>0

2700

MHz

dB

Degree

V

P_INat INPA, P_INat INPB = –30 dBm

30

90

1.8

φ

_INat INPA > φ_INat INPB

Pin VREF, –40°C ≤ T_A≤ +85°C

1.72

1.88

INPUT INTERFACE

Pins INPA and INPB

Input Simplified Equivalent Circuit To AC Ground, f ≤ 500 MHz

3ʈ2

kΩʈpF

dBV

dBm

dBV

dBm

Input Voltage Range

AC-Coupled (0 dBV = 1 V rms)

–73

–60

–13

0

re: 50 Ω

Center of Input Dynamic Range

–43

–30

MAGNITUDE OUTPUT

Output Voltage Minimum

Output Voltage Maximum

Center Point of Output (MCP)

Output Current

Small Signal Envelope Bandwidth

Slew Rate

Response Time

Pin VMAG

20 × Log (V_INPA/V_INPB) = –30 dB

20 × Log (V_INPA/V_INPB) = +30 dB

V_INPA= V_INPB

Source/Sink

Pin MFLT Open

30

1.8

900

8

30

25

mV

V

mV

mA

MHz

V/µs

40 dB Change, Load 20 pFʈ10 kΩ

Rise Time

Fall Time

Settling Time

Any 20 dB Change, 10%–90%

Any 20 dB Change, 90%–10%

Full-Scale 60 dB Change, to 1% Settling

50

60

300

ns

PHASE OUTPUT

Pin VPHS

Output Voltage Minimum

Output Voltage Maximum

Phase Center Point

Output Current Drive

Slew Rate

Phase Difference 180 Degrees

Phase Difference 0 Degrees

When φ_INPA= φ_INPB90°

Source/Sink

30

1.8

900

8

25

30

40

500

mV

V

mV

mA

V/µs

MHz

ns

Small Signal Envelope Bandwidth

Response Time

Any 15 Degree Change, 10%–90%

120 Degree Change C_FILT= 1 pF, to 1% Settling

ns

100 MHz

MAGNITUDE OUTPUT

Dynamic Range

1 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.5 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.2 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

From Linear Regression

58

55

42

29

dB

mV/dB

Slope

Deviation vs. Temperature

Deviation from Output at 25°C

–40°C ≤ T_A≤ +85°C, P_INPA= P_INPB= –30 dBm

Deviation from Best Fit Curve at 25°C

0.25

dB

–40°C ≤ T_A≤ +85°C, P_INPA

=

25 dB, P_INPB= –30 dBm

0.25

0.2

dB

Gain Measurement Balance

Dynamic Range

P_INPA= P_INPB= –5 dBm to –50 dBm

PHASE OUTPUT

Less than 1 Degree Deviation from Best Fit Line

Less than 10% Deviation in Instantaneous Slope

From Linear Regression about –90° or +90°

Deviation from Output at 25°C

145

143

10

Degree

mV/Degree

Slope (Absolute Value)

Deviation vs. Temperature

–40°C ≤ T_A≤ +85°C, Delta Phase = 90 Degrees

Deviation from Best Fit Curve at 25°C

–40°C ≤ T_A≤ +85°C, Delta Phase = 30 Degrees

0.7

Degree

–2–

REV. B

AD8302

Parameter

Conditions

Min

Typ

Max

Unit

900 MHz

MAGNITUDE OUTPUT

Dynamic Range

1 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.5 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.2 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

From Linear Regression

58

54

42

28.7

dB

mV/dB

Slope

Deviation vs. Temperature

Deviation from Output at 25°C

–40°C ≤ T_A≤ +85°C, P_INPA= P_INPB= –30 dBm

Deviation from Best Fit Curve at 25°C

0.25

dB

–40°C ≤ T_A≤ +85°C, P_INPA

=

25 dB, P_INPB= –30 dBm

0.25

0.2

dB

Gain Measurement Balance

Dynamic Range

P_INPA= P_INPB= –5 dBm to –50 dBm

PHASE OUTPUT

Less than 1 Degree Deviation from Best Fit Line

Less than 10% Deviation in Instantaneous Slope

From Linear Regression about –90° or +90°

Linear Deviation from Best Fit Curve at 25°C

–40°C ≤ T_A≤ +85°C, Delta Phase = 90 Degrees

–40°C ≤ T_A≤ +85°C, Delta Phase = 30 Degrees

Phase @ INPA = Phase @ INPB, P_IN= –5 dBm to –50 dBm

143

10.1

Degree

mV/Degree

Slope (Absolute Value)

Deviation

0.75

0.8

Degree

Phase Measurement Balance

1900 MHz

MAGNITUDE OUTPUT

Dynamic Range

1 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.5 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.2 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

From Linear Regression

57

54

42

27.5

dB

mV/dB

Slope

Deviation vs. Temperature

Deviation from Output at 25°C

–40°C ≤ T_A≤ +85°C, P_INPA= P_INPB= –30 dBm

Deviation from Best Fit Curve at 25°C

0.27

dB

–40°C ≤ T_A≤ +85°C, P_INPA

=

25 dB, P_INPB= –30 dBm

0.33

0.2

dB

Gain Measurement Balance

Dynamic Range

P_INPA= P_INPB= –5 dBm to –50 dBm

PHASE OUTPUT

Less than 1 Degree Deviation from Best Fit Line

Less than 10% Deviation in Instantaneous Slope

From Linear Regression about –90° or +90°

Linear Deviation from Best Fit Curve at 25°C

–40°C ≤ T_A≤ +85°C, Delta Phase = 90 Degrees

–40°C ≤ T_A≤ +85°C, Delta Phase = 30 Degrees

Phase @ INPA = Phase @ INPB, P_IN= –5 dBm to –50 dBm

128

120

10.2

Degree

mV/Degree

Slope (Absolute Value)

Deviation

0.8

1

Degree

Phase Measurement Balance

2200 MHz

MAGNITUDE OUTPUT

Dynamic Range

1 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.5 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

0.2 dB Linearity P_REF= –30 dBm (V_REF= –43 dBV)

From Linear Regression

53

51

38

27.5

dB

mV/dB

Slope

Deviation vs. Temperature

Deviation from Output at 25°C

–40°C ≤ T_A≤ +85°C, P_INPA= P_INPB= –30 dBm

Deviation from Best Fit Curve at 25°C

0.28

dB

–40°C ≤ T_A≤ +85°C, P_INPA

=

25 dB, P_INPB= –30 dBm

0.4

0.2

dB

Gain Measurement Balance

Dynamic Range

P_INPA= P_INPB= –5 dBm to –50 dBm

PHASE OUTPUT

Less than 1 Degree Deviation from Best Fit Line

Less than 10% Deviation in Instantaneous Slope

From Linear Regression about –90° or +90°

Linear Deviation from Best Fit Curve at 25°C

–40°C ≤ T_A≤ +85°C, Delta Phase = 90 Degrees

–40°C ≤ T_A≤ +85°C, Delta Phase = 30 Degrees

115

110

10

Degree

mV/Degree

Slope (Absolute Value)

Deviation

0.85

0.9

Degree

REFERENCE VOLTAGE

Output Voltage

PSRR

Pin VREF

Load = 2 kΩ

V_S= 2.7 V to 5.5 V

Source/Sink (Less than 1% Change)

1.7

2.7

1.8

0.25

5

1.9

V

mV/V

mA

Output Current

POWER SUPPLY

Supply

Operating Current (Quiescent)

Pin VPOS

5.0

19

21

5.5

25

27

V

mA

V_S= 5 V

–40°C ≤ T_A≤ +85°C

Specifications subject to change without notice.

REV. B

–3–

AD8302

ABSOLUTE MAXIMUM RATINGS¹

PIN CONFIGURATION

Supply Voltage V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

PSET, MSET Voltage . . . . . . . . . . . . . . . . . . . . . . V_S+ 0.3 V

INPA, INPB Maximum Input . . . . . . . . . . . . . . . . . . –3 dBV

Equivalent Power Re. 50 Ω . . . . . . . . . . . . . . . . . . 10 dBm

COMM

INPA

1

2

3

4

5

6

7

14 MFLT

13 VMAG

12 MSET

2

OFSA

VPOS

OFSB

INPB

AD8302

θ_JA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

TOP VIEW

11

10

9

VREF

PSET

VPHS

PFLT

Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

(Not to Scale)

Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C

8

COMM

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²JEDEC 1S Standard (2-layer) board data.

PIN FUNCTION DESCRIPTIONS

Equivalent

Circuit

Pin No.

Mnemonic

Function

Device Common. Connect to low impedance ground.

High Input Impedance to Channel A. Must be ac-coupled.

A capacitor to ground at this pin sets the offset compensation filter corner

and provides input decoupling.

1, 7

2

3

COMM

INPA

OFSA

Circuit A

4

5

VPOS

OFSB

Voltage Supply (V_S), 2.7 V to 5.5 V

A capacitor to ground at this pin sets the offset compensation filter corner

and provides input decoupling.

Circuit A

6

8

9

INPB

PFLT

VPHS

Input to Channel B. Same structure as INPA.

Low Pass Filter Terminal for the Phase Output

Single-Ended Output Proportional to the Phase Difference between INPA

and INPB.

Circuit A

Circuit E

Circuit B

10

PSET

Feedback Pin for Scaling of VPHS Output Voltage in Measurement Mode.

Apply a setpoint voltage for controller mode.

Circuit D

11

12

VREF

MSET

Internally Generated Reference Voltage (1.8 V Nominal)

Feedback Pin for Scaling of VMAG Output Voltage Measurement Mode.

Accepts a set point voltage in controller mode.

Circuit C

Circuit D

13

14

VMAG

MFLT

Single-Ended Output. Output voltage proportional to the decibel ratio

of signals applied to INPA and INPB.

Low Pass Filter Terminal for the Magnitude Output

Circuit B

Circuit E

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD8302 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

AD8302

VPOS

100mV

4k⍀

INPA(INPB)

+

4k⍀

750⍀

2k⍀

25⍀

VMAG

(VPHS)

ON TO

LOG-AMP

OFSA(OFSB)

CLASS A-B

CONTROL

–

10pF

COMM

Circuit A

Circuit B

VPOS

MFLT

(PFLT)

VREF

10k⍀

MSET

(PSET)

10k⍀

5k⍀

1.5pF

10k⍀

ACTIVE LOADS

COMM

Circuit E

Circuit D

Circuit C

Figure 1. Equivalent Circuits

REV. B

–5–

AD8302–Typical Performance Characteristics

(V_S= 5 V, V_INPBis the reference input and V_INPAis swept, unless otherwise noted. All references to dBm are referred to 50 ⍀. For the phase output

curves, the input signal levels are equal, unless otherwise noted.)

1.80

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

900

100

2200

–40؇C

1900

+25؇C

2700

+85؇C

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

–30

–20

–10

0

10

20

30

MAGNITUDE RATIO – dB

TPC 1. Magnitude Output (VMAG) vs. Input Level Ratio

(Gain) V_INPA/V_INPB, Frequencies 100 MHz, 900 MHz,

1900 MHz, 2200 MHz, 2700 MHz, 25؇C, P_INPB= –30 dBm,

(Re: 50 Ω)

TPC 4. VMAG and Log Conformance vs. Input Level Ratio

(Gain), Frequency 900 MHz, –40؇C, +25؇C, and +85

Reference Level = –30 dBm

؇C,

1.80

1.65

1.50

1.35

1.20

2.0

3.0

1900

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

2700

1.2

1.0

0.8

1.05

–40؇C

0.90

+25؇C

0.75

–0.5

–1.0

+85؇C

0.60

0.45

0.30

0.15

0

0.6

2200

–1.5

0.4

–2.0

–2.5

–3.0

0.2

900

100

0

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

–30

–20

–10

0

10

20

30

MAGNITUDE RATIO – dB

TPC 2. VMAG vs. Input Level Ratio (Gain) V_INPA/V_INPB

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz,

2700 MHz, P_INPA= –30 dBm

,

TPC 5. VMAG and Log Conformance vs. Input Level Ratio

(Gain), Frequency 1900 MHz, –40؇C, +25؇C, and +85؇C,

Reference Level = –30 dBm

1.80

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

2.5

2.0

1.5

1.0

–40؇C

0.5

–40؇C

+25؇C

0.0

+25؇C

+85؇C

–0.5

–1.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–1.5

–2.0

–2.5

–3.0

–30

–20

–10

0

10

20

30

–30

–20

–10

0

10

20

30

MAGNITUDE RATIO – dB

TPC 3. VMAG Output and Log Conformance vs. Input

Level Ratio (Gain), Frequency 100 MHz, –40؇C, +25؇C,

and +85؇C, Reference Level = –30 dBm

TPC 6. VMAG Output and Log Conformance vs. Input

Level Ratio (Gain), Frequency 2200 MHz, –40؇C, +25؇C,

and +85؇C, Reference Level = –30 dBm

–6–

REV. B

AD8302

3.0

2.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.0

1.5

–40 C

+85 C

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

+85 C

+25 C

–40 C

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

MAGNITUDE RATIO – dB

TPC 7. Distribution of Magnitude Error vs. Input Level

Ratio (Gain), Three Sigma to Either Side of Mean,

Frequency 900 MHz, –40؇C, +25؇C, and +85؇C, Refer-

ence Level = –30 dBm

TPC 10. Distribution of VMAG vs. Input Level Ratio (Gain),

Three Sigma to Either Side of Mean, Frequency 1900 MHz,

Temperatures Between –40؇C and +85؇C, Reference Level

= –30 dBm

3.0

2.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

3.0

–45dBm

2.5

2.0

–45dBm

–30dBm

1.5

–40 C

+85 C

1.0

0.5

–15dBm

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.5

–1.0

–30dBm

–15dBm

+25 C

–1.5

–40 C

+85 C

–2.0

–2.5

–3.0

–30

–20

–10

0

10

20

30

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

MAGNITUDE RATIO – dB

TPC 8. Distribution of Error vs. Input Level Ratio (Gain),

Three Sigma to Either Side of Mean, Frequency 1900 MHz,

–40؇C, +25؇C, and +85؇C, Reference Level = –30 dBm

TPC 11. VMAG Output and Log Conformance vs. Input

Level Ratio (Gain), Reference Level = –15 dBm, –30 dBm,

and –45 dBm, Frequency 1900 MHz

3.0

2.5

1.10

P

= P

+ 5dB

INPA

INPB

1.05

1.00

0.95

0.90

0.85

0.80

0.75

2.0

–40 C

1.5

1.0

+85 C

0.5

0.0

P

= P

INPB

INPA

–0.5

–1.0

+25 C +85 C

–1.5

–40 C

–2.0

P

= P

– 5dB

INPA

INPB

–2.5

–3.0

–30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30

–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

INPUT LEVEL – dBm

0

MAGNITUDE RATIO – dB

TPC 9. Distribution of Magnitude Error vs. Input Level

Ratio (Gain), Three Sigma to Either Side of Mean,

Frequency 2200 MHz, Temperatures –40؇C, +25؇C, and

+85؇C, Reference Level = –30 dBm

TPC 12. VMAG Output vs. Input Level for P_INPA= P_INPB

P_INPA= P_INPB+ 5 dB, P_INPA= P_INPB– 5 dB, Frequency 1900 MHz

,

REV. B

–7–

AD8302

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

0.88

0.86

0.84

0.82

0.80

0.78

0.76

18

15

12

9

P

= P

+ 5dB

INPB

INPA

P

= P

INPA

INPB

6

3

P

= P

– 5dB

INPB

INPA

0

0.80

0.74

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

0.85

0.90

0.95

1.00

FREQUENCY – MHz

MCP –V

TPC 13. VMAG Output vs. Frequency, for P_INPA= P_INPB, P_INPA

= P_INPB+ 5 dB, and P_INPA= P_INPB– 5 dB, P_INPB= –30 dBm

TPC 16. Center Point of Magnitude Output (MCP)

Distribution Frequencies 900 MHz, 17,000 Units

0.4

0.2

18

15

12

9

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

6

3

0

27.0

27.5

28.0

28.5

29.0

29.5

30.0

–40

–20

0

20

40

60

80 85

TEMPERATURE – ؇C

VMAG SLOPE – mV/dB

TPC 17. VMAG Slope, Frequency 900 MHz, 17,000 Units

TPC 14. Change in VMAG Slope vs. Temperature, Three

Sigma to Either Side of Mean, Frequencies 1900 MHz

25

20

0.032

0.030

0.028

0.026

0.024

15

10

5

0

–5

–10

–15

–20

–25

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE – ؇C

FREQUENCY – MHz

TPC 15. Change in Center Point of Magnitude Output

(MCP) vs. Temperature, Three Sigma to Either Side of

Mean, Frequencies 1900 MHz

TPC 18. VMAG Slope vs. Frequency

–8–

REV. B

AD8302

10000

1000

100

INPUT –50dBm

INPUT –30dBm

INPUT –10dBm

20mV PER

VERTICAL

DIVISION

25ns

HORIZONTAL

10

1k

10k

100k

1M

10M

100M

FREQUENCY – Hz

TPC 22. Magnitude Output Noise Spectral

Density, P_INPA= P_INPB= –10 dBm, –30 dBm,

–50 dBm, No Filter Capacitor

TPC 19. Magnitude Output Response to 4 dB Step, for

_INPB= –30 dBm, P_INPA= –32 dBm to –28 dBm, Frequency

1900 MHz, No Filter Capacitor

P

10000

INPUT –50dBm

1000

100

10

INPUT –30dBm

20mV PER

VERTICAL

DIVISION

INPUT –10dBm

1.00␮s

HORIZONTAL

1k

10k

100k

1M

10M

100M

FREQUENCY – Hz

TPC 23. Magnitude Output Noise Spectral Density, P_INPA= P_INPB

= –10 dBm, –30 dBm, –50 dBm, with Filter Capacitor, C = 1 nF

TPC 20. Magnitude Output Response to 4 dB Step, for

P_INPB= –30 dBm, P_INPA= –32 dBm to –28 dBm, Frequency

1900 MHz, 1 nF Filter Capacitor

0.18

0.16

0.14

0.12

0.10

200mV PER

VERTICAL

DIVISION

0.08

2700

1900

0.06

2200

900

0.04

100ns

HORIZONTAL

100

0.02

0.00

–25 –20 –15 –10

–5

0

5

10

15

20

25

MAGNITUDE RATIO – dB

TPC 24. VMAGPeak-to-Peak Output Induced by Sweeping

Phase Difference through 360 Degrees vs. Magnitude Ratio,

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and

2700 MHz

TPC 21. Magnitude Output Response to 40 dB Step, for

P_INPB= –30 dBm, P_INPA= –50 dBm to –10 dBm, Supply 5 V,

Frequency 1900 MHz, No Filter Capacitor

REV. B

–9–

AD8302

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

10

8

100MHz

900MHz

6

1900MHz

4

2200MHz

2700MHz

2

0

–2

–4

–6

–8

–10

–180 –140 –100 –60

–20

20

60

100

140

180

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 25. Phase Output (VPHS) vs. Input Phase Difference,

Input Levels –30 dBm, Frequencies 100 MHz, 900 MHz,

1900 MHz, 2200 MHz, Supply 5 V, 2700 MHz

TPC 28. VPHS Output and Nonlinearity vs. Input Phase

Difference, Input Levels –30 dBm, Frequency 1900 MHz

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

10

8

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

10

8

6

4

2

0

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 29. VPHS Output and Nonlinearity vs. Input Phase

TPC 26. VPHS Output and Nonlinearity vs. Input Phase

Difference, Input Levels –30 dBm, Frequency 2200 MHz

Difference, Input Levels –30 dBm, Frequency 100 MHz

10

8

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

10

8

6

4

+25؇C

2

0

–2

–4

–6

–8

–10

+85؇C

–4

–40؇C

–6

–8

–10

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 30. Distribution of VPHS Error vs. Input Phase Differ-

ence, Three Sigma to Either Side of Mean, Frequency

900 MHz, –40؇C, +25؇C, and +85؇C, Input Levels –30 dBm

TPC 27. VPHS Output and Nonlinearity vs. Input Phase

Difference, Input Levels –30 dBm, Frequency 900 MHz

–10–

REV. B

AD8302

10

8

0.15

0.10

6

0.05

MEAN +3 SIGMA

0.00

4

+25؇C –40؇C

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

2

0

–2

–4

–6

–8

–10

MEAN –3 SIGMA

+85؇C

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

TEMPERATURE – ؇C

PHASE DIFFERENCE – Degrees

TPC 31. Distribution of VPHS Error vs. Input Phase

Difference, Three Sigma to Either Side of Mean, Frequency

1900 MHz, –40؇C, +25؇C, and +85؇C, Supply 5 V, Input

Levels P_INPA= P_INPB= –30 dBm

TPC 34. Change in VPHS Slope vs. Temperature, Three

Sigma to Either Side of Mean, Frequency 1900 MHz

10

8

10

+3 SIGMA

5

0

6

4

–5

+85؇C

+25؇C

2

0

–10

–3 SIGMA

–15

–2

–4

–6

–8

–10

–20

–25

–30

–35

–40

–40؇C

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

VPHS – mV/Degree

PHASE DIFFERENCE – Degrees

TPC 32. Distribution of VPHS Error vs. Input Phase Differ-

ence, Three Sigma to Either Side of Mean, Frequency

2200 MHz, –40؇C, +25؇C, and +85؇C, Input Levels –30 dBm

TPC 35. Change in Phase Center Point (PCP) vs.

Temperature, Three Sigma to Either Side of Mean,

Frequency 1900 MHz

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

18

15

12

9

6

3

0

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

0.75

0.80

0.85

0.90

0.95

1.00

1.05

PHASE DIFFERENCE – Degrees

PCP –V

TPC 33. Distribution of VPHS vs. Input Phase Differ-

ence, Three Sigma to Either Side of Mean, Frequency

900 MHz, Temperature between –40؇C and +85؇C, Input

Levels –30 dBm

TPC 36. Phase Center Point (PCP) Distribution, Frequency

900 MHz, 17,000 Units

REV. B

–11–

AD8302

16

14

12

10

8

100mV PER

VERTICAL

DIVISION

6

4

2

50ns HORIZONTAL

0

9.5

9.7

9.9

10.1

10.3

10.5

10.7

10.9

11.1

VPHS – mV/Degree

TPC 37. VPHS Slope Distribution, Frequency

900 MHz

TPC 40. VPHS Output Response to 40؇ Step with Nominal

Phase Shift of 90؇, Input Levels P_INPA= P_INPB= –30 dBm,

Frequency 1900 MHz,1 pF Filter Capacitor

10000

INPUT –50dBm

1000

INPUT –30dBm

10mV PER

VERTICAL

DIVISION

INPUT –10dBm

100

50ns HORIZONTAL

10

1k

10k

100k

1M

10M

100M

FREQUENCY – Hz

TPC 38. VPHS Output Response to 4؇ Step with Nominal

Phase Shift of 90؇, Input Levels –30 dBm, Frequency

1900 MHz, 25؇C, 1 pF Filter Capacitor

TPC 41. VPHS Output Noise Spectral Density vs. Frequency,

_INPA= –30 dBm, P_INPB= –10 dBm, –30 dBm, –50 dBm, and

90؇ Input Phase Difference

P

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

P

= –30dBm

INPA

P

= –15dBm

INPA

10mV PER

VERTICAL

DIVISION

P

= –45dBm

INPA

2␮s HORIZONTAL

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 39. VPHS Output Response to 4؇ Step with Nominal

Phase Shift of 90؇, Input Levels P_INPA= P_INPB= –30 dBm,

Supply 5 V, Frequency 1900 MHz, 25؇C, with 100 pF Filter

Capacitor

TPC 42. Phase Output vs. Input Phase Difference, P_INPA

=

P

_INPB, P_INPA= P_INPB+ 15 dB, P_INPA= P_INPB– 15 dB, Frequency

900 MHz

–12–

REV. B

AD8302

12

10

8

1.80

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

P

= –15dBm

P

= –30dBm

INPA

P

= –20dBm

INPA

P

= –45dBm

INPA

P

= –40dBm

INPA

6

4

2

P

= –30dBm

INPA

0

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 43. Phase Output Instantaneous Slope,

P_INPA= P_INPB, P_INPA= P_INPB+ 15 dB, P_INPA= P_INPB– 15 dB,

Frequency 900 MHz

TPC 46. Phase Output vs. Input Phase Difference,

P_INPA= P_INPB, P_INPA= P_INPB+ 10 dB, P_INPA= P_INPB– 10 dB,

Frequency 2200 MHz

1.80

12

P

= –20dBm

P

= –20dBm

INPA

1.62

1.44

1.26

1.08

0.90

0.72

0.54

0.36

0.18

0.00

10

8

P

= –40dBm

INPA

P

= –30dBm

INPA

P

= –40dBm

INPA

6

P

= –30dBm

INPA

4

2

0

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

PHASE DIFFERENCE – Degrees

TPC 47. Phase Output Instantaneous Slope, P_INPA= P_INPB

P_INPA= P_INPB+ 10 dB, P_INPA= P_INPB– 10 dB, Frequency

2200 MHz

,

TPC 44. Phase Output vs. Input Phase Difference,

P

_INPA= P_INPB, P_INPA= P_INPB+ 10 dB, P_INPA= P_INPB– 10 dB,

Frequency 1900 MHz, Supply 5 V

4000

3500

3000

2500

2000

1500

1000

500

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

12

10

REAL SHUNT Z (⍀)

P

= –30dBm

INPA

8

6

4

2

0

P

= –40dBm

INPA

SHUNT R

SHUNT C

CAPACITANCE SHUNT Z (pF)

P

= –20dBm

INPA

0

500

1000

1500

2000

2500

–180 –150 –120 –90 –60 –30

0

30 60 90 120 150 180

FREQUENCY – MHz

PHASE DIFFERENCE – Degrees

TPC 48. Input Impedance, Modeled as Shunt R in Parallel

with Shunt C

TPC 45. Phase Output Instantaneous Slope, P_INPA

P_INPB, P_INPA= P_INPB+ 10 dB, P_INPA= P_INPB– 10 dB,

Frequency 1900 MHz, Supply 5 V

=

REV. B

–13–

AD8302

8

18

15

12

9

6

4

2

0

6

–2

–4

–6

3

0

1.74

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

1.76

1.78

1.80

1.82

1.84

1.86

1.88

TEMPERATURE – ؇C

VREF –V

TPC 49. Change in VREF vs. Temperature, Three Sigma to

Either Side of Mean

TPC 51. VREF Distribution, 17,000 Units

120

100

80

60

40

20

0

1k

10k

100k

1M

10M

100M

FREQUENCY – Hz

TPC 50. VREF Output Noise Spectral Density vs.

Frequency

–14–

REV. B

AD8302

GENERAL DESCRIPTION AND THEORY

V_PHS=V_ΦΦ V

− Φ V

(3)

(

)

(

)

]

[

INA

INB

The AD8302 measures the magnitude ratio, defined here as

gain, and phase difference between two signals. A pair of

matched logarithmic amplifiers provide the measurement, and

their hard-limited outputs drive the phase detector.

where V_Φis the phase slope in mV/degree and Φ is each signal’s

relative phase in degrees.

Structure

Basic Theory

The general form of the AD8302 is shown in Figure 2. The

major blocks consist of two demodulating log amps, a phase

detector, output amplifiers, a biasing cell, and an output refer-

ence voltage buffer. The log amps and phase detector process

the high frequency signals and deliver the gain and phase infor-

mation in current form to the output amplifiers. The output

amplifiers determine the final gain and phase scaling. External

filter capacitors set the averaging time constants for the respec-

tive outputs. The reference buffer provides a 1.80 V reference

voltage that tracks the internal scaling constants.

Logarithmic amplifiers (log amps) provide a logarithmic com-

pression function that converts a large range of input signal

levels to a compact decibel-scaled output. The general math-

ematical form is:

V_OUT=V_SLPlog V /V_Z

(1)

(

)

IN

where V_INis the input voltage, V_Zis called the intercept (voltage),

and V_SLPis called the slope (voltage). It is assumed throughout

that log(x) represents the log10(x) function. V_SLPis thus the

volts/decade, and since a decade of voltage corresponds to

20 dB, V_SLP/20 is the volts/dB. V_Zis the value of input

signal that results in an output of zero and need not correspond

to a physically realizable part of the log amp signal range.

While the slope is fundamentally a characteristic of the log amp,

the intercept is a function of the input waveform as well.¹

Furthermore, the intercept is typically more sensitive to tem-

perature and frequency than the slope. When single log amps

are used for power measurement, this variability introduces

errors into the absolute accuracy of the measurement since the

intercept represents a reference level.

MFLT

VIDEO OUTPUT – A

+

VMAG

–

INPA

OFSA

60dB LOG AMPS

(7 DETECTORS)

MSET

PSET

PHASE

DETECTOR

COMM

–

OFSB

INPB

60dB LOG AMPS

(7 DETECTORS)

The AD8302 takes the difference in the output of two identical

log amps, each driven by signals of similar waveforms but at

different levels. Since subtraction in the logarithmic domain

corresponds to a ratio in the linear domain, the resulting

output becomes:

VPHS

+

PFLT

VREF

VIDEO OUTPUT – B

VPOS

BIAS

x3

1.8V

Figure 2. General Structure

V_MAG=V_SLPlog V_INA/V_INB

(2)

(

)

Each log amp consists of a cascade of six 10 dB gain stages with

seven associated detectors. The individual gain stages have 3 dB

bandwidths in excess of 5 GHz. The signal path is fully differen-

tial to minimize the effect of common-mode signals and noise.

Since there is a total of 60 dB of cascaded gain, slight dc offsets

can cause limiting of the latter stages, which may cause mea-

surement errors for small signals. This is corrected by a feedback

loop. The nominal high-pass corner frequency, f_HP, of this loop

is set internally at 200 MHz but can be lowered by adding external

capacitance to the OFSA and OFSB pins. Signals at frequencies

well below the high-pass corner are indistinguishable from dc

offsets and are also nulled. The difference in the log amp out-

puts is performed in the current domain, yielding by analogy to

Equation 2:

where V_INAand V_INBare the input voltages, V_MAGis the output

corresponding to the magnitude of the signal level difference,

and V_SLPis the slope. Note that the intercept, V_Z, has dropped

out. Unlike the measurement of power, when measuring a dimen-

sionless quantity such as relative signal level, no independent

reference or intercept need be invoked. In essence, one signal

serves as the intercept for the other. Variations in intercept due

to frequency, process, temperature, and supply voltage affect both

channels identically and hence do not affect the difference. This

technique depends on the two log amps being well matched

in slope and intercept to ensure cancellation. This is the case

for an integrated pair of log amps. Note that if the two signals

have different waveforms (e.g., different peak-to-average ratios)

or different frequencies, an intercept difference may appear, intro-

ducing a systematic offset.

I_LA= I_SLPlogV_INA/V_INB

(4)

(

)

where I_LAand I_SLPare the output current difference and the

characteristic slope (current) of the log amps, respectively. The

slope is derived from an accurate reference designed to be insen-

sitive to temperature and supply voltage.

The log amp structure consists of a cascade of linear/limiting

gain stages with demodulating detectors. Further details about

the structure and function of log amps can be found in data

sheets for other log amps produced by Analog Devices.²The

output of the final stage of a log amp is a fully limited signal

over most of the input dynamic range. The limited outputs from

both log amps drive an exclusive-OR style digital phase detector.

Operating strictly on the relative zero-crossings of the limited sig-

nals, the extracted phase difference is independent of the original

input signal levels. The phase output has the general form:

The phase detector uses a fully symmetric structure with respect

to its two inputs to maintain balanced delays along both signal

paths. Fully differential signaling again minimizes the sensitivity

to common-mode perturbations. The current-mode equivalent

to Equation 3 is:

I_PD= I_ΦΦ V

− Φ V

− 90°

(5)

(

)

(

)

[

]

INA

INB

NOTES

¹See the data sheet for the AD640 for a description of the effect of waveform on

the intercept of log amps.

where I_PDand I_Φare the output current and characteristic slope

associated with the phase detector, respectively. The slope is

derived from the same reference as the log amp slope.

²For example, see the data sheet for the AD8307.

REV. B

–15–

AD8302

VP

C7

Note that by convention, the phase difference is taken in the range

from –180° to +180°. Since this style of phase detector does not

distinguish between 90°, it is considered to have an unambiguous

180° phase difference range that can be either 0° to +180° centered

at +90° or 0° to –180° centered at –90°.

AD8302

R4

1

2

3

4

5

6

7

COMM

MFLT 14

VMAG 13

MSET 12

VREF 11

V

C1

MAG

C2

V

INPA

INA

R1

R2

The basic structure of both output interfaces is shown in Figure 3. It

accepts a setpoint input and includes an internal integrating/averag-

ing capacitor and a buffer amplifier with gain K. External access to

these setpoints provides for several modes of operation and enables

flexible tailoring of the gain and phase transfer characteristics. The

setpoint interface block, characterized by a transresistance R_F, gener-

ates a current proportional to the voltage presented to its input pin,

MSET or PSET. A precise offset voltage of 900 mV is introduced

internally to establish the center-point (V_CP) for the gain and phase

functions, i.e., the setpoint voltage that corresponds to a gain of 0 dB

and a phase difference of 90°. This setpoint current is subtracted

from the signal current, I_IN, coming from the log amps in the gain

channel or from the phase detector in the phase channel. The result-

ing difference is integrated on the averaging capacitors at either pin

MFLT or PFLT and then buffered by the output amplifier to the

respective output pins, VMAG and VPHS. With this open-loop

arrangement, the output voltage is a simple integration of the differ-

ence between the measured gain/phase and the desired setpoint:

OFSA

VPOS

OFSB

INPB

C4

C6

10

9

PSET

VPHS

PFLT

V

INB

V

PHS

C5

C3

8

COMM

C8

Figure 4. Basic Connections in Measurement Mode with

30 mV/dB and 10 mV/Degree Scaling

In the low frequency limit, the gain and phase transfer functions

given in Equations 4 and 5 become:

V_MAG= R_FI_SLPlogV_INA/V_INB+V or

(8a)

(8b)

(9)

(

)

CP

V_MAG= R I

/ 20 P_INA− P

+V

CP

(

) (

INA

)

F SLP

INB

V_PHS= –R I |Φ V

− Φ V

|–90° +V

(

)

(

)

(

)

F

Φ

INB

CP

V_OUT= R I − I_FB/ sT

(6)

(

) (

)

F

IN

which are illustrated in Figure 5. In Equation 8b, P_INAand P_INBare

the power in dBm equivalent to V_INAand V_INBat a specified refer-

ence impedance. For the gain function, the slope represented by

R_FI_SLPis 600 mV/decade or, dividing by 20 dB/decade, 30 mV/dB.

With a center point of 900 mV for 0 dB gain, a range of –30 dB to

+30 dB covers the full-scale swing from 0 V to 1.8 V. For the phase

function, the slope represented by R_FI_Φis 10 mV/degree. With a

center point of 900 mV for 90°, a range of 0° to 180° covers the

full-scale swing from 1.8 V to 0 V. The range of 0° to –180° covers

the same full-scale swing but with the opposite slope.

where I_FBis the feedback current equal to (V_SET– V_CP)/R_F, V_SET

is the setpoint input, and T is the integration time constant equal

to R_FC_AVE/K, where C_AVEis the parallel combination of the inter-

nal 1.5 pF and the external capacitor C_FLT

.

1.5pF

MFLT/PFLT

+

C

FLT

K

I

= I OR I

LA

VMAG/VPHS

IN

PD

–

V

= 900mV

+

CP

1.8V

I

FB

R

MSET/PSET

F

+

20k⍀

30mV/dB

Figure 3. Simplified Block Diagram of the Output Interface

900mV

V

CP

BASIC CONNECTIONS

Measurement Mode

The basic function of the AD8302 is the direct measurement of gain

and phase. When the output pins, VMAG and VPHS, are connected

directly to the feedback setpoint input pins, MSET and PSET, the

default slopes and center points are invoked. This basic connection

shown in Figure 4 is termed the measurement mode. The current

from the setpoint interface is forced by the integrator to be equal to

the signal currents coming from the log amps and phase detector.

The closed loop transfer function is thus given by:

0V

–30

0

+30

MAGNITUDE RATIO – dB

1.8V

+10mV/DEG

–10mV/DEG

V_OUT= I_INR_F+V_CP/ 1+ sT

(7)

(

) (

)

V

900mV

CP

The time constant T represents the single-pole response to the enve-

lope of the dB-scaled gain and the degree-scaled phase functions. A

small internal capacitor sets the maximum envelope bandwidth to

approximately 30 MHz. If no external C_FLTis used, the AD8302

can follow the gain and phase envelopes within this bandwidth. If

longer averaging is desired, C_FLTcan be added as necessary accord-

ing to T (ns) = 3.3 × C_AVE(pF). For best transient response with

minimal overshoot, it is recommended that 1 pF minimum value

external capacitors be added to the MFLT and PFLT pins.

0V

–180

–90

0

90

180

PHASE DIFFERENCE – Degrees

Figure 5. Idealized Transfer Characteristics for the Gain

and Phase Measurement Mode

–16–

REV. B

AD8302

Interfacing to the Input Channels

Dynamic Range

The single-ended input interfaces for both channels are identical.

Each consists of a driving pin, INPA and INPB, and an ac-

grounding pin, OFSA and OFSB. All four pins are internally

dc-biased at about 100 mV from the positive supply and should

be externally ac-coupled to the input signals and to ground. For

the signal pins, the coupling capacitor should offer negligible

impedance at the signal frequency. For the grounding pins, the

coupling capacitor has two functions: It provides ac grounding

and sets the high-pass corner frequency for the internal offset

compensation loop. There is an internal 10 pF capacitor to ground

that sets the maximum corner to approximately 200 MHz.

The corner can be lowered according the formula f_HP(MHz) =

2/C_C(nF), where C_Cis the total capacitance from OFSA or OFSB

to ground, including the internal 10 pF.

The maximum measurement range for the gain subsystem is lim-

ited to a total of 60 dB distributed from –30 dB to +30 dB. This

means that both gain and attenuation can be measured. The limits

are determined by the minimum and maximum levels that each

individual log amp can detect. In the AD8302, each log amp can

detect inputs ranging from –73 dBV [(223 µV, –60 dBm re: 50 Ω

to –13 dBV (223 mV, 0 dBm re: 50 Ω)]. Note that log

amps respond to voltages and not power. An equivalent power

can be inferred given an impedance level, e.g., to convert from

dBV to dBm in a 50 Ω system, simply add 13 dB. To cover

the entire range, it is necessary to apply a reference level to one log

amp that corresponds precisely to its midrange. In the AD8302,

this level is at –43 dBV, which corresponds to –30 dBm in a 50 Ω

environment. The other channel can now sweep from its low end,

30 dB below midrange, to its high end, 30 dB above midrange. If

the reference is displaced from midrange, some measurement

range will be lost at the extremes. This can occur either if the log

amps run out of range or if the rails at ground or 1.8 V are reached.

Figure 7 illustrates the effect of the reference channel level placement.

If the reference is chosen lower than midrange by 10 dB, then the

lower limit will be at –20 dB rather than –30 dB. If the reference chosen

is higher by 10 dB, the upper limit will be 20 dB rather than 30 dB.

The input impedance to INPA and INPB is a function of

frequency, the offset compensation capacitor, and package

parasitics. At moderate frequencies above f_HP, the input network

can be approximated by a shunt 3 kΩ resistor in parallel with a

2 pF capacitor. At higher frequencies, the shunt resistance

decreases to approximately 500 Ω. The Smith Chart in Figure 6

shows the input impedance over the frequency range 100 MHz

to 3 GHz.

OPT

MAX RANGE FOR V

= V

REF

1.80

100MHz

0.90

OPT

V > V

REF

V

< V

REF

900MHz

1.8GHz

2.2GHz

2.7GHz

3.0GHz

–30

0

+30

GAIN MEASUREMENT RANGE – dB

Figure 6. Smith Chart Showing the Input Impedance of a

Single Channel from 100 MHz to 3 GHz

Figure 7. The Effect of Offsetting the Reference Level Is to

Reduce the Maximum Dynamic Range

A broadband resistive termination on the signal side of the coupling

capacitors can be used to match to a given source impedance.

The value of the termination resistor, R_T, is determined by:

The phase measurement range is of 0° to 180°. For phase differ-

ences of 0° to –180°, the transfer characteristics are mirrored as

shown in Figure 5, with a slope of the opposite sign. The phase

detector responds to the relative position of the zero crossings

between the two input channels. At higher frequencies, the finite

rise and fall times of the amplitude limited inputs create an

ambiguous situation that leads to inaccessible dead zones at the

0° and 180° limits. For maximum phase difference coverage, the

reference phase difference should be set to 90°.

(10)

R_T= R_INR / R − R_S

(

)

S

IN

where R_INis the input resistance and R_Sthe source impedance.

At higher frequencies, a reactive, narrow-band match might be

desirable to tune out the reactive portion of the input impedance.

An important attribute of the two-log-amp architecture is that if

both channels are at the same frequency and have the same input

network, then impedance mismatches and reflection losses become

essentially common-mode and hence do not impact the relative

gain and phase measurement. However, mismatches in these

external components can result in measurement errors.

REV. B

–17–

AD8302

Cross Modulation of Magnitude and Phase

reference that determines the nominal center point, their

tracking with temperature, supply, and part-to-part variations

should be better in comparison to a fixed external voltage. If the

center point is shifted to 0 dB in the previous example where

the slope was doubled, then the range spans from –15 dB at

At high frequencies, unintentional cross coupling between signals

in Channels A and B inevitably occurs due to on-chip and board-

level parasitics. When the two signals presented to the AD8302

inputs are at very different levels, the cross coupling introduces

cross modulation of the phase and magnitude responses. If the two

signals are held at the same relative levels and the phase between

them is modulated then only the phase output should respond.

Due to phase-to-amplitude cross modulation, the magnitude out-

put shows a residual response. A similar effect occurs when the

relative phase is held constant while the magnitude difference is

modulated, i.e., an expected magnitude response and a residual

phase response are observed due to amplitude-to-phase cross

modulation. The point where these effects are noticeable depends

on the signal frequency and the magnitude of the difference. Typi-

cally, for differences <20 dB, the effects of cross modulation are

negligible at 900 MHz.

V

_MAG= 0 V to 15 dB at V_MAG= 1.8 V.

R1

10k⍀

1؉

NEW SLOPE = 30mV/dB

؋

VMAG

MSET

R1

20k⍀

VREF

20k⍀

Figure 9. The Center Point Is Repositioned with the Help

of the Internal Reference Voltage of 1.80 V

Modifying the Slope and Center Point

Comparator and Controller Modes

The default slope and center point values can be modified with

the addition of external resistors. Since the output interface

blocks are generalized for both magnitude and phase functions,

the scaling modification techniques are equally valid for both

outputs. Figure 8 demonstrates how a simple voltage divider

from the VMAG and VPHS pins to the MSET and PSET pins

can be used to modify the slope. The increase in slope is given by

1 + R1/(R2ʈ20 kΩ). Note that it may be necessary to account for

the MSET and PSET input impedance of 20 kΩ which has a 20%

manufacturing tolerance. As is generally true in such feedback

systems, envelope bandwidth is decreased and the output noise

transferred from the input is increased by the same factor. For

example, by selecting R1 and R2 to be 10 kΩ and 20 kΩ,

respectively, gain slope increases from the nominal 30 mV/dB

by a factor of 2 to 60 mV/dB. The range is reduced by a factor

of 2 and the new center point is at –15 dB, i.e., the range now

extends from –30 dB, corresponding to V_MAG= 0 V, to 0 dB,

corresponding to V_MAG= 1.8 V.

The AD8302 can also operate in a comparator mode if used in

the arrangement shown in Figure 10 where the DUT is the element

to be evaluated. The VMAG and VPHS pins are no longer

connected to MSET and PSET. The trip-point thresholds for the

gain and phase difference comparison are determined by the

voltages applied to pins MSET and PSET according to:

V_MSET(V ) = 30 mV dB ×Gain^SP(dB) + 900 mV

(11)

/

V_PSET(V ) = −10 mV ° × |Phase^SP(°)|–90° + 900 mV

/

(12)

(

)

where Gain^SP(dB) and Phase^SP(°) are the desired gain and

phase thresholds. If the actual gain and phase between the two

input channels differ from these thresholds, the V_MAGand V_PHS

outputs toggle like comparators, i.e.,

1.8V if Gain > Gain^SP

V_MAG

=

(13)

(14)

0V if Gain < Gain^SP

1.8V if Phase > Phase^SP

0V if Phase < Phase^SP

R1

VMAG

MSET

V_PHS

=

1؉

NEW SLOPE = 30mV/dB

؋

R2||R20k⍀

R1

R2

20k⍀

VP

Figure 8. Increasing the Slope Requires the Inclusion of a

Voltage Divider

C7

AD8302

R4

1

2

3

4

5

6

7

COMM

MFLT 14

VMAG 13

MSET 12

VREF 11

C1

C2

Repositioning the center point back to its original value of 0 dB

simply requires that an appropriate voltage be applied to the

grounded side of the lower resistor in the voltage divider. This

voltage may be provided externally or derived from the internal

reference voltage on pin VREF. For the specific choice of R2 =

20 kΩ, the center point is easily readjusted to 0 dB by connecting

the VREF pin directly to the lower pin of R2 as shown in Figure 9.

The increase in slope is now simplified to 1 + R1/10 kΩ. Since this

1.80 V reference voltage is derived from the same band gap

V

INPA

INA

MAG

R1

R2

V

OFSA

VPOS

OFSB

INPB

MSET

C4

C6

V

10

9

PSET

VPHS

PFLT

PSET

V

INB

PHS

C5

C3

8

COMM

C8

Figure 10. Disconnecting the Feedback to the Setpoint

Controls, the AD8302 Operates in Comparator Mode

–18–

REV. B

AD8302

The comparator mode can be turned into a controller mode by

closing the loop around the VMAG and VPHS outputs.

Figure 11 illustrates a closed loop controller that stabilizes the gain

and phase of a DUT with gain and phase adjustment elements.

If VMAG and VPHS are properly conditioned to drive gain and

phase adjustment blocks preceding the DUT, the actual gain and

phase of the DUT will be forced toward the prescribed setpoint

gain and phase given in Equations 11 and 12. These are essentially

AGC and APC loops. Note that as with all control loops of this kind,

loop dynamics and appropriate interfaces all must be considered

in more detail.

When the insertion phase is nominal, the VPHS output is 900 mV.

Deviations from the nominal are reported with a 10 mV/degree

scaling. Table I gives suggested component values for the

measurement of an amplifier with a nominal gain of 10 dB and

an input power of –10 dBm.

ATTEN

A

DC

A

VP

C7

AD8302

R4

1

2

3

4

5

6

7

COMM

MFLT 14

VMAG 13

MSET 12

VREF 11

C2

R5

C1

H

INPA

R1

R2

INPA

INPB

VMAG

MSET

⌬MAG

OFSA

VPOS

OFSB

INPB

MAG

C4

C6

SETPOINT

AD8302

“BLACK BOX”

PHASE

SETPOINT

PSET

10

9

PSET

VPHS

PFLT

VPHS

⌬⌽

R6

C8

C5

C3

8

COMM

Figure 11. By Applying Overall Feedback to a DUT Via

External Gain and Phase Adjusters, the AD8302 Acts

as a Controller

DC

B

ATTEN

B

Figure 12. Using the AD8302 to Measure the Gain and

Insertion Phase of an Amplifier or Mixer

APPLICATIONS

Measuring Amplifier Gain and Compression

The most fundamental application of AD8302 is the monitoring

of the gain and phase response of a functional circuit block such as

an amplifier or a mixer. As illustrated in Figure 12, directional

couplers, DC_Band DC_A, sample the input and output signals of

the “Black Box” DUT. The attenuators ensure that the signal

levels presented to the AD8302 fall within its dynamic range.

From the discussion in the Dynamic Range section, the optimal

choice places both channels at P_OPT= –30 dBm referenced to 50 Ω,

which corresponds to –43 dBV. To achieve this, the combination

of coupling factor and attenuation are given by:

Table I. Component Values for Measuring a 10 dB Amplifier

with an Input Power of –10 dBm

Component

Value

Quantity

R1, R2

R5, R6

C1, C4, C5, C6

C2, C8

C3

52.3 Ω

2

4

100 Ω

0.001 µF

Open

100 pF

1

2

C7

0.1 µF

(15)

(16)

C_B+ L_B= P − P

IN

OPT

AttenA

AttenB

DC_A, DC_B

10 dB (See Text)

1 dB (See Text)

20 dB

C_A+ L_A= P_IN+ GAIN_NOM− P_OPT

where C_Band C_Aare the coupling coefficients, L_Band L_Aare the

attenuation factors, and GAIN_NOMis the nominal DUT gain. If

identical couplers are used for both ports, then the difference in the

two attenuators compensates for the nominal DUT gain. When the

actual gain is nominal, the VMAG output is 900 mV, corresponding

to 0 dB. Variations from nominal gain appear as a deviation from

900 mV or 0 dB with a 30 mV/dB scaling. Depending on the nominal

insertion phase associated with DUT, the phase measurement may

require a fixed phase shift in series with one of the channels to bring

the nominal phase difference presented to the AD8302 near the

optimal 90° point.

The gain measurement application can also monitor gain and

phase distortion in the form of AM-AM (gain compression) and

AM-PM conversion. In this case, the nominal gain and phase

corresponds to those at low input signal levels. As the input level

is increased, output compression and excess phase shifts are

measured as deviations from the low level case. Note that the signal

levels over which the input is swept must remain within the dynamic

range of the AD8302 for proper operation.

REV. B

–19–

AD8302

Reflectometer

The measurement accuracy can be compromised if board

level details are not addressed. Minimize the physical distance

between the series connected couplers since the extra path

length adds phase error to ⌫. Keep the paths from the couplers

to the AD8302 as well matched as possible since any differences

introduce measurement errors. The finite directivity, D, of the

couplers sets the minimum detectable reflection coefficient, i.e.,

The AD8302 can be configured to measure the magnitude ratio

and phase difference of signals that are incident on and reflected

from a load. The vector reflection coefficient, ⌫, is defined as,

Γ = Reflected Voltage / Incident Voltage = Z − Z_O/ Z + Z_O(17)

(

) (

)

L

where Z_Lis the complex load impedance and Z_Ois the charac-

teristic system impedance.

|

_MIN(dB)|<|D(dB)|.

Γ

The measured reflection coefficient can be used to calculate the

level of impedance mismatch or standing wave ratio (SWR) of a

particular load condition. This proves particularly useful in diag-

nosing varying load impedances such as antennas that can degrade

performance and even cause physical damage. The vector

reflectometer arrangement given in Figure 13 consists of a pair

of directional couplers that sample the incident and reflected sig-

nals. The attenuators reposition the two signal levels within the

dynamic range of the AD8302. In analogy to Equations 15 and

16, the attenuation factors and coupling coefficients are given by:

SOURCE

Z

INCIDENT

WAVE

REFLECTED

WAVE

LOAD

20dB

1dB

R2

R1

C5 C6

C4 C1

C3

R4

(18)

(19)

C_B+ L_B= P − P

VP

IN

OPT

C7

C_A+ L_A= P_IN+ Γ_NOM− P

OPT

where ⌫_NOMis the nominal reflection coefficient in dB and is

negative for passive loads. Consider the case where the incident

signal is 10 dBm and the nominal reflection coefficient is –19 dB.

As shown in Figure 13, using 20 dB couplers on both sides and

–30 dBm for P_OPT, the attenuators for Channel A and B paths

are 1 dB and 20 dB, respectively. The magnitude and phase of

the reflection coefficient are available at the VMAG and VPHS

pins scaled to 30 mV/dB and 10 mV/degree. When ⌫ is –19 dB,

the VMAG output is 900 mV.

AD8302

C2

1

2

3

4

5

6

7

COMM

MFLT 14

⌫

INPA

VMAG 13

MSET 12

VREF 11

R5

R6

OFSA

VPOS

OFSB

INPB

10

9

PSET

VPHS

PFLT

⌫

8

COMM

C8

Figure 13. Using the AD8302 to Measure the Vector

Reflection Coefficient Off an Arbitrary Load

–20–

REV. B

AD8302

VP

C7

R4

AD8302

1

2

3

4

5

6

7

COMM MFLT 14

C2

GAIN

C1

Table II. P1 Pin Allocations

R5

INPA

VMAG 13

MSET 12

VREF 11

R1

1

2

3

Common

VPOS

Common

SW1

OFSA

VPOS

OFSB

INPB

GSET

R7

C4

C6

GND

INPB

VREF

R9

SW2

R8

R3

10

9

PSET

VPHS

PFLT

R2

PSET

C5

8

COMM

PHASE

C3

C8

R6

Figure 14. Evaluation Board Schematic

Figure 15a. Component Side Metal of Evaluation Board

Figure 15b. Component Side Silkscreen of Evaluation Board

Table III. Evaluation Board Configuration Options

Component

Function

Default Condition

P1

R1, R2

R3

Power Supply and Ground Connector: Pin 2 VPOS and Pins 1 and 3 Ground.

Input Termination. Provide termination for input sources.

VREF Output Load. This load is optional and is meant to allow the user to simulate

their circuit loading of the device.

Not Applicable

R1 = R2 = 52.3 Ω (Size 0402)

R3 = 1 kΩ (Size 0603)

R5, R6, R9

C3, C7, R4

Snubbing Resistor

R5 = R6 = 0 Ω (Size 0603)

R9 = 0 Ω (Size 0603)

C3 = 100 pF (Size 0603)

C7 = 0.1 µF (Size 0603)

R4 = 0 Ω (Size 0603)

Supply Decoupling

C1, C5

C2, C8

Input AC-Coupling Capacitors

Video Filtering. C2 and C8 limit the video bandwidth of the gain and phase

output respectively.

C1 = C5 = 1 nF (Size 0603)

C2 = C8 = Open (Size 0603)

C4, C6

SW1

Offset Feedback. These set the high-pass corner of the offset cancellation loop

and thus with the input ac-coupling capacitors the minimum operating frequency. C4 = C6 = 1 nF (Size 0603)

GSET Signal Source. When SW1 is in the position shown, the device is in gain

measure mode; when switched, it operates in comparator mode and a signal

must be applied to GSET.

SW1 = Installed

SW2

PSET Signal Source. When SW2 is in the position shown, the device is in phase

measure mode; when switched, it operates in comparator mode and a signal

must be applied to PSET.

SW1 = Installed

REV. B

–21–

AD8302

CHARACTERIZATION SETUPS AND METHODS

The general hardware configuration used for most of the AD8302

characterization is shown in Figure 16. The characterization board

is similar to the Customer Evaluation Board. Two reference-locked

R and S SMT03 signal generators are used as the inputs to

INPA and INPB, while the gain and phase outputs are monitored

using both a TDS 744A oscilloscope with 10× high impedance

probes and Agilent 34401A multimeters.

Phase

The majority of the VPHS output data was collected by generating

phase change, again by operating the two input sources with a

small frequency offset (normally 100 kHz) using the same

configuration shown in Figure 16. Although this method gives

excellent linear phase change, good for measurement of slope

and linearity, it lacks an absolute phase reference point. In the

curves showing swept phase, the phase at which the VPHS is the

same as VPHS with no input signal is taken to be –90° and all

other angles are references to there. Typical Performance Curves

show two figures of merit; instantaneous slope and error. Instanta-

neous slope, as shown in TPCs 43, 44, 45, and 47, was calculated

simply by taking the delta in VPHS over angular change for adjacent

measurement points.

Gain

The basic technique used to evaluate the static gain (VMAG)

performance was to set one source to a fixed level and sweep the

amplitude of the other source, while measuring the VMAG output

with the DMM. In practice, the two sources were run at 100 kHz

frequency offset and average output measured with the DMM to

alleviate errors that might be induced by gain/phase modulation

due to phase jitter between the two sources.

TEKTRONIX

TDS 744A

OSCILLOSCOPE

TEKTRONIX

VX1410A

The errors stated are the difference between a best fit line calcu-

lated by a linear regression and the actual measured data divided

by the slope of the line to give an error in V/dB. The referred to

25°C error uses this same method while always using the slope

and intercept calculated for that device at 25°C.

MULTIMETER/

OSCILLOSCOPE

R & S

SIGNAL GENERATOR

SMTO3

VMAG

INPA

INPB

3dB

HP 34401A

MULTIMETER

VREF

VPHS

EVB

R & S

SIGNAL GENERATOR

SMTO3

Response measurement made of the VMAG output used the

configuration shown in Figure 17. The variable attenuator,

Alpha AD260, is driven with a HP8112A pulse generator pro-

ducing a change in RF level within 10 ns.

SAME SETUP AS

V

MAG

Figure 16. Primary Characterization Setup

Noise spectral density measurements were made using a

HP3589A with the inputs delivered through a Narda 4032C

90° phase splitter.

TEKTRONIX

VX1410A

To measure the modulation of VMAG due to phase variation

again the sources were run at a frequency offset, f_OS, effectively

creating a continuous linear change in phase going through 360°

once every 1/f_OSseconds. The VMAG output is then measured

with a DSO. When perceivable, only at high frequencies and

large input magnitude differences, the linearly ramping phase

creates a near sinusoid output riding on the expected VMAG dc

output level. The curves in TPC 24 show the peak-to-peak out-

put level measured with averaging.

TEKTRONIX

TDS 744A

OSCILLOSCOPE

FIXED

ATTEN

VMAG

VREF

INPA

3dB

P

R & S

SIGNAL

GENERATOR

SMTO3

EVB

VARIABLE

ATTEN

VPHS

INPB

SPLITTER

PULSE

GENERATOR

Figure 17. VMAG Dynamic Performance Measurement Setup

–22–

REV. B

Data Sheet

AD8302

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 18. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD8302ARUZ

−40°C to +85°C

14-Lead Thin Shrink Small Outline Package [TSSOP]

RU-14

AD8302ARUZ-REEL

AD8302ARUZ-RL7

AD8302-EVALZ

¹Z = RoHS Compliant Part.

REVISION HISTORY

4/2018—Rev. A to Rev. B

Updated Outline Dimensions........................................................23

Moved Ordering Guide ..................................................................23

Changes to Ordering Guide...........................................................23

7/2002—Rev. 0 to Rev. A.

TPC 3 Through TPC 6 Replaced ....................................................6

registered trademarks are the property of their respective owners.

D02492-0-4/18(B)

Rev. B | Page 23 of 23


型号：	AD8302-EVALZ
厂家：	ADI
描述：	LFâ2.7 GHz RF/IF Gain and Phase Detector
文件：	总23页 (文件大小：581K)
中文：	中文翻译
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