AD8303 [ADI]
+3 V, Dual, Serial Input Complete 12-Bit DAC; +3 V，双通道，串行输入完整的12位DAC
| 型号： | AD8303 |
| 厂家： | 
ADI |
| 描述： | +3 V, Dual, Serial Input Complete 12-Bit DAC |
| 文件： | 总16页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3 V, Dual, Serial Input
Complete 12-Bit DAC
a
AD8303
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete Dual 12-Bit DAC
V
DD
Pretrimmed Internal Voltage Reference
Single +3 V Operation
0.5 mV/Bit with 2.0475 V Full Scale
Low Power: 9.6 mW
3-Wire Serial SPI Compatible Interface
Power Shutdown IDD < 1 A
Compact SO-14, 1.75 mm Height Package
R
E
OP
V
DAC A
R
AMP
A
OUTA
D
A
C
En
G
I
S
T
E
R
CS
CLK
A
D
REF
BUF
B
E
F
R
E
G
I
S
T
E
R
SDI
(DATA)
P
R
A
N
D
G
A
P
S
H
I
F
T
E
R
E
N
C
E
V
REF
APPLICATIONS
R
E
G
I
S
T
E
R
REF
BUF
Portable Communications
Digitally Controlled Calibration
Servo Controls
D
D
A
C
LDA
LDB
B
PC Peripherals
OP
AMP
B
DAC B
V
OUTB
P
R
AD8303
RS
SHDN
DGND
MSB
AGND
GENERAL DESCRIPTION
A double buffered serial data interface offers high speed, three-
wire, DSP and SPI microcontroller compatible inputs using
data in (SDI), clock (CLK) and load strobe (LDA + LDB)
pins. A chip-select (CS) pin simplifies connection of multiple
DAC packages by enabling the clock input when active low.
Additionally, an RS input sets the output to zero scale or to 1/2
scale based on the level applied to the MSB pin. A power
shutdown feature reduces power dissipation to less than 3 µW.
The AD8303 is a complete (includes internal reference) dual,
12-bit, voltage output digital-to-analog converter designed to
operate from a single +3 volt supply. Built using a CBCMOS
process, this monolithic DAC offers the user low cost and ease-
of-use in single-supply +3 volt systems. Operation is guaranteed
over the supply voltage range of +2.7 V to +5.5 V making this
device ideal for battery operated applications.
The 2.0475 V full-scale voltage output is laser-trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 3 mA.
The AD8303 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8303s are available in plastic
DIP and low profile 1.75 mm height SO-14 surface mount
packages. For single-channel DAC applications, see the
AD8300 which is offered in the 8-lead DIP and SO-8 packages.
1.0
2
V
= +5V
V
= +5V
DD
= –40°C, +25°C, +85°C
DD
0.8
0.6
T
A
1.5
1
–40°C
0.4
+25°C
0.5
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1
+85°C
–1.5
–2
0
1024
2048
3072
4096
0
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
DIGITAL INPUT CODE – Decimal
Figure 2. Linearity Error vs. Digital Code and Temperature
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD8303–SPECIFICATIONS
(@ VDD = +2.7 V to +3.6 V, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
+3 V OPERATION
Parameter
Symbol Condition
Min Typ1 Max Units
STATIC PERFORMANCE
Resolution2
N
INL
DNL
DNL
VZSE
12
–2
Bits
LSB
+3/4 LSB
+1 LSB
+4.5 mV
Relative Accuracy2
±1/2
+2
Differential Nonlinearity2
Differential Nonlinearity2
Zero-Scale Error
Monotonic, TA = +25°C
Monotonic
–3/4 ±1/4
–1
±1/2
1.25
Data = 000H
Data = FFFH
Full-Scale Voltage3
Full-Scale Tempco3, 4
VFS
TCVFS
2.039 2.0475 2.056 Volts
2
16
ppm/°C
ANALOG OUTPUTS
Output Current
IOUT
ROUT
CL
Data = 800H, ∆VOUT < 3 mV
Data = 000H
±3
mA
Ω
pF
Output Resistance to GND
30
500
Capacitive Load4
No Oscillation3
REFERENCE OUTPUT
Output Voltage
VREF
Load > 1 MΩ
1
V
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance4
VIL
VIH
IIL
0.6
V
V
µA
pF
2.1
10
10
CIL
INTERFACE TIMING SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Reset Pulse Width
Load Setup
tCH
tCL
tLDW
tDS
tDH
tRS
tLD1
tLD2
tCSS
tCSH
40
40
40
15
15
40
15
40
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load Hold
Select
Deselect
AC CHARACTERISTICS4
Voltage Output Settling Time6
Voltage Output Settling Time6
Shutdown Recovery Time
Output Slew Rate
tS
tS
tDSR
SR
Q
To ±0.1% of Full Scale
To ±1 LSB of Final Value
To ±0.1% of Full Scale
4
µs
µs
µs
V/µs
nV/s
nV/s
14
10
2.0
15
15
Data = 000H to FFFH to 000H
DAC Glitch
Digital Feedthrough
Q
SUPPLY CHARACTERISTICS
Power Supply Range
Shutdown Current
VDD RANGE DNL < ±1 LSB
IDD_SD SHDN = 0, No Load, VIL = 0 V, TA = +25°C
IDD
PDISS
PSS
2.7
5.5
1
3.2
9.6
V
0.02
2
6
µA
mA
mW
Supply Current7
VDD = 3 V, VIL = 0 V, No Load
VDD = 3 V, VIL = 0 V, No Load
∆VDD = ± 5%
Power Dissipation
Power Supply Sensitivity
0.001 0.004 %/%
NOTES
1Typical readings represent the average value of room temperature operation.
21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.
7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.
Specifications subject to change without notice.
–2–
REV. 0
SPECIFICATIONS
AD8303
(@ VDD = +5 V ؎ 10%, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
+5 V OPERATION
Parameter
Symbol Condition
Min Typ1 Max Units
STATIC PERFORMANCE
Resolution2
N
INL
DNL
DNL
VZSE
12
–2
–3/4
–1
Bits
LSB
LSB
LSB
mV
Relative Accuracy2
±1/2
±1/4
±1/2
1.25
+2
+3/4
+1
Differential Nonlinearity2
Differential Nonlinearity2
Zero-Scale Error
Monotonic, TA = +25°C
Monotonic
Data = 000H
Data = FFFH
+4.5
Full-Scale Voltage3
Full-Scale Tempco3, 4
VFS
TCVFS
2.039 2.0475 2.056 Volts
16
ppm/°C
ANALOG OUTPUTS
Output Current
IOUT
ROUT
CL
Data = 800H, ∆VOUT < 3 mV
Data = 000H
No Oscillation
±3
mA
Ω
pF
Output Resistance to GND
30
500
Capacitive Load4
REFERENCE OUTPUT
Output Voltage
VREF
Load > 1 MΩ
1
V
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance4
VIL
VIH
IIL
0.8
V
V
µA
pF
2.4
10
10
CIL
INTERFACE TIMING SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Reset Pulse Width
Load Setup
tCH
tCL
tLDW
tDS
tDH
tRS
tLD1
tLD2
tCSS
tCSH
30
30
30
15
15
30
15
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load Hold
Select
Deselect
AC CHARACTERISTICS4
Voltage Output Settling Time6
Voltage Output Settling Time6
Shutdown Recovery Time
Output Slew Rate
tS
tS
tSDR
SR
Q
To ±0.1% of Full Scale
4
µs
µs
µs
V/µs
nV s
nV s
To ±1 LSB of Final Value5
To ±0.1% of Full Scale
12
10
2
15
15
Data = 000H to FFFH to 000H
DAC Glitch
Digital Feedthrough
Q
SUPPLY CHARACTERISTICS
Power Supply Range
Shutdown Supply Current
Positive Supply Current7
Power Dissipation
VDD RANGE DNL < ±1 LSB
IDD_SD SHDN = 0, No Load, VIL = 0 V, TA = +25°C
IDD
PDISS
PSS
2.7
3.0
0.02
2.1
5.5
1
3.4
17
V
µA
mA
mW
VDD = 5 V, VIL = 0 V, No Load
VDD = 5 V, VIL = 0 V, No Load
∆VDD = ± 10%
10.5
Power Supply Sensitivity
0.001 0.004 %/%
NOTES
1Typical readings represent the average value of room temperature operation.
21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.
7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.
Specifications subject to change without notice.
REV. 0
–3–
AD8303
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . . (TJ MAX–TA)/θJA
Thermal Resistance θJA
Temperature Package
Package
Model
DNL Range
Description Option
AD8303AN ±0.75 –40°C to +85°C 14-Pin P-DIP N-14
AD8303AR ±0.75 –40°C to +85°C 14-Lead SOIC R-14
The AD8303 contains 700 transistors. The die size measures 70 mil × 99 mil.
14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . 103°C/W
14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (TJ MAX
) . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . .+300°C
*Stress above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
SDI
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
tCSS
tCSH
CS
tLD2
LDA, B
tLD1
SDI
tDS
tDH
tCL
CLK
tCH
tLDW
LDA, B
RS
tRS
tS
FS
±1 LSB
ERROR BAND
V
OUT
ZS
tS
a.
b.
SHDN
tSDR
I
DD
Figure 3. Timing Diagrams
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8303 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD8303
Table I. Control-Logic Truth Table
CS CLK RS
MSB SHDN LDA/B Serial Shift Register Function
DAC Register Function
H
L
L
X
L
H
↑+
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
L
↑+
L
↑+
X
X
X
X
X
X
X
X
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
↓–
L
X
H
X
H
X
No Effect
No Effect
No Effect
Latched
Latched
Latched
L
Shift-Register-Data Advanced One Bit Latched
↑+
H
H
X
X
X
X
X
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with 800H
Latched with 800H
Loaded with All Zeros
Latched All Zeros
X
X
No Effect
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2Do not clock in serial data while LDA or LDB is LOW.
PIN DESCRIPTIONS
Pin No.
Name
Function
1
2
AGND
VOUTA
Analog Ground.
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
3
VREF
Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual
ground.
4
5
DGND
Digital Ground
CS
Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB
operation.
6
7
8
CLK
SDI
Clock Input, positive edge clocks data into shift register.
Serial Data Input, input data loads directly into the shift register.
LDA
Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active
low input. See Control Logic Truth Table for operation.
9
RS
Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input.
10
LDB
Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active
low input. See Control Logic Truth Table for operation.
11
12
MSB
Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin
is strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.
SHDN
Active low shutdown control input. Does not affect register contents as long as power is present on VDD
.
13
14
VDD
VOUTB
Positive power supply input. Specified range of operation +2.7 V to +5.5 V
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
PIN CONFIGURATION
14-Pin P-DIP (N-14)
14-Lead SOIC (R-14)
AGND
1
2
3
4
5
6
7
14
13
12
11
V
V
OUTB
V
OUTA
DD
V
SHDN
REF
AD8303
TOP VIEW
(Not to Scale)
DGND
CS
MSB
10 LDB
9
8
RS
CLK
SDI
LDA
REV. 0
–5–
AD8303–Typical Performance Characteristics
7
6
5
4
3
2
1
0
120
POSITIVE
CURRENT
LIMIT
T
A
= +25°C
V
= +5V
DD
T
= +25°C
A
DATA = 000
H
80
40
NBW = 635kHz
100
90
DATA = 800
H
V
= +5V
DD
0
R
L
TIED TO
+1.024V
V
= +3V
DD
–40
–80
–120
10
0%
NEGATIVE
CURRENT
LIMIT
TIME = 100µs/DIV
0
1
2
3
4
5
0
1
2
LOGIC VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
Figure 5. Broadband Noise
Figure 6. Supply Current vs. Logic
Input Voltage
Figure 4. IOUT vs. VOUT
75
60
45
30
15
V
= +5V ± 10%
DD
50mV
1V
5µs
100
90
100
90
T
A
= +25°C
V
V
OUT
OUT
DATA = 800
H
V
= +3V ± 10%
DD
LD
LD
10
10
0%
0%
5V
200ns
5V
0
10
CODE 800 TO 7FF
H
H
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 7. Power Supply Rejection
vs. Frequency
Figure 8. Midscale Transition
Performance
Figure 9. Large Signal Settling Time
120
2.5
TUE = ∑ (INL+ZS+FS)
NO LOAD
SS = 200 UNITS
SS = 200 UNITS
NORMALIZED TO +25°C
10mV
100
2.0
V
= +2.7V
DD
100
90
80
60
40
20
0
1.5
V
OUT
1.0
0.5
0
V
= +5.5V
DD
V
= +2.7V
DD
10
0%
CLK
2V
1µs
–0.5
–55 –35 –15
–5 –3 –1
1
3
5
7
9 11 13 15
5
25 45 65 85 105 125
TOTAL UNADJUSTED ERROR – LSB
TEMPERATURE – °C
Figure 12. Full-Scale Voltage Drift
vs. Temperature
Figure 11. Total Unadjusted
Error Histogram
Figure 10. Clock Feedthrough vs.
Time
REV. 0
–6–
AD8303
2.0
1.5
10
2
1.5
1
NO LOAD
SS = 200 UNITS
NORMALIZED TO +25°C
V
= +2.7V
DD
SS = 212 UNITS
V
= +5V
DD
DATA = FFF
H
V
= +2.7V
DD
1.0
0.5
1
0.5
0
V
DD
= +4.5V
FULL SCALE
(DATA = FFF
)
H
0.0
–0.5
–1.0
–0.5
–1
ZERO SCALE
(DATA = 000
)
H
0.1
–55 –35 –15
5
25 45 65 85 105 125
1
10
100
1k
10k
100k
0
100
200
300
400
500
600
TEMPERATURE – °C
HOURS OF OPERATION AT +150°C
FREQUENCY – Hz
Figure 13. Zero-Scale Voltage Drift
vs. Temperature
Figure 14. Output Voltage Noise
Density vs. Frequency
Figure 15. Long-Term Drift
Accelerated by Burn-In
30
6
70
60
50
40
30
20
10
0
χ
χ
+2σ
V
V
= +5.5V,
DD
= 2.4V, DATA = FFF
25
20
15
10
5
LOGIC
H
V
= +2.7V
DD
SS = 200 UNITS
= –40 TO +85°C
5
4
3
2
1
T
A
V
V
= +3.6V,
= 2.1V, DATA = FFF
DD
LOGIC
H
χ
–2σ
V
= +5V
DD
SS = 212 UNITS
V
V
= +3.0V OR +5.0V,
= 0V, DATA = 000
DD
LOGIC
H
0
0
100
200
300
400
500
600
120
140
–60 –40 –20
0
20 40 60 80 100
–40 –32 –24 –16 –8
0
8
16 24
HOURS OF OPERATION AT +150°C
TEMPERATURE – °C
TEMPERATURE COEFFICIENT – ppm/°C
Figure 16. Shutdown Current vs.
Time Accelerated by Burn-In
Figure 17. Supply Current vs.
Temperature
Figure 18. Full-Scale Output
Tempco Histogram
1000
500mV
500mV
100
100
90
90
V
V
OUT
OUT
100
V
= +5.5V
DD
10
10
0%
SHDN
0%
SHDN
1µs
5V
1µs
5V
10
–55 –35 –15
5
25 45 65 95 105 125
TEMPERATURE – °C
Figure 19. Shutdown Current vs.
Temperature
Figure 20. Shutdown Recovery Time
Figure 21. Shutdown Time
REV. 0
–7–
AD8303
THEORY OF OPERATION
OUTPUT SECTION
The AD8303 is a complete, ready-to-use, dual, 12-bit digital-to-
analog converter. Only one +2.7 V to +5.5 V power supply is
necessary for operation. It contains two voltage-switched, 12-bit,
laser-trimmed digital-to-analog converters, a curvature-
corrected bandgap reference, rail-to-rail output op amps, input
shift register, and two DAC registers. The serial data interface
consists of a serial data input (SDI), clock (CLK), chip select
(CS) and two DAC load strobe pins (LDA and LDB).
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 23 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
The rail-to-rail output stage permits operation at supply
voltages down to +2.7 V. The N-channel output pull-down
MOSFET shown in Figure 23 has a 35 Ω ON resistance which
sets the sink current capability near ground. In addition to
resistive load driving capability, the amplifier has also been
carefully designed and characterized for up to 500 pF capacitive
load driving capability.
For battery operation and similar low power applications, a
shutdown feature (SHDN) is available to reduce power supply
current to less than 1 µA. In addition an asynchronous reset pin
(RS) will set both DAC outputs to either zero volts or to
midscale, depending on the logic value applied to the MSB pin.
This function is useful for power-on reset or system failure
recovery to a known state.
V
DD
P-CH
N-CH
D/A CONVERTER SECTION
Each of the two DACs is a 12-bit device with an output that
swings from GND potential to 0.4 V generated from the internal
bandgap voltage (Figure 22). Each DAC uses a laser-trimmed
segmented R-2R ladder that is switched by n-channel
MOSFETs. The output voltage of the DAC has a constant
resistance independent of digital input code. The DAC output is
internally connected to the rail-to-rail output op amp.
V
OUT
AGND
Figure 23. Equivalent Analog Output Circuit
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output
performance of full-scale versus temperature, which is dominated
by the reference performance.
V
REF
1.0V
BANDGAP
REF
2kΩ
0.4V
FS
12-BIT DAC
1.0V
0.4V
V
OUT
10kΩ
2.047V
FS
10kΩ
2.5kΩ
VREF Output
The internal reference drives two resistor-divider networks. One
divider provides a 0.4 V reference for the DAC. The second
divider is trimmed to 1.0 V and is available at the VREF pin. The
VREF output is useful for ratiometric applications, and also for
generating a “false ground” or bipolar offset. See Figures 30
and Figure 31 for typical applications. Since VREF has a high
output impedance, it must be buffered if it is required to deliver
current to an external load.
Figure 22. AD8303 Equivalent Schematic of Analog Section
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power
consumption, precision amplifier. This low power amplifier
contains a differential PNP pair input stage that provides low
offset voltage and low noise, as well as the ability to amplify the
zero-scale DAC output voltages, The rail-to-rail amplifier is
configured with a gain of approximately five in order to set the
2.0475 volt full-scale output (0.5 mV/LSB). An equivalent
circuit schematic for the amplifier section is shown in Figure 22.
The op amp has a 4 µs typical settling time to 0.1% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also, negative transition settling time to
within the last 6 LSBs of zero volts has an extended settling
time. See the oscilloscope photos in the typical performances
section of this data sheet.
–8–
REV. 0
AD8303
POWER SUPPLY
Whether or not a separate power supply trace is available,
however, generous supply bypassing will reduce supply-line
induced errors. Local supply bypassing consisting of a 10 µF
tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor
is recommended in all applications (Figure 25).
The very low power consumption of the AD8303 is a direct
result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic, and the low noise, tight matching of the complementary
bipolar transistors, excellent analog accuracy is achieved.
+2.7V TO +5.5V
One advantage of the rail-to-rail output amplifiers used in the
AD8303 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from +2.7 V to +5.5 V.
If reduced linearity and source current capability near full scale
can be tolerated, operation of the AD8303 is possible down to
+2.7 V.
13
7
6
V
10µF
0.1µF
DD
SDI
CLK
CS
2
V
OUTA
5
8
LDA
LDB
RS
AD8303
14
V
10
9
OUTB
11
12
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products, such as the AD8303, require a well
filtered power source. Since the AD8303 operates from a single
+3 V to +5 V supply, it seems convenient to simply tap into the
digital logic power supply. Unfortunately, the logic supply is
often a switch-mode design, which generates noise in the
20 kHz to 1 MHz range. In addition, fast logic gates can
generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances. The power supply noise
generated thereby means that special care must be taken to
insure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when addressing
the power supply grounding and bypassing of the AD8303.
MSB
SHDN
AGND DGND
1
4
TO ANALOG GROUND
Figure 25. Recommended Supply Bypassing for the
AD8303
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure (Figure 26) that allows logic input voltages to exceed
the VDD supply voltage. This feature can be useful if the user is
driving one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8303 on a +3 V power
supply. If this mode of interface is used, make sure that the VOL
of the 5 V CMOS meets the VIL input requirement of the
AD8303 operating at 3 V. See Figure 6 for a graph for digital
logic input threshold versus operating VDD supply voltage.
The AD8303 should be powered directly from the system power
supply. This arrangement, shown in Figure 24, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients. Analog and
digital ground pins of the AD8303 should be connected
together directly at the IC package.
V
DD
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
LOGIC
IN
+5V
TTL/CMOS
LOGIC
GND
CIRCUITS
100µF
ELECT.
10-22µF
TANT.
0.1µF
CER.
+5V
RETURN
Figure 26. Equivalent Digital Input ESD Protection
For power consumption-sensitive applications, it is important to
note that the internal power consumption of the AD8303 is
strongly dependent on the actual logic input voltage levels
present in the SDI, CLK, CS, LDA, LDB, SHDN, RS and
MSB pins. Since these inputs are standard CMOS logic
structures, they contribute static power dissipation which
depends on the actual driving logic VOH and VOL voltage levels.
Consequently, using CMOS logic versus TTL will provide
minimal dissipation in the static state.
+5V
POWER SUPPLY
Figure 24. Use Separate Traces to Reduce Power Supply
Noise
REV. 0
–9–
AD8303
MSB
12
DAC REGISTER A
DAC A
V
OUTA
RESET LOAD
SDI
D
12-BIT SHIFT
REGISTER
12
CLK
CLK
Q11–Q0
en
MSB
CS
12
DAC REGISTER B
DAC B
V
OUTB
AD8303
RESET LOAD
MSB RS LDA
LDB
SHDN
Figure 27. AD8303 Digital Section Functional Block Diagram
DIGITAL INTERFACE
Separate Load pins (LDA and LDB) are provided to control the
flow of data from the shift register to the DAC registers. After
the new value is loaded in the serial-input register, it can be
asynchronously transferred to either DAC register by strobing
the appropriate Load pin (LDA or LDB). The Load pins are
level sensitive, so they should be returned high before any new
data is loaded into the serial-input register.
The AD8303 has a double-buffered serial data input. The
serial-input register is separate from the two DAC registers,
which allows preloading of a new data value into the serial
register without disturbing the present DAC values. A
functional block diagram of the digital section is shown in
Figure 27, while Table I contains the truth table for the control
logic inputs.
RESET (RS) AND MSB PINS
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit DAC value. If additional
bits are clocked into the shift register, for example when a µC
sends two 8-bit bytes, the MSBs are ignored (Figure 28). The
CLK pin is only enabled when Chip Select (CS) is low. If only
one AD8303 is connected to a serial data bus, then CS can be
tied (hardwired) to ground.
The RS pin forces both of the DAC registers to a known state,
based on the logic level on the MSB pin. If MSB is a logic zero,
then forcing RS low will set the DAC latches to all zeros and the
DAC output voltage will be zero volts. If MSB is a logic one, then
RS will force the DAC latches to one-half scale (800H) and the
DAC outputs will be 1.024 V. The half-scale reset is useful for
systems where the DAC output is referenced to a “false
ground” (see the Generating Bipolar Outputs with a Single
Supply section of this data sheet for more information).
BYTE 1
BYTE 2
The reset function is useful for setting the DAC outputs to zero
at power-up or after a power supply interruption. Test systems
and motor controllers are two of many applications which
benefit from powering up to a known state. The reset pulse can
be generated by the microprocessor’s power-on RESET signal,
by an output from the microprocessor (Figure 33), or by an
external resistor and capacitor (Figure 34).
MSB
B15 B14 B13 B12 B11 B10 B9 B8 B7
D11 D10 D9 D8 D7
LSB MSB
LSB
B6 B5 B4 B3 B2 B1 B0
D6 D5 D4 D3 D2 D1 D0
X
X
X
X
D11–D0: 12-BIT DAC VALUE
X = DON'T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC
RS and MSB have level-sensitive thresholds. The RS input
overrides other logic inputs (specifically, LDA and LDB).
However, LDA and LDB should be set high before RS goes
high. If LDA or LDB are kept low, then the contents of the shift
register will be transferred to the DAC register as soon as RS
goes high.
Figure 28. Typical AD8303-Microprocessor Serial Data
Input Format
–10–
REV. 0
AD8303
SHUTDOWN (SHDN)
GENERATING “BIPOLAR” OUTPUTS WITH A SINGLE
SUPPLY
The shutdown feature is activated when SHDN is pulled low.
While the AD8303 is in shutdown mode, the voltage reference,
DACs, and output amplifiers are all turned off. Supply current
is less than 1 µA. The DAC output voltage goes to 0 V, pulled
to GND by the 12.5 kΩ feedback resistors (Figure 22).
To maximize output signal swings in single supply operation,
many circuit designs employ a “false-ground” configuration.
This method defines a voltage, usually at one half of full scale or
at one half of the power supply, as the “ground” reference.
Signals are then measured differentially from the false ground,
which produces a “quasi-bipolar” output swing.
If power (i.e., VDD) is maintained to the AD8303 during
shutdown, the value stored in the DAC input latches will not
change. When the SHDN pin is driven high, the DACs will
return to the same voltages as before shutdown. The CMOS
logic section of the AD8303 remains active while SHDN is low.
Thus, new data can be loaded while the DACs are shut down
and, when SHDN goes high, the DACs will assume the new
output voltage. The AD8303 recovers from shutdown very
quickly. The voltage output settling time after shutdown is
typically only a few microseconds longer than the normal
settling time (Figure 20).
The AD8303’s voltage reference output, combined with an op
amp, can provide a temperature compensated false-ground
reference, as shown in Figure 30. The op amp amplifies the
AD8303’s 1.0 V reference by 1.024 to provide an analog
common (false ground) at one-half scale (1.024 V). With this
method, the DAC output is ±1.024 V (referenced to the false
ground). The “Quasi-Bipolar” code table is given in Table III.
+3V
13
V
+3V TO +5V
DD
2
V
V
= ±1.024V
OUTA
OUT
13
(REFERENCED TO
SIGNAL GROUND)
+3V
0.1µF
10µF
AD8303
V
3
7
6
DD
V
SDI
CLK
CS
100Ω
REF
SIGNAL GROUND
(FALSE GROUND, +1.024V)
OP193
5
AGND DGND
AD8303
8
1
4
0V ≤ V
≤ 2.0475V
LDA
LDB
RS
OUT
, V
OUTA OUTB
2, 14
14
10
9
V
V
0.022µF
OUTA
500pF
2kΩ
11
12
V
OUTB
MSB
SHDN
R1
2.4kΩ
R2A
1µF
97.6kΩ
AGND DGND
4
R2B*
2kΩ
1
*ZERO-SCALE TRIM
Figure 29. Unipolar Output Operation
Figure 30. A False-Ground Generator
UNIPOLAR OUTPUT OPERATION
Table III. Quasi-Bipolar Code Table
This is the basic mode of operation for the AD8303. As shown
in Figure 29, the AD8303 has been designed to drive loads as
low as 2 kΩ in parallel with 500 pF. The code table for this
operation is shown in Table II.
DAC
Output Common
Voltage (False-Ground) Analog
Analog
Hexadecimal
Number
Decimal
Number In
“Bipolar”
in DAC Register DAC Register (V)
Voltage (V)
Voltage (V)
Table II. Unipolar Code Table
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.0475 1.024
1.0245 1.024
1.024 1.024
1.0235 1.024
1.024
+1.2035
0.0005
0
–0.0005
–1.024
Hexadecimal Number Decimal Number Analog Output
in DAC Register
in DAC Register
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.0475
1.0245
1.024
1.0235
0
0
Since the AD8303’s reference voltage output limits are typical, a
trim potentiometer is included so that the “false-ground” output
can be adjusted to exactly 1.024 V. To maintain accuracy,
resistors R1 and R2A must be of the same type (preferably
metal film) to insure temperature coefficient matching. The
circuit includes compensation to allow for a 1 µF bypass
capacitor at the false-ground output. The benefit of a large
capacitor is that not only does the false ground present a very
low dc resistance to the load, but its ac impedance is low as
well.
REV. 0
–11–
AD8303
BIPOLAR OUTPUT OPERATION
important to maintain accuracy. Resistor pairs R1-R2 and
R3-R4 should be selected to match within 0.01%. In addition,
these resistors must be of the same type (preferably metal film)
to insure temperature coefficient matching. Mismatching
between R1 and R2 causes offset and gain errors while an R3 to
R4 mismatch yields gain errors.
Although the AD8303 has been designed for single-supply
operation, the output can also be configured for bipolar
operation. A typical circuit is shown in Figure 31. This circuit
uses the AD8303’s internal voltage reference to generate a
bipolar offset. Since VREF must source current in this
application, one half of an OP293 dual op amp is used as a
buffer. The other op amp then amplifies the DAC output
voltage to produce a bipolar output swing. The output voltage is
coded in offset binary and is given by:
GENERATING A NEGATIVE SUPPLY VOLTAGE
Some applications may require a bipolar output configuration,
as shown in Figure 31, but only have a single power supply rail
available. This is very common in data acquisition systems using
microprocessor-based systems. In these systems, +12 V, +15 V,
and/or +5 V only are available. Single supply rails are, of course,
common in battery-powered systems. Shown in Figure 32 is a
method of generating a negative supply using a single IC and
two capacitors. The ADM8660 employs a charge pump
technique to invert supply voltages as low as 1.5 V. A shutdown
feature on the ADM8660 complements the shutdown of the
AD8303. Note, however, that the ADM8660 requires about
500 µs to turn on after exiting the shutdown state.
R4
R2
R1
R2
R1
V
= 0.5 mV × Digital Code ×
× 1+
–1.0V ×
O
R3 + R4
where 0.5 mV represents the pretrimmed value for one LSB of
the AD8303, Digital Code is the digital code sent to the DAC,
and 1.0 V is the AD8303 reference voltage.
+3V
13
V
R2
OPTIONAL
R1
10kΩ
20.48kΩ ZERO TRIM
DD
7
6
3
SDI
V
REF
1/2
OP293
+3V
8
CLK
5
+3V
1/2
CS AD8303
R3
10kΩ
8
OP293
V+
–3V
10µF
LDA
2
4
5
7
V
= ±2.048V
2
OUT
CAP+
CAP–
OSC
10
9
V
OUTA
LDB
RS
ADM8660
10µF
–3V
R4
19.08kΩ
14
11
12
SHUTDOWN
V
OUTB
MSB
SHDN
OPTIONAL
FULL-SCALE
TRIM
LV
6
GND
3
FC
1
AGND DGND
4
1
SHDN FROM AD8303
1/6
74HC04
Figure 31. Bipolar Output Operation
Figure 32. Generating a Negative Supply Voltage
For a ±2.048 V full scale using the circuit values shown, the
transfer function becomes:
MICROCOMPUTER INTERFACES
V
= 1 mV × Digital Code – 2.048 V
O
The AD8303 serial data input provides an easy interface to a
variety of single-chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for communi-
cating with the DAC. In cases where no serial port is provided,
or it is being used for some other purpose (such as an RS-232
communications interface), the AD8303 can easily be addressed
in software.
Note that the full-scale span has increased from 2.048 V to
4.096 V (±2.048 V). Therefore, although each AD8303 LSB
represents 0.5 mV, each output LSB of the bipolar circuit has
been scaled to 1 mV. The code table for this circuit is shown in
Table IV.
Table IV. Bipolar Code Table
Twelve data bits are required to load a value into the AD8303.
If more than 12 bits are transmitted before the Chip Select
input goes high, the extra (i.e., the most significant) bits are
ignored. This feature is valuable because most µCs only transmit
data in 8-bit increments. Thus, the µC sends 16 bits to the DAC
instead of 12 bits. The AD8303 will only respond to the last 12
bits clocked into the SDI input, however, so the serial data
interface is not affected.
Hexadecimal Number Decimal Number Analog Output
in DAC Register
in DAC Register
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.047
0.001
0
–0.001
–2.048
As with the false-ground generator circuit, resistor matching is
–12–
REV. 0
AD8303
AD8303-MC68HC11 INTERFACE
The 8051’s serial data transmission is straightforward. When
data is written to the serial buffer register (SBUF, at Special
Function Register location 99H), the data is automatically
converted to serial format and clocked out via Port 3.0 and Port
3.1 After 8 bits have been transmitted, the Transmit Interrupt
flag (SCON.1) is set and the next 8 bits can be transmitted.
The circuit illustrated in Figure 33 shows a serial interface
between the AD8303 and the MC68HC11 8-bit micro-
processor. The MOSI output drives the AD8303’s serial data
input, SDI, while SCK drives the clock (CLK). The DAC’s CS,
LDA, LDB, MSB and RS inputs are driven by lines PD5 and
PC0–PC3, respectively.
The circuit of Figure 34 demonstrates “hardwiring” many of the
AD8303 features which may not have to be changed within a
given design. For example, the reset feature is controlled by a
resistor and capacitor. This produces a power-on reset pulse
without requiring a µC I/O pin. The MSB pin can be hardwired
to VDD or ground, depending on whether a reset to 0 V or half
scale is required. If the AD8303 is the only device on the serial
interface, CS can also be tied to ground. Finally, SHDN can be
tied to VDD if the shutdown feature will not be used.
(PD3) MOSI
(PD4) SCK
(PD5) SS
PC0
SDI
CLK
CS
AD8303
LDA
LDB
MSB
RS
PC1
MC68HC11
PC2
PC3
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Software for the interface of Figure 34 is shown in Figure 35.
This routine sends the 12-bit value placed in registers
DAC_VAL0 and DAC_VAL1 to the DAC addressed by the two
LSBs of DAC_ADDR.
Figure 33. AD8303-MC68HC11 Serial Interface
To load data into the AD8303, the 68HC11’s CPOL and
CPHA bits are set high. This action configures the µC to
transfer data on the rising edge of the serial clock. After CS is
set low, two bytes of data are sent to the AD8303 using the
format shown in Figure 28. Then LDA or LDB are strobed low,
transferring the serial-input register contents to the appropriate
DAC. The RS and MSB inputs allow the DAC to be reset to
either zero volts or half scale at any time.
The subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0
operation. The MSBs of the DAC value are obtained from
memory location DAC_VAL1, adjusted to compensate for the
8051’s serial data format, and moved to the serial buffer
register. At this point, serial data transmission begins
automatically. When all 8 bits have been sent, the Transmit
Interrupt bit is set, and the subroutine then proceeds to send the
LSBs of the DAC value, stored at location DAC_VAL0. Next
the LDA and LDB bits from DAC_ADDR are logically ANDed
with Port1. This action sets the appropriate AD8303 DAC
select input low and transfers the DAC value from the serial-
input register to the DAC register, causing the DAC output
voltage to change. Finally the LDA and LDB inputs are driven
high to await the next DAC update.
AN 8051 µC INTERFACE
A typical interface between the AD8303 and an 8051 µC is
shown in Figure 34. This interface also uses the µC’s internal
serial port. The serial port is programmed for Mode 0
operation, which functions as a simple 8-bit shift register. The
8051’s Port 3.0 pin functions as the serial data output, while
Port 3.1 serves as the serial clock. The LDA and LDB pins are
controlled by the 8051’s Port 1.0 and Port 1.1 lines, respectively.
The 8051 sends data out of its shift register LSB first, while the
AD8303 requires data MSB first. The subroutine therefore
includes a BYTESWAP subroutine to reformat the data. This
routine transfers the MSB-first byte at location SHIFTREG to
an LSB-first byte at location SENDBYTE. The routine rotates
the MSB of the first byte into the carry with a Rotate Left Carry
instruction, then rotates the carry into the MSB of the second
byte with a Rotate Right Carry instruction. After 8 loops,
SENDBYTE contains the data in the proper format. The
BYTESWAP routine in Listing C is convenient because the
DAC data can be calculated in normal LSB form.
7
(P3.0) RxD
(P3.1) TxD
P1.0
SDI
6
8
CLK
LDA
LDB
10
AD8303
P1.1
80CL51
RS CS MSB SHDN
10k
1µF
9
5
11
12
V
DD
+
V
DD
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 34. AD8303-80CL51 Serial Interface
REV. 0
–13–
AD8303
;AD8303.ASM
;
;
;
;
;
;
;
This subroutine loads an AD8303 shift register with a 12-bit
DAC value, and transfers the value to DAC A or DAC B.
The DAC value is stored at location DAC-VAL1 (MSB) and DAC_VAL0 (LSB)
The DAC address (A or B) is stored at DAC_ADDR, (b0=0 for A, b1=0 for B)
Primary controls
$MOD51
$TITLE(AD8303 Interface, Using the Serial Port in Mode 0)
;
;
;
Variable declarations
PORT1
DATA
DATA
DATA
DATA
90H
40H
41H
42H
;SFR register for port 1
;LSBs of 12-bit DAC Value
; MSBs of DAC Value
;DAC address, format is:
; 1,1,1,1,1,1,LDB,LDA
DAC_VAL0
DAC_VAL1
DAC_ADDR
;
Set bit low to select DAC
LOOPCOUNT
SHIFTREG
SENDBYTE
DATA
DATA
DATA
;
43H
44H
45H
;Count loops for byte swap
;Shift reg. for byte swap
; Destination reg. for SR
ORG
CLR
CLR
CLR
CLR
MOV
ACALL
MOV
ACALL
MOV
ANL
MOV
ORL
MOV
RET
;
100H
SCON.7
SCON.6
SCON.5
SCON.1
SHIFTREG,DAC_VAL1
SEND_IT
SHIFTREG,DAC_VAL0
SEND_IT
A,PORT1
;arbitrary starting address
;set serial
DO_8303:
;
data mode 0
;Clr SM2 for mode 0
;Clr the transmit flag
;Get Most Significant Byte
;
send to AD8303
;Get Least Significant Byte
send it to the AD8303
;
;Get I/O port contents
;Clr LDA/LDB, other bits unchanged
;Send to I/O port
;Set LDA and LDB high
;Send to I/O port
A,DAC_ADDR
PORT1,A
A,#00000011B
PORT1,A
;Done
;Convert the byte to LSB-first format and send it to the AD8303
SEND_IT:
BYTESWAP:
MOV
MOV
RLC
MOV
MOV
RRC
MOV
DJNZ
MOV
LOOPCOUNT,#8
A,SHIFTREG
A
SHIFTREG,A
A,SENDBYTE
A
SENDBYTE,A
LOOPCOUNT,BYTESWAP
SBUF,SENDBYTE
SCON.1,SEND_WAIT
SCON.1
;Shift 8 bits
;Get source byte
;rotate MSB to carry
;Save new source byte
;get destination byte
;Move carry into MSB
;Save
;Done?
;Send the byte
;Wait until 8 bits are send
;Clear the serial flag
;Done
SEND_WAIT: JNB
CLR
RET
END
Figure 35. Software Listing for the AD8303-80CL51 Interface
–14–
REV. 0
AD8303
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Epoxy DIP (N-14)
0.795 (20.19)
0.725 (18.42)
14
1
8
0.280 (7.11)
0.240 (6.10)
7
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 0.070 (1.77)
(2.54)
BSC
0.045 (1.15)
14-Lead Narrow Body SOIC (R-14)
0.3444 (8.75)
0.3367 (8.55)
14
1
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. 0
–15–
–16–
相关型号：
AD8303AR-REEL
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