AD8304ARU-REEL [ADI]
160 dB Range (100 pA -10 mA) Logarithmic Converter; 160分贝范围（ 100 pA的-10 mA）的对数转换器
| 型号： | AD8304ARU-REEL |
| 厂家： | 
ADI |
| 描述： | 160 dB Range (100 pA -10 mA) Logarithmic Converter |
| 文件： | 总20页 (文件大小：4103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
160 dB Range (100 pA –10 mA)
Logarithmic Converter
a
AD8304
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Optimized for Fiber Optic Photodiode Interfacing
Eight Full Decades of Range
VPS2
10
PWDN
2
VPS1
12
Law Conformance 0.1 dB from 1 nA to 1 mA
Single-Supply Operation (3.0 V– 5.5 V)
Complete and Temperature Stable
AD8304
PDB
BIAS
VREF
7
8
VREF
VLOG
VPDB
6
Accurate Laser-Trimmed Scaling:
~10k⍀
0.5V
VSUM
INPT
Logarithmic Slope of 10 mV/dB (at VLOG Pin)
Basic Logarithmic Intercept at 100 pA
Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/s Slew Rate
1-, 2-, or 3-Pole Low-Pass Filtering at Output
Miniature 14-Lead Package (TSSOP)
Low Power: ~4.5 mA Quiescent Current (Enabled)
3
4
I
PD
9
BFIN
5k⍀
TEMPERATURE
COMPENSATION
5
VSUM
BFNG
13
1
14
11
APPLICATIONS
VNEG
ACOM
VOUT
High Accuracy Optical Power Measurement
Wide Range Baseband Log Compression
Versatile Detector for APC Loops
PRODUCT DESCRIPTION
The default value of the logarithmic slope at the output VLOG is
accurately scaled to 10 mV/dB (200 mV/decade). The resistance
at this output is laser-trimmed to 5 kΩ, allowing the slope to be
lowered by shunting it with an external resistance; the addition
of a capacitor at this pin provides a simple low-pass filter. The
intermediate voltage VLOG is buffered in an output stage that can
swing to within about 100 mV of ground (or VN) and the posi-
tive supply, VP, and provides a peak current drive capacity of
20 mA. The slope can be increased using the buffer and a pair
of external feedback resistors. An accurate voltage reference of
2 V is also provided to facilitate the repositioning of the intercept.
The AD8304 is a monolithic logarithmic detector optimized for
the measurement of low frequency signal power in fiber optic
systems. It uses an advanced translinear technique to provide an
exceptionally large dynamic range in a versatile and easily used
form. Its wide measurement range and accuracy are achieved
using proprietary design techniques and precise laser trimming.
In most applications only a single positive supply, VP, of 5 V
will be required, but 3.0 V to 5.5 V can be used, and certain
applications benefit from the added use of a negative supply,
VN. When using low supply voltages, the log slope is readily
altered to fit the available span. The low quiescent current and
chip disable features facilitate use in battery-operated applications.
Many operational modes are possible. For example, low-pass filters
of up to three poles may be implemented, to reduce the output
noise at low input currents. The buffer may also serve as a com-
parator, with or without hysteresis, using the 2 V reference, for
example, in alarm applications. The incremental bandwidth of
a translinear logarithmic amplifier inherently diminishes for small
input currents. At the 1 nA level, the AD8304’s bandwidth is
about 2 kHz, but this increases in proportion to IPD up to a
maximum value of 10 MHz.
The input current, IPD, flows in the collector of an optimally
scaled NPN transistor, connected in a feedback path around a
low offset JFET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5 V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply.
An adaptive biasing scheme is provided for reducing the dark
current at very low light input levels. The voltage at Pin VPDB
applies approximately 0.1 V across the diode for IPD = 100 pA,
rising linearly with current to 2.0 V of net bias at IPD = 10 mA.
The input pin INPT is flanked by the guard pins VSUM that
track the voltage at the summing node to minimize leakage.
The AD8304 is available in a 14-lead TSSOP package and specified
for operation from –40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD8304–SPECIFICATIONS (VP = 5 V, VN = 0 V, TA = 25ꢀC, unless otherwise noted.)
Parameter
Conditions
Min1
Typ
Max1
Unit
INPUT INTERFACE
Specified Current Range
Pin 4, INPT; Pin 3 and Pin 5, VSUM
Flows toward INPT Pin
100
0.46
–20
pA
mA
V
mV/°C
mV
10
0.54
Input Node Voltage
Temperature Drift
Input Guard Offset Voltage
Internally preset; may be altered
–40°C < TA < +85°C
VIN – VSUM
0.5
0.02
+20
PHOTODIODE BIAS2
Minimum Value
Transresistance
Established between Pin 6, VPDB, and Pin 4
IPD = 100 pA
70
100
200
mV
mV/mA
LOGARITHMIC OUTPUT
Slope
Pin 8, VLOG
Laser-trimmed at 25°C
196
194
60
200
100
204
207
140
175
0.25
0.7
mV/dec
mV/dec
pA
pA
dB
dB
V
V
kΩ
0°C < TA < 70°C
Intercept
Laser-trimmed at 25°C
0°C < TA < 70°C
35
Law Conformance Error
10 nA < IPD < 1 mA, Peak Error
1 nA < IPD < 1 mA, Peak Error
0.05
0.1
1.6
0.1
5
Maximum Output Voltage
Minimum Output Voltage
Output Resistance
Limited by VN = 0 V
Laser-trimmed at 25°C
4.95
5.05
REFERENCE OUTPUT
Voltage WRT Ground
Pin 7, VREF
Laser-trimmed at 25°C
–40°C < TA < +85°C
1.98
1.92
2
2
2.02
2.08
V
V
Ω
Output Resistance
OUTPUT BUFFER
Input Offset Voltage
Input Bias Current
Incremental Input Resistance
Output Range
Output Resistance
Wide-Band Noise3
Small Signal Bandwidth3
Slew Rate
Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
Flowing out of Pin 9 or Pin 13
RL = 1 kΩ to ground
–20
+20
mV
µA
0.4
35
VP – 0.1
0.5
1
10
15
MΩ
V
Ω
IPD > 1 µA (see Typical Performance Characteristics)
IPD > 1 µA (see Typical Performance Characteristics)
0.2 V to 4.8 V output swing
µV/√Hz
MHz
V/µs
POWER-DOWN INPUT
Logic Level, HI State
Logic Level, LO State
Pin 2, PWDN
–40°C < TA < +85°C, 2.7 V < VP < 5.5 V
–40°C < TA < +85°C, 2.7 V < VP < 5.5 V
2
V
V
1
POWER SUPPLY
Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG
Positive Supply Voltage
Quiescent Current
3.0
5
5.5
5.3
V
4.5
60
0
mA
µA
V
In Disabled State
Negative Supply Voltage4
|1VP –VN| < 8V
–5.5
NOTES
1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.
3Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.
4Optional
Specifications subject to change without notice.
–2–
REV. A
AD8304
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 270 mW
Pin No. Mnemonic Function
1
VNEG
Optional Negative Supply, VN. This
pin is usually grounded; for details of
usage, see Applications section.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
JA
Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
2
PWDN
VSUM
INPT
Power-Down Control Input. Device is
active when PWDN is taken LOW.
Guard Pins. Used to shield the INPT
current line.
Photodiode Current Input. Usually
connected to photodiode anode (the
photo current flows toward INPT).
3, 5
4
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
6
VPDB
Photodiode Biaser Output. May be
connected to photodiode cathode to
provide adaptive bias control.
PIN CONFIGURATION
7
8
VREF
VLOG
Voltage Reference Output of 2 V
Output of the Logarithmic Front-End
Processor; ROUT = 5 kΩ to ground.
Buffer Amplifier Noninverting Input
(High Impedance)
Positive Supply, VP (3.0 V to 5.5 V)
Buffer Output; Low Impedance
Positive Supply, VP (3.0 V to 5.5 V)
Buffer Amplifier Inverting Input
Analog Ground
14 ACOM
13 BFNG
1
2
3
4
5
6
7
VNEG
PWDN
9
BFIN
VSUM
INPT
12
11
10
9
VPS1
VOUT
VPS2
BFIN
AD8304
TOP VIEW
(Not to Scale)
10
11
12
13
14
VPS2
VOUT
VPS1
BFNG
ACOM
VSUM
VPDB
VREF
8
VLOG
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
Package Description
Package Option
AD8304ARU
Tube, 14-Lead TSSOP
13" Tape and Reel
7" Tape and Reel
RU-14
AD8304ARU-REEL
AD8304ARU-REEL7
AD8304-EVAL
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD8304–Typical Performance Characteristics
(VP = 5 V, VN = 0 V, TA = 25ꢀC, unless otherwise noted.)
1.6
0.510
0.508
0.506
0.504
0.502
0.500
T
V
= –40ꢀC, +25ꢀC, +85ꢀC
= –0.5V
T
= –40ꢀC, +25ꢀC, +85ꢀC
A
A
N
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40ꢀC
+25ꢀC
+85ꢀC
0ꢀC
+70ꢀC
–40ꢀC
+25ꢀC
+85ꢀC
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
INPUT – A
INPUT – A
TPC 1. VLOG vs. IPD
TPC 4. VSUM vs. IPD
2.0
1.5
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
T
V
= –40ꢀC, +25ꢀC, +85ꢀC
= –0.5V
T = –40ꢀC, +25ꢀC, +85ꢀC
A
A
N
–40ꢀC
–40ꢀC
+25ꢀC
+85ꢀC
1.0
+25ꢀC
0ꢀC
0.5
0
–0.5
–1.0
–1.5
–2.0
+85ꢀC
+70ꢀC
100p
1n
10n
100n
1ꢁ
INPUT – A
10ꢁ
100ꢁ
1m
10m
0
1
2
3
4
5
6
7
8
9
10
INPUT – mA
TPC 2. Logarithmic Conformance (Linearity) for VLOG
TPC 5. VPDB vs. IPD
2.0
1.25
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
V
= 4.5V, 5.0V, 5.5V
= –0.1V
T
V
= –40ꢀC, +25ꢀC, +85ꢀC
= 3.0V
P
N
A
1.00
0.75
0.50
0.25
0
1.5
1.0
P
–40ꢀC
0.5
4.5V
5.0V
5.5V
0
+25ꢀC
+85ꢀC
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
100p
1n
10n 100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
INPUT – A
INPUT – A
TPC 3. Absolute Deviation from Nominal Speci-
fied Value of VLOG for Several Supply Voltages
TPC 6. Logarithmic Conformance (Linearity) for a
3 V Single Supply (See Figure 6)
–4–
REV. A
AD8304
10
0
10
9
8
7
6
5
4
3
2
1
0
100nA
10nA
1ꢁA
10ꢁA
100ꢁA
10mA
1nA
–10
–20
–30
–40
–50
–60
–70
1mA
100
1k
10k
100k
1M
10M
100M
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
FREQUENCY – Hz
INPUT CURRENT – A
TPC 10. Total Wideband Noise Voltage at VLOG vs. IPD
TPC 7. Small Signal AC Response, IPD to VLOG
(5% Sine Modulation of IPD at Frequency)
3
100
GAIN = 1ꢂ, 2ꢂ, 2.5ꢂ, 5ꢂ
10kHz
0
100kHz
10
A
= 1
A
= 5
V
V
–3
–6
A
= 2.5
V
1
100Hz
A
= 2
V
1kHz
1MHz
0.1
–9
–12
100
0.01
1k
10k
100k
1M
10M
100M
1n
10n
100n
1ꢁ
10ꢁ
– ꢁA
100ꢁ
1m
10m
FREQUENCY – Hz
I
PD
TPC 11. Small Signal Response of Buffer
TPC 8. Spot Noise Spectral Density at VLOG vs. IPD
10
100
fC = 1kHz
1nA
0
–10
–20
–30
–40
–50
–60
–70
10
10nA
1ꢁA
100nA
1
10ꢁA
>100ꢁA
0.1
0.01
100
10
100
1k
10k
100k
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 12. Small Signal Response of Buffer
Operating as Two-Pole Filter
TPC 9. Spot Noise Spectral Density at VLOG vs. Frequency
REV. A
–5–
AD8304
2.0
20
15
T
= 25ꢀC
A
1.5
1.0
MEAN + 3ꢃ
10
5
0.5
0
MEAN + 3ꢃ
–5
0
–10
–15
–20
–25
–30
MEAN – 3ꢃ
–0.5
–1.0
–1.5
–2.0
MEAN – 3ꢃ
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
INPUT – A
TEMPERATURE – ꢀC
TPC 13. Logarithmic Conformance Error
Distribution (3σ to Either Side of Mean)
TPC 16. VREF Drift vs. Temperature (3σ to Either
Side of Mean)
5
3
T
= 0ꢀC, 70ꢀC
A
4
3
2
MEAN + 3ꢃ
1
0
2
MEAN + 3ꢃ @ 70ꢀC
MEAN – 3ꢃ @ 70ꢀC
1
MEAN ꢄ 3ꢃ @ 0ꢀC
0
–1
–2
–1
–2
–3
–4
–5
–3
–4
–5
MEAN – 3ꢃ
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
–40 –30 –20
60 70 80 90
–10
0
10 20 30 40 50
INPUT – A
TEMPERATURE – ꢀC
TPC 14. Logarithmic Conformance Error
Distribution (3σ to Either Side of Mean)
TPC 17. Slope Drift vs. Temperature (3σ to Either
Side of Mean)
5
40
30
T
= ꢅ40ꢀC, ꢆ85ꢀC
A
4
3
MEAN ꢆ3ꢃ @ꢅ40ꢀC
MEAN + 3ꢃ
20
2
10
0
1
0
MEAN ꢄ3ꢃ @ ꢆ85ꢀC
–10
–20
–1
–2
–3
–4
–5
MEAN – 3ꢃ
–30
–40
–50
MEAN ꢅ3ꢃ @ꢅ40ꢀC
100p
1n
10n
100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE – ꢀC
INPUT – A
TPC 15. Logarithmic Conformance Error
Distribution (3σ to Either Side of Mean)
TPC 18. Intercept Drift vs. Temperature (3σ to
Either Side of Mean)
–6–
REV. A
AD8304
160
140
120
100
80
8
6
MEAN + 3ꢃ
4
2
0
60
–2
–4
–6
40
MEAN – 3ꢃ
20
0
60
80
100
120
140
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
LOGARITHMIC INTERCEPT – pA
TEMPERATURE – ꢀC
TPC 19. Output Buffer Offset vs. Temperature
(3σ to Either Side of Mean)
TPC 21. Distribution of Logarithmic Intercept,
Sample 1000
180
160
140
120
100
80
180
160
140
120
100
80
60
60
40
40
20
20
0
0
196
198
200
202
204
–20
–10
0
10
20
LOGARITHMIC SLOPE – mV/dec
INPUT GUARD OFFSET – mV
TPC 20. Distribution of Logarithmic Slope, Sample 1000
TPC 22. Distribution of Input Guard Offset Voltage
(VINPT – VSUM), Sample 1000
REV. A
–7–
AD8304
BASIC CONCEPTS
Optical Measurements
The AD8304 uses an advanced circuit implementation that
exploits the well known logarithmic relationship between the
base-to-emitter voltage, VBE, and collector current, IC, in a
bipolar transistor, which is the basis of the important class of
translinear circuits*:
When interpreting the current IPD in terms of optical power inci-
dent on a photodetector, it is necessary to be very clear about the
transducer properties of a biased photodiode. The units of this
transduction process are expressed as amps per watt. The param-
eter , called the photodiode responsivity, is often used for this
purpose. For a typical InGaAs p-i-n photodiode, the responsivity
is about 0.9 A/W.
(1)
VBE = VT log(IC /IS )
There are two scaling quantities in this fundamental equation, namely
the thermal voltage VT = kT/q and the saturation current IS. These
are of key importance in determining the slope and intercept for this
class of log amp. VT has a process-invariant value of 25.69 mV
at T = 25°C and varies in direct proportion to absolute temperature,
while IS is very much a process- and device-dependent parameter,
and is typically 10–16 A at T = 25°C but exhibits a huge variation
over the temperature range, by a factor of about a billion.
It is also important to note that amps and watts are not usually
related in this proportional manner. In purely electrical circuits,
a current IPD applied to a resistive load RL results in a power
proportional to the square of the current (that is, IPD2 RL). The
reason for the difference in scaling for a photodiode interface is
that the current IPD flows in a diode biased to a fixed voltage,
VPDB. In this case, the power dissipated within the detector
diode is simply proportional to the current IPD (that is, IPDVPDB
and the proportionality of IPD to the optical power, POPT, is
preserved.
)
While these variations pose challenges to the use of a transistor as
an accurate measurement device, the remarkable matching and
isothermal properties of the components in a monolithic process
can be applied to reduce them to insignificant proportions, as will
be shown. Logarithmic amplifiers based on this unique property
of the bipolar transistor are called translinear log amps to distin-
guish them from other Analog Devices products designed for RF
applications that use quite different principles.
(4)
IPD = ρPOPT
Accordingly, a reciprocal correspondence can be stated between the
intercept current, IZ, and an equivalent “intercept power,” PZ, thus:
(5)
IZ = ρPZ
and Equation 2 may then be written as:
VLOG = VY log10(POPT /PZ )
The very strong temperature variation of the saturation current
IS is readily corrected using a second reference transistor, having
an identical variation, to stabilize the intercept. Similarly, propri-
etary techniques are used to ensure that the logarithmic slope is
temperature-stable. Using these principles in a carefully scaled
design, the now accurate relationship between the input current,
(6)
For the AD8304 operating in its default mode, its IZ of 100 pA
corresponds to a PZ of 110 picowatts, for a diode having a
responsivity of 0.9 A/W. Thus, an optical power of 3 mW would
generate:
I
PD, applied to Pin INPT, and the voltage appearing at the inter-
mediate output Pin VLOG is:
(7)
VLOG = 0.2V log10(3 mW/110 pW ) = 1.487V
(2)
VLOG = VY log10(IPD/IZ )
Note that when using the AD8304 in optical applications, the
interpretation of VLOG is in terms of the equivalent optical
power, the logarithmic slope remains 10 mV/dB at this output.
This can be a little confusing since a decibel change on the
optical side has a different meaning than on the electrical side.
In either case, the logarithmic slope can always be expressed in
units of mV per decade to help eliminate any confusion.
VY is called the slope voltage (in the case of base-10 logarithms,
it is also the “volts per decade”). The fixed current IZ is called
the intercept. The scaling is chosen so that VY is trimmed to
200 mV/decade (10 mV/dB). The intercept is positioned at
100 pA; the output voltage VLOG would cross zero when IPD is
of this value. However, when using a single supply the actual
VLOG must always be slightly above ground. On the other hand,
by using a negative supply, this voltage can actually cross zero at
the intercept value.
Decibel Scaling
In cases where the power levels are already expressed as so many
decibels above a reference level (in dBm, for a reference of 1 mW),
the logarithmic conversion has already been performed, and the
“log ratio” in the above expressions becomes a simple differ-
ence. One needs to be careful in assigning variable names here,
because “P” is often used to denote actual power as well as this
same power expressed in decibels, while clearly these are numeri-
cally different quantities.
Using Equation 2, one can calculate the output for any value of IPD
.
Thus, for an input current of 25 nA,
(3)
VLOG = 0.2V log10(25 nA/100 pA) = 0.4796V
In practice, both the slope and intercept may be altered, to either
higher or lower values, without any significant loss of calibration
accuracy, by using one or two external resistors, often in conjunc-
tion with the trimmed 2 V voltage reference at Pin VREF.
Such potential misunderstandings can be avoided by using “D”
to denote decibel powers. The quantity VY (“volts per decade”)
must now be converted to its decibel value, VY´ = VY/10, because
there are 10 dB per decade in the context of a power measurement.
Then it can be stated that:
VLOG = 20 D
− DZ mV/dB
(8)
(
)
OPT
where DOPT is the optical power in decibels above a reference level,
and DZ is the equivalent intercept power relative to the same level.
This convention will be used throughout this data sheet.
*For a basic discussion of the topic, see Translinear Circuits: An Historical Overview,
B. Gilbert, Analog Integrated Circuits and Signal Processing, 9, pp. 95–118, 1996.
–8–
REV. A
AD8304
To repeat the previous example: for a reference power level of
1 mW, a POPT of 3 mW would correspond to a DOPT of 10 log10(3) =
4.77 dBm, while the equivalent intercept power of 110 pW will
correspond to a DZ of –69.6 dBm; now using Equation 8:
voltage is applied to a processing block—essentially an analog divider
that effectively puts a variable proportional to temperature
underneath the T in Equation 10. In this same block, IREF is trans-
formed to the much smaller current IZ, to provide the previously
defined value for VLOG, that is,
VLOG = 20 mV 4.77 – (–69.9) = 1.487V
(9)
{
}
(11)
VLOG =VY log10 (IPD /IZ )
which is in agreement with the result from Equation 7.
Recall that VY is 200 mV/decade and IZ is 100 pA. Internally,
this is generated first as an output current of 40 µA/decade
(2 µA/dB) applied to an internal load resistor from VLOG to
ACOM that is laser-trimmed to 5 kΩ 1%. The slope may be
altered at this point by adding an external shunt resistor. This is
required when using the minimum supply voltage of 3.0 V,
because the span of VLOG for the full 160 dB (eight-decade)
range of IPD amounts to 8 ϫ 0.2 V = 1.6 V, which exceeds the
internal headroom at this node. Using a shunt of 5 kΩ, this is
reduced to 800 mV, that is, the slope becomes 5 mV/dB. In
those applications needing a higher slope, the buffer can provide
voltage gain. For example, to raise the output swing to 2.4 V,
which can be accommodated by the rail-to-rail buffer when
using a 3.0 V supply, a gain of 3ϫ can be used which raises the
slope to 15 mV/dB. Slope variations implemented in these ways
do not affect the intercept. Keep in mind these measures to
address the limitations of a small positive supply voltage will not
be needed when IPD is limited to about 1 mA maximum. They
can also be avoided by using a negative supply that allows VLOG
to run below ground, which will be discussed later.
GENERAL STRUCTURE
The AD8304 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will also
be useful in many nonoptical applications. These notes explain
the structure of this unique translinear log amp. Figure 1 is a
simplified schematic showing the key elements.
V
PDB
V
V
BE1
INTERCEPT AND
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BYTꢀK)
0.5V
VPDB
PHOTODIODE
INPUT CURRENT
BE2–
296mVP
200ꢇ
~10kꢇ
VSUM
I
REF
(INTERNAL)
I
PD
40ꢁA/dec
INPT
0.5V
VLOG
V
LOG
0.6V
C1
0.5V
Q1
5kꢇ
QM
Q2
V
V
BE2
BE1
R1
ACOM
Figure 1 shows how a sample of the input current is derived using
a very small monitoring transistor, QM, connected in parallel with
VNEG (NORMALLY GROUNDED)
Q1. This is used to generate the photodiode bias, VPDB, at Pin VPDB
which varies from 0.6 V when IPD = 100 pA, and reverse-biases
the diode by 0.1 V (after subtracting the fixed 0.5 V at INPT)
and rises to 2.6 V at IPD = 10 mA, for a net diode bias of 2 V.
The driver for this output is current-limited to about 20 mA.
,
Figure 1. Simplified Schematic
The photodiode current IPD is received at input Pin INPT. The
summing voltage at this node is essentially equal to that on the
two adjacent guard pins, VSUM, due to the low offset voltage of
the ultralow bias J-FET op amp used to support the operation of
the transistor Q1, which converts the current to a logarithmic
voltage, as delineated in Equation 1. VSUM is needed to provide
the collector-emitter bias for Q1, and is internally set to 0.5 V,
using a quarter of the reference voltage of 2 V appearing on
Pin VREF.
The system is completed by the final buffer amplifier, which is
essentially an uncommitted op amp with a rail-to-rail output
capability, a 10 MHz bandwidth, and good load-driving capabili-
ties, and may be used to implement multipole low-pass filters,
and a voltage reference for internal use in controlling the scaling,
but that is also made available at the 2.0 V level at Pin VREF.
In conventional translinear log amps, the summing node is gener-
ally held at ground potential, but that condition is not readily
realized in a single-supply part. To address this, the AD8304 also
supports the use of an optional negative supply voltage, VN, at
Pin VNEG. For a VN of at least –0.5 V the summing node can
be connected to ground potential. Larger negative voltages may
be used, with essentially no effect on scaling, up to a maximum
supply of 8 V between VPOS and VNEG. Note that the resistance
at the VSUM pins is approximately 10 kΩ to ground; this voltage
is not intended as a general bias source.
Figure 2 shows the ideal output VLOG versus IPD
.
Bandwidth and Noise Considerations
The response time and wide-band noise of translinear log amps
are fundamentally a function of the signal current IPD. The
bandwidth becomes progressively lower as IPD is reduced,
largely due to the effects of junction capacitances in Q1. This is
easily understood by noting that the transconductance (gm) of a
bipolar transistor is a linear function of collector current, IC,
(hence, translinear), which in this case is just IPD. The corre-
sponding incremental emitter resistance is:
The input-dependent VBE of Q1 is compared with the fixed VBE of
a second transistor, Q2, which operates at an accurate internally
generated current, IREF = 10 µA. The overall intercept is arranged
to be 100,000 times smaller than IREF, in later parts of the signal chain.
The difference between these two VBE values can be written as
1
kT
re =
=
(12)
gm qIPD
Basically, this resistance and the capacitance CJ of the transistor
generate a time constant of reCJ and thus a corresponding low-pass
corner frequency of:
qIPD
(10)
VBE1 –VBE2 = kT/q log10 (IPD/IREF
)
f3dB
=
(13)
2 π kTCj
showing the proportionality of bandwidth to current.
Thus, the uncertain and temperature-dependent saturation current,
IS that appears in Equation 1, has been eliminated. Next, to
eliminate the temperature variation of kT/q, this difference
REV. A
–9–
AD8304
1.6
is thus 4.0 V, which can be accommodated by the rail-to-rail
output stage when using the recommended 5 V supply.
The capacitor from VLOG to ground forms an optional single-
pole low-pass filter. Since the resistance at this pin is trimmed
to 5 kΩ, an accurate time constant can be realized. For ex-
ample, with CFLT = 10 nF, the –3 dB corner frequency is
3.2 kHz. Such filtering is useful in minimizing the output noise,
particularly when IPD is small. Multipole filters are more effec-
tive in reducing noise, and are discussed below. A capacitor
between VSUM and ground is essential for minimizing the
noise on this node. When the bias voltage at either VPDB or
VREF is not needed these pins should be left unconnected.
1.2
0.8
0.4
0
Slope and Intercept Adjustments
100p
1n
10n 100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
The choice of slope and intercept depends on the application.
The versatility of the AD8304 permits optimal choices to be
made in two common situations. First, it allows an input current
range of less than the full 160 dB to use the available voltage span
at the output. Second, it allows this output voltage range to be
optimally positioned to fit the input capacity of a subsequent
ADC. In special applications, very high slopes, such as 1 V/dec,
allow small subranges of IPD to be covered at high sensitivity.
INPUT – A
Figure 2. Ideal Form of VLOG vs. IPD
Using a value of 0.3 pF for CJ evaluates to 20 MHz/mA. There-
fore, the minimum bandwidth at IPD = 100 pA would be 2 kHz.
While this simple model is useful in making a point, it excludes
other effects that limit its usefulness. For example, the network
R1, C1 in Figure 1, which is necessary to stabilize the system over
The slope can be lowered without limit by the addition of a
shunt resistor, RS, from VLOG to ground. Since the resistance
at this pin is trimmed to 5 kΩ, the accuracy of the modified
slope will depend on the external resistor. It is calculated using:
the full range of currents, affects bandwidth at all values of IPD
Later signal processing blocks also limit the maximum value.
.
TPC 7 shows ac response curves for the AD8304 at eight repre-
sentative currents of 100 pA to 10 mA, using R1 = 750 Ω and
C1 = 1000 pF. The values for R1 and C1 ensure stability over
the full 160 dB dynamic range. More optimal values may be used
for smaller subranges. A certain amount of experimental trial and
error may be necessary to select the optimum input network
component values for a given application.
VY RS
R'S +5 kΩ
VY
=
(15)
V
P
VPS2
PWDN
VPS1
10
2
12
Turning now to the noise performance of a translinear log amp,
the relationship between IPD and the voltage noise spectral density,
I
PD
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VREF
S
NSD, associated with the VBE of Q1, evaluates to the following:
VPDB
NC
200mV/DEC
CFLT
14.7
SNSD
=
VSUM
INPT
(14)
3
4
VLOG
IPD
8
9
5kꢇ
BFIN
where SNSD is nV/Hz, IPD is expressed in microamps and TA = 25°C.
For an input of 1 nA, SNSD evaluates to almost 0.5 µV/√Hz; assum-
ing a 20 kHz bandwidth at this current, the integrated noise
voltage is 70 µV rms. However, the calculation is not complete.
The basic scaling of the VBE is approximately 3 mV/dB; translated
to 10 mV/dB, the noise predicted by Equation 14 must be multi-
plied by approximately 3.33. The additive noise effects associated
with the reference transistor, Q2, and the temperature compen-
sation circuitry must also be included. The final voltage noise
spectral density presented at the VLOG Pin varies inversely with
VSUM
TEMPERATURE
COMPENSATION
RB
10kꢇ
C1
5
BFNG
1nF
13
10nF
R1
RA
15kꢇ
750ꢇ
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
500mV/DEC
Figure 3. Basic Connections (RA, RB, CFLT are
optional; R1 and C1 are the default values)
I
PD, but not as simple as square root. TPC
S
8 and 9 show the
measured noise spectral density versus frequency at the VLOG
output, for the same nine-decade spaced values of IPD
.
For example, using RS = 3 kΩ, the slope is lowered to 75 mV per
decade or 3.75 mV/dB. Table I provides a selection of suitable
values for RS and the resulting slopes.
Chip Enable
The AD8304 may be powered down by taking the PWDN Pin
to a high logic level. The residual supply current in the disabled
mode is typically 60 µA.
Table I. Examples of Lowering the Slope
USING THE AD8304
RS (kꢇ)
VY (mV/dec)
The basic connections (Figure 3) include a 2.5:1 attenuator in
the feedback path around the buffer. This increases the basic slope
of 10 mV/dB at the VLOG Pin to 25 mV/dB at VOUT. For the
full dynamic range of 160 dB (80 dB optical), the output swing
3
5
15
75
100
150
–10–
REV. A
AD8304
In addition to uses in filter and comparator functions, the buffer
amplifier provides the means to adjust both the slope and inter-
cept, which require a minimal number of external components.
The high input impedance at BFIN, low input offset voltage,
large output swing, and wide bandwidth of this amplifier permit
numerous transformations of the basic VLOG signal, using stan-
dard op amp circuit practices. For example, it has been noted
that to raise the gain of the buffer, and therefore the slope, a
feedback attenuator, RA and RB in Figure 3, should be inserted
between VLOG and the inverting input Pin BFNG.
Table II. Examples of Lowering the Intercept
VY (mV/decade) IZ (pA) RA (kꢇ) RB (kꢇ) RZ (kꢇ)
200
200
200
300
300
300
400
400
400
500
500
500
1
20.0
10.0
3.01
10.0
8.06
6.65
11.5
9.76
8.66
16.5
14.3
13.0
100
100
100
12.4
12.4
12.4
8.2
8.2
8.2
8.2
8.2
25
50
165
25
50
165
25
50
165
25
50
10
50
1
10
50
1
10
50
1
10
50
A wide range of gains may be used and the resistor magnitudes
are not critical; their parallel sum should be about equal to the
net source resistance at the noninverting input. When high gains
are used, the output dynamic range will be reduced; for maxi-
mum swing of 4.8 V, it will amount to simply 4.8 V/VY decades.
Thus, using a ratio of 3ϫ, to set up a slope 30 mV/dB (600 mV/
decade), eight decades can be handled, while with a ratio of 5ϫ,
which sets up a slope of 50 mV/dB (1 V/decade), the dynamic
range is 4.8 decades, or 96 dB. When using a lower positive
supply voltage, the calculation proceeds in the same way,
remembering to first subtract 0.2 V to allow for 0.1 V upper and
lower headroom in the output swing.
8.2
165
Equations for use with Table II:
RZ
IPD
RLOG
RLOG + RZ
VOUT = G V ×
× log10
+VREF ×
Y
RZ + RLOG
IZ
where
RA
RB
G = 1+
and RLOG = 5 kΩ
Alteration of the logarithmic intercept is only slightly more tricky.
First note that it will rarely be necessary to lower the intercept
below a value of 100 pA, since this merely raises all output volt-
ages further above ground. However, where this is required, the
first step is to raise the voltage VLOG by connecting a resistor, RZ,
from VLOG to VREF (2 V) as shown in Figure 4.
Generally, it will be useful to raise the intercept. Keep in mind
that this moves the VLOG line in Figure 2 to the right, lowering all
output values. Figure 5 shows how this is achieved. The feedback
resistors, RA and RB, around the buffer are now augmented with
a third resistor, RZ, placed between the Pins BFNG and VREF.
This raises the zero-signal voltage on BFNG, which has the effect
of pushing VOUT lower. Note that the addition of this resistor also
alters the feedback ratio. However, this is readily compensated
in the design of the network. Table III lists the resistor values
for representative intercepts.
V
P
VPS2
PWDN
VPS1
10
2
12
I
PD
VREF
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VPDB
NC
6
RZ
VSUM
INPT
3
4
Table III. Examples of Raising the Intercept
VLOG
8
5kꢇ
BFIN
VY (mV/decade) IZ (nA)
RA (kꢇ)
RB (kꢇ) RC(kꢇ)
9
VSUM
TEMPERATURE
COMPENSATION
C1
5
BFNG
1nF
300
300
400
400
400
500
500
500
10
100
10
100
500
10
100
500
7.5
8.25
10
9.76
9.76
12.4
12.4
11.5
37.4
130
24.9
18.2
25.5
16.2
13.3
24.9
16.5
12.4
13
10nF
R1
750ꢇ
16.5
25.5
36.5
12.4
16.5
20.0
RA
RB
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
Figure 4. Method for Lowering the Intercept
This has the effect of elevating VLOG for small inputs while lower-
ing the slope to some extent because of the shunt effect of RZ
on the 5 kΩ output resistance. Then, if necessary, the slope may
be increased as before, using a feedback attenuator around the
buffer. Table II lists some examples of lowering the intercept
combined with various slope variations.
Equations for use with Table III:
RA RB
RA RB + R
IPD
VOUT = G V × log
–VREF ×
Y
10
IZ
C
where
RA
RA × RB
RA + RB
G = 1+
and RA RB =
RB RC
REV. A
–11–
AD8304
V
P
Using the Adaptive Bias
VPS2
PWDN
VPS1
12
For most photodiode applications, the placement of the anode
somewhat above ground is acceptable, as long as the positive
bias on the cathode is adequate to support the peak current for a
particular diode, limited mainly by its series resistance. To address
this matter, the AD8304 provides for the diode a bias that varies
linearly with the current. This voltage appears at Pin VPDB, and
10
2
I
PD
VREF
VLOG
PDB
BIAS
~10kꢇ
VREF
0.5V
7
8
VPDB
NC
6
VSUM
INPT
3
4
RC
RB
varies from 0.6 V (reverse-biasing the diode by 0.1 V) for IPD
=
5kꢇ
BFIN
100 pA and rises to 2.6 V (for a diode bias of 1 V) at IPD = 10 mA.
This results in a constant internal junction bias of 0.1 V when the
series resistance of the photodiode is 200 Ω. For optical power
measurements over a wide dynamic range the adaptive biasing
function will be valuable in minimizing dark current while pre-
venting the loss of photodiode bias at high currents. Use of the
adaptive bias feature is shown in Figure 7.
9
VSUM
TEMPERATURE
COMPENSATION
C1
1nF
5
BFNG
13
10nF
R1
750ꢇ
RA
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
Figure 5. Method for Raising the Intercept
V
P
VPS2
PWDN
VPS1
10
2
12
Low Supply Slope and Intercept Adjustment
When using the device with a positive supply less than 4 V, it is
necessary to reduce the slope and intercept at the VLOG Pin in
order to preserve good log conformance over the entire 160 dB
operating range. The voltage at the VLOG Pin is generated by
an internal current source with an output current of 40 µA/decade
feeding the internal laser-trimmed output resistance of 5 kΩ. When
the voltage at the VLOG Pin exceeds VP – 2.3 V, the current
source ceases to respond linearly to logarithmic increases in current.
This headroom issue can be avoided by reducing the logarithmic
slope and intercept at the VLOG Pin. This is accomplished by
connecting an external resistor RS from the VLOG Pin to ground
in combination with an intercept lowering resistor RZ. The values
shown in Figure 6 illustrate a good solution for a 3.0 V positive
supply. The resulting logarithmic slope measured at VLOG is
62.5 mV/decade with a new intercept of 57 fA. The original
logarithmic slope of 200 mV/decade can be recovered using voltage
gain on the internal buffer amplifier.
CPB
VPDB
PDB
BIAS
~10kꢇ
VREF
0.5V
VREF
7
6
VSUM
INPT
I
PD
CFILT
3
4
VLOG
8
5kꢇ
BFIN
9
VSUM
TEMPERATURE
COMPENSATION
C1
1nF
5
RB
BFNG
13
10nF
R1
750ꢇ
RA
1
14
11
VNEG
ACOM
VOUT
V
OUT
Figure 7. Using the Adaptive Biasing
Capacitor CPB, between the photodiode cathode at Pin VPDB
and ground, is included to lower the impedance at this node and
thereby improve the high frequency accuracy at those current
levels where the AD8304 bandwidth is high. It also ensures an
HF path for any high frequency modulation on the optical signal
which might not otherwise be accurately averaged. It will not be
necessary in all cases, and experimentation may be required to find
an optimum value.
V
P
VPS2
PWDN
VPS1
12
10
2
I
PD
VREF
VLOG
PDB
BIAS
~10kꢇ
VREF
0.5V
7
RZ
VPDB
15.4kꢇ
6
Changing the Voltage at the Summing Node
NC
RS
2.67kꢇ
VSUM
INPT
The default value of VSUM is determined by using a quarter of
VREF (2 V). This may be altered by applying an independent volt-
age source to VSUM, or by adding an external resistive divider
from VREF to VSUM. This network will operate in parallel with
the internal divider (40 kΩ and 13.3 kΩ), and the choice of external
resistors should take this into account. In practice, the total
resistance of the added string may be as low as 10 kΩ (consuming
400 µA from VREF). Low values of VSUM and thus VCE (see
Figure 13) are not advised when large values of IPD are expected.
3
4
8
5kꢇ
BFIN
9
VSUM
TEMPERATURE
COMPENSATION
C1
1nF
62.5mV/DEC
5
BFNG
13
10nF
R1
750ꢇ
RA
RB
4.98kꢇ 2.26kꢇ
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
Implementing Low-Pass Filters
Figure 6. Recommended Low Supply Application Circuit
Noise, leading to uncertainty in an observed value, is inherent to
all measurement systems. Translinear log amps exhibit significant
amounts of noise for reasons stated above, and are more trouble-
some at low current levels. The standard way of addressing this
problem is to average the measurement over an appropriate time
interval. This can be achieved in the digital domain, in post-ADC
DSP, or in analog form using a variety of low-pass structures.
–12–
REV. A
AD8304
V
P
The use of a capacitor at the VLOG Pin to create a single-pole
filter has already been mentioned. The small added cost of the few
external components needed to realize a multipole filter is often
justified in a high performance measurement system. Figure 8
shows a Sallen-Key filter structure. Here, the resistor needed at
the front of the network is provided entirely by the accurate 5 kΩ
present at the VLOG output; RB will have a similar value. The corner
frequency and Q (damping factor) are determined by the capacitors
CA and CB and the gain G = (RA + RB)/RB. A suggested starting
point for choosing these components using various gains is pro-
vided in Table IV; the values shown are for a 1 kHz corner (also
see TPC 12). This frequency can be increased or decreased by
scaling the capacitor values. Note that RD, G, and the capacitor ratio
CA/CB should not deviate from the suggested values to maintain the
shape of the ac amplitude response and pulse overshoot provided
by the values shown in this table. In all cases, the roll-off rate above
the corner is 40 dB/dec.
VPS2
PWDN
VPS1
10
2
12
I
PD
VREF
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VPDB
NC
6
VSUM
INPT
3
4
VLOG
8
RG
RA
5kꢇ
BFIN
9
VSUM
TEMPERATURE
COMPENSATION
C1
1nF
5
BFNG
13
10nF
R1
750ꢇ
RH
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
Figure 9. Using the Buffer as a Comparator
Using a Negative Supply
Most applications of the AD8304 will require only a single supply
of 3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 10.
V
P
VPS2
PWDN
VPS1
12
10
2
I
PD
The use of a negative supply, VN, allows the summing node to
be placed exactly at ground level, because the input transistor
(Q1 in Figure 1) will have a negative bias on its emitter. VN may
be as small as –0.5 V, making the VCE the same as for the default
case. This bias need not be accurate, and a poorly defined source
can be used.
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VREF
VPDB
NC
6
VSUM
INPT
3
4
VLOG
RD
8
5kꢇ
BFIN
9
VSUM
TEMPERATURE
COMPENSATION
C1
1nF
5
RB
BFNG
13
A larger supply of up to –5 V may be used. The effect on scaling
is minor. It merely moves the intercept by ~0.01 dB/V. Accord-
ingly, an uncertainty of 0.2 V in VN would result in a negligible
error of 0.002 dB. The slope is unaffected by VN. The log lin-
earity will be degraded at the extremes of the dynamic range as
indicated in Figure 11. The bias current, buffer output (and its
load) current, and the full IPD all have to be absorbed by this
negative supply, and its supply capacity must be ensured for the
maximum current condition.
10nF
R1
CA
CB
750kꢇ
RA
1
14
11
VNEG
NC = NO CONNECT
ACOM
VOUT
V
OUT
Figure 8. Two-Pole Low-Pass Filter
Table IV. Two-Pole Filter Parameters for 1 kHz Cutoff
Frequency*
V
P
RA
RB
VY
RD
(kꢇ)
CA
CB
VPS2
PWDN
VPS1
12
10
2
(kꢇ) (kꢇ)
G
(V/decade)
(nF) (nF)
I
PD
0
open
10
8
1
2
0.2
0.4
11.3
6.02
12.1
10.0
12
33
33
33
12
22
18
18
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VREF
VPDB
10
12
24
NC
6
2.5 0.5
5 1.0
VSUM
INPT
3
4
VLOG
6
8
5kꢇ
BFIN
The corner frequency can be adjusted by scaling capacitors CA and CB. For
example, to reduce the corner frequency to 100 Hz, raise the values of CA and
CB by 10 ϫ.
*See TPC 12.
9
VSUM
TEMPERATURE
COMPENSATION
C1
5
BFNG
1nF
13
R1
RA
750ꢇ
Operation in Comparator Modes
RB
In certain applications, the need may arise to generate a logical
output when the input current has reached a certain value. This
can be easily addressed by using a fraction of the voltage refer-
ence to provide the setpoint (threshold) and using the buffer
without feedback in a comparator mode, as illustrated in Figure 9.
Since VLOG runs from ground up to 1.6 V maximum, the 2 V
reference is more than adequate to cover the full dynamic range
of IPD. Note that the threshold for an increasing IPD is unchanged,
while the release point for decreasing currents is 5 dB below
this. Raising RH to 5 MΩ reduces the hysteresis to 0.5 dB, or it
may be increased using a lower value for RH.
1
14
11
VNEG
ACOM
VOUT
V
NC = NO CONNECT
OUT
V
N (–0.5VTO –3V)
Figure 10. Using a Negative Supply
With the summing node at ground, the AD8304 may now be used
as a voltage-input log amp, simply by inserting a suitably scaled
resistor from the voltage source to the INPT Pin. The logarith-
mic accuracy for small voltages is limited by the offset of the JFET
op amp, appearing between this pin and VSUM.
The use of a negative supply also allows the output to swing below
ground, thereby allowing the intercept to correspond to a midrange
value of IPD. However, the voltage VLOG remains referenced to the
REV. A
–13–
AD8304
ACOM Pin, and does not normally go negative with regard to this
pin, but is free to do so. Therefore, a resistor from VLOG to the
negative supply can lower VLOG, thus raising the intercept. A more
accurate method for repositioning the intercept is described below.
APPLICATIONS
The AD8304 incorporates features that improve its usefulness in
both fiber optic supervisory applications and in more general ones.
To aid in the exploration of these possibilities, a SPICE macro-
model is provided and a versatile evaluation board is available.
2.0
1.5
1.0
The macromodel is shown in generalized schematic form (and thus
is independent of variations in SPICE programs) in Figure 12.
Q1, QM, and Q2 (here made equal in size) correspond to the
identical transistors in Figure 1. The model parameters for these
transistors are not critical; the default model provided in SPICE
libraries will be satisfactory. However, the AD8304 employs
compensation techniques to reduce errors caused by junction
resistances (notably, RB and RE) at high input currents. There-
fore, it is advisable to set these to zero. While this will not model
the AD8304 precisely, it is safer than using possibly high default
values for these parameters. The low current model parameters
may also need consideration. Note that no attempt is made to
capture either dynamic behavior or the effects of temperature in this
simple macromodel; scaling is correct for 27°C.
WITHOUT INTERCEPT ADJUST
0.5
V
= 0
NEG
0
–0.5
–1.0
–1.5
–2.0
V
= –0.5
= –3
NEG
WITH INTERCEPT ADJUST
V
NEG
100p
1n
10n 100n
1ꢁ
10ꢁ
100ꢁ
1m
10m
INPUT – A
Figure 11. Log Conformance (Linearity) vs. IPD for
Various Negative Supplies
E2
5
I1
3
I2
4
E4
V2
V1
V
1
+
R2
R1
C2
7
+
2
E3
VLOG
ꢂ 100k
V
ꢂ 3k
IN
6
RL
C1
I1
IPD
Q1
Q3
Q2
I1
0
IN
0
0
0
2
3
3
4
4
DC
1ꢁA
1
C1
E1
V1
Q1
I2
IN
2
1.0N
IN
3K
1
0.5
IN
0
0
NPN
NPN
NPN
1ꢁ
Q2
I3
Q3
3
0
0
316.2ꢁ
4
0
.MODEL NPN NPN
E2
E3
E4
V2
R1
C2
R2
RL
5
0
0
0
7
9
0
POLY (2) 2 3 1 0 0, 0, 0, 0, 1
POLY (2) 4 3 7 0 0, 0, 0, 0, 1
6
0.8
100
163P
6
7
5
100K
8
8
9
9
VLOG 4.9K
1000K
VLOG
0
Figure 12. Basic Macromodel
–14–
REV. A
AD8304
Summing Node at Ground and Voltage Inputs
A negative supply may be used to reposition the input node at
ground potential. A voltage as small as –0.5 V is sufficient. Figure 13
shows the use of this feature. An input current of up to 10 mA is
supported.
is grounded. A negative supply capable of supporting the input
current IPD must be used, the fraction of quiescent bias that flows
out of the VNEG Pin, and the load current at VLOG. For the
example shown in Figure 14, this totals less than 20 mA when
driving a 1 kΩ load as far as –4 V.
This connection mode will be useful in cases where the source is a
positive voltage VSIG referenced to ground, rather than for use with
photodiodes, or other “perfect” current sources. RIN scales the
input current and should be chosen to optimally position the range
of IPD, or provide a very high input resistance, thus minimizing
the loading of the signal source. For example, assume a voltage
source that spans the four-decade range from 100 mV to 1 kV and
is desired to maximize RIN. When set to 1 GΩ, IPD spans the range
100 pA to 1 mA. Using a value of 10 MΩ, the same four decades
of input voltage would span the central current range of 10 nA
to 100 mA.
The use of a much larger value for the intercept may be useful in
certain situations. In this example, it has been moved up four
decades, from the default value of 100 pA to the center of the full
eight-decade range at 1 mA. Using a voltage input as described
above, this corresponds to an altered voltage-mode intercept, VZ,
which would be 1 V for RIN = 1 MΩ. To take full advantage of the
larger output swing, the gain of the buffer has been increased to
4.53, resulting in a scaling of 900 mV/decade and a full-scale
output of 3.6 V.
V
P
VPS2
PWDN
VPS1
10
2
12
Smaller input voltages can be measured accurately when aided by
a small offset-nulling voltage applied to VSUM. The optional
network shown in Figure 13 provides more than 20 mV for
this purpose.
AD8304
VREF
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VPDB
NC
6
VSUM
INPT
3
4
VLOG
V
P
8
RIN
V
RC
VPS2
PWDN
VPS1
5kꢇ
10
2
12
12.4kꢇ
BFIN
I
PD
9
VSUM
AD8304
TEMPERATURE
COMPENSATION
5
BFNG
SIG
13
PDB
BIAS
~10kꢇ
VREF
0.5V
VREF
7
RA
13.3kꢇ
VPDB
NC
6
1kꢇ
VSUM
INPT
RB
22.6kꢇ
3
4
VLOG
8
1
14
11
RIN
V
VNEG
V
ACOM
VOUT
V
V
OUT
LOW
5kꢇ
BFIN
V
I
P
N
PD
9
RL
1kꢇ
VSUM
TEMPERATURE
COMPENSATION
10kꢇ
NC = NO CONNECT
5
SIG
BFNG
13
RA
Figure 14. Using a Negative Supply to Allow the
Output to Swing Below Ground
1kꢇ
RB
1
14
11
Inverting the Slope
VNEG
V
ACOM
VOUT
V
V
OUT
LOW
V
The buffer is essentially an uncommitted op amp that can be used
to support the operation of the AD8304 in a variety of ways. It
can be completely disconnected from the signal chain when not
needed. Figure 15 shows its use as an inverting amplifier; this
changes the polarity of the slope. The output can either be
repositioned to all positive values by applying a fraction of VREF
to the BFIN Pin, or range negative when using a negative supply.
The full design for a practical application is left undefined in this
brief illustration, but a few cases will be discussed.
P
N
10kꢇ
NC = NO CONNECT
Figure 13. Using a Negative Supply and Placing VSUM at
Ground Permits Voltage-Mode Inputs
The minimum voltage that can be accurately measured is then
limited only by the drift in the input offset of the AD8304. The
specifications show the maximum spread over the full tempera-
ture and supply range. Over a limited temperature range, and with
a regulated supply, the offset drift will be lower; in this situation,
processing of inputs down to 5 mV is practicable.
For example, suppose we need a slope of –30 mV/dB; this requires
the gain to be three. Since VLOG exhibits a source resistance of
5 kΩ, RB must be 15 kΩ. In cases where a small negative supply
is available, the output voltage can swing below ground, and the
BFIN Pin may be grounded. But a negative slope is still possible
when only a single supply is used; a positive offset, VOFS, is applied
to this pin, as indicated in Figure 15. In general, the resulting
output voltage can be expressed as:
The input system of the AD8304 is quasi-differential, so VSUM
can be placed at an arbitrary reference level VLOW, over a wide
range, and used as the “signal LO” of the source. For example,
using VP = 5 V and VN = –3 V, VLOW can be any voltage within
a
2.5 V range.
Providing Negative Outputs and Rescaling
As noted, the AD8304 allows the buffer to drive a load to negative
voltages with respect to ACOM, the analog common pin, which
RB
IPD
VOUT = –
VY × log10
+VOFS
(16)
5 kΩ
IZ
REV. A
–15–
AD8304
V
P
down by 1.6 V. Clearly, a higher slope (or gain) is desirable, in
which case VOFS should be set to a smaller voltage to avoid railing
the output at low currents. If VOFS = 1.2 V and G = 33, VOUT
now starts at 4.8 V and falls through this same voltage toward
ground with a slope of –0.6 V per decade, spanning the full
VPS2
PWDN
VPS1
12
10
2
AD8304
I
PD
PDB
BIAS
~10kꢇ
VREF
0.5V
7
8
VREF
VLOG
VPDB
NC
6
range of IPD
.
VSUM
INPT
3
4
Programmable Level Comparator with Hysteresis
The buffer amplifier and reference voltage permit a calibrated
level detector to be realized. Figure 16 shows the use of a 10-bit
MDAC to control the setpoint to within 0.1 dB of an exact value
over the 100 dB range of 1 nA ≤ IPD ≤ 100 µA when the full-
scale output of the MDAC is equal to that of its reference. The
2 V VREF also sets the minimum value of VSPT to 0.2 V, correspond-
ing to an input of 1 nA. Since 100 dB at the VLOG interface
corresponds to a 1 V span, the resistor network is calculated to
provide a maximum VSPT of 1.2 V while adding the required
5kꢇ
V
OFS
BFIN
9
VSUM
TEMPERATURE
COMPENSATION
C1
5
BFNG
1nF
13
10nF
R1
750ꢇ
RB
1
14
11
VNEG
ACOM
VOUT
NC = NO CONNECT
V
V
OUT
N (–0.5VTO –3V)
10% of VREF
.
Figure 15. Using the Buffer to Invert the Polarity
of the Slope
In this example, the hysteresis range is arranged to be 0.1 dB,
(1 mV at VLOG) when using a 5 V supply. This will usually be
adequate to prevent noise that causes the comparator output to
thrash. That risk can be reduced further by using a low-pass filtering
capacitor at VLOG (shown dotted) to decrease the noise bandwidth.
When the gain is set to 13 (RB = 5 kΩ) the 2 V VREF can be tied
directly to BFIN, in which case the starting point for the output
response is at 4 V. However, since the slope in this case is only
–0.2 V/decade, the full current range will only take the output
V
P
VPS2
PWDN
VPS1
10
2
12
AD8304
I
PD
VREF
PDB
BIAS
~10kꢇ
VREF
0.5V
7
VPDB
NC
6
VSUM
INPT
3
4
VLOG
8
5kꢇ
BFIN
9
1nF
VSUM
VREF
MDAC
TEMPERATURE
COMPENSATION
5
VOUT
49.9kꢇ
100kꢇ
BFNG
13
V
10nF
750ꢇ
SPT
RH 50Mꢇ
1
14
11
V
OUT
VNEG
ACOM
VOUT
NC = NO CONNECT
Figure 16. Calibrated Level Comparator
V
P
VPS2
PWDN
VPS1
10
2
12
AD8304
VREF
VLOG
PDB
BIAS
~10kꢇ
VREF
0.5V
7
I
SRC
VPDB
NC
6
VSUM
INPT
3
4
8
VREF
MDAC
5kꢇ
BFIN
VOUT
9
VSUM
TEMPERATURE
COMPENSATION
25kꢇ
5
BFNG
13
C1
10nF
100kꢇ
1
14
11
VNEG
ACOM
VOUT
V
(–0.5VTO –5V)
N
1kꢇ
C2
1nF
NC = NO CONNECT
Figure 17. Multidecade Current Source
–16–
REV. A
AD8304
Programmable Multidecade Current Source
TRIAX
CONNECTOR*
The AD8304 supports a wide variety of general (nonoptical)
applications. For example, the need frequently arises in test
equipment to provide an accurate current that can be varied over
many decades. This can be achieved using a logarithmic amplifier
as the measuring device in an inverse function loop, as illustrated
in Figure 16. This circuit generates the current:
PWDN VNEG VPOS
VOUT
BFIN
AD8304
KEITHLEY 236
INPT
CHARACTERIZATION
BOARD
VLOG
VSUM VPDB VREF
*SIGNAL: INPT;
VSPT /0.2
RIBBON
CABLE
)
ISRC = 100 pA ×10(
GUARD: VSUM;
(17)
SHIELD: GROUND
The principle is as follows. The current in QA is forced to supply
a certain IPD by measuring the error between a setpoint VSPT and
VLOG, and nulling this error by integration. This is performed by
the internal op amp and capacitor C1, with a time constant formed
with the internal 5 kΩ resistor. The choice of C1 in this example
ensures loop stability over the full eight-decade range of output
currents; C2 reduces phase lag. The system is completed with a
10-bit MDAC using VREF as its reference, whose output is scaled
to 1.6 V FS by R1 and R2 (whose parallel sum is also 5 kΩ).
DC MATRIX, DC SUPPLIES, DMM
Figure 18. Primary Characterization Setup
The primary characterization setup shown in Figure 18 is used to
measure the static performance, logarithmic conformance, slope
and intercept, buffer offset and VREF drift with temperature, and
the performance of the VPDB Pin functions. For the dynamic tests,
such as noise and bandwidth, more specialized setups are used.
Transistor QA may be a single bipolar device, which will result in
a small alpha error in ISRC (the current is monitored in the emitter
branch), or a Darlington pair or an MOS device, either of which
ensure a negligible difference between IPD and ISRC. In this example,
the bipolar pair is used. The output voltage compliance is deter-
mined by the collector breakdown voltage of these transistors,
while the minimum voltage depends on where VSUM is placed.
Optional components could be added to put this node and VNEG
at a low enough bias to allow the voltage to go slightly below ground.
HP 3577A
NETWORK
ANALYZER
OUTPUT INPUT INPUTA INPUTB
AD8304
+IN
Many variations of this basic circuit are possible. For example, the
current can be continuously controlled by a simple voltage, or
by a second current. Larger output currents can be controlled by
setting VSUM to zero and using a current shunt divider.
1
2
3
4
5
6
7
ACOM 14
BFNG 13
VPS1 12
VNEG
B
A
AD8138
PWDN
EVALUATION
BOARD
POWER
SPLITTER
+V
S
VSUM
INPT
0.1ꢁF
11
10
9
VOUT
VPS2
BFIN
Characterization Setups and Methods
VSUM
VPDB
During the primary characterization of the AD8304, the device
was treated as a high precision current-in logarithmic amplifier
(converter). Rather than attempting to accurately generate photo-
currents by illuminating a photodiode, precision current sources,
like the Keithley 236, were used as input sources. Great care was
taken when applying the low level input currents. The triax output
of the current source was used with the guard connected to VSUM
at the characterization board. On the board the input trace was
guarded by connecting adjacent traces and a portion of an internal
copper layer to the VSUM Pins. One obvious reason for the care
was leakage current. With 0.5 V as the nominal bias on the
INPT Pin, a resistance of 50 GΩ to ground would cause 10 pA
of leakage, or about one decibel of error at the low end of the
measurement range. Additionally, the high output resistance of
the current source and the long signal cable lengths commonly
needed in characterization make a good receiver for 60 Hz emis-
sions. Good guarding techniques help to reduce the pickup of
unwanted signals.
49.9ꢇ
8
VLOG
VREF
Figure 19. Configuration for Buffer Amplifier
Bandwidth Measurement
Figure 19 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 Evaluation Board provides a
dc offset at the buffer input, allowing measurement in single-supply
mode. The network analyzer input impedance was set to 1 MΩ.
REV. A
–17–
AD8304
HP 3577A
NETWORK
ANALYZER
HP 89410A
CHANNEL CHANNEL
SOURCE TRIGGER
1
2
OUTPUT INPUT INPUTA INPUTB
AD8304
POWER
SPLITTER
1
2
3
4
5
6
7
14
13
12
11
10
9
VNEG
ACOM
BFNG
VPS1
AD8304
PWDN
VSUM
ACOM
1
2
3
4
5
6
7
VNEG
PWDN
VSUM
INPT
14
13
12
11
10
9
BFNG
VPS1
VOUT
VPS2
BFIN
+IN
R1
+V
B
S
AD8138
INPT
VOUT
VPS2
BFIN
ALKALINE
D CELL
R1
EVALUATION
BOARD
0.1F
VSUM
VPDB
VREF
A
750⍀
VSUM
VPDB
VREF
ALKALINE
D CELL
750⍀
1nF
8
VLOG
1nF
VLOG
8
Figure 20. Configuration for Logarithmic
Amplifier Bandwidth Measurement
Figure 21. Configuration for Noise Spectral
Density Measurement
The setup shown in Figure 20 was used for frequency response
measurements of the logarithmic amplifier section. In this con-
figuration, the AD8138 output was offset to 1.5 V and R1 was
adjusted to provide the appropriate operating current. The
buffer amplifier was then used; still any capacitance added at
the VLOG Pin during measurement would form a filter with the
on-chip 5 kΩ resistor.
Evaluation Board
An evaluation board is available for the AD8304, the schematic
for which is shown in Figure 22, and the two board sides are
shown in Figure 23 and Figure 24. It can be configured for a wide
variety of experiments. The board is factory set for Photocon-
ductive Mode with a buffer gain of unity, providing a slope of
10 mV/dB and an intercept of 100 pA. By substituting resistor and
capacitor values, all of the application circuits presented in this
data sheet can be evaluated. Table V describes the various configu-
ration options.
The configuration illustrated in Figure 21 measures the device
noise. Batteries provide both the supply and the input signal to
remove the supplies as a possible noise source and to reduce
ground loop effects. The AD8304 Evaluation Board and the
current setting resistors are mounted in closed aluminum enclo-
sures to provide additional shielding to external noise sources.
+V
GND
–V
S
S
AD8304
R10
10k⍀
1
2
3
4
5
6
7
14
13
12
11
10
9
VNEG
PWDN
VSUM
INPT
ACOM
BFNG
VPS1
VOUT
VPS2
BFIN
C1
C2
R1
0.1nF
1nF
OPEN
R5
OPEN
R2
0⍀
SW1
R7
OPEN
C3
1nF
C4
BUFFER
OUT
0.1F
LK2 OPEN
R13
R7
OPEN
INPUT
LK1
0⍀
R15
750⍀
C11
C8
OPEN
C7
R12
INSTALLED
VSUM
VPDB
VREF
OPEN OPEN
R9
R6
1nF
R11
0⍀
0.1F OPEN
LOG
OUT
C10
0.1F
R14
0⍀
BIASER
8
VLOG
C9
10nF
C6
OPEN
C5
OPEN
R4
OPEN
R3
OPEN
Figure 22. Evaluation Board Schematic
–18–
REV. A
AD8304
Figure 23. Component Side Layout
Figure 24. Component Side Silkscreen
Table V. Evaluation Board Configuration Options
Component
Function
Default Condition
VP, VN, AGND
SW1, R10
Positive and Negative Supply and Ground Pins
Not Applicable
Device Enable: When SW1 is in the “0” position, the PWDN Pin is
connected to ground and the AD8304 is in its normal operating mode.
SW1 = Installed
R10 = 10 kΩ (Size 0603)
R1, R2
Buffer Amplifier Gain/Slope Adjustment: The logarithmic slope
of the AD8304 can be altered using the buffer’s gain-setting resistors,
R1 and R2.
R1 = Open (Size 0603)
R2 = 0 Ω (Size 0603)
R3, R4
Intercept Adjustment: A dc offset can be applied to the input term-
inals of the buffer amplifier to adjust the effective logarithmic intercept.
R3 = Open (Size 0603)
R4 = Open (Size 0603)
R5, R6, R7, R8, R9
Bias Adjustment: The voltage on the VSUM and INPT Pins can be
altered using appropriate resistor values. R9 is populated with a decoup-
ling capacitor to reduce noise pickup. The decoupling capacitor can be
removed when a fixed bias is applied to VSUM.
R5 = R6 = Open (Size 0603)
R7 = R8 = Open (Size 0603)
R9 = 0.1 µF (Size 0603)
C1, C2, C3, C4, C9
C10
Supply Decoupling Capacitors
C1 = C4 = 0.1 µF (Size 0603)
C2 = C3 = 1 nF (Size 0603)
C9 = 10 nF (Size 0603)
Photodiode Biaser Decoupling: Provides high frequency decoupling
of the adaptive bias output at Pin VPDB.
C10 = 0.1 µF (Size 0603)
C5, C6, C7, C8, R11, Output Filtering: Allows implementation of a variety of filter config-
R11 = R13 = 0 Ω (Size 0603)
R12 = Open (Size 0603)
R12, R13, R14
urations, from simple RC low-pass filters to three-pole Sallen and Key.
R14 = 0 Ω (Size 0603)
C5 = C6 = Open (Size 0603)
C7 = C8 = Open (Size 0603)
R15, C11
LK1, LK2
Input Filtering: Provides essential HF compensation at the input
Pin INPT.
R15 = 750 Ω (Size 0603)
C11 = 1 nF (Size 0603)
Guard/Shield Options: The shells of the SMA connectors used
for the input and the photodiode bias can be set to the voltage on the
VSUM Pin or connected to ground.
LK1 = Installed
LK2 = Open
REV. A
–19–
AD8304
OUTLINE DIMENSIONS
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.05
1.00
0.80
0.65
BSC
0.20
0.09
1.20
0.75
0.60
0.45
MAX
8؇
0؇
0.15
0.05
0.30
0.19
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Revision History
Location
Page
8/02—Data Sheet changed from REV. 0 to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
New TPC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to TPC 7 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TPC 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to USING THE AD8304 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
New Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Changes to Table V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
–20–
REV. A
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