AD8305-EVALZ [ADI]
100 dB Range (10 nA to 1 mA) ogarithmic Converter; 百分贝范围（ 10 nA的至1 mA ） ogarithmic转换器
| 型号： | AD8305-EVALZ |
| 厂家： | 
ADI |
| 描述： | 100 dB Range (10 nA to 1 mA) ogarithmic Converter |
| 文件： | 总24页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100 dB Range (10 nA to 1 mA)
Logarithmic Converter
AD8305
FEATURES
FUNCTIONAL BLOCK DIAGRAM
I
V
PD
P
Optimized for fiber optic photodiode interfacing
Measures current over 5 decades
Law conformance 0.1 dB from 10 nA to 1 mA
Single- or dual-supply operation (3 V to 12 V total)
Full log-ratio capabilities
Nominal slope of 10 mV/dB (200 mV/decade)
Nominal intercept of 1 nA (set by external resistor)
Optional adjustment of slope and intercept
Complete and temperature stable
Rapid response time for a given current level
Miniature 16-lead chip scale package
(LFCSP 3 mm × 3 mm)
0.20 log
10
1nA
VPOS
VRDZ
VREF
VOUT
80kΩ
BIAS
GENERATOR
2.5V
200kΩ
20kΩ
COMM
0.5V
SCAL
BFIN
IREF
V
14.2kΩ
BE2
V
I
BIAS
LOG
451Ω
Q2
Q1
–
TEMPERATURE
COMPENSATION
+
VLOG
I
PD
V
BE1
6.69kΩ
COMM
INPT
VSUM
0.5V
Low power: ~5 mA quiescent current
COMM
VNEG
Figure 1.
APPLICATIONS
Optical power measurement
Wide range baseband logarithmic compression
Measurement of current and voltage ratios
Optical absorbance measurement
GENERAL DESCRIPTION
The AD83051 is an inexpensive microminiature logarithmic converter
optimized for determining optical power in fiber optic systems. It uses
an advanced implementation of a classic translinear (junction based)
technique to provide a large dynamic range in a versatile and easily
used form. A single-supply voltage of between 3 V and 12 V is
adequate; dual supplies may optionally be used. The low quiescent
current (typically 5 mA) permits use in battery-operated applications.
The logarithmic intercept (also known as the reference current) is
nominally positioned at 1 nA by the use of the externally generated
current, IREF, of 10 μA, provided by a 200 kΩ resistor connected
between VREF, at 2.5 V, and the reference input, IREF, at 0.5 V. The
intercept can be adjusted over a wide range by varying this resistor.
The AD8305 can also operate in a log ratio mode, with the numerator
current applied to INPT and the denominator current applied to IREF.
The input current, IPD, of 10 nA to 1 mA applied to the INPT pin is the
collector current of an optimally scaled NPN transistor, which converts
this current to a voltage (VBE) with a precise logarithmic relationship. A
A buffer amplifier is provided for driving a substantial load, for use in
raising the basic slope of 10 mV/dB to higher values, as a precision
comparator (threshold detector), or in implementing low-pass filters.
Its rail-to-rail output stage can swing to within 100 mV of the positive
and negative supply rails, and its peak current sourcing capacity is
25 mA.
second such converter is used to handle the reference current (IREF
)
applied to pin IREF. These input nodes are biased slightly above ground
(0.5 V). This is generally acceptable for photodiode applications where
the anode does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating IREF. The output of the logarithmic
front end is available at Pin VLOG.
It is a fundamental aspect of translinear logarithmic converters that the
small signal bandwidth falls as the current level diminishes, and the
low frequency noise-spectral density increases. At the 10 nA level, the
bandwidth of the AD8305 is about 50 kHz and increases in proportion
to IPD up to a maximum value of about 15 MHz. Using the buffer
amplifier, the increase in noise level at low currents can be addressed by
using it to realize lowpass filters of up to three poles.
The basic logarithmic slope at this output is nominally 200 mV/decade
(10 mV/dB). Thus, a 100 dB range corresponds to an output change of
1 V. When this voltage (or the buffer output) is applied to an ADC that
permits an external reference voltage to be employed, the AD8305
voltage reference output of 2.5 V at Pin VREF can be used to improve
the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit),
AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other
values of the logarithmic slope can be provided using a simple external
The AD8305 is available in a 16-lead LFCSP package and is specified
for operation from −40°C to +85°C.
resistor network.
1 Protected by U.S. Patent No. 5,519,308.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
AD8305
TABLE OF CONTENTS
Features .............................................................................................. 1
Managing Intercept and Slope.................................................. 12
Response Time and Noise Considerations ............................. 12
Power Supply Sequencing ......................................................... 12
Applications..................................................................................... 14
Calibration....................................................................................... 15
Using A Negative Supply ............................................................... 16
Log-Ratio Applications.................................................................. 17
Reversing The Input Polarity........................................................ 18
Characterization Methods............................................................. 19
Evaluation Board ............................................................................ 21
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
General Structure ........................................................................... 11
Theory.......................................................................................... 11
REVISION HISTORY
4/10—Rev. A to Rev. B
Updated Data Sheet............................................................Universal
Change to Figure 2 and Table 3 ...................................................... 5
Added Power Supply Sequencing Section................................... 12
Added Figure 34; Renumbered Sequentially .............................. 12
Changes to Ordering Guide .......................................................... 24
3/03—Rev. 0 to Rev. A
Changes to TPC 3............................................................................. 4
Changes to TPC 18........................................................................... 6
Changes to Figure 3........................................................................ 11
Changes to Figure 8........................................................................ 13
Updated Outline Dimensions....................................................... 18
Rev. B | Page 2 of 24
AD8305
SPECIFICATIONS
VP = 5 V, VN = 0 V, TA = 25°C, RREF = 200 kΩ, and VRDZ connected to VREF, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Specified Current Range, IPD
Pin 4, INPT, Pin 3, IREF
Flows toward INPT pin
10
nA
1
10
mA
mA
nA
Input Current Min/Max Limits
Reference Current, IREF, Range
Flows toward INPT pin
Flows toward IREF pin
10
1
0.54
mA
V
Summing Node Voltage
Temperature Drift
Input Offset Voltage
LOGARITHMIC OUTPUT
Logarithmic Slope
Internally preset; may be altered by the user
−40°C < TA < +85°C
VINPT − VSUM, VIREF − VSUM
Pin 9, VLOG
0.46
−20
0.5
0.015
mV/°C
mV
+20
190
185
0.3
200
1
210
215
1.7
2.5
0.4
mV/dec
mV/dec
nA
nA
dB
mV√Hz
MHz
V
V
kΩ
−40°C < TA < +85°C
Logarithmic Intercept1
−40°C < TA < +85°C
10 nA < IPD < 1 mA
IPD > 1 μA
0.1
Law Conformance Error
Wideband Noise2
Small Signal Bandwidth2
Maximum Output Voltage
Minimum Output Voltage
Output Resistance
0.1
0.7
0.7
1.7
0.01
5
IPD > 1 μA
Limited by VN = 0 V
Pin 2, VREF
4.375
5.625
REFERENCE OUTPUT
Voltage With Reference to Ground
2.435
2.4
2.5
2.565
2.6
V
V
−40°C < TA < +85°C
Maximum Output Current
Incremental Output Resistance
OUTPUT BUFFER
Sourcing (grounded load)
Load current < 10 mA
20
2
mA
Ω
Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT
Input Offset Voltage
Input Bias Current
−20
+20
mV
mA
MΩ
V
Flowing out of Pin 10 or Pin 11
0.4
35
VP − 0.1
0.5
25
Incremental Input Resistance
Output Range
Incremental Output Resistance
Peak Source/Sink Current
Small Signal Bandwidth
Slew Rate
RL = 1 kΩ to ground
Load current < 10 mA
Ω
mA
MHz
V/μs
GAIN = 1
15
15
0.2 V to 4.8 V output swing
Pin 8, VPOS; Pin 6 and Pin 7, VNEG
(VP − VN) ≤ 12 V
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
3
5
5.4
0
12
6.5
V
mA
V
Negative Supply Voltage (Optional)
(VP − VN) ≤ 12 V
−5.5
1 Other values of logarithmic intercept can be achieved by adjusting RREF
2 Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.
.
Rev. B | Page 3 of 24
AD8305
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage VP − VN
Input Current
12 V
20 mA
Internal Power Dissipation
θJA
500 mW
30°C/W
1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
125°C
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
300°C
Lead Temperature (Soldering 60 sec)
1 With package die paddle soldered to thermal pad containing nine vias
connected to inner and bottom layers.
Rev. B | Page 4 of 24
AD8305
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
12 VOUT
11 SCAL
10 BFIN
9 VLOG
VRDZ 1
VREF 2
IREF 3
INPT 4
INDICATOR
AD8305
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT EPAD TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
VRDZ
Top of a Resistive Divider Network that Offsets VLOG to Position the Intercept. Normally connected to VREF;
may also be connected to ground when bipolar outputs are to be provided.
2
3
4
VREF
IREF
INPT
Reference Output Voltage of 2.5 V.
Accepts (Sinks) Reference Current, IREF
Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo current
flows into INPT.
.
5
VSUM
Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node
potential.
6, 7
8
9
10
11
12
VNEG
VPOS
VLOG
BFIN
SCAL
VOUT
Optional Negative Supply, VN (this pin is usually grounded; for details of usage, see the Applications section.
Positive Supply, (VP − VN ) ≤ 12 V.
Output of the Logarithmic Front End.
Buffer Amplifier Noninverting Input.
Buffer Amplifier Inverting Input.
Buffer Output.
13 to 16 COMM
EPAD
Analog Ground.
The exposed pad must be soldered to ground.
Rev. B | Page 5 of 24
AD8305
TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V, VN = 0 V, RREF = 200 kΩ, TA = 25°C, unless otherwise noted.
2.0
1.5
1.6
T
V
= –40°C, 0°C, +25°C, +70°C, +85°C
= 0V
T
V
= –40°C, 0°C, +25°C, +70°C, +85°C
= 0V
A
A
N
N
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
+85°C
+70°C
–40°C
+25°C
+85°C
0.5
0
–0.5
–1.0
–1.5
–2.0
+25°C
0°C
–40°C
0°C
+70°C
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
I
I
PD
PD
Figure 3. VLOG vs. IPD for Multiple Temperatures
Figure 6. Law Conformance Error vs. IPD (at IREF = 10 μA) for Multiple
Temperatures, Normalized to 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
T
V
= –40°C, 0°C, +25°C, +70°C, +85°C
= 0V
T
V
= –40°C, 0°C, +25°C, +70°C, +85°C
= 0V
A
A
–40°C
N
N
1.5
1.0
0°C
+70°C
+85°C
+70°C
0.5
+25°C
+85°C
0
–0.5
–1.0
–1.5
–2.0
+25°C
0°C
–40°C
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
I
REF
I
PD
Figure 4. VLOG vs. IREF for Multiple Temperatures
Figure 7. Law Conformance Error vs. IREF (at IPD = 10 μA) for Multiple
Temperatures, Normalized to 25°C
0.5
0.4
0.3
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10µA
100µA 1mA
0.2
0.1
10nA
100nA
1µA
0
–0.1
–0.2
–0.3
–0.4
–0.5
1µA
10µA
10nA 100nA
100µA
1mA
1n
10n
100n
1µ
I
10µ
(A)
100µ
1m
10m
1n
10n
100n
1µ
I
10µ
(A)
100µ
1m
10m
PD
PD
Figure 5. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps
from 10 nA to 1 mA)
Rev. B | Page 6 of 24
AD8305
0.5
0.4
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1µA
10nA
100nA
0.3
10µA
0.2
0.1
0
1mA
100µA
10µA
1µA
100nA
10nA
–0.1
–0.2
–0.3
–0.4
–0.5
1mA
100n
100µA
10n
1n
1µ
10µ
(A)
100µ
1m
10m
1n
10n
100n
1µ
I
10µ
(A)
100µ
1m
10m
I
REF
REF
Figure 9. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from
10 nA to 1 mA)
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade
Steps from 10 nA to 1 mA)
0.5
1.4
+3V, 0V
0.4
+5V, 0V
+9V, 0V
+12V, 0V
1.2
100µA TO 1mA:T-RISE = <1µs,
T- FAL L = < 1µ s
0.3
0.2
1.0
10µATO 10µA:T-RISE = <1µs,
T- FAL L = < 1µ s
0.1
0.8
1µATO 10µA:T-RISE = 1µs,
T- FAL L = 5 µ s
0
0.6
–0.1
–0.2
–0.3
–0.4
–0.5
100nA TO 1µA:T-RISE = 5µs,
T-FALL = 20µs
+3V, –0.5V
+5V, –5V
0.4
10nATO 100nA:T-RISE = 20µs,
T- FA L L = 30 µ s
0.2
0
–20
1n
10n
100n
1µ
I
10µ
100µ
1m
10m
0
20
40
60
80
100 120 140 160 180
(A)
TIME (µs)
PD
Figure 10. Law Conformance Error vs. IPD for Various Supply Conditions (See
Annotations)
Figure 13. Pulse Response − IPD to VOUT (G = 1)
0.4
0.3
1.6
1.4
1.2
1.0
0.8
10nATO 100nA:T-RISE = 30µs,
T-FALL = 20µs
0.2
100nA TO 1µA:T-RISE = 30µs,
T- FAL L = 5µ s
0.1
1µATO 10µA:T-RISE = 5µs,
T- FA L L = 1µ s
0
10µATO 100µA:T-RISE = 1µs,
T- FAL L = < 1µ s
0.6
0.4
–0.1
–0.2
–0.3
–0.4
100µA TO 1mA:T-RISE = <1µs,
T- FAL L = < 1µ s
0.2
0
–20
0
20
40
60
80
100 120 140 160 180
1n
10n
100n
1µ
I
10µ
100µ
1m
10m
TIME (µs)
(A)
PD
Figure 11. VINPT − VSUM vs. IPD
Figure 14. Pulse Response − IREF to VOUT (G = 1)
Rev. B | Page 7 of 24
AD8305
10
3
0
10nA
100nA
10µA
0
100µA
A
= 1
V
–10
–20
–30
–40
–3
A
= 2
V
A
= 5
V
1mA
–6
–9
A
= 2.5
1µA
V
–50
100
–12
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 15. Small Signal AC Response (5% Sine Modulation), from IPD to VOUT
(G = 1) for IPD in Decade Steps from 10 nA to 1 mA, IREF = 10 μA
Figure 18. Small Signal AC Response of the Buffer for Various Closed-Loop
Gains (RL = 1 kΩ CL < 2 pF)
10
2.0
1.5
100nA
10µA
10nA
0
–10
–20
–30
100µA
1.0
MEAN + 3σ
0.5
0
1mA
–0.5
MEAN – 3σ
1µA
–1.0
–40
–50
–1.5
–2.0
100
1k
10k
100k
1M
10M
100M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 19. Buffer Input Offset Drift vs. Temperature (3σ to Either Side of
Mean)
Figure 16. Small Signal AC Response (5% Sine Modulation), from IREF to VOUT
(G = 1) for IREF in Decade Steps from 10 nA to 1 mA, IPD = 10 μA
6
5
4
3
2
1
0
100
10nA
10
100nA
1
1µA
10µA
0.1
100µA
0.01
100
10n
100n
1µ
10µ
(A)
100µ
1m
10m
1k
10k
100k
1M
10M
FREQUENCY (Hz)
I
PD
Figure 20. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1)
Figure 17. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency for IPD in
Decade Steps from 10 nA to 1 mA
Rev. B | Page 8 of 24
AD8305
2.0
1.5
20
15
T
= 25°C
A
10
1.0
MEAN + 3σ
5
0.5
MEAN + 3σ
MEAN – 3σ
0
0
–5
–0.5
–1.0
–1.5
–2.0
–10
–15
–20
–25
MEAN – 3σ
1n
10n
100n
1µ
I
10µ
(A)
100µ
1m
10m
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
PD
Figure 21. Law Conformance Error Distribution (3σ to Either Side of Mean)
Figure 24. VREF Drift vs. Temperature (3σ to Either Side of Mean)
20
2.0
T
= 0°C, 70°C
A
1.5
1.0
15
10
MEAN + 3σ @ 70°C
MEAN + 3σ
MEAN – 3σ
0.5
5
0
0
MEAN ± 3σ @ 0°C
MEAN – 3σ @ 70°C
–5
–0.5
–1.0
–1.5
–2.0
–10
–15
–20
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
I
PD
Figure 22. Law Conformance Error Distribution (3σ to Either Side of Mean)
Figure 25. VREF − VIREF Drift vs. Temperature (3σ to Either Side of Mean)
4
5
4
3
2
T
= –40°C, +85°C
A
3
2
MEAN + 3σ @ –40°C
1
1
MEAN + 3σ
MEAN ± 3σ @ +85°C
0
–1
–2
0
–1
–2
–3
–4
MEAN – 3σ
–3
MEAN – 3σ @ –40°C
–4
–5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
I
PD
Figure 26. VINPT Drift vs. Temperature (3σ to Either Side of Mean)
Figure 23. Law Conformance Error Distribution (3σ to Either Side of Mean)
Rev. B | Page 9 of 24
AD8305
10
4000
3500
8
6
3000
2500
2000
1500
4
MEAN + 3σ
MEAN – 3σ
2
0
–2
–4
–6
–8
–10
1000
500
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
INTERCEPT (nA)
Figure 27. Slope Drift vs. Temperature (3σ to Either Side of Mean of
200 mV/decade)
Figure 30. Distribution of Logarithmic Intercept (Nominally 1 nA when
RREF = 200 kΩ 0.1%) Sample >22,000
350
7000
6000
5000
4000
3000
2000
250
MEAN + 3σ
150
50
–50
–150
MEAN – 3σ
1000
0
–250
–350
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
2.44
2.46
2.48
2.50
(V)
2.52
2.54
2.56
85
V
TEMPERATURE (°C)
REF
Figure 28. Intercept Drift vs. Temperature (3σ to Either Side of Mean of 1 nA)
Figure 31. Distribution of VREF (RL = 100 kΩ) Sample >22,000
6000
6000
5000
4000
5000
4000
3000
2000
1000
3000
2000
1000
0
190
0
195
200
205
210
–0.015
–0.010
–0.005
0
0.005
VOLTAGE (V)
SUM
0.010
0.015
SLOPE (mV/dec)
V
– V
INPT
Figure 29. Distribution of Logarithmic Slope (Nominally
200 mV/decade) Sample >22,000
Figure 32. Distribution of Offset Voltage (VINPT − VSUM) Sample >22,000
Rev. B | Page 10 of 24
AD8305
GENERAL STRUCTURE
The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and is also
useful in many nonoptical applications. These notes explain the
structure of this unique style of translinear log amp. Figure 33 is
a simplified schematic showing the key elements.
THEORY
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
VBE = kT/qIn(IC/IS)
where:
(1)
BIAS
GENERATOR
V
BE1
IREF
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T × K
PHOTODIODE
2.5V
80kΩ
0.5V
VREF
I
REF
V
BE2
INPUT CURRENT
IC is its collector current.
IS is a scaling current, typically only 10−17 A.
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT) and is 25.85 mV at 300 K.
20kΩ
I
PD
COMM
0.5V
VSUM
44µA/dec
INPT
14.2kΩ
6.69kΩ
451Ω
VRDZ
VLOG
The current, IS, is never precisely defined and exhibits an even
stronger temperature dependence, varying by a factor of
roughly a billion between −35°C and +85°C. Thus, to make use
of the BJT as an accurate logarithmic element, both of these
temperature dependencies must be eliminated.
0.5V
Q1
Q2
V
V
BE2
BE1
COMM
VNEG (NORMALLY GROUNDED)
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current IPD and the
second operating at a reference current IREF, can be written as:
Figure 33. Simplified Schematic
The photodiode current, IPD, is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current IPD to a corresponding logarithmic voltage, as shown in
Equation 1. A finite positive value of VSUM is needed to bias the
collector of Q1 for the usual case of a single-supply voltage. This
is internally set to 0.5 V, that is, one fifth of the reference voltage
of 2.5 V appearing on Pin VREF. The resistance at the VSUM
pin is nominally 16 kΩ; this voltage is not intended as a general
bias source.
V
BE1 − VBE2 = kT/q In(IC/IS) − kT/q In(IREF/IS)
= In(10)kT/qlog10(IPD/IREF
= 59.5 mVlog10(IPD/IREF)(T = 300 K)
)
(2)
The uncertain and temperature dependent saturation current
IS, which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage-
mode to current-mode, is an intermediate, temperature-
corrected current:
The AD8305 also supports the use of an optional negative
supply voltage, VN, at Pin VNEG. When VN is −0.5 V or more
negative, VSUM may be connected to ground; thus, INPT and
IREF assume this potential. This allows operation as a voltage-
input logarithmic converter by the inclusion of a series resistor
at either or both inputs. Note that the resistor setting IREF needs
to be adjusted to maintain the intercept value. It should also be
noted that the collector-emitter voltages of Q1 and Q2 are now
the full VN, and effects due to self-heating causes errors at large
input currents.
I
LOG = IY log10(IPD/IREF
)
(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, IY is 44 μA, resulting in a temperature
independent slope of 44 mA/decade, for all values of IPD and
I
REF. This current is subsequently converted back to a voltage-
mode output, VLOG, scaled 200 mV/decade.
It is apparent that this output should be zero for IPD = IREF and
would need to swing negative for smaller values of input
current. To avoid this, IREF would need to be as small as the
smallest value of IPD. However, it is impractical to use such a
small reference current as 1 nA. Accordingly, an offset voltage is
added to VLOG to shift it upward by 0.8 V when Pin VRDZ is
directly connected to VREF. This has the effect of moving the
intercept to the left by four decades, from 10 μA to 1 nA:
The input dependent, VBE1, of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. This is generated
externally, to a recommended value of 10 μA. However, other
values over a several-decade range can be used with a slight
degradation in law conformance (see Figure 3).
ILOG = IY log10(IPD/IINTC
)
(4)
where IINTC is the operational value of the intercept current. To
disable this offset, Pin VRDZ should be grounded, then the
intercept IINTC is simply IREF. Because values of IPD < IINTC result in
a negative VLOG, a negative supply of sufficient value is
Rev. B | Page 11 of 24
AD8305
required to accommodate this situation (see the Using A
Negative Supply section).
RESPONSE TIME AND NOISE CONSIDERATIONS
The response time and output noise of the AD8305 are
fundamentally a function of the signal current, IPD. For small
currents, the bandwidth is proportional to IPD, as shown in
Figure 15. The output low frequency voltage-noise spectral-
density is a function of IPD (Figure 17) and also increases for
small values of IREF. Details of the noise and bandwidth
performance of translinear log amps can be found in the
AD8304 data sheet.
The voltage, VLOG, is generated by applying ILOG to an internal
resistance of 4.55 kΩ, formed by the parallel combination of a
6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the
VRDZ pin. When the VLOG pin is unloaded and the intercept
repositioning is disabled by grounding VRDZ, the output
current, ILOG, generates a voltage at the VLOG pin of
V
LOG = ILOG × 4.55 kΩ
= 44 μA × 4.55 kΩ × log10(IPD/IREF
)
(5)
POWER SUPPLY SEQUENCING
= VY log10(IPD/IREF
)
Some applications may result in the presence of large input
signal current (>1 mA) prior to the AD8305 being powered on.
In such cases, it is recommended that power supply sequencing
be implemented such that the AD8305 is powered on prior to
the photodiode or current source.
where VY = 200 mV/decade, or 10 mV/dB. Note that any
resistive loading on VLOG lowers this slope and also result in
an overall scaling uncertainty due to the variability of the on-
chip resistors. Consequently, this practice is not recommended.
V
LOG may also swing below ground when dual supplies (VP and
In those applications where it is not possible to implement
supply sequencing, VSUM should be driven externally by a low
impedance source. In applications where a low-impedance bias-
source is not readily available, the circuit shown in Figure 34
can be used.
VN) are used. When VN = −0.5 V or larger, the input pins INPT
and IREF may now be positioned at ground level by simply
grounding VSUM.
MANAGING INTERCEPT AND SLOPE
+V
P
When using a single supply, VRDZ should be directly connected to
VREF to allow operation over the entire five-decade input current
range. As noted previously, this introduces an accurate offset
voltage of 0.8 V at the VLOG pin, equivalent to four decades,
resulting in a logarithmic transfer function that can be written as
+V
BIAS
VPOS
I
PD
INPT
C1
R1
V
LOG = VY log10(104 × IPD/IREF
= VY log10 (IPD/IINTC
where IINTC = IREF/104.
)
)
(6)
Thus, the effective intercept current IINTC is only one ten-
thousandth of IREF, corresponding to 1 nA when using the
recommended value of IREF = 10 mA.
+V
S
VSUM
+
I
R
E
A
V
–
BE
VNEG COMM
≈0.5V
2N2907
C
2
β
The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged, in view of the fact that the on-
chip resistors do not ratio correctly to the added resistance. Also, it
is rare that one would want to lower the basic slope of 10 mV/dB; if
this is needed, it should be effected at the low impedance output
of the buffer, which is provided to avoid such miscalibration and
also allow higher slopes to be used.
R
B
I
C
Figure 34. VSUM Biasing Circuit for Applications Where Large Input Signals
Are Present Prior to AD8305 Power-On
The 2N2907 transistor used in Figure 34 is a common PNP-type
switching transistor. Ra and Rb are selected such that the voltage
at the base of the transistor is ~0.5 V.
The AD8305 buffer is essentially an uncommitted op amp with
rail-to-rail output swing, good load-driving capabilities, and a
unity-gain bandwidth of >12 MHz. In addition to allowing the
introduction of gain, using standard feedback networks and
thereby increasing the slope voltage VY, the buffer can be used
to implement multipole low-pass filters, threshold detectors,
and a variety of other functions. Further details of these can be
found in the AD8304 data sheet.
In general, VS × [Rb/(Ra+Rb)] should equal approximately 0.5 V.
Setting Ra = 5 kꢀ and Rb = 1 kꢀ, results in 500 μA of additional
quiescent current for a 3 V supply under normal operation.
Larger resistor values may be used for this divider network by
choosing a transistor with a higher β than the 2N2907.
Given a typical Vbe of 0.7 V, the voltage at VSUM is ~1.2 V when
the AD8305 is off and a large input signal is being applied. Once
the AD8305 is powered on the voltage at VSUM is pulled down
to its nominal value of 0.5 V. The circuit in Figure 34 is tested
for 3 V to 5 V positive supplies over the full temperature range
for the AD8305. C1, and R1 are the components that make up
Rev. B | Page 12 of 24
AD8305
the input compensation network and C2 is the recommended
bypassing capacitor on VSUM.
and connect the resistor divider directly to VSUM. In this case
the bias voltage at VSUM and INPT is set by the resistor values
selected for the divider, not the internal biasing of the AD8305.
If board space limits the amount of external circuitry to the
AD8305 it is possible to eliminate the transistor in Figure 34
Rev. B | Page 13 of 24
AD8305
APPLICATIONS
The AD8305 is easy to use in optical supervisory systems and in
similar situations where a wide ranging current is to be
converted to its logarithmic equivalent, which is represented in
decibel terms. Basic connections for measuring a single-current
input are shown in Figure 35, which also includes various
nonessential components.
Because the basic scaling at VLOG is 0.2 V/decade, and a swing
of 4 V at the buffer output would correspond to 20 decades, it is
often useful to raise the slope to make better use of the rail-to- rail
voltage range. For illustrative purposes, the circuit in Figure 35
provides an overall slope of 0.5 V/ decade (25 mV/dB). Thus,
using IREF = 10 μA, VLOG runs from 0.2 V at IPD = 10 nA to 1.4 V
at IPD = 1 mA while the buffer output runs from 0.5 V to 3.5 V,
corresponding to a dynamic range of 120 dB (electrical, that is,
60 dB optical power).
I
PD
+5V
VPOS
0.5 log
10
1nA
VRDZ
VREF
VOUT
BIAS
GENERATOR
The optional capacitor from VLOG to ground forms a single-
pole low-pass filter in combination with the 4.55 kΩ resistance
at this pin. For example, using a CFLT of 10 nF, the −3 dB corner
frequency is 3.5 kHz. Such filtering is useful in minimizing the
output noise, particularly when IPD is small. Multipole filters are
more effective in reducing the total noise; examples are provided in
the AD8304 data sheet.
12kΩ
8kΩ
80kΩ 2.5V
200kΩ
20kΩ
COMM
0.5V
SCAL
BFIN
IREF
V
14.2kΩ
BE2
1kΩ
I
V
LOG
BIAS
451Ω
Q2
Q1
–
TEMPERATURE
COMPENSATION
1nF
VLOG
+
C
10nF
I
INPT
FLT
PD
V
BE1
6.69kΩ
COMM
VSUM
1nF
1kΩ
0.5V
The dynamic response of this overall input system is influenced
by the external RC networks connected from the two inputs
(INPT, IREF) to ground. These are required to stabilize the
input systems over the full current range. The bandwidth
changes with the input current due to the widely varying pole
frequency. The RC network adds a zero to the input system to
ensure stability over the full range of input current levels. The
network values shown in Figure 35 usually suffice, but some
experimentation may be necessary when the photodiode
capacitance is high.
1nF
VNEG
COMM
Figure 35. Basic Connections for Fixed Intercept Use
The 2 V difference in voltage between the VREF and INPT pins
in conjunction with the external 200 kΩ resistor RREF provide a
reference current, IREF, of 10 μA into Pin IREF. Connecting pin
VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively
lowering the intercept current, IINTC, by a factor of 104 to
position it at 1 nA. A wide range of other values for IREF, from
under 100 nA to over 1 mA, may be used. The effect of such
changes is shown in Figure 5.
Although the two current inputs are similar, some care is
needed to operate the reference input at extremes of current
(<100 nA) and temperature (<0°C). Modifying the RC network
to 4.7 nF and 2 kΩ is recommended for measuring 10 nA at
−40°C. By inspecting the transient response to perturbations in
Any temperature variation in RREF must be taken into account
when estimating the stability of the intercept. Also, the overall
noise increases when using very low values of IREF. In fixed
intercept applications, there is little benefit in using a large
reference current, since this only compresses the low current
end of the dynamic range when operated from a single supply,
here shown as 5 V. The capacitor between VSUM and ground is
recommended to minimize the noise on this node and to help
provide a clean reference current.
I
REF at representative current levels, the capacitor value can be
adjusted to provide fast rise and fall times with acceptable
settling. To fine tune the network zero, the resistor value should be
adjusted.
Rev. B | Page 14 of 24
AD8305
CALIBRATION
The AD8305 has a nominal slope and intercept of 200 mV/decade
and 1 nA, respectively. These values are untrimmed, and the
slope alone may vary as much as 7.5% over temperature. For
this reason, it is recommended that a simple calibration be done
to achieve increased accuracy.
Figure 36 shows the improvement in accuracy when using a two
point calibration method. To perform this calibration, apply
two known currents, I1 and I2, in the linear operating range
between 10 nA and 1 mA. Measure the resulting output, V1 and
V2, respectively, and calculate the slope m and intercept b.
1.4
4
m = (V1 − V2)/[log10(I1) − log10(I2)]
b = V1 – m × log10(I1)
(7)
(8)
UNCALIBRATED ERROR
MEASURED OUTPUT
1.2
3
The same calibration is performed with two known optical
powers, P1 and P2. This allows for calibration of the entire
measurement system while providing a simplified relationship
between the incident optical power and VLOG voltage.
1.0
0.8
0.6
0.4
0.2
0
2
1
0
m = (V1 − V2)/(P1 − P2)
(9)
(10)
CALIBRATED ERROR
–1
b = V1 − m × P1
IDEAL OUTPUT
The uncalibrated error line in Figure 36 is generated assuming
that the slope of the measured output was 200 mV/ decade
when in fact it was actually 194 mV/decade. Correcting for this
discrepancy decreased measurement error up to 3 dB.
–2
–3
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
I
PD
Figure 36. Using Two-Point Calibration to Increase Measurement Accuracy
Rev. B | Page 15 of 24
AD8305
USING A NEGATIVE SUPPLY
Most applications of the AD8305 require only a single supply of
3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 37.
I
source does, however, need to be able to support the quiescent
current as well as the INPT and IREF signal current. For
example, it may be convenient to utilize a forward-biased
junction voltage of about 0.7 V or a Schottky barrier voltage of a
little over 0.5 V. The effect of supply on the dynamic range and
accuracy can be seen in Figure 10.
5V
PD
0.5 log
10
1nA
VPOS
VRDZ
VREF
VOUT
BIAS
GENERATOR
With the summing node at ground, the AD8305 may now be
used as a voltage-input log amp at either the numerator input,
INPT, or the denominator input, IREF, by inserting a suitably
scaled resistor from the voltage source to the relevant pin. The
overall accuracy for small input voltages is limited by the
voltage offset at the inputs of the JFET op amps.
12k
8k
Ω
80k
Ω
2.5V
RREF
200k
20k
Ω
Ω
Ω
COMM
0.5V
SCAL
BFIN
IREF
V
14.2k
Ω
BE2
1k
Ω
V
I
LOG
BIAS
Q2
Q1
TEMPERATURE
COMPENSATION
–
1nF
+
VLOG
451
Ω
C
FLT
10nF
I
INPT
PD
V
BE1
6.69kΩ
COMM
VSUM
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of IPD. However, the voltage, VLOG, remains
referenced to the ACOM pin, and while it does not swing
negative for default operating conditions, it is free to do so,
thus, adding a resistor from VLOG to the negative supply
lowers all values of VLOG, which raises the intercept. The
disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistances causes errors in both the slope
and the intercept.
1k
Ω
1nF
0.5V
+
F
–
VNEG
COMM
V
I
+ I
SIG
q
V
≤ –0.5V
NEG
I
= I + I
PD REF
SIG
R
S
V
– V
F
C1
N
R
≤
S
I
+ I
SIGMAX
q
V
N
Figure 37. Negative Supply Application
The use of a negative supply, VN, allows the summing node to
be placed at ground level whenever the input transistor (Q1 in
Figure 33) has a sufficiently negative bias on its emitter. When
VNEG = −0.5 V, the VCE of Q1 and Q2 is the same as for the
default case when VSUM is grounded. This bias does not need
to be accurate, and a poorly defined source can be used. The
5V
VPOS
VRDZ
VOUT
I
PD
80kΩ
2.5V
0.5 log
10
VREF
+ 2
BIAS
GENERATOR
I
REF
P
44.2kΩ
REF
18nF
20kΩ
28.0kΩ
COMM
REFERENCE
DETECTOR
0.5V
SCAL
BFIN
33nF
IREF
V
BE2
14.2kΩ
I
REF
1kΩ
I
12.1kΩ
LOG
451Ω
Q2
Q1
–
+
TEMPERATURE
COMPENSATION
5V
1nF
VLOG
I
PD
V
BE1
6.69kΩ
COMM
INPT
SIGNAL
1kΩ
DETECTOR
0.5V
VSUM
1nF
P
SIG
VNEG
COMM
Figure 38. Optical Absorbance Measurement
Rev. B | Page 16 of 24
AD8305
LOG-RATIO APPLICATIONS
It is often desirable to determine the ratio of two currents, for
example, in absorbance measurements. These are commonly
used to assess the attenuation of a passive optical component,
such as an optical filter or variable optical attenuator. In these
situations, a reference detector is used to measure the incident
power entering the component. The exiting power is then
measured using a second detector and the ratio is calculated to
determine the attenuation factor. Because the AD8305 is
fundamentally a ratiometric device, having nearly identical
logging systems for both numerator and denominator (IPD and
of 4.55 kΩ present at Pin VLOG. While this does not ratio
exactly to the external resistor, which may slightly alter the Q of
the filter, the effect on pulse response is be negligible for most
purposes. Note that the gain of the buffer (×2.5) is an integral
part of this illustrative filter design; in general, the filter may be
redesigned for other closed-loop gains.
The transfer characteristics can be expressed in terms of optical
power. If we assume that the two detectors have equal
responsivities, the relationship is
V
OUT = 0.5 V log10(104 × PSIG/PREF
)
(11)
I
REF, respectively), it can greatly simplify such measurements.
Using the identity log10(AB) = log10A + log10B and defining the
attenuation as −10 × log10(PSIG/PREF), the overall transfer
characteristic can be written as
Figure 38 illustrates the AD8305 log-ratio capabilities in optical
absorbance measurements. Here a reference detector diode is
used to provide the reference current, IREF, proportional to the
optical reference power level. A second detector measures the
transmitted signal power, proportional to IPD. The AD8305
calculates the logarithm of the ratio of these two currents, as
shown in Equation 11, and which is reformulated in power
terms in Equation 12. Both of these equations include the
internal factor of 10,000 introduced by the output offset applied
to VLOG via pin VRDZ. If the true (nonoffset) log ratio shown in
Equation 4 is preferred, VRDZ should be grounded to remove
the offset. As already noted, the use of a negative supply at Pin
VNEG allows both VLOG and the buffer output to swing below
ground, and also allow the input pins INPT and IREF to be set
to ground potential. Therefore, the AD8305 may also be used to
determine the log ratio of two voltages.
V
OUT = 2 − 50 mV/dB × α
(12)
where α = −10 × log10(PSIG/PREF
)
Figure 39 illustrates the linear-in-dB relationship between the
absorbance and the output of the circuit in Figure 38.
2.5
2.0
1.5
1.0
Figure 38 also illustrates how a second order Sallen-Key low-
pass filter can be realized using two external capacitors and one
resistor. Here, the corner frequency is set to 1 kHz and the filter
Q is chosen to provide an optimally flat (overshoot-free) pulse
response. To scale this frequency either up or down, simply
scale the capacitors by the appropriate factor. Note that one of
the resistors needed to realize this filter is the output resistance
0.5
0
0
5
10
15
20
25
30
35
40
45
50
ATTENUATION (dB)
Figure 39. Example of an Absorbance Transfer Function
Rev. B | Page 17 of 24
AD8305
REVERSING THE INPUT POLARITY
Some applications may require interfacing to a circuit that
sources current rather than sinks current, such as connecting to
the cathode side of a photodiode. Figure 40 shows the use of a
current mirror circuit. This allows for simultaneous monitoring
of the optical power at the cathode, and a data recovery path
using a transimpedance amplifier at the anode. The modified
Wilson mirror provides a current gain very close to unity and a
high output resistance. Figure 41 shows measured transfer
function and law conformance performance of the AD8305 in
conjunction with this current mirror interface.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.00
0.75
0.50
0.25
0
+5V
+3V
–0.25
–0.50
–0.75
–1.00
5V
+3V
+5V
5V
0.1µF
V
= 0.2 ×
OUT
5V
log (I /1nA)
10 PD
16
COMM COMM COMM COMM
VRDZ VOUT
15
14
13
1n
10n
100n
1µ
10µ
(A)
100µ
1m
10m
OUTPUT
12
MAT03
I
PD
1
2
3
4
Figure 41. Log Output and Error Using Current Mirror with Various Supplies
2.5V
0V
11
10
9
VREF
IREF
INPT
SCAL
BFIN
200kΩ
MAT03
AD8305
1nF
0V
VLOG
I
≈ I
IN PD
10nA TO 1mA
I
PD 1kΩ
VSUM VNEG VNEG VPOS
5
7
8
6
1nF
0.1µF
5V
TIA
DATA PATH
Figure 40. Wilson Current Mirror for Cathode Interfacing
Rev. B | Page 18 of 24
AD8305
CHARACTERIZATION METHODS
During the characterization of the AD8305, the device was
treated as a precision current-input logarithmic converter,
because it is not practical for several reasons to generate
accurate photocurrents by illuminating a photodiode. The test
currents are generated by using well calibrated current sources,
such as the Keithley 236, or by using a high value resistor from a
voltage source to the input pin. Great care is needed when using
very small input currents. For example, the triax output
connection from the current generator was used with the guard
tied to VSUM. The input trace on the PC board was guarded by
connecting adjacent traces to VSUM.
HP 3577A
NETWORK ANALYZER
OUTPUT
INPUT R
INPUT A
INPUT B
AD8138
B
+IN
EVALUATION
16
15
14
13
BNC-T
BOARD
A
COMM COMM COMM COMM
AD8138
PROVIDES DC OFFSET
12
VRDZ
VOUT
SCAL
BFIN
1
These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GΩ to ground would subtract
0.5 nA from the input, which amounts to an error of −0.44 dB
for a source current of 10 nA. Additionally, the very high output
resistance at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reduce the pickup of these spurious
signals.
11
10
9
VREF
IREF
INPT
2
3
4
AD8305
VLOG
VSUM VNEG VNEG VPOS
5
6
7
8
+V
S
0.1µF
Figure 43. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 43 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
provisions to offset VLOG at the buffer input, allowing
measurements over the full range of IPD using a single supply.
The network analyzer input impedances were set to 1 MΩ.
VREF
IREF
VNEG
VPOS
VOUT
KEITHLEY 236
KEITHLEY 236
AD8305
CHARACTERIZATION BFIN
BOARD
VLOG
INPT
VSUM
HP 3577A
NETWORK ANALYZER
TRIAX CONNECTORS
(SIGNAL – INPT AND IREF
GUARD – VSUM
DC MATRIX/DC SUPPLIES/DMM
OUTPUT
INPUT R
INPUT A
INPUT B
SHIELD – GROUND)
Figure 42. Primary Characterization Setup
The primary characterization setup shown in Figure 42 is used
to measure VREF, the static (dc) performance, logarithmic
conformance, slope and intercept, the voltages appearing at pins
VSUM, INPT and IREF, and the buffer offset and VREF drift with
temperature. To ensure stable operation over the full current
range of IREF and temperature extremes, filter components of
C1 = 4.7 nF and R13 = 2 kΩ are used at pin to IREF ground. In
some cases, a fixed resistor between pins VREF and IREF was
used in place of a precision current source. For the dynamic
tests, including noise and bandwidth measurements, more
specialized setups are required.
POWER
SPLITTER
16
15
14
13
COMM COMM COMM COMM
12
VRDZ
VOUT
SCAL
BFIN
1
2
3
4
11
10
VREF
IREF
INPT
AD8305
R2
1nF
B
+IN AD8138
EVALUATION
BOARD
1kΩ
R1
9
VLOG
A
VSUM VNEG VNEG VPOS
1kΩ
5
7
8
6
1nF
+V
S
0.1µF
Figure 44. Configuration for Logarithmic Amplifier Bandwidth Measurement
Rev. B | Page 19 of 24
AD8305
The setup shown in Figure 44 was used for frequency response
measurements of the logarithmic amplifier section. The
AD8138 output is offset to 1.5 V dc and modulated to a depth
of 5% at frequency. R1 is chosen (over a wide range of values up
to 1.0 GΩ) to provide IPD. The buffer was used to deload VLOG
from the measurement system.
LECROY 9210
CH A
9213
TDS5104
CH1
HP 89410A
16
15
14
13
SOURCE
TRIGGER CHANNEL 1 CHANNEL 2
COMM COMM COMM COMM
12
VRDZ
VOUT
SCAL
BFIN
1
2
3
4
11
10
9
VREF
IREF
INPT
AD8305
200kΩ
1kΩ
16
15
14
13
1nF
R1
COMM COMM COMM COMM
VLOG
12
VSUM VNEG VNEG VPOS
VRDZ
VOUT
SCAL
BFIN
1
2
3
4
1kΩ
5
7
8
6
1nF
11
10
9
VREF
IREF
INPT
+V
S
AD8305
200kΩ
1kΩ
1nF
0.1µF
ALKALINE
“D” CELL
Figure 46. Configuration for Logarithmic Amplifier Pulse Response
Measurement
R1
VLOG
+
–
VSUM VNEG VNEG VPOS
1kΩ
Figure 46 shows the setup used to make the pulse response
measurements. As with the bandwidth measurement, the
VLOG is connected directly to BFIN and the buffer amplifier is
configured for unity gain. The output of the buffer is connected
through a short cable to the TDS5104 scope with input
impedance set to 1 MΩ. The LeCroy’s output is offset to create
the initial pedestal current for a given value of R1, the pulse
then creates one-decade current step.
5
7
8
6
ALKALINE
“D” CELL
1nF
+
–
0.1µF
+
–
+
–
Figure 45. Configuration for Noise Spectral Density Measurement
The configuration in Figure 45 is used to measure the noise
performance. Batteries provide both the supply voltage and the
input current to minimize the introduction of spurious noise
and ground loop effects. The entire evaluation system,
including the current setting resistors, is mounted in a closed
aluminum enclosure to provide additional shielding to external
noise sources.
Rev. B | Page 20 of 24
AD8305
EVALUATION BOARD
An evaluation board is available for the AD8305, the schematic for which is shown in Figure 49. It can be configured for a wide variety of
experiments. The buffer gain is factory-set to unity, providing a slope of 200 mV/decade, and the intercept is set to 1 nA. Table 4 describes
the various configuration options.
Table 4. Evaluation Board Configuration Options
Component
Function
Default Condition
P1
Supply interface. Provides access to supply pins, VNEG, COMM, and VPOS.
P1 = installed
P2, R8, R9, R10,
R11, R17, R18
Monitor Interface. By adding 0 Ω resistors to R8, R9, R10, R11, R17, and R18, the
VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored using a high
impedance probe.
P2 = Not installed
R8 = R9 = R10 = Open (size 0603)
R17 = R18 = Open (size 0603)
R2, R3, R4, R6,
R14, C2, C7, C9,
C10
Buffer amplifier/output interface. The logarithmic slope of the AD8305 can be
altered using the buffer’s gain-setting resistors, R2 and R3. R4, R14, and C2 allow
variation in the buffer loading. R6, C7, C9, and C10 are provided for a variety of
filtering applications.
R2 = R6 = 0 Ω (size 0603)
R3 = R4 = open (size 0603)
R11 = R14 = 0 Ω (size 0603)
C2 = C7 = open (size 0603)
C9 = C10 = open (size 0603)
VLOG = VOUT = installed
R1, R7, R19, R20
Intercept adjustment. The voltage dropped across resistor R1 determines the
intercept reference current, nominally set to 10 μA using a 200 kΩ 1% resistor. R7
and R19 can be used to adjust the output-offset voltage at the VLOG output.
R1 = 200 kΩ (size 0603)
R7 = R19 = 0 Ω (size 0603)
R20 = open (size 0603)
R12, R15, C3, C4,
C5, C6
Supply Decoupling.
C3 = C4 = 0.01 μF
(size 0603)
C5 = C6 = 0.1 μF (size 0603)
R12 = R15 = 0 Ω (size 0603)
C11
VSUM decoupling capacitor.
C11 = 1 nF (size 0603)
R13, R16, C1, C8
Input compensation. Provides essential HF compensation at the input pins, INPT
and IREF.
R13 = R16 = 1 kΩ (size 0603)
C1 = C8 = 1 nF (size 0603)
IREF, INPT, PD,
LK1, R5
Input interface. The test board is configured to accept a current through the SMA
connector labeled INPT. An SC-style packaged photodiode can be used in place
of the INPT SMA for optical interfacing. By removing R1 and adding a 0 Ω short
IREF = INPT = installed
PD = not installed
LK1 = installed
for R5, a second current can be applied to the IREF input (also SMA) for evaluating R5 = open (size 0603)
the AD8305 in log-ratio applications.
J1
SC-Style Photodiode. Allows for direct mounting of SC style photodiodes.
J1 = not installed
Rev. B | Page 21 of 24
AD8305
Figure 47. Component Side Layout
Figure 48. Component Side Silkscreen
Rev. B | Page 22 of 24
AD8305
R10
16
15
14
13
VOUT
VOUT
OPEN
COMM COMM COMM COMM
R20
OPEN
R14
R17
VOUT 12
1
2
3
4
VRDZ
VREF
VRDZ
VREF
IREF
INPT
0Ω
OPEN
C2
OPEN
R4
R7
R2
OPEN
0Ω
0Ω
R3
R18
R19
C9
OPEN
SCAL
BFIN
11
10
OPEN
OPEN
0Ω
R1
200kΩ
1%
AD8305
R8
I
R6
R5
REF
VLOG
IREF
0Ω
C10
OPEN
OPEN
OPEN
R13
1kΩ
I
R11
PD
VLOG
9
VLOG
C1
1nF
1
2
3
0Ω
C7
OPEN
VSUM VNEG
VNEG
VPOS
SC-STYLE
PD
5
6
7
8
VRDZ
1
INPT
AGND
VOUT
VREF
2
3
C4
C3
0.01µF
0.01µF
R16
LK1
1kΩ
R9
OPEN
C11
1nF
R15
0Ω
R12
0Ω
C8
1nF
C5
0.1µF
4
5
C6
0.1µF
VSUM
AGND
2
VSUM
VLOG
VPOS
VNEG
1
3
P1
6
P2
Figure 49. Evaluation Board Schematic
Rev. B | Page 23 of 24
AD8305
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
16-Lead LFCSP
16-Lead LFCSP, 7”Tape and Reel
16-Lead LFCSP
16-Lead LFCSP, 7”Tape and Reel
Evaluation Board
Package Option Ordering Quantity Branding
CP-16-2
CP-16-2
CP-16-2
CP-16-2
JEA
AD8305ACP-R2
−40°C to +85°C
250
1500
250
AD8305ACP-REEL7 −40°C to +85°C
JEA
JEA#
JEA#
AD8305ACPZ-R2
AD8305ACPZ-RL7
AD8305-EVALZ
−40°C to +85°C
−40°C to +85°C
1500
1 Z = RoHS Compliant Part; # denotes lead-free product may be top or bottom marked.
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03053-0-4/10(B)
Rev. B | Page 24 of 24
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