AD8306AR-REEL [ADI]
5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier; 5兆赫， 400兆赫百分贝高精度限流，对数放大器
| 型号： | AD8306AR-REEL |
| 厂家： | 
ADI |
| 描述： | 5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier |
| 文件： | 总16页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
a
AD8306
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
؎0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
LIM
INHI
LMHI
12dB
12dB
12dB
INLO
LMLO
BIAS
LADR ATTEN
LMDR
CTRL
4
؋
DET DET
DET
DET
Overall Gain 90 dB, Bandwidth 400 MHz
VLOG
FLTR
I–V
Constant Phase (Typical ؎56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 k⍀, CIN = 2.5 pF
500 ns Power-Up Time, <1 A Sleep Current
TEN DETECTORS SPACED 12dB
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
ENBL
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 Ω level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each of
2 V in amplitude, which would correspond to a sine wave power
of +22 dBm if the differential input were terminated in 50 Ω.
Through laser trimming, the slope of the RSSI output is closely
controlled to 20 mV/dB, while the intercept is set to –108 dBV
(–95 dBm re 50 Ω). These scaling parameters are determined
by a band-gap voltage reference and are substantially indepen-
dent of temperature and supply. The logarithmic law conform-
ance is typically within ±0.4 dB over the central 80 dB of this
range at any frequency between 10 MHz and 200 MHz, and is
degraded only slightly at 400 MHz.
PRODUCT DESCRIPTION
The AD8306 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 400 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and typi-
cally 2 mA, providing a limiter gain of 90 dB when using 200 Ω
loads. A CMOS-compatible control interface can enable the
AD8306 within about 500 ns and disable it to a standby current
of under 1 µA.
The RSSI response time is nominally 73 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 Ω and
this interface remains stable with any value of capacitance on
the output.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kΩ in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 Ω, source is 1.28 nV/√Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8306 can be raised by using an input matching network.
The AD8306 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead narrow body SO package. The AD8306 is
also available for the full military temperature range of –55°C to
+125°C, in a 16-lead side-brazed ceramic DIP.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(V = +5 V, T = +25؇C, f = 10 MHz, unless otherwise noted)
AD8306–SPECIFICATIONS
S
A
Parameter
Conditions
Min1
Typ
Max1
Units
INPUT STAGE
Maximum Input2
(Inputs INHI, INLO)
Differential Drive, p-p
±3.5
±4
V
+9
dBV
dBm
nV/√Hz
dBm
Ω
Equivalent Power in 50 Ω
Noise Floor
Equivalent Power in 50 Ω
Input Resistance
Input Capacitance
DC Bias Voltage
Terminated in 52.3 ΩʈRIN
Terminated 50 Ω Source
400 MHz Bandwidth
From INHI to INLO
From INHI to INLO
Either Input
+22
1.28
–78
1000
2.5
800
1200
400
pF
V
1.725
LIMITING AMPLIFIER
Usable Frequency Range
At Limiter Output
(Outputs LMHI, LMLO)
5
0
MHz
MHz
Degrees
mA
RLOAD = RLIM = 50 Ω, to –10 dB Point
585
±2
1
Phase Variation at 100 MHz
Limiter Output Current
Versus Temperature
Over Input Range –73 dBV to –3 dBV
Nominally 400 mV/RLIM
–40°C ≤ TA ≤ +85°C
10
–0.008
%/°C
dBV
V
Input Range3
–78
1
+9
Maximum Output Voltage
Rise/Fall Time (10%–90%)
At Either LMHI or LMLO, wrt VPS2
RLOAD = 50 Ω, 40 Ω ≤ RLIM ≤ 400 Ω
1.25
0.6
ns
LOGARITHMIC AMPLIFIER
±3 dB Error Dynamic Range
Transfer Slope4
(Output VLOG)
From Noise Floor to Maximum Input
f = 10 MHz
f = 100 MHz
–40°C < TA < +85°C
f = 10 MHz
100
20
19.6
20
–108
–108.4
–108
–0.009
±0.4
0.34
2.34
2.10
50
dB
19.5
20.5
20.7
mV/dB
mV/dB
mV/dB
Over Temperature
19.3
–109.5
Intercept (Log Offset)4
–106.5 dBV
dBV
f = 100 MHz
–40°C ≤ TA ≤ +85°C
Over Temperature
–111
–105
dBV
dB/°C
dB
V
V
V
Ω
mA
Ω
Temperature Sensitivity
Linearity Error (Ripple)
Output Voltage
Input from –80 dBV to +0 dBV
Input = –91 dBV, VS = +5 V, +2.7 V
Input = +9 dBV, VS = +5 V
2.75
1.25
Input = –3 dBV, VS = +3 V
Minimum Load Resistance, RL
Maximum Sink Current
Output Resistance
40
0.75
To Ground
1.0
0.3
Small-Signal Bandwidth
Output Settling Time to 2%
Rise/Fall Time (10%–90%)
3.5
120
73
MHz
ns
ns
Large Scale Input, +3 dBV, RL ≥ 50 Ω, CL ≤ 100 pF
Large Scale Input, +3 dBV, RL ≥ 50 Ω, CL ≤ 100 pF
220
100
POWER INTERFACES
Supply Voltage, VS
Quiescent Current
Over Temperature
Disable Current
Additional Bias for Limiter
Logic Level to Enable Power
Input Current when HI
Logic Level to Disable Power
2.7
13
11
5
16
16
0.01
2.0
6.5
20
23
4
2.25
VS
60
V
Zero-Signal, LMDR Open
–40°C < TA < +85°C
–40°C < TA < +85°C
mA
mA
µA
mA
V
RLIM = 400 Ω (See Text)
HI Condition, –40°C < TA < +85°C
3 V at ENBL, –40°C < TA < +85°C
LO Condition, –40°C < TA < +85°C
2.7
40
1
µA
V
–0.5
TRANSISTOR COUNT
# of Transistors
207
207
NOTES
1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50 Ω termination, dBV values
can be converted into dBm by adding a fixed offset of +13 to the dBV rms value.
3Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50 Ω).
4Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17.
Specifications subject to change without notice.
–2–
REV. A
AD8306
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature Range
–65°C to +150°C
Lead Temperature Range (Soldering 60 sec)
+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 V
Input Level, Differential (re 50 Ω) . . . . . . . . . . . . . . . +26 dBm
Input Level, Single-Ended (re 50 Ω) . . . . . . . . . . . . . +20 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 800 mW
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
Model
AD8306AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
16-Lead Narrow Body SO
13" Tape and Reel
7" Tape and Reel
SO-16
SO-16
SO-16
AD8306AR-REEL
AD8306AR-REEL7
AD8306ACHIPS
5962-9864601QEA
AD8306-EVAL
Die
16-Lead Side-Brazed Ceramic DIP
Evaluation Board
D-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8306 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
Pin
Name Function
1
2
3
4
5
6
7
8
16 VLOG
15 VPS2
COM2
VPS1
PADL
INHI
1
2
COM2 Special Common Pin for RSSI Output.
VPS1
Supply Pin for First Five Amplifier Stages
and the Main Biasing System.
PADL
LMHI
14
13
AD8306
TOP VIEW
(Not to Scale)
3, 6, 11, 14 PADL Four Tie-Downs to the Paddle on
which the IC Is Mounted; Grounded.
INLO
PADL
COM1
ENBL
12 LMLO
PADL
FLTR
LMDR
11
10
9
4
INHI
Signal Input, HI or Plus Polarity.
5
INLO Signal Input, LO or Minus Polarity.
COM1 Main Common Connection.
7
8
ENBL Chip Enable; Active When HI.
LMDR Limiter Drive Programming Pin.
FLTR RSSI Bandwidth-Reduction Pin.
LMLO Limiter Output, LO or Minus Polarity.
LMHI Limiter Output, HI or Plus Polarity.
9
10
12
13
15
VPS2
Supply Pin for Sixth Gain Stage, Limiter
and RSSI Output Stage Load Current.
16
VLOG Logarithmic (RSSI) Output.
REV. A
–3–
AD8306–Typical Performance Characteristics
100
10
1
VLOG
500mV PER
VERTICAL
DIVISION
T
= +25؇C
A
T
= –40؇C
A
0.1
0.01
T
= +85؇C
A
GROUND REFERENCE
INPUT
INPUT LEVEL
SHOWN IS –3dBV
0.001
1V PER
VERTICAL
DIVISION
0.0001
100ns PER HORIZONTAL DIVISION
0.00001
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
ENABLE VOLTAGE – V
Figure 1. Supply Current vs. Enable Voltage @
TA = –40°C, +25°C and +85°C
Figure 4. RSSI Pulse Response for Inputs Stepped from
Zero to –83 dBV, –63 dBV, –43 dBV, –23 dBV, –3 dBV
14
12
VLOG
500mV PER
VERTICAL
DIVISION
10
ADDITIONAL SUPPLY CURRENT
8
6
4
GROUND REFERENCE
INPUT
2V PER
VERTICAL
DIVISION
LIMITER OUTPUT
2
CURRENT
100ns PER HORIZONTAL DIVISION
0
0
50
100
150
200
250
– ⍀
300
350
400
450
R
LIM
Figure 2. Additional Supply Current and Limiter Output
Current vs. RLIM
Figure 5. Large Signal RSSI Pulse Response with RL = 100 Ω
and CL = 33 pF, 100 pF and 330 pF (Overlapping Curves)
270pF
27pF
VLOG
VLOG
500mV PER
VERTICAL
DIVISION
200mV PER
3300pF
VERTICAL
DIVISION
GROUND REFERENCE
INPUT
GROUND REFERENCE
2V PER
VERTICAL
DIVISION
100ns PER HORIZONTAL DIVISION
100s PER HORIZONTAL DIVISION
Figure 3. Large Signal RSSI Pulse Response with
CL = 100 pF and RL = 50 Ω and 75 Ω (Curves Overlap)
Figure 6. Small Signal AC Response of RSSI Output with
External Filter Capacitance of 27 pF, 270 pF and 3300 pF
–4–
REV. A
AD8306
2.5
2
5
4
3
2
T
= +85؇C
A
1
0
1.5
1
T
= +25؇C
A
–1
–2
–3
T
= –40؇C
A
T
= +85؇C
A
0.5
0
–4
–5
T
= –40؇C
A
T
= +25؇C
A
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
(+13dBm)
(+13dBm)
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 7. RSSI Output vs. Input Level, 100 MHz Sine In-
Figure 10. Log Linearity of RSSI Output vs. Input Level,
put, at TA = –40°C, +25°C and +85°C, Single-Ended Input
100 MHz Sine Input, at TA = –40°C, +25°C, and +85°C
2.5
5
100MHz
DYNAMIC RANGE ؎1dB ؎3dB
4
10MHz
50MHz
100MHz
86
90
96
93
97
100
2
3
2
50MHz
10MHz
1
0
1.5
100MHz
10MHz
50MHz
1
0.5
0
–1
–2
–3
–4
–5
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
(+13dBm)
(+13dBm)
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 8. RSSI Output vs. Input Level, at TA = +25°C, for
Figure 11. Log Linearity of RSSI Output vs. Input Level, at
Frequencies of 10 MHz, 50 MHz and 100 MHz
TA = +25°C, for Frequencies of 10 MHz, 50 MHz and 100 MHz
2.5
5
200MHz
DYNAMIC RANGE ؎1dB ؎3dB
4
200MHz
300MHz
400MHz
96
90
85
100
100
100
2
3
2
400MHz
300MHz
1
0
1.5
200MHz
400MHz
300MHz
1
0.5
0
–1
–2
–3
–4
–5
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
–120
–100
(–87dBm)
–80
–60
–40
–20
0
20
(+13dBm)
(+13dBm)
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 9. RSSI Output vs. Input Level, at TA = +25°C, for
Frequencies of 200 MHz, 300 MHz and 400 MHz
Figure 12. Log Linearity of RSSI Output vs. Input Level,
at TA = +25°C, for Frequencies of 200 MHz, 300 MHz and
400 MHz
REV. A
–5–
AD8306
21
–106
–107
–108
–109
–110
–111
–112
20
19
18
17
0
0
100
200
300
400
100
200
300
400
FREQUENCY – MHz
FREQUENCY – MHz
Figure 13. RSSI Slope vs. Frequency Using Termination of
Figure 16. RSSI Intercept vs. Frequency Using Termina-
52.3 Ω
tion of 52.3 Ω
0.4
0.40
0.375
0.35
0.35
0.30
0.325
0.3
0.25
0.20
0.275
0.25
0.15
0.10
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
FREQUENCY – MHz
FREQUENCY – MHz
Figure 14. RSSI Slope Standard Deviation vs. Frequency
Figure 17. RSSI Intercept Standard Deviation vs. Frequency
10
8
LMLO
6
4
LMHI
2
T
= +85؇C
LIMITER OUTPUTS: 50mV PER VERTICAL DIVISION
A
0
–2
–4
–6
T
= –40؇C
A
T
= +25؇C
A
INPUT: 1mV PER VERTICAL DIVISION
12.5ns PER HORIZONTAL DIVISION
–8
–10
–73
–63
(–50dBm)
–53
–43
–33
–23
–13
(0dBm)
–3
INPUT LEVEL – dBV
Figure 15. Limiter Response at LMHI, LMLO with Pulsed
Sine Input of –73 dBV (–60 dBm) at 50 MHz; RLOAD = 50 Ω,
RLIM = 200 Ω
Figure 18. Normalized Limiter Phase Response vs. Input
Level. Frequency = 100 MHz; TA = –40°C, +25°C and +85°C
–6–
REV. A
AD8306
PRODUCT OVERVIEW
differential current-mode outputs of all ten detectors stages are
summed with equal weightings and converted to a single-sided
voltage by the output stage, generating the logarithmic (or RSSI)
output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is,
400 mV per decade). The junction between the lower and upper
regions is seamless, and the logarithmic law-conformance is
typically well within ±0.4 dB over the 80 dB range from –80 dBV
to 0 dBV (–67 dBm to +13 dBm).
The AD8306 is built on an advanced dielectrically-isolated
complementary bipolar process using thin-film resistor technol-
ogy for accurate scaling. It follows well-developed foundations
proven over a period of some fifteen years, with constant refine-
ment. The backbone of the AD8306 (Figure 19) comprises a
chain of six main amplifier/limiter stages, each having a gain of
12.04 dB (×4) and small-signal –3 dB bandwidth of 850 MHz.
The input interface at INHI and INLO (Pins 4 and 5) is fully
differential. Thus it may be driven from either single-sided or
balanced inputs, the latter being required at the very top end of
the dynamic range, where the total differential drive may be as
large as 4 V in amplitude.
The full-scale rise time of the RSSI output stage, which operates
as a two-pole low-pass filter with a corner frequency of 3.5 MHz,
is about 200 ns. A capacitor connected between FLTR (Pin 10)
and VLOG can be used to lower the corner frequency (see be-
low). The output has a minimum level of about 0.34 V (corre-
sponding to a noise power of –78 dBm, or 17 dB above the
nominal intercept of –95 dBm). This rather high baseline level
ensures that the pulse response remains unimpaired at very low
inputs.
The first six stages, also used in developing the logarithmic
RSSI output, are followed by a versatile programmable-output,
and thus programmable-gain, final limiter section. Its open-
collector outputs are also fully differential, at LMHI and LMLO
(Pins 12 and 13). This output stage provides a gain of 18 dB
when using equal valued load and bias setting resistors and the
pin-to-pin output is used. The overall voltage gain is thus 90 dB.
When using RLIM = RLOAD = 200 Ω, the additional current
consumption in the limiter is approximately 2.8 mA, of which
2 mA goes to the load. The ratio depends on RLIM (for example,
when 20 Ω, the efficiency is 90%), and the voltage at the pin
LMDR is rather more than 400 mV, but the total load current
The maximum RSSI output depends on the supply voltage and
the load. An output of 2.34 V, that is, 20 mV/dB × (9 + 108) dB, is
guaranteed when using a supply voltage of 4.5 V or greater and
a load resistance of 50 Ω or higher, for a differential input of
9 dBV (a 4 V sine amplitude, using balanced drives). When
using a 3 V supply, the maximum differential input may still be
as high as –3 dBV (1 V sine amplitude), and the corresponding
RSSI output of 2.1 V, that is, 20 mV/dB × (–3 + 108) dB is also
guaranteed.
is accurately (400 mV)/RLIM
.
The rise and fall times of the hard-limited (essentially square-
wave) voltage at the outputs are typically 0.6 ns, when driven by
a sine wave input having an amplitude of 316 µV or greater, and
A fully-programmable output interface is provided for the hard-
limited signal, permitting the user to establish the optimal output
current from its differential current-mode output. Its magnitude
is determined by the resistor RLIM placed between LMDR (Pin
9) and ground, across which a nominal bias voltage of ~400 mV
appears. Using RLIM = 200 Ω, this dc bias current, which is
commutated alternately to the output pins, LMHI and LMLO,
by the signal, is 2 mA. (The total supply current is somewhat
higher).
RLOAD = 50 Ω. The change in time-delay (“phase skew”) over
the input range –73 dBV (316 µV in amplitude, or –60 dBm in
50 Ω) to –3 dBV (1 V or +10 dBm) is ±56 ps (±2° at 100 MHz).
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
LIM
INHI
LMHI
12dB
12dB
12dB
INLO
LMLO
These currents may readily be converted to voltage form by the
inclusion of load resistors, which will typically range from a few
tens of ohms at 400 MHz to as high as 2 kΩ in lower frequency
applications. Alternatively, a resonant load may be used to extract
the fundamental signal and modulation sidebands, minimizing
the out-of-band noise. A transformer or impedance matching
network may also be used at this output. The peak voltage swing
down from the supply voltage may be 1.2 V, before the output
transistors go into saturation. (The Applications section provides
further information on the use of this interface).
BIAS
CTRL
LADR ATTEN
LMDR
4
؋
DET DET
DET
DET
I–V
VLOG
FLTR
TEN DETECTORS SPACED 12dB
GAIN
BIAS
BAND-GAP
SLOPE
BIAS
INTERCEPT
TEMP COMP
ENBL
REFERENCE
Figure 19. Main Features of the AD8306
The six main cells and their associated full-wave detectors,
having a transconductance (gm) form, handle the lower part of
the dynamic range. Biasing for these cells is provided by two
references, one of which determines their gain, the other being a
band-gap cell which determines the logarithmic slope, and sta-
bilizes it against supply and temperature variations. A special
dc-offset-sensing cell (not shown in Figure 19) is placed at the
end of this main section, and used to null any residual offset at
the input, ensuring accurate response down to the noise floor.
The first amplifier stage provides a short-circuited voltage-noise
spectral-density of 1.07 nV/√Hz.
The supply current for all sections except the limiter output
stage, and with no load attached to the RSSI output, is nomi-
nally 16 mA at TA = 27°C, substantially independent of supply
voltage. It varies in direct proportion to the absolute tempera-
ture (PTAT). The RSSI load current is simply the voltage at
VLOG divided by the load resistance (e.g., 2.4 mA max in a
1 kΩ load). The limiter supply current is 1.1 times that flowing
in RLIM. The AD8306 may be enabled/disabled by a CMOS-
compatible level at ENBL (Pin 8).
In the following simplified interface diagrams, the components
denoted with an uppercase “R” are thin-film resistors having a
very low temperature-coefficient of resistance and high linearity
under large-signal conditions. Their absolute value is typically
within ±20%. Capacitors denoted using an uppercase “C” have
a typical tolerance of ±15% and essentially zero temperature or
The last detector stage includes a modification to temperature-
stabilize the log-intercept, which is accurately positioned so as
to make optimal use of the full output voltage range. Four fur-
ther “top end” detectors are placed at 12.04 dB taps along a
passive attenuator, to handle the upper part of the range. The
REV. A
–7–
AD8306
handled using a supply of 4.5 V or greater. When using a fully-
balanced drive, the +3 dBV level may be achieved for the sup-
plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies
in the range 10 MHz to 200 MHz these high drive levels are
easily achieved using a matching network. Using such a net-
work, having an inductor at the input, the input transient is
eliminated.
voltage sensitivity. Most interfaces have additional small junc-
tion capacitances associated with them, due to active devices or
ESD protection; these may be neither accurate nor stable.
Component numbering in each of these interface diagrams is
local.
Enable Interface
The chip-enable interface is shown in Figure 20. The current in
R1 controls the turn-on and turn-off states of the band-gap
reference and the bias generator, and is a maximum of 100 µA
when Pin 8 is taken to 5 V. Left unconnected, or at any voltage
below 1 V, the AD8306 will be disabled, when it consumes a
sleep current of much less than 1 µA (leakage currents only); when
tied to the supply, or any voltage above 2 V, it will be fully enabled.
The internal bias circuitry requires approximately 300 ns for
either OFF or ON, while a delay of some 6 µs is required for the
supply current to fall below 10 µA.
Limiter Output Interface
The simplified limiter output stage is shown in Figure 22. The
bias for this stage is provided by a temperature-stable reference
voltage of nominally 400 mV which is forced across the exter-
nal resistor RLIM connected from Pin 9 (LMDR, or limiter
drive) by a special op amp buffer stage. The biasing scheme
also introduces a slight “lift” to this voltage to compensate for
the finite current gain of the current source Q3 and the output
transistors Q1 and Q2. A maximum current of 10 mA is per-
missible (RLIM = 40 Ω). In special applications, it may be desir-
able to modulate the bias current; an example of this is provided
in the Applications section. Note that while the bias currents are
temperature stable, the ac gain of this stage will vary with tem-
perature, by –6 dB over a 120°C range.
ENBL
R1
60k⍀
TO BIAS
ENABLE
1.3k⍀
A pair of supply and temperature stable complementary cur-
rents is generated at the differential output LMHI and LMLO
(Pins 12 and 13), having a square wave form with rise and fall
times of typically 0.6 ns, when load resistors of 50 Ω are used.
The voltage at these output pins may swing to 1.2 V below the
supply voltage applied to VPS2 (Pin 15).
50k⍀
4k⍀
COMM
Figure 20. Enable Interface
Because of the very high gain bandwidth product of this ampli-
fier considerable care must be exercised in using the limiter
outputs. The minimum necessary bias current and voltage
swings should be used. These outputs are best utilized in a
fully-differential mode. A flux-coupled transformer, a balun, or
an output matching network can be selected to transform these
voltages to a single-sided form. Equal load resistors are recom-
mended, even when only one output pin is used, and these
should always be returned to the same well decoupled node on
the PC board. When the AD8306 is used only to generate an
RSSI output, the limiter should be completely disabled by
omitting RLIM and strapping LMHI and LMLO to VPS2.
Input Interface
Figure 21 shows the essentials of the signal input interface. The
parasitic capacitances to ground are labeled CP; the differential
input capacitance, CD, mainly due to the diffusion capacitance
of Q1 and Q2. In most applications both input pins are ac-
coupled. The switch S closes when Enable is asserted. When
disabled, the inputs float, bias current IE is shut off, and the
coupling capacitors remain charged. If the log amp is disabled
for long periods, small leakage currents will discharge these
capacitors. If they are poorly matched, charging currents at
power-up can generate a transient input voltage which may
block the lower reaches of the dynamic range until it has be-
come much less than the signal.
VPS2
LMHI LMLO
VPS1
1.3k⍀ 1.3k⍀
TO STAGES
1 THRU 5
S
3.65k⍀
1.725V
= 1k⍀
1.78V
Q1
67⍀
67⍀
3.65k⍀
= 15mA
4e
FROM FINAL
LIMITER STAGE
I
C
B
INHI
C
Q1
TO 2ND
STAGE
Q2
20e
SIGNAL
INPUT
C
4e
D
R
R
= 3k⍀
IN
IN
2.5pF
Q2
400mV
1.725V
20e
OA
ZERO-TC
C
INLO
C
Q3
2.6k⍀
2.6k⍀
1.3k⍀
1.3k⍀
GAIN BIAS
1.26V
(TOP-END
DETECTORS)
COM1
3.4mA
PTAT
C
C
130⍀
P
P
LMDR
COMM
R
LIM
Figure 22. Limiter Output Interface
RSSI Output Interface
The outputs from the ten detectors are differential currents,
having an average value that is dependent on the signal input
level, plus a fluctuation at twice the input frequency. The cur-
rents are summed at the internal nodes LGP and LGN shown
in Figure 23. A further current IT is added to LGP, to position
Figure 21. Signal Input Interface
In most applications, the input signal will be single-sided, and
may be applied to either Pin 4 or 5, with the remaining pin ac-
coupled to ground. Under these conditions, the largest input
signal that can be handled is –3 dBV (sine amplitude of 1 V)
when operating from a 3 V supply; a +3 dBV input may be
–8–
REV. A
AD8306
range: a 60 Hz hum, picked up due to poor grounding tech-
niques; spurious coupling from digital logic on the same PC
board; a strong EMI source; etc.
the intercept to –108 dBV, by raising the RSSI output voltage for
zero input, and to provide temperature compensation, resulting
in a stable intercept. For zero signal conditions, all the detector
output currents are equal. For a finite input, of either polarity,
their difference is converted by the output interface to a single-
sided voltage nominally scaled 20 mV/dB (400 mV per decade), at
the output VLOG (Pin 16). This scaling is controlled by a sepa-
rate feedback stage, having a tightly controlled transcon-
ductance. A small uncertainty in the log slope and intercept
remains (see Specifications); the intercept may be adjusted (see
Applications).
Very careful shielding is essential to guard against such un-
wanted signals, and also to minimize the likelihood of instability
due to HF feedback from the limiter outputs to the input. With
this in mind, the minimum possible limiter gain should be used.
Where only the logarithmic amplifier (RSSI) function is re-
quired, the limiter should be disabled by omitting RLIM and
tying the outputs LMHI and LMLO directly to VPS2. A good
ground plane should be used to provide a low impedance con-
nection to the common pins, for the decoupling capacitor(s)
used at VPS1 and VPS2, and at the output ground. Note that
COM2 is a special ground pin serving just the RSSI output.
VPS2
I
SOURCE
>50mA
CURRENT
MIRROR
ON DEMAND
1.3k⍀
1.3k⍀
SUMMED
DETECTOR
OUTPUTS
The four pins labeled PADL tie down directly to the metallic
lead frame, and are thus connected to the back of the chip. The
process on which the AD8306 is fabricated uses a bonded-wafer
technique to provide a silicon-on-insulator isolation, and there is
no junction or other dc path from the back side to the circuitry
on the surface. These paddle pins must be connected directly to
the ground plane using the shortest possible lead lengths to
minimize inductance.
FLTR
C1
3.5pF
LGP
C
F
LGN
VLOG
20mV/dB
I
SINK
I
T
3.3k⍀
3.3k⍀
FIXED
1mA
VLOG
125A
250s
COMM
The voltages at the two supply pins should not be allowed to
differ greatly; up to 500 mV is permissible. It is desirable to
allow VPS1 to be slightly more negative than VPS2. When the
primary supply is greater than 2.7 V, the decoupling resistors R1
and R2 (Figure 24) may be increased to improve the isolation
and lower the dissipation in the IC. However, since VPS2 sup-
ports the RSSI load current, which may be large, the value of
R2 should take this into account.
TRANSCONDUCTANCE
DETERMINES SLOPE
Figure 23. Simplified RSSI Output Interface
The RSSI output bandwidth, fLP, is nominally 3.5 MHz. This is
controlled by the compensation capacitor C1, which may be
increased by adding an external capacitor, CF, between FLTR
(Pin 10) and VLOG (Pin 16). An external 33 pF will reduce fLP
to 350 kHz, while 360 pF will set it to 35 kHz, in each case with
an essentially one-pole response. In general, the relationships
(for fLP in MHz) are:
Basic Connections for Log (RSSI) Output
Figure 24 shows the connections required for most applications.
The AD8306 is enabled by connecting ENBL to VPS1. The
device is put into the sleep mode by grounding this pin. The
inputs are ac-coupled by C1 and C2, which normally should
have the same value (CC). The input is, in this case, terminated
with a 52.3 Ω resistor that combines with the AD8306’s input
resistance of 1000 Ω to give a broadband input impedance of
50 Ω. Alternatively an input matching network can be used (see
Input Matching section).
12.7×10–10
12.7×10−6
CF +3.5 pF
CF =
–3.5 pF; fLP =
(1)
fLP
Using a load resistance of 50 Ω or greater, and at any tempera-
ture, the peak output voltage may be at least 2.4 V when using a
supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is
consistent with the maximum permissible input levels. The incre-
mental output resistance is approximately 0.3 Ω at low frequen-
cies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.
V
(2.7V TO 6.5V)
RSSI
S
R1
10⍀
R2
10⍀
The output is unconditionally stable with load capacitance, but
it should be noted that while the peak sourcing current is
over 100 mA, and able to rapidly charge even large capacitances,
the internally provided sinking current is only 1 mA. Thus, the
fall time from the 2 V level will be as long as 2 µs for a 1 nF
load. This may be reduced by adding a grounded load resistance.
16
VLOG
1
2
3
4
5
6
7
8
COM2
VPS1
PADL
INHI
0.1F
0.1F
VPS2 15
C1
0.01F
14
PADL
AD8306
13
12
LMHI
R
52.3⍀
SIGNAL
INPUTS
T
C
F
INLO
PADL
COM1
ENBL
LMLO
(OPTIONAL
SEE TEXT)
C2
0.01F
USING THE AD8306
PADL 11
The AD8306 exhibits very high gain from 1 MHz to over 1 GHz,
at which frequency the gain of the main path is still over 65 dB.
Consequently, it is susceptible to all signals, within this very
broad frequency range, that find their way to the input termi-
nals. It is important to remember that these are quite indistin-
guishable from the “wanted” signal, and will have the effect of
raising the apparent noise floor (that is, lowering the useful
dynamic range). Therefore, while the signal of interest may be
an IF of, say, 200 MHz, any of the following could easily be
larger than this signal at the lower extremities of its dynamic
10
9
FLTR
LMDR
ENABLE
Figure 24. Basic Connections for RSSI (Log) Output
The 0.01 µF coupling capacitors and the resulting 50 Ω input
impedance give a high-pass corner frequency of around 600 kHz.
(1/(2 π RC)), where C = (C1)/2. In high frequency applications,
this corner frequency should be placed as high as possible, to
minimize the coupling of unwanted low frequency signals. In
REV. A
–9–
AD8306
low frequency applications, a simple RC network forming a low-
pass filter should be added at the input for the same reason.
where VOUT is the demodulated and filtered RSSI output,
SLOPE is the logarithmic slope, expressed in V/dB, PIN is the
V
input signal, expressed in decibels relative to some reference
level (either dBm or dBV in this case) and PO is the logarithmic
intercept, expressed in decibels relative to the same reference
level.
If the limiter output is not required, Pin 9 (LMDR) should be
left open and Pins 12 and 13 (LMHI, LMLO) should be tied to
VPS2 as shown in Figure 24.
Figure 25 shows the output versus the input level in dBV, for
sine inputs at 10 MHz, 50 MHz and 100 MHz (add 13 to the
dBV number to get dBm Re 50 Ω. Figure 26 shows the typi-
cal logarithmic linearity (log conformance) under the same
conditions.
For example, for an input level of –33 dBV (–20 dBm), the
output voltage will be
VOUT = 0.02 V/dB × (–33 dBV – (–108 dBV)) = 1.5 V
(3)
The most widely used convention in RF systems is to specify
power in dBm, that is, decibels above 1 mW in 50 Ω. Specifica-
tion of log amp input level in terms of power is strictly a conces-
sion to popular convention; they do not respond to power (tacitly
“power absorbed at the input”), but to the input voltage. The
use of dBV, defined as decibels with respect to a 1 V rms sine wave,
is more precise, although this is still not unambiguous because
waveform is also involved in the response of a log amp, which,
for a complex input (such as a CDMA signal) will not follow the
rms value exactly. Since most users specify RF signals in terms
of power—more specifically, in dBm/50 Ω—we use both dBV
and dBm in specifying the performance of the AD8306, showing
equivalent dBm levels for the special case of a 50 Ω environment.
Values in dBV are converted to dBm re 50 Ω by adding 13.
2.5
100MHz
2
50MHz
10MHz
1.5
1
0.5
0
Output Response Time and CF
–120
–100
–80
–60
–40
–20
0
20
The RSSI output has a low-pass corner frequency of 3.5 MHz,
which results in a 10% to 90% rise time of 73 ns. For low fre-
quency applications, the corner frequency can be reduced by
adding an external capacitor, CF, between FLTR (Pin 10) and
VLOG (Pin 16) as shown in Figure 24. For example, an exter-
nal 33 pF will reduce the corner frequency to 350 kHz, while
360 pF will set it to 35 kHz, in each case with an essentially
one-pole response.
INPUT LEVEL – dBV
Figure 25. RSSI Output vs. Input Level at TA = +25°C for
Frequencies of 10 MHz, 50 MHz and 100 MHz
5
DYNAMIC RANGE ؎1dB ؎3dB
4
10MHz
50MHz
100MHz
86
90
96
93
97
100
3
2
Using the Limiter
Figure 27 shows the basic connections for operating the limiter
and the log output concurrently. The limiter output is a pair of
differential currents of magnitude, IOUT, from high impedance
(open-collector) sources. These are converted to equal-amplitude
voltages by supply-referenced load resistors, RLOAD. The limiter
output current is set by RLIM, the resistor connected between
Pin 9 (LMDR) and ground. The limiter output current is set
according the equation:
1
0
100MHz
10MHz
50MHz
–1
–2
–3
–4
–5
I
OUT = –400 mV/RLIM
(5)
–120
–100
–80
–60
–40
–20
0
20
and has an absolute accuracy of ±5%.
INPUT LEVEL – dBV
The supply referenced voltage on each of the limiter pins will
thus be given by:
Figure 26. Log Linearity vs. Input Level at TA = +25°C, for
Frequencies of 10 MHz, 50 MHz and 100 MHz
VLIM = VS –400 mV × RLOAD/RLIM
(6)
Transfer Function in Terms of Slope and Intercept
The transfer function of the AD8306 is characterized in terms
of its Slope and Intercept. The logarithmic slope is defined as
the change in the RSSI output voltage for a 1 dB change at the
input. For the AD8306 the slope is calibrated to be 20 mV/dB.
The intercept is the point at which the extrapolated linear re-
sponse would intersect the horizontal axis. For the AD8306 the
intercept is calibrated to be –108 dBV (–95 dBm). Using the
slope and intercept, the output voltage can be calculated for any
input level within the specified input range using the equation:
VOUT = VSLOPE × (PIN – PO)
(2)
–10–
REV. A
AD8306
V
(2.7V TO 6.5V)
will be a contribution from the input noise current. Thus, the
total noise will be reduced by a smaller factor. The intercept at
the primary input will be lowered to –121 dBV (–108 dBm).
S
R1
10⍀
R2
10⍀
16
RSSI
1
2
3
4
5
6
7
8
COM2
VPS1
PADL
VLOG
0.1F
0.1F
VPS2 15
Impedance matching and drive balancing using a flux-coupled
transformer is useful whenever broadband coupling is required.
However, this may not always be convenient. At high frequen-
cies, it will often be preferable to use a narrow-band matching
network, as shown in Figure 28, which has several advantages.
First, the same voltage gain can be achieved, providing increased
sensitivity, but now a measure of selectively is simultaneously
introduced. Second, the component count is low: two capacitors
and an inexpensive chip inductor are needed. Third, the net-
work also serves as a balun. Analysis of this network shows that
the amplitude of the voltages at INHI and INLO are quite simi-
lar when the impedance ratio is fairly high (i.e., 50 Ω to 1000 Ω).
0.01F
C1
0.01F
14
13
12
PADL
LMHI
AD8306
R
INHI
LOAD
R
52.3⍀
SIGNAL
INPUTS
LIMITER
OUTPUT
T
R
0.01F
INLO
PADL
COM1
ENBL
LMLO
L
C2
0.01F
PADL 11
10 NC
FLTR
R
(SEE TEXT)
LIM
LMDR
9
ENABLE
NC = NO CONNECT
Figure 27. Basic Connections for Operating the Limiter
Depending on the application, the resulting voltage may be used
in a fully balanced or unbalanced manner. It is good practice to
retain both load resistors, even when only one output pin is
used. These should always be returned to the same well de-
coupled node on the PC board (see layout of evaluation board).
The unbalanced, or single-sided mode, is more inclined to result
in instabilities caused by the very high gain of the signal path.
The limiter current may be set as high as 10 mA (which requires
RLIM to be 40 Ω) and can be optionally increased somewhat
beyond this level. It is generally inadvisable, however, to use a
high bias current, since the gain of this wide bandwidth signal
path is proportional to the bias current, and the risk of instabil-
ity is elevated as RLIM is reduced (recommended value is 400 Ω).
V
S
10⍀
10⍀
16
VLOG
COM2
VPS1
PADL
RSSI
1
2
3
4
5
6
7
8
0.1F
0.1F
VPS2 15
14
13
12
PADL
LMHI
C1 = C
C2 = C
M
AD8306
INHI
LIMITER
OUTPUT
Z
L
IN
M
INLO
PADL
COM1
ENBL
LMLO
M
PADL 11
10 NC
FLTR
R
LIM
LMDR
9
However, as the size of RLOAD is increased, the bandwidth of the
NC = NO CONNECT
limiter output decreases from 585 MHz for RLOAD = RLIM
50 Ω to 50 MHz for RLOAD = RLIM = 400 Ω (bandwidth =
=
Figure 28. High Frequency Input Matching Network
Figure 29 shows the response for a center frequency of 100 MHz.
The response is down by 50 dB at one-tenth the center frequency,
falling by 40 dB per decade below this. The very high frequency
attenuation is relatively small, however, since in the limiting
case it is determined simply by the ratio of the AD8306’s input
capacitance to the coupling capacitors. Table I provides solu-
tions for a variety of center frequencies fC and matching from
impedances ZIN of nominally 50 Ω and 100 Ω. Exact values are
shown, and some judgment is needed in utilizing the nearest
standard values.
210 MHz for RLOAD = RLIM = 100 Ω and 100 MHz for RLOAD
RLIM = 200 Ω). As a result, the minimum necessary limiter
output level should be chosen while maintaining the required
limiter bandwidth. For RLIM = RLOAD = 50 Ω, the limiter output
is specified for input levels between –78 dBV (–65 dBm) and
+9 dBV (+22 dBm). The output of the limiter may be unstable
for levels below –78 dBV (–65 dBm). However, keeping RLIM
above 100 Ω will make instabilities on the output less likely for
input levels below –78 dBV.
=
A transformer or a balun (e.g., MACOM part number ETC1-1-13)
can be used to convert the differential limiter output voltages to
a single-ended signal.
14
13
12
Input Matching
GAIN
11
Where either a higher sensitivity or a better high frequency
match is required, an input matching network is valuable. Using
a flux-coupled transformer to achieve the impedance transfor-
mation also eliminates the need for coupling capacitors, lowers
any dc offset voltages generated directly at the input, and use-
fully balances the drives to INHI and INLO, permitting full
utilization of the unusually large input voltage capacity of the
AD8306.
10
9
8
7
6
5
4
INPUT AT
TERMINATION
3
2
The choice of turns ratio will depend somewhat on the fre-
quency. At frequencies below 30 MHz, the reactance of the
input capacitance is much higher than the real part of the input
impedance. In this frequency range, a turns ratio of 2:9 will
lower the effective input impedance to 50 Ω while raising the
input voltage by 13 dB. However, this does not lower the effect
of the short circuit noise voltage by the same factor, since there
1
0
–1
60
70
80
90
100
110
120
130
140
150
FREQUENCY – MHz
Figure 29. Response of 100 MHz Matching Network
REV. A
–11–
AD8306
Table I.
Step 2: Calculate CO and LO
Now having a purely resistive input impedance, we can calculate
the nominal coupling elements CO and LO, using
Match to 50 ⍀
(Gain = 13 dB)
Match to 100 ⍀
(Gain = 10 dB)
fC
MHz
CM
pF
LM
nH
CM
pF
LM
nH
RIN RM
(
; LO =
)
1
CO =
(8)
2 πfC
2 πfC RIN RM
10
10.7
15
20
21.4
25
30
35
40
45
140
133
3500
3200
2250
1660
1550
1310
1070
904
779
682
604
489
100.7
94.1
67.1
50.3
47.0
40.3
33.5
28.8
25.2
22.4
20.1
16.8
12.6
10.1
8.4
4790
4460
3120
2290
2120
1790
1460
1220
1047
912
804
644
448
335
261
191
125
(
)
For the AD8306, RIN is 1 kΩ. Thus, if a match to 50 Ω is
needed, at fC = 100 MHz, CO must be 7.12 pF and LO must be
356 nH.
95.0
71.0
66.5
57.0
47.5
40.7
35.6
31.6
28.5
23.7
17.8
14.2
11.9
9.5
Step 3: Split CO Into Two Parts
Since we wish to provide the fully-balanced form of network
shown in Figure 28, two capacitors C1 = C2each of nominally
twice CO, shown as CM in the figure, can be used. This requires
a value of 14.24 pF in this example. Under these conditions, the
voltage amplitudes at INHI and INLO will be similar. A some-
what better balance in the two drives may be achieved when C1
is made slightly larger than C2, which also allows a wider range
of choices in selecting from standard values. For example, ca-
pacitors of C1 = 15 pF and C2 = 13 pF may be used (making
CO = 6.96 pF).
50
60
80
346
262
208
155
100
120
150
200
250
300
350
400
450
500
6.7
7.1
5.7
104
5.03
4.03
3.36
2.87
2.52
2.24
2.01
Step 4: Calculate LM
75.3
57.4
45.3
36.7
30.4
25.6
89.1
66.8
52.1
41.8
34.3
28.6
The matching inductor required to provide both LIN and LO is
just the parallel combination of these:
4.75
4.07
3.57
3.16
2.85
L
M = LINLO/(LIN + LO)
(9)
With LIN = 1 µH and LO = 356 nH, the value of LM to complete
this example of a match of 50 Ω at 100 MHz is 262.5 nH. The
nearest standard value of 270 nH may be used with only a slight
loss of matching accuracy. The voltage gain at resonance de-
pends only on the ratio of impedances, as is given by
General Matching Procedure
For other center frequencies and source impedances, the following
method can be used to calculate the basic matching parameters.
Step 1: Tune Out CIN
RIN
RS
RIN
RS
At a center frequency fC, the shunt impedance of the input
capacitance CIN can be made to disappear by resonating with a
temporary inductor LIN, whose value is given by
2
GAIN = 20 log
= 10 log
(10)
Altering the Logarithmic Slope
L
IN = 1/{(2 π fC)2CIN} = 1010/fC
(7)
Simple schemes can be used to increase and decrease the loga-
rithmic slope as shown in Figure 30. For the AD8306, only
power, ground and logarithmic output connections are shown;
refer to Figure 24 for complete circuitry. In Figure 30(a), the op
amp’s gain of +2 increases the slope to 40 mV/dB. In Figure
30(b), the AD8031 buffers a resistive divider to give a slope of
when CIN = 2.5 pF. For example, at fC = 100 MHz, LIN = 1 µH.
+5V
+5V
0.1F
0.1F
0.1F
0.1F
10⍀ 10⍀
10⍀
0.1F
10⍀ 10⍀
VPS1
VPS2
VLOG
VPS1
VPS2
VLOG
10⍀
0.1F
40mV/dB
AD8031
5k⍀
AD8306
AD8306
AD8031
10mV/dB
PADL, COM1, COM2
PADL, COM1, COM2
5k⍀
5k⍀
5k⍀
(a)
(b)
Figure 30. Altering the Logarithmic Slope
–12–
REV. A
AD8306
V
10 mV/dB The AD8031 rail-to-rail op amp, used in both ex-
amples, can swing from 50 mV to 4.95 mV on a single +5 V
supply. If high output current is required (> 10 mA), the AD8051,
which also has rail-to-rail capability but can deliver up to 45 mA
of output current, can be used.
S
10⍀
10⍀
16
COM2
VPS1
PADL
1
2
3
4
5
6
7
8
VLOG
RSSI
0.1F
VPS2 15
0.1F
0V TO +1V
0.1F
14
13
12
PADL
LMHI
AD8306
INHI
APPLICATIONS
8.2k⍀
VARIABLE
OUTPUT
The AD8306 is a versatile and easily applied log-limiting ampli-
fier. Being complete, it can be used with very few external com-
ponents, and most applications can be accommodated using the
simple connections shown in the preceding section. A few ex-
amples of more specialized applications are provided here.
INLO
PADL
COM1
ENBL
LMLO
PADL 11
2N3904
AD8031
1.8k⍀
10
9
FLTR
LMDR
18⍀
0mA TO
10mA
High Output Limiter Loading
The AD8306 can generate a fairly large output power at its
differential limiter output interface. This may be coupled into a
50 Ω grounded load using the narrow-band coupling network
following similar lines to those provided for input matching.
Alternatively, a flux-linked transformer, having a center-tapped
primary, may be used. Even higher output powers can be ob-
tained using emitter-followers. In Figure 31, the supply voltage
to the AD8306 is dropped from 5 V to about 4.2 V, by the
diode. This increases the available swing at each output to about
2 V. Taking both outputs differentially, a square wave output of
4 V p-p can be generated.
Figure 32. Variable Limiter Output Programming
Effect of Waveform Type on Intercept
The AD8306 fundamentally responds to voltage and not to
power. A direct consequence of this characteristic is that input
signals of equal rms power, but differing crest factors, will pro-
duce different results at the log amp’s output.
The effect of differing signal waveforms is to shift the effective
value of the log amp’s intercept. Graphically, this looks like a
vertical shift in the log amp’s transfer function. The device’s
logarithmic slope however is not affected. For example, consider
the case of the AD8306 being alternately fed by an unmodu-
lated sine wave and by a single CDMA channel of the same rms
power. The AD8306’s output voltage will differ by the equiva-
lent of 3.55 dB (71 mV) over the complete dynamic range of the
device (the output for a CDMA input being lower).
IN914
+5V
APPROX. 4.2V
R
R
LOAD
10⍀
LOAD
10⍀
16
VLOG
COM2
VPS1
PADL
RSSI
1
2
3
4
5
6
7
8
SET R = 5*R
0.1F
0.1F
L
LIM
VPS2 15
Table II shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A sine
wave input is used as a reference. To measure the rms power of
a square wave, for example, the mV equivalent of the dB value
given in the table (20 mV/dB times 3.01 dB) should be sub-
tracted from the output voltage of the AD8306.
14
13
12
PADL
LMHI
AD8306
3V TO 5V
5V TO 3V
INHI
INLO
PADL
COM1
ENBL
LMLO
DIFFERENTIAL
OUTPUT = 4V pk-pk
PADL 11
10
9
FLTR
R
LIM
Table II. Shift in AD8306 Output for Signals with Differing
Crest Factors
LMDR
Figure 31. Increasing Limiter Output Voltage
Correction Factor
When operating at high output power levels and high frequen-
cies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is
low, due to the extremely high gain-bandwidth product of the
AD8306 under such conditions. These oscillations will be less
evident when signal-balancing networks are used, operating at
frequencies below 200 MHz, and they will generally be fully
quenched by the signal at input levels of a few dB above the
noise floor.
Signal Type
(Add to Output Reading)
Sine Wave
Square Wave or DC
Triangular Wave
GSM Channel (All Time Slots On) +0.55 dB
CDMA Channel (Forward Link, 9
Channels On)
CDMA Channel (Reverse Link)
PDC Channel (All Time Slots On) +0.58 dB
Gaussian Noise
0 dB
–3.01 dB
+0.9 dB
+3.55 dB
+0.5 dB
Modulated Limiter Output
+2.51 dB
The limiter output stage of the AD8306 also provides an analog
multiplication capability: the amplitude of the output square
wave can be controlled by the current withdrawn from LMDR
(Pin 9). An analog control input of 0 V to +1 V is used to gener-
ate an exactly-proportional current of 0 mA to 10 mA in the npn
transistor, whose collector is held at a fixed voltage of 400 mV
by the internal bias in the AD8306. When the input signal is
above the limiting threshold, the output will then be a square-
wave whose amplitude is proportional to the control bias.
Evaluation Board
An evaluation board, carefully laid out and tested to demon-
strate the specified high speed performance of the AD8306 is
available. Figure 33 shows the schematic of the evaluation
board, which fairly closely follows the basic connections sche-
matic shown in Figure 27. For ordering information, please
refer to the Ordering Guide. Links, switches and component
settings for different setups are described in Table III.
REV. A
–13–
AD8306
R3
0⍀
V
RSSI
R4
(OPEN)
COM2
VPS1
PADL
INHI
16
VLOG
1
2
3
4
5
6
7
8
R2
10⍀
R5
10⍀
+V
+V
VPS2 15
S
S
C3
0.1F
C4
0.1F
R6
50⍀
R7
50⍀
PADL 14
C1
0.01F
C5
0.01F
R12
0⍀
SIG
INHI
AD8306
13
LMHI
R10
52.3⍀
C7 (OPEN)
L1
(OPEN)
R11
INLO
PADL
COM1
ENBL
LMLO 12
PADL 11
0⍀
SIG
C2
0.01F
INLO
R1
C6
0.01F
0⍀
R9
(OPEN)
10
9
FLTR
R8
402⍀
LK1
A
LMDR
EXT
ENABLE
B
SW1
Figure 33. Evaluation Board Schematic
Table III. Evaluation Board Setup Options
Component Function
Default Condition
SW1
Device Enable. When in Position A, the ENBL pin is connected to +VS and the
AD8306 is in normal operating mode. In Position B, the ENBL pin is connected
to an SMA connector labeled Ext Enable. A signal can be applied to this connector
to enable/disable the AD8306.
SW1 = A
R1
This pad is used to ac-couple INLO to ground for single-ended input drive. To drive
the AD8306 differentially, R1 should be removed.
R1 = 0 Ω
R/L, C1, C2
Input Interface. The 52.3 Ω resistor in position R10, along with C1 and C2, create
a high-pass input filter whose corner frequency (640 kHz) is equal to 1/(2πRC),
where C = (C1)/2 and R is the parallel combination of 52.3 Ω and the AD8306’s
input impedance of 1000 Ω. Alternatively, the 52.3 Ω resistor can be replaced by
an inductor to form an input matching network. See Input Matching Network
section for more details.
R10 = 52.3 Ω
C1 = C2 = 0.01 µF
R3/R4
Slope Adjust. A simple slope adjustment can be implemented by adding a resistive
divider at the VLOG output. R3 and R4, whose sum should be about 1 kΩ, and
never less than 40 Ω (see specs), set the slope according to the equation:
Slope = 20 mV/dB × R4/(R3 + R4).
R3 = 0 Ω
R4 =
ϱ
L1, C5, C6
Limiter Output Coupling. C5 and C6 ac-couple the limiter’s differential outputs.
By adjusting these values and installing an inductor in L1, an output matching
network can be implemented. To convert the limiter’s differential output to single-
ended, R11 and R12 (nominally 0 Ω) can be replaced with a surface mount balun
such as the ETC1-1-13 (Macom). The balun can be grounded by soldering a 0 Ω
into Position R9 (nominally open).
L1 = Open
C5 = 0.01 µF
C6 = 0.01 µF
R9 = Open
R10 = R11 = 0 Ω
R8, LK1
Limiter Output Current. With LK1 installed, R8 enables and sets the limiter
output current. The limiter’s output current is set according to the equation
(IOUT = 400 mV/R8). The limiter current can be as high as 10 mA (R8 = 40 Ω).
To disable the limiter (recommended if the limiter is not being used), LK1 should
be removed.
LK1 Installed. R8 = 402 Ω
R6, R7 (Limited Load
Resistors) = 50 Ω
C7
RSSI Bandwidth Adjust. The addition of C7 (farads) will lower the RSSI bandwidth of
the VLOG output according to the equation: fCORNER (Hz) = 12.7 × 10–6/(C7 + 3.5 × 10–12).
C7 = Open
–14–
REV. A
AD8306
Figure 34. Layout of Signal Layer
Figure 36. Signal Layer Silkscreen
Figure 35. Layout of Power Layer
Figure 37. Power Layer Silkscreen
REV. A
–15–
AD8306
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Narrow Body SO
(SO-16)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
8
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
؋
45؇ 8؇
0؇
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
–16–
REV. A
相关型号：
AD8306ARU
IC LOG OR ANTILOG AMPLIFIER, 350 MHz BAND WIDTH, PDSO16, TSSOP-16, Analog Computational Function
ADI
AD8306ARZ-REEL
<span class="noTransform">5 MHz TO 400 MHz, 100 dB</span> High Precision Limiting - Logarithmic Amplifier Package: 16 ld SOIC; No of Pins: 16; Temperature Range: INDUSTRIAL; Container: 2500/Reel
ADI
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