AD8316ARM [ADI]
Dual Output GSM PA Controller; 双输出GSM PA控制器
| 型号： | AD8316ARM |
| 厂家： | 
ADI |
| 描述： | Dual Output GSM PA Controller |
| 文件： | 总20页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Output
GSM PA Controller
AD8316
FEATURES
Complete RF Detector/Controller Function
Selectable Dual Outputs
49 dB Range at 0.9 GHz (–47.6 dBm to +1.5 dBm re 50 ꢀ)
Accurate Scaling from 0.1 GHz to 2.5 GHz
Temperature-Stable Linear-in-dB Response
Log Slope of 22 mV/dB
True Integration Function in Control Loop
Low Power: 23 mW at 2.7 V
power control signal is required for each band. The logarithmic
amplifier technique provides a much wider measurement range
and better accuracy than is possible using controllers based on
diode detectors. In particular, multiband and multimode cellu-
lar designs can benefit from the temperature-stable (–30°C to
+85°C) operation over all cellular telephony frequencies.
Its high sensitivity allows control at low input signal levels, thus
reducing the amount of power that needs to be coupled to the
detector. The selected output, OUT1 or OUT2, has the voltage
range and current drive to directly connect to the gain control
pin of most handset power amplifiers; the deselected output is
pulled low to ensure that the inactive PA remains off. Each
output has a dedicated integrating filter capacitor that allows
separate control loop settings for each PA. OUT1 and OUT2 can
swing from 125 mV above ground to within 100 mV below the
supply voltage. Load currents of up to 12 mA can be supported.
Power-Down to 11 ꢁW
APPLICATIONS
Single-Band, Dual-Band, and Triband Mobile Handsets
(GSM, DCS, PCS, EDGE)
Wireless Terminal Devices
Transmitter Power Control
The setpoint control input applied to pin VSET has an operating
range of 0.25 V to 1.4 V. The input resistance of the setpoint
interface is over 100 MΩ, and the bias current is typically 0.5 µA.
GENERAL DESCRIPTION
The AD8316 is a complete, low cost subsystem for the precise
control of dual RF power amplifiers (PAs) operating in the
frequency range 0.1 GHz to 2.5 GHz and over a typical dynamic
range of 50 dB. The device is a dual-output version of the AD8315
and intended for use in dual-band or triband cellular handsets
and other battery-operated wireless devices where a separate
The AD8316 is available in 10-lead MSOP and 16-lead LFCSP
packages and consumes 8.5 mA from a 2.7 V to 5.5 V supply.
When it is powered down, the sleep current is 4 µA.
FUNCTIONAL BLOCK DIAGRAM
FLT1
OUTPUT
ENABLE
DELAY
LOW NOISE
LOW NOISE
GAIN BIAS
VPOS
ENBL
BAND GAP
HI-Z
ꢂ1.35
REFERENCE
OUT1
BSEL
DET
DET
DET
DET
DET
RFIN
HI-Z
10dB
10dB
10dB
10dB
OUT2
ꢂ1.35
FLT2
VSET
OFFSET
COMPENSATION
INTERCEPT
POSITIONING
V–I
COMM
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8316–SPECIFICATIONS
(VPOS = 2.7 V, TA = 25ꢃC, 52.3 ꢀ on RFIN, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range1
To Meet All Specifications
1 dB Log Conformance, 0.1 GHz
0.1
2.5
–10
+3
24.5
–78
–65
GHz
dBV
dBm
mV/dB
dBV
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope2, 3
Logarithmic Intercept2, 3
Equivalent dBm Level
–58.6
–45.6
20.5
–68
0.1 GHz
0.1 GHz
22.1
–74
–61
–55
dBm
RF INPUT INTERFACE
Input Resistance4
Pin RFIN
0.1 GHz
0.1 GHz
2.9
1.0
kΩ
pF
Input Capacitance4
OUTPUTS
Pins OUT1 and OUT2
Minimum Output Voltage
VSET ≤ 200 mV, ENBL High, RF Input ≤ –60 dBm
0.1
0.15
0.025
0.25
2.6
12
V
V
V
V
ENBL Low
RL > 800 Ω
2.7 V ≤ VPOS ≤ 5.5 V
Source
Maximum Output Voltage
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
2.45
VPOS – 0.1
mA
nV/√Hz
nV/√Hz
25
100
RF Input = 2 GHz, 0 dBm,
CFLT = 220 pF, fNOISE = 400 kHz
0.2 V to 2.6 V Swing
Small Signal Bandwidth
Slew Rate
Full-Scale Response Time
30
20
50
MHz
V/µs
ns
10%–90%, 250 mV Step (VSET), Open Loop5
FLTR = Open; Refer to TPC 28
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Pin VSET
Corresponding to Central 50 dB
0.25
1.8
1.5
V
43.5
100
16
dB/V
kΩ
V/µs
Slew Rate
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable High
Logic Level to Disable Power
Enable Time
Pin ENBL
VPOS
0.8
V
µA
V
20
7
Time from ENBL High to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from ENBL Low to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from VPOS/ENBL Low to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
Time from VPOS/ENBL High to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
µs
Disable Time
3
µs
µs
µs
Power-On/Enable Time
Power-Off/Disable Time
3
4
BAND SELECT INTERFACE
Logic Level to Enable OUT1
Input Current when BSEL High
Logic Level to Enable OUT2
Pin BSEL
1.8
0.0
VPOS
1.7
V
µA
V
50
POWER INTERFACE
Supply Voltage
Quiescent Current
Over Temperature
Disable Current6
Over Temperature
Pin VPOS
2.7
5.5
10.7
12
10
13
V
ENBL High
–30°C ≤ TA ≤ +85°C
ENBL Low
8.5
3
mA
mA
µA
µA
–30°C ≤ TA ≤ +85°C
NOTES
1Operation down to 0.02 GHz is possible.
2Calculated over the input range of –40 dBm to –10 dBm.
3Mean and standard deviation specifications are in Table I.
4See TPC 9 for plot of Input Impedance vs. Frequency.
5Response time in a closed-loop system will depend upon the filter capacitor (CFLT) used and the response of the variable gain element.
6This parameter is guaranteed but not tested in production. The maximum specified limit on this parameter is the +6 sigma value from characterization.
Specifications subject to change without notice.
–2–
REV. C
AD8316
Table I. Typical Specifications at Selected Frequencies at 25°C
Dynamic Range
Dynamic Range
Slope (mV/dB)
Intercept (dBm)
Standard
Low Point (dBm)
High Point (dBm)
Frequency
(GHz)
Standard
Standard
Standard
Mean
Deviation
Mean
Deviation
Mean
Deviation
Mean
Deviation
0.1
0.9
1.9
2.5
22.1
22.2
21.6
21.3
0.3
0.3
0.3
0.3
–61.0
–62.2
–63.1
–66.0
1.5
1.5
1.5
1.6
–45.6
–47.6
–49.2
–51.5
0.7
0.6
0.8
1.1
3.0
1.5
–4.5
–3.0
0.7
0.6
0.8
1.1
Slope and intercept calculated over the input amplitude range of –40 dBm to –10 dBm.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature Range . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec)
MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUT1, OUT2, VSET, ENBL . . . . . . . . . . . . . . . . . . . 0 V, VPOS
RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dBm
Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 100 mW
ꢀJA (MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200°C/W
ꢀJA (LFCSP, Paddle soldered) . . . . . . . . . . . . . . . . . . . . . 80°C/W
ꢀJA (LFCSP, Paddle not soldered) . . . . . . . . . . . . . . . . . 130°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . . . . –40°C to +85°C
PIN FUNCTION DESCRIPTIONS
Pin No.
PIN CONFIGURATION
MSOP LFCSP Mnemonic Function
1
2
1
2
RFIN
ENBL
RF Input.
10-Lead MSOP
16-Lead LFCSP
Connect to VPOS for Normal
Operation. Connect pin to
ground for disable mode.
Setpoint Input.
Integrator Capacitor for OUT1.
Connect between FLT1 and
COMM.
Band Select. LO = OUT2,
HI = OUT1.
Integrator Capacitor for OUT2.
Connect between FLT2 and
COMM.
Band 2 Output.
Device Common (Ground).
Band 1 Output.
Positive Supply Voltage: 2.7 V
to 5.5 V.
1
VPOS
OUT1
COMM
RFIN
ENBL
VSET
FLT1
10
3
4
3
4
VSET
FLT1
2
3
4
5
9
8
7
6
AD8316
TOP VIEW
12
11
10
9
1
2
3
4
RFIN
VPOS
(NOT TO SCALE)
AD8316
ENBL
VSET
OUT1
OUT2
FLT2
TOP VIEW
5
6
6
7
BSEL
FLT2
COMM
(Not to Scale)
BSEL
FLT1
OUT2
NC = NO CONNECT
7
8
9
10
9
OUT2
COMM
OUT1
VPOS
10, 14
11
12
5, 8, 13, NC
15, 16
No Connection.
ORDERING GUIDE
Temperature Range Package Description
Model
AD8316ARM
Package Option Branding
–30°C to +85°C
10-Lead MSOP, Tube
MSOP, 7" Tape and Reel
MSOP Evaluation Board
RM-10
RM-10
J8A
J8A
AD8316ARM-REEL7 –30°C to +85°C
AD8316-EVAL
AD8316ACP-REEL
AD8316ACP-REEL7 –30°C to +85°C
AD8316ACP-EVAL
–30°C to +85°C
16-Lead LFCSP, 13" Tape and Reel CP-16-3
J8A
J8A
LFCSP, 7" Tape and Reel
LFCSP Evaluation Board
CP-16-3
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8316 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
–3–
AD8316–Typical Performance Characteristics
INPUT AMPLITUDE – dBV
–53 –43 –33 –23
INPUT AMPLITUDE – dBV
–73
4
–63
–13
–3
–73
1.6
–63
–53
–43
–33
–23
–13
–3
3
2
1
1.4
1.2
1.0
0.8
1.9GHz
1.9GHz
0.9GHz
0.1GHz
2.5GHz
0
–1
–2
–3
–4
1.9GHz
2.5GHz
0.9GHz
0.6
0.4
0.2
0.1GHz
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
TPC 1. VSET vs. Input Amplitude
TPC 4. Log Conformance vs. Input Amplitude at
Selected Frequencies
INPUT AMPLITUDE – dBV
INPUT AMPLITUDE – dBV
–73
1.6
–63
–53
–43
–33
–23
–13
–30ꢃC
–3
–73
1.6
–63
–53
–43
–33
–23
–13
–3
4
4
3
1.4
1.2
1.0
1.4
1.2
3
2
+25ꢃC
+25ꢃC
2
1
+85ꢃC
+85ꢃC
+85ꢃC
1.0
0.8
0.6
0.4
0.2
0
1
–30ꢃC
–30ꢃC
0
0.8
0.6
0.4
0.2
0
0
+25ꢃC
–1
–2
–3
–4
–1
–2
–3
–4
+85ꢃC
–30ꢃC
+25ꢃC
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
TPC 2. VSET and Log Conformance vs. Input
Amplitude at 0.1 GHz
TPC 5. VSET and Log Conformance vs. Input
Amplitude at 1.9 GHz
INPUT AMPLITUDE – dBV
INPUT AMPLITUDE – dBV
–73
–63
–53
–43
–33
–23
–13
–3
–73
1.6
–63
–53
–43
–33
–23
–13
–3
4
1.6
4
3
+85ꢃC
1.4
1.4
1.2
3
2
2
1
1.2
1.0
+25ꢃC
+25ꢃC
+85ꢃC
1.0
0.8
0.6
0.4
0.2
0
1
–30ꢃC
0.8
0.6
0.4
0
0
–30ꢃC
–1
–2
–3
–4
–1
–2
–3
–4
+85ꢃC
+25ꢃC
+85ꢃC
0.2
0
–30ꢃC
–30ꢃC
+25ꢃC
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
TPC 3. VSET and Log Conformance vs. Input
Amplitude at 0.9 GHz
TPC 6. VSET and Log Conformance vs. Input
Amplitude at 2.5 GHz
–4–
REV. C
AD8316
INPUT AMPLITUDE – dBV
–53 –43 –33 –23
INPUT AMPLITUDE – dBV
–53 –43 –33 –23
–73
4
–63
–13
–3
–73
4
–63
–13
–3
3
3
+85ꢃC
+85ꢃC
2
1
2
1
0
0
–1
–1
–30ꢃC
–2
–2
–30ꢃC
–3
–4
–3
–4
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
TPC 7. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 0.1 GHz
TPC 10. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 1.9 GHz
INPUT AMPLITUDE – dBV
INPUT AMPLITUDE – dBV
–73
4
–63
–53
–43
–33
–23
–13
–3
–73
4
–63
–53
–43
–33
–23
–13
–3
3
3
+85ꢃC
+85ꢃC
2
1
2
1
0
0
–1
–1
–30ꢃC
–2
–2
–30ꢃC
–3
–4
–3
–4
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
TPC 8. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 0.9 GHz
TPC 11. Distribution of Error at Temperature after Ambient
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 2.5 GHz
8
3100
2800
2500
2200
1900
1600
1300
1000
700
0
X (MSOP)
–200
FREQ MSOP
CHIP-SCALE (LFCSP)
Rꢀ – jXꢀ
–400
–600
(GHz)
0.1
Rꢀ – jXꢀ
3100ꢀ – j1220
600ꢀ – j194
320ꢀ – j134
110ꢀ – j86
6
2630ꢀ – j1800
1000ꢀ – j270
620ꢀ – j130
0.9
1.9
2.5
INCREASING
435ꢀ – j110
–800
V
ENBL
X (LFCSP)
–1000
–1200
4
X
R
DECREASING
V
ENBL
–1400
–1600
–1800
–2000
R (CSP)
2
400
R (MSOP)
0.5
100
0
0
1.0
1.5
2.0
2.5
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
FREQUENCY – GHz
V
– V
ENBL
TPC 9. Input Impedance vs. Frequency
TPC 12. Supply Current vs. VENBL
REV. C
–5–
AD8316
23
–60
–62
+25ꢃC
–30ꢃC
22
21
+25ꢃC
+85ꢃC
–64
–66
–68
–30ꢃC
+85ꢃC
20
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY – GHz
FREQUENCY – GHz
TPC 13. Slope vs. Frequency at Selected Temperatures
TPC 16. Intercept vs. Frequency at Selected Temperatures
22.5
–58
–60
0.1GHz
22.0
0.9GHz
0.1GHz
–62
–64
21.5
0.9GHz
1.9GHz
–66
1.9GHz
21.0
2.5GHz
2.5GHz
–68
20.5
2.5
–70
2.5
3.0
3.5
4.0
– V
4.5
5.0
5.5
3.0
3.5
4.0
– V
4.5
5.0
5.5
V
V
S
S
TPC 14. Slope vs. Supply Voltage
TPC 17. Intercept vs. Supply Voltage
50
40
0
10000
–20
–50dBm
–40dBm
–25dBm
–40
30
–60
20
1000
100
10
–80
10
C
= 220pF
FLT
–100
–120
–140
–160
–180
–200
–210
0
0dBm
C
= 0pF
FLT
–10
–20
–30
–40
–20dBm
RF INPUT
–10dBm
ꢄ28dBm
–50
–60
1
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 15. AC Response from VSET to OUT1 and OUT2
TPC 18. Output Noise Spectral Density, RL = ꢁ,
CFLT = 220 pF, by RF Input Amplitude
–6–
REV. C
AD8316
2.8
2.7
2.6
2.5
3.5
3.3
3.1
2.9
2.7
2.5
4mA
I
2mA
LOAD
0mA
2mA
6mA
10mA
12 mA
8mA
2.4
6mA
2.3
2.1
1.9
SHADING INDICATES ꢅ3 SIGMA
2.3
2.2
2.8
2.9
3.0
2.7
2.8
2.9
3.0
3.1
– V
3.2
3.3
3.4
3.5
2.7
V
V
– V
S
S
TPC 19. Maximum OUT Voltage vs. Supply Voltage by
Load Current, AD8316 Sourcing
TPC 22. Distribution of Maximum OUT Voltage vs. Supply
Voltage with 2 mA and 6 mA Loads, 3 Sigma to Either
Side of Mean, AD8316 Sourcing
AVERAGING = 16 SAMPLES
AVERAGING = 16 SAMPLES
C
= 68pF
FLT
50mV PER
VERTICAL
DIVISION
V
10mV PER VERTICAL DIVISION
OUT2
GND
C
= 220pF
FLT
V
GND
GND
OUT
BSEL INPUT
V
1V PER
VERTICAL
DIVISION
1V PER
VERTICAL
DIVISION
ENBL
GND
2ꢁs PER HORIZONTAL DIVISION
2ꢁs PER HORIZONTAL DIVISION
TPC 20. ENBL Response Time, Rise/Fall Time = 250 ns
TPC 23. BSEL Response Time, ENBL Grounded
H-P 8110A
PULSE
GENERATOR
H-P 8110A
PULSE
GENERATOR
H-P 8648B
SIGNAL
GENERATOR
0.1GHz
–60dBm
0.1GHz
ꢄ60dBm
H-P 8648B
SIGNAL
PULSE OUT
RF OUT
PULSE OUT
GENERATOR
2.7V
2.7V
TEK P6204
FET PROBE
TEK P6204
FET PROBE
RF OUT
AD8316
AD8316
0.1ꢁF
0.1ꢁF
RFIN
ENBL
VPOS
OUT1
RFIN
ENBL
VPOS
OUT1
TEK P6204
FET PROBE
TEK P6204
FET PROBE
52.3ꢀ
52.3ꢀ
VSET COMM
VSET COMM
TEK 1103
PWR SUPPLY
TEK 1103
PWR SUPPLY
R
1kꢀ
R
1kꢀ
L
L
FLT1
FLT1
OUT2
FLT2
OUT2
FLT2
C
C
FLT
FLT
BSEL*
BSEL*
C
C
FLT
FLT
TEK TDS3054
SCOPE
TEK TDS3054
SCOPE
2.7V
*BSEL HIGH OUT1;
BSEL LOW OUT2
*BSEL HIGH OUT1;
BSEL LOW OUT2
TPC 21. Test Setup for ENBL Response Time
TPC 24. Test Setup for BSEL Response Time
REV. C
–7–
AD8316
AVERAGING = 16 SAMPLES
= 220pF
AVERAGING = 16 SAMPLES
V
OUT
C
FLT
V
OUT
1V PER
VERTICAL
DIVISION
50mV PER
VERTICAL
DIVISION
GND
C
= 68pF
FLT
PULSED RF
INPUT
0.1GHz, –3dBm
GND
V
/V
POS ENBL
GND
2V PER
VERTICAL
DIVISION
250ns
RISE TIME
GND
2ꢁs PER HORIZONTAL DIVISION
100ns PER HORIZONTAL DIVISION
TPC 25. Power-On and Power-Off Response with
VSET Grounded, Rise/Fall Time = 250 ns
TPC 28. Pulse Response Time, Full-Scale Amplitude
Change, Open Loop, CFLT = 0 pF
AVERAGING = 16 SAMPLES
AVERAGING = 16 SAMPLES
V
OUT
C
= 68pF
FLT
1V PER
VERTICAL
DIVISION
GND
50mV PER
VERTICAL
DIVISION
V
OUT
C
= 220pF
FLT
PULSED RF
INPUT
0.1GHz, –3dBm
GND
GND
GND
V
/V
POS ENBL
2V PER
VERTICAL
DIVISION
1ꢁs
RISE TIME
2ꢁs PER HORIZONTAL DIVISION
2ꢁs PER HORIZONTAL DIVISION
TPC 26. Power-On and Power-Off Response with
VSET Grounded, Rise/Fall Time = 1 µs
TPC 29. Pulse Response Time, Full-Scale Amplitude
Change, Open Loop, CFLT = 68 pF
EXT TRIG
H-P 8110A
PULSE
H-P 8648B
SIGNAL
H-P 8648B
SIGNAL
GENERATOR
10MHz REF OUT
0.1GHz
GENERATOR
–60dBm
H-P 8110A
TRIG OUT
GENERATOR
PULSE OUT
RF OUT
PULSE MODE IN
PULSE OUT
PULSE
GENERATOR
0.1GHz
0dBm
RFOUT
AD811
49.9ꢀ
TEK P6204
FET PROBE
3dB
PWR DIVIDER
2.7V
AD8316
732ꢀ
AD8316
TEK P6204
FET PROBE
0.1ꢁF
RFIN
ENBL
VPOS
OUT1
RFIN
VPOS
OUT1
TEK P6204
FET PROBE
TEK P6204
FET PROBE
52.3ꢀ
52.3ꢀ
ENBL
2.7V
0.4V
VSET COMM
VSET COMM
R
L
1kꢀ
R
1kꢀ
TEK 1103
PWR SUPPLY
L
FLT1
TEK 1103
PWR SUPPLY
OUT2
FLT2
FLT1
OUT2
FLT2
C
FLT
C
FLT
BSEL*
BSEL*
C
FLT
C
FLT
2.7V
TEK TDS3054
SCOPE
TEK TDS3054
SCOPE
*BSEL HIGH OUT1;
BSEL LOW OUT2
*BSEL HIGH OUT1;
BSEL LOW OUT2
TPC 27. Test Setup for Power-On and Power-Off
Response with VSET Grounded
TPC 30. Test Setup for Pulse Response Time
–8–
REV. C
AD8316
amplifiers. When the band select pin, BSEL, directs one of the
controller outputs to servo its amplifier toward the setpoint
indicated by the power control pin VSET, the other output is
forced to ground, disabling the second amplifier. Each output
has a dedicated filter pin, FLT1 and FLT2, that allows the
filtering and loop dynamics for each control loop to be opti-
mized independently.
AVERAGING = 16 SAMPLES
V
OUT
10mV PER
VERTICAL
DIVISION
250ns
RISE TIME
1ꢁs
RISE TIME
Basic Theory
Logarithmic amplifiers provide a type of compression in which a
signal with a large range of amplitudes is converted to one of
a smaller range. The use of the logarithmic function uniquely
results in the output representing the decibel value of the input.
The fundamental mathematical form is
V
POS
2V PER
INPUT
VERTICAL DIVISION
2ꢁs PER HORIZONTAL DIVISION
VIN
VZ
TPC 31. Power-On and Power-Off Response with
VSET and ENBL Grounded
VOUT =VSLP log
(1)
Here VIN is the input voltage and VZ is called the intercept (volt-
age) because when VIN = VZ the argument of the logarithm is
unity, and thus the result is zero; VSLP is called the slope (volt-
age), which is the amount by which the output changes for a
certain change in the ratio (VIN/VZ).
H-P 8110A
PULSE
GENERATOR
PULSE OUT
49.9ꢀ
H-P 8648B
SIGNAL
GENERATOR
0.1GHz
–60dBm
RFOUT
AD811
Because log amps do not respond to power, but only to voltages,
and the calibration of the intercept is waveform dependent and
only quoted for a sine wave signal, the equivalent power response
can be written as
AD8316
732ꢀ
TEK P6204
FET PROBE
RFIN
ENBL
VPOS
OUT1
TEK P6204
FET PROBE
52.3ꢀ
(2)
VOUT =VDB (P – PZ )
VSET COMM
IN
R
1kꢀ
L
TEK 1103
PWR SUPPLY
FLT1
OUT2
FLT2
C
where the input power PIN and the equivalent intercept PZ are
both expressed in dBm (thus, the quantity in the parentheses is
simply a number of decibels), and VDB is the slope expressed as
so many mV/dB. When base 10 logarithms are used, denoted by
the function log10, VSLP represents V/dec, and since a decade
corresponds to 20 dB, VSLP/20 represents the change in V/dB. For
the AD8316, a nominal (low frequency) slope of 22 mV/dB
(corresponding to a VSLP of 0.022 mV/dB × 20 dB = 440 mV)
was chosen, and the intercept VZ was placed at the equivalent of
–74 dBV, or 199 µV rms, for a sine wave input. This corre-
sponds to a power level of –61 dBm when the net resistive part
of the input impedance of the log amp is 50 Ω. However, both
the slope and the intercept are dependent on frequency (see for
example, TPC 13 and TPC 16).
FLT
BSEL*
C
FLT
TEK TDS3054
SCOPE
*BSEL HIGH OUT1;
BSEL LOW OUT2
TPC 32. Test Setup for Power-On and Power-Off
Response with VSET and ENBL Grounded
GENERAL DESCRIPTION AND THEORY
The AD8316 is a wideband logarithmic amplifier (log amp) with
two selectable outputs suitable for dual-band/dual-mode power
amplifier control. It is strictly optimized for power control appli-
cations rather than for use as a measurement device. Figure 1
shows its main features in block schematic form. The output
pins, OUT1 and OUT2, are intended to be applied directly to
the automatic power control (APC) pins of two distinct power
For a log amp with a slope VDB of +22 mV/dB and an inter-
cept at –61 dBm, the output voltage for an input power of
–30 dBm is 0.022 × (–30 – [–61]) = 0.682 V.
FLT1
LOW NOISE
BAND GAP
REFERENCE
OUTPUT
ENABLE
DELAY
VPOS
ENBL
LOW NOISE
GAIN BIAS
HI-Z
ꢂ1.35
OUT1
BSEL
LOW NOISE
RAIL-TO-RAIL
BUFFERS
DET
DET
DET
DET
DET
RFIN
HI-Z
10dB
10dB
10dB
10dB
OUT2
FLT2
ꢂ1.35
OFFSET
COMPENSATION
INTERCEPT
POSITIONING
VSET
325mV TO
1.4V = 49dB
V–I
COMM
Figure 1. Block Schematic of the AD8316
–9–
REV. C
AD8316
Further details about the structure and function of log amps are
provided in data sheets for other log amps produced by Analog
Devices. The AD640 and AD8307 include detailed discussions
of the basic principles of operation and explain why the intercept
depends on waveform, an important consideration when complex
modulation is imposed on an RF carrier.
In a device intended for measurement applications, this current
would be converted to an equivalent voltage to provide the
log(VIN) function shown in Equation 1. However, the design of
the AD8316 differs from standard practice in that its output
needs to be a low noise control voltage for an RF power ampli-
fier, not a direct measure of the input level. Further, it is highly
desirable that this voltage be proportional to the time integral of
the error between the actual input VIN and a dc voltage VSET
(applied to Pin 3, VSET) that defines the setpoint, that is, a
target value for the power level, typically generated by a DAC.
The intercept need not correspond to a physically realizable part
of the signal range for the log amp. Thus, for the AD8316, the
specified intercept is –62 dBm at 0.9 GHz, whereas the lowest
acceptable input for accurate measurement (+1 dB error) is
–48 dBm. At 2.5 GHz, the +1 dB error point shifts to –52 dBm.
This positioning of the intercept is deliberate and ensures that
the VSET voltage is within the capabilities of certain DACs,
whose outputs cannot swing below 200 mV. Figure 2 shows the
0.9 GHz response of the AD8316; the vertical axis represents
the value required at the power control pin VSET to null the
control loop rather than the voltage at the OUT1 or OUT2
pins.
This is achieved by converting the difference between the sum
of the detector outputs (still in current form) and an internally
generated current proportional to VSET to a single-sided
current-mode signal. This, in turn, is converted to a voltage
(at FLT1 or FLT2, the low-pass filter capacitor nodes) to
provide a close approximation to an exact integration of the
error between the power present in the termination at the input
of the AD8316 and the setpoint voltage. Finally, the voltages
developed across the ground referenced filter capacitors CFLT
are buffered by a special low noise amplifier of low voltage
gain (×1.35) and presented at OUT2 or OUT1 for use as the
control voltage for the appropriate RF power amplifier. This
buffer can provide rail-to-rail swings and can drive a substan-
tial load current, including large capacitors. Note: The RF
power delivered by the power amplifier is assumed to increase mono-
tonically with an increasingly positive voltage on its APC control pin.
V
, dBV
IN
IN
100ꢁV
1mV
ꢄ60dBV
100mV
1V (rms)
0dBV
10mV
ꢄ40dBV
ꢄ80dBV
ꢄ20dBV
1.5V
1.408V AT +2dBm
1.0V
Band selection in the AD8316 relies on the fact that dual-band/
dual-mode amplifier systems require only one active amplifier at
a time. This allows both amplifier outputs to share the RF input
of the AD8316 (Pin 1, RFIN) as long as the inactive amplifier is
disabled, i.e., it is not delivering RF power. In this case, power
control is directed solely through the selected amplifier. The
AD8316 ensures that the output control pin associated with the
unselected amplifier pulls its APC pin to ground. It is assumed
that the amplifier is essentially disabled when its APC pin is
grounded.
ACTUAL
SLOPE = 22mV/dB
0.5V
0.308V AT –48dBm
IDEAL
0
–62dBm
–67dBm
–47dBm
–27dBm
–7dBm
+13dBm
P
IN
Control Loop Dynamics
Figure 2. Basic Calibration of the AD8316 at 0.9 GHz
To understand how the AD8316 behaves in a complete control
loop, it is necessary to develop an expression for the current in
the integration capacitor as a function of the input VIN and the
setpoint voltage VSET. Refer to Figure 3.
Controller-Mode Log Amps
The AD8316 combines the two key functions required for the
measurement and control of the power level over a moder-
ately wide dynamic range. First, it provides the amplification
needed to respond to small signals with a chain of four ampli-
fier/limiter cells, each with a small signal gain of 10 dB and a
bandwidth of approximately 4 GHz (see Figure 1). At the
output of each of these amplifier stages is a full-wave recti-
fier, essentially a square-law detector cell that converts the
RF signal voltages to a fluctuating current having an average
value that increases with signal level. A passive detector stage is
added ahead of the first stage. These five detectors are separated
by 10 dB, spanning 50 dB of dynamic range. Their outputs are
in the form of a differential current, making summation a
simple matter. It is readily shown that the summed output can
closely approximate a logarithmic function. The overall accu-
racy at the extremes of the total range, viewed as the deviation
from an ideal logarithmic response, that is, the law-conformance
error, can be judged by referring to TPC 4, which shows that
errors across the central 40 dB are moderate. Other perfor-
mance curves show how conformance to an ideal logarithmic
function varies with supply voltage, temperature, and frequency.
VSET
3
I
= V
SET
/ 4.15kꢀ
SET
SETPOINT
INTERFACE
V
SET
FLT1
4
VOUT1
9
RFIN
1
LOGARITHMIC
RF DETECTION
SUBSYSTEM
ꢂ1.35
V
IN
I
DET
I
ERR
C
FLT
I
= I
SLP
log (V /V )
10 IN
DET
Z
Figure 3. Behavioral Model for the AD8316 with
OUT1 Selected
First, write the summed detector currents as a function of the
input:
(3)
IDET = ISLP log10 (VIN /VZ )
where IDET is the partially filtered demodulated signal, whose
exact average value will be extracted through the subsequent
integration step; ISLP is the current-mode slope, and has a value
of 106 mA per decade (that is, 5.3 mA/dB); VIN is the input in
–10–
REV. C
AD8316
volts rms; and VZ is the effective intercept voltage, which, as
previously noted, is dependent on waveform but is 199 µV rms
for a sine wave input. Now, the current generated by the setpoint
interface is simply
point for understanding the more complex situation that arises
when the gain control law is less than ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is
(4)
ISET =VSET /4.15 kΩ
V
OUT (s) =
IERR, the difference between this current and IDET, is applied to
the loop filter capacitor CFLT. It follows that the voltage appearing
on this capacitor, VFLT, is the time integral of the difference
current
(10)
(VSET
VGSC )/VSLP − VGSC log10 (kGO VCW /VZ )
1+ sTO
where k is the voltage coupling factor from the output of the
power amplifier to the input of the AD8316 (e.g., ×0.1 for a 20 dB
coupler) and TO is a modified time constant (VGSC/VSLP)T.
V
FLT (s) = (ISET – IDET )/ sCFLT
(5)
VSET /4.15 kΩ – ISLP log10(VIN /V )
Z
=
(6)
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level VSET or the carrier input VCW. Second, it reveals that the
final value of the control voltage VOUT will be determined by
several fixed factors
sCFLT
The control output VOUT is slightly greater than this, since the
gain of the output buffer is ×1.35. Also, an offset voltage is delib-
erately introduced in this stage, but this is inconsequential, since
the integration function implicitly allows for an arbitrary constant
to be added to the form of Equation 6. The polarity is such that
VOUT will rise to its maximum value for any value of VSET greater
than the equivalent value of VIN. In practice, the output will rail
to the positive supply under this condition unless the control
loop through the power amplifier is present. In other words, the
AD8316 seeks to drive the RF power to its maximum value when-
ever it falls below the setpoint. The use of exact integration results
in a final error that is theoretically zero, and the logarithmic
detection law would ideally result in a constant response time
following a step change of either the setpoint or the power level, if
the power amplifier control function were likewise “linear-in-dB.”
This latter condition is rarely true, however, and it follows that
the loop response time will, in practice, depend on the power level,
and this effect can strongly influence the design of the control loop.
VOUT t = ∞ = (VSET VGSC )/VSLP − VGSC log10 (kGO VCW /V )
(
)
(11)
Z
V
V
CW
DIRECTIONAL COUPLER
RF
RF PA
RF DRIVE: UP
TO 2.5GHz
V
= kV
RF
IN
V
AD8316
OUT1
V
SET
C
RESPONSE-SHAPING
OF OVERALL CONTROL
LOOP (EXTERNAL CAP)
FLT
Figure 4. Idealized Control Loop for Dynamic
Analysis, OUT1 Selected
Equation 6 can be clarified by noting that it can be restated in
the following way
Example
VSET –VSLP log10(VIN /VZ )
Assume that the gain magnitude of the power amplifier runs from
a minimum value of ×0.316 (–10 dB) at VOUT = 0 to ×100
(40 dB) at VOUT = 2.5 V. Applying Equation 9, we find GO =
0.316 and VGSC = 1 V. Using a coupling factor of k = 0.0316
(that is, a 30 dB directional coupler) and recalling that the nominal
value of VSLP is 440 mV and VZ = 199 µV for the AD8316, we will
first calculate the range of values needed for VSET to control an
output range of +32 dBm to –17 dBm. Note that, in the steady
state, the numerator of Equation 7 must be zero, that is
VOUT (s) =
(7)
sT
where VSLP is the volts-per-decade slope from Equation 1, having a
value of 440 mV/dec, and T is an effective time constant for
the integration, being equal to (4.15 kΩ × CFLT)/1.35; the resis-
tor value comes from the setpoint interface scaling Equation 4
and the factor 1.35 arises as a result of the voltage gain of the
buffer. So the integration time constant can be written as
T = 3.07 ×CFLT
(8)
VSET =VSLP log10 kV VZ
(12)
(
)
PA
in µs whenC
(
is expressed in nF
)
FLT
when VIN is expanded to kVPA, the fractional voltage sample of
the power amplifier output. Now, for +32 dBm, VPA = 8.9 V rms,
this evaluates to
To simplify understanding of the control loop dynamics, begin
by assuming that the power amplifier gain function actually is
linear-in-dB; for now, we will also use voltages to express the
signals at the power amplifier input and output. Let the RF output
voltage be VPA and its input be VCW; further, to characterize the
gain control function, this form is used
VSET max = 0.44 log 281 mV/199 µV =
(
)
(
)
10
(13)
1.39V
For a delivered power of –17 dBm, VPA = 31.6 mV rms,
VPA = GO VCW 10(V
OUT/VGSC
)
(9)
VSET min = 0.44 log 1.0 mV/199 µV =
(
)
(
)
10
(14)
where GO is the gain of the power amplifier when VOUT = 0 and
VGSC is the gain scaling. While few amplifiers will conform so
conveniently to this law, it nevertheless provides a clearer starting
0.310V
Note: The power range is 49 dB, which corresponds to a voltage
change of 49 dB × 22 mV/dB = 1.08 V in VSET
.
REV. C
–11–
AD8316
The value of VOUT is of interest, although it is a dependent param-
eter inside the loop. It depends on the characteristics of the
is not. For example, 224 mV rms is always –13 dBV, with one
further condition of an assumed sinusoidal waveform; see the
AD640 data sheet for more information about the effect of wave-
form on logarithmic intercept. This corresponds to a power
of 0 dBm when the net impedance at the input is 50 Ω. When
this impedance is altered to 200 Ω, however, the same voltage
corresponds to a power level that is four times smaller (P = V2/R),
or –6 dBm. A dBV level may be converted to dBm in the special
case of a 50 Ω system and a sinusoidal signal simply by adding
13 dB. 0 dBV is then, and only then, equivalent to 13 dBm.
power amplifier, and the value of the carrier amplitude VCW
Using the control values derived above, that is, GO = 0.316 and
GSC = 1 V, and assuming that the applied power is fixed at
–7 dBm (so that VCW = 100 mV rms), Equation 11 shows
.
V
(15)
(16)
VOUT max = VSETVGSC
V
− log10 kG V
VZ
(
)
(
)
(
)
SLP
O
CW
0.0316 × 0.316 ×
= 1.39 ×1 0.44 − log
(
)
10
0.1/ 199 µV
P
RF
= 3.2 − 0.7 = 2.5V
V
P
2
2,
33dBm
23dBm
13dBm
3dBm
VOUT min = VSETVGSC
V
− log10 kG V
VZ
(
)
(
)
(
)
SLP
O
CW
0.0316 × 0.316 ×
= 0.31 ×1 0.44 −log
(
)
10
0.1/199 µV
= 0.7 − 0.7 = 0
Both results are consistent with the assumptions made about the
amplifier control function. Note that the second term is inde-
pendent of the delivered power and is a fixed function of the
drive power.
Finally, the loop time constant for these parameters, using an
illustrative value of 2 nF for the filter capacitor CFLT, evaluates to
V
OUT1
–7dBm
V
P
1
TO = V
/VSLP T
1,
(
)
GSC
–67dBm
–47dBm
–27dBm
–7dBm
+13dBm
(17)
= 1/ 0.44 × 3.07 µs × 2 nF = 13.95 µs
(
)
(
)
Figure 5. Typical Power Control Curve
Practical Loop
Therefore, the external termination added ahead of the AD8316
determines the effective power scaling. This often takes the
form of a simple resistor (52.3 Ω will provide a net 50 Ω input),
but more elaborate matching networks may be used. The choice
of impedance determines the logarithmic intercept, that is, the
input power for which the VSET versus PIN function would cross
the baseline if that relationship were continuous for all values of
VIN. This is never the case for a practical log amp; the intercept
(so many dBV) refers to the value obtained by the minimum-error
straight-line fit to the actual graph of VSET versus PIN (more
generally, VIN). Where the modulation is complex, as in CDMA,
the calibration of the power response needs to be adjusted; the
intercept will remain stable for any given arbitrary waveform.
When a true power (waveform independent) response is needed,
a mean-responding detector, such as the AD8361, should be
considered.
At the present time, power amplifiers, or VGAs preceding such
amplifiers, do not provide an exponential gain characteristic. It
follows that the loop dynamics (the effective time constant) will
vary with the setpoint, since the exponential function is unique
in providing constant dynamics. The procedure must therefore
be as follows. Beginning with the curve usually provided for the
power output versus APC voltage, draw a tangent at the point
on this curve where the slope is highest (see Figure 5). Using
this line, calculate the effective minimum value of the variable
VGSC, and use it in Equation 17 to determine the time constant.
(Note that the minimum in VGSC corresponds to the maximum
rate of change in the output power versus VOUT.)
For example, suppose it is found that, for a given drive power,
the amplifier generates an output power of P1 at VOUT = V1, and
P2 at VOUT = V2. Then, it is readily shown that
The logarithmic slope, VSLP in Equation 1, which is the amount by
which the setpoint voltage needs to be changed for each decade
of input change (voltage or power) is, in principle, independent
of waveform or termination impedance. In practice, it usually
falls off somewhat at higher frequencies, because of the declining
gain of the amplifier stages and other effects in the detector
cells (see TPC 13).
VGSC = 20V –V / P – P
1) (
This should be used to calculate the filter capacitance. The
response time at high and low power levels (on the “shoulders”
of the curve shown in Figure 5) will be slower. Note also that it
is sometimes useful to add a zero in the closed-loop response by
(18)
(
)
2
2
1
placing a resistor in series with CFLT
.
A Note About Power Equivalency
Basic Connections
Users of the AD8316 must understand that log amps funda-
mentally do not respond to power. For this reason, dBV
(decibels above 1 V rms) are included in addition to the com-
monly used metric dBm. The dBV scaling is fixed, independent
of termination impedance, while the corresponding power level
Figure 6 shows the basic connections for operating the AD8316
and Figure 7 shows a block diagram of a typical application.
The AD8316 is typically used in the RF power control loop of
dual mode and trimode mobile handsets where there is more
than one RF power control line.
–12–
REV. C
AD8316
level and the level corresponding to the setpoint voltage will be
corrected by the selected output, OUT1 or OUT2, which drives
the gain control terminal of the PAs. This restores a balance
between the actual power level sensed at the input of the AD8316
and the demanded value determined by the setpoint. This assumes
that the gain control sense of the variable gain element is posi-
tive; that is, an increasing voltage from OUT1 or OUT2 will
tend to increase gain. The outputs can swing from 100 mV
above ground to within 100 mV of the supply rail and can source
up to 12 mA. (A plot of maximum output voltage versus output
current is shown in TPC 19.) OUT1/OUT2 are capable of
sinking more than 200 µA.
C1
0.1ꢁF
R1
52.3ꢀ
AD8316
+V
S
RFIN
VPOS
RFIN
+V
1
10
2.7 TO 5.5V
ENBL
OUT1
V
2
3
4
5
9
8
7
6
OUT1
S
VSET COMM
V
SET
FLT1
OUT2
FLT2
V
OUT2
C
FLT1
BSEL
C
V
FLT2
BSEL
Figure 6. Basic Connections (Shown with MSOP Pinout)
Range on VSET and RF Input
RX1
ANT
RX2
TX1
The relationship between RF input level and the setpoint volt-
age follows from the nominal transfer function of the device (see
TPCs 2, 3, 5, and 6). At 0.9 GHz, for example, a voltage of 1 V
on VSET indicates a demand for –17 dBm (–30 dBV) at RFIN.
The corresponding power level at the output of the power ampli-
fier will be greater than this amount due to the attenuation
through the directional coupler. For setpoint voltages of less
than approximately 200 mV and RF input amplitudes greater
than approximately –50 dBm, VOUT will remain unconditionally
at its minimum level of approximately 250 mV. This feature can
be used to prevent any spurious emissions during power-up and
power-down phases. Above 250 mV, VSET will have a linear
control range up to 1.4 V, corresponding to a dynamic range of
49 dB. This results in a slope of 22.2 mV/dB or approximately
45.5 dB/V.
RFIN2
RFIN1
PWR
AMP
TX2
GAIN
CONTROL
VOLTAGES
DIRECTIONAL
COUPLER
OUT1 OUT2
VSET
DAC
ATTN
RFIN
BSEL
FLT2
R1
52.3ꢀ
BAND
SELECT
FLT1
C
C
FLT1
FLT2
Figure 7. Block Diagram of Typical Application
A supply voltage of 2.7 V to 5.5 V is required for the AD8316.
The supply to the VPOS pin should be decoupled with a low
inductance 0.1 µF surface-mount ceramic capacitor close to the
device. The AD8316 has an internal input coupling capacitor,
which negates the need for external ac coupling. This capacitor,
along with the device’s low frequency input impedance of approxi-
mately 3.0 kΩ, sets the minimum usable input frequency to around
20 MHz. A broadband 50 Ω input match is achieved in this
example by connecting a 52.3 Ω resistor between RFIN and
ground (COMM). A plot of input impedance versus frequency
is shown TPC 9. Other matching methods are also possible
(see the Input Coupling Options section).
Transient Response
The time domain response of power amplifier control loops,
using any kind of controller, is only partially determined by the
choice of filter which, in the case of the AD8316, has a true
integrator form 1/sT, as shown in Equation 7, with a time con-
stant given by Equation 8. The large signal step response is also
strongly dependent on the form of the gain control law. Never-
theless, some simple rules can be applied. When the filter capacitor
CFLT is very large, it will dominate the time domain response,
but the incremental bandwidth of this loop will still vary as
VOUT traverses the nonlinear gain control function of the PA, as
shown in Figure 5. This bandwidth will be highest at the
point where the slope of the tangent drawn on this curve is
greatest—that is, for power outputs near the center of the PA’s
range—and will be much reduced at both the minimum and the
maximum power levels, where the slope of the gain control
curve is lowest, due to its S-shaped form. Using smaller values
of CFLT, the loop bandwidth will generally increase, in inverse
proportion to its value. Eventually, however, a secondary effect
will appear, due to the inherent phase lag in the power amplifier’s
control path, some of which may be due to parasitic or deliber-
ately added capacitance at the OUT1 and OUT2 pins. This results
in the characteristic poles in the ac loop equation moving off the
real axis and thus becoming complex (and somewhat resonant).
This is a classic aspect of control loop design.
In a power control loop, the AD8316 provides both the detector
and controller functions.
A number of options exist for coupling the RF signal from the
power amplifiers (PA) to the AD8316 input. Because only one
PA output is active at any time, a single RF input on the
AD8316 is sufficient in all cases.
Two directional couplers can be used directly at the PA outputs.
The outputs of these couplers would be passively combined
before being applied to the AD8316 RF input (in general,
some additional attenuation will be required between the coupler
and the AD8316). Another option involves using a dual-direc-
tional coupler between the PA and T/R switch. This device has
two inputs/outputs and a single-coupled output so that no exter-
nal combiner is required.
A third option is to use a single broadband directional coupler
at the output of the transmit/receive (T/R) switch (the outputs
from the two PAs are combined in the T/R switch). This is
shown in Figure 7. This provides the advantage of enabling the
power at the output of the T/R switch to be precisely set, elimi-
nating any errors due to insertion loss and insertion loss
variations of the T/R switch.
The lowest permissible value of CFLT needs to be determined
experimentally for a particular amplifier and circuit board lay-
out. For GSM and DCS power amplifiers, CFLT will typically
range from 150 pF to 300 pF.
In many cases, some improvement in the worst-case response
time can be achieved by including a small resistance in series with
C
FLT; this generates an additional zero in the closed-loop trans-
fer function, which will serve to cancel some of the higher-order
–13–
A setpoint voltage is applied to VSET from the controlling
source, generally a DAC. Any imbalance between the RF input
REV. C
AD8316
3.5V
4.7ꢁF
1ꢁF
GSM
RF OUTPUT
+35.5dBm MAX
TO
LDC15D190A0007A
GSM RF IN
+6dBm
T/R SWITCH
1
7
R7
PCS/DCS
RF OUTPUT
+33dBm MAX
49.9ꢀ
RF3108
GND
8
5
4
3
DCS/PCS RF IN
+6dBm
2
6
C1
0.1ꢁF
GSM/DCS
16.5dBm/19dBm
21.5dB ATTENUATOR
R1
52.3ꢀ
R5
R4
+V
S
AD8316
54.9ꢀ
576ꢀ
2.7V TO 5.5V
RFIN
VPOS
1
10
9
R8
R6
ENABLE
R2
ENBL
OUT1
2
3
4
5
0V/+V
S
8-BIT
RAMP DAC
0Vꢄ2.55V
600ꢀ
(R5, R6 OPTIONAL)
(SEE TEXT)
VSET COMM
8
R3
FLT1
OUT2
FLT2
7
1kꢀ
C
FLT1
BSEL
6
(R2, R3 OPTIONAL)
(SEE TEXT)
220pF
C
FLT2
220pF
BAND SELECT
0V/+V
S
GSM/(DCS/PCS)
Figure 8. Dual-Mode (GSM/DCS) PA Control Example (Shown with AD8316 MSOP Pinout)
a 2.7 V supply, the voltage on OUT1/OUT2 can come to within
approximately 100 mV of the supply rail. This will depend, how-
ever, on the current draw (see TPC 19).
poles in the overall loop. A combination of main capacitor CFLT
shunted by a second capacitor and resistor in series will also be
useful in minimizing the settling time of the loop.
During initialization and completion of the transmit sequence,
Mobile Handset Power Control Example
V
V
OUT should be held at its minimum level of 250 mV by keeping
SET below 200 mV. In this example, VSET is supplied by an 8-bit
Figure 8 shows a complete power amplifier control circuit for a
dual-mode handset. The RF3108 (RF Micro Devices), dual-
input, trimode (GSM, DCS, PCS) PA is driven by a nominal
power level of 6 dBm at both inputs and has two gain control
lines. Some of the output power from the PA is coupled off
using a dual-band directional coupler (Murata part number
LDC15D190A0007A). This has a coupling factor of approxi-
mately 20 dB for the GSM band and 15 dB for DCS and an
insertion loss of 0.38 dB and 0.45 dB, respectively. Because the
RF3108 transmits a maximum power level of approximately
35 dBm for GSM and 32 dBm for DCS/PCS, additional attenua-
tion of 20 dB is required before the coupled signal is applied to
the AD8316. This results in peak input levels of –5 dBm (GSM)
and –3 dBm (DCS). While the AD8316 gives a linear response
for input levels up to +3 dBm, for highly temperature-stable
performance at maximum PA output power, the maximum
input level should be limited to approximately –3 dBm (see
TPC 3 and TPC 5). This does, however, reduce the sensitivity
of the circuit at the low end.
DAC that has an output range from 0 V to 2.55 V or 10 mV
per bit. This sets the control resolution of VSET to 0.4 dB/bit
(0.04 dB/mV ꢂ 10 mV). If finer resolution is required, the
DAC’s output voltage can be scaled using two resistors as
shown. This converts the DAC’s maximum voltage of 2.55 V
down to 1.6 V and increases the control resolution to 0.25 dB/bit.
Two filter capacitors (CFLT1/CFLT2) must be used to stabilize
the loop for each band. The choice of CFLT will depend to a
large degree on the gain control dynamics of the power ampli-
fier, something that is frequently poorly characterized, so some
trial and error may be necessary. In this example, a 220 pF
capacitor is used. The user may want to add a resistor in series
with the filter capacitor. The resistor adds a zero to the control
loop and increases the phase margin, which helps to make the
step response of the circuit more stable when the slope of the
PA’s power control function is the steepest. In this example,
the two filter capacitors are equal values; however, this is not
a requirement.
The operational setpoint voltage, in the range 250 mV to 1.4 V,
is applied to the VSET pin of the AD8316. This will typically be
supplied by a DAC. The desired output is selected by applying
a high or low signal to the BSEL pin (HI = OUT1, LO = OUT2).
The selected output directly drives the level control pin of the
power amplifier. In this case a minimum supply voltage of 2.9 V
is required and VOUT reaches a maximum value of approximately
2.6 V while delivering about 5 mA to the PA’s VAPC input. For
power amplifiers with lower VAPC input ranges, a corresponding
low power supply to the AD8316 can be used. For example, on
A smaller filter capacitor can be used by inserting a series resis-
tor between VOUT and the control input of the PA. A series
resistor will work with the input impedance of the PA to create a
resistor divider and will reduce the loop gain. The size of the
resistor divider ratio depends upon the available output swing of
V
OUT and the required control voltage on the PA. This tech-
nique can also be used to limit the control voltage in situations
where the PA cannot deliver the power level demanded by VOUT. Over-
drive of the control input of some PAs causes increased distortion.
–14–
REV. C
AD8316
Enable and Power-On
Figure 9c shows a third method for coupling the input signal
into the AD8316, applicable where the input signal is larger
than the input range of the log amp. A series resistor, connected
to the RF source, combines with the input impedance of the
AD8316 to resistively divide the input signal being applied to
the input. This has the advantage of very little power being
tapped off in RF power transmission applications.
The AD8316 may be disabled by pulling the ENBL pin to
ground. This reduces the supply current from its nominal level
of 8.5 mA to 3 µA at 2.7 V. The logic threshold for turning on
the device is at 1.8 V at 2.7 V. A plot of the enable glitch is
shown in TPC 20. Alternatively, the device can be completely
disabled by pulling the supply voltage to ground; ENBL would be
connected to VPOS. The glitch in this mode of operation is
shown on TPC 25 and TPC 26. If VPOS is applied before the
device is enabled, a narrow glitch of less than 50 mV will result.
This is shown in TPC 31.
Using the Chip Scale Package
On the underside of the chip scale package, there is an exposed
paddle. This paddle is internally connected to the chip’s ground.
For better electrical performance, this paddle should be soldered
down to the printed circuit board’s ground plane, even though
there is no thermal requirement to do so.
In both situations, the voltage on VSET should be kept below
250 mV during power-on and power-off, preventing any unwanted
transients on VOUT
.
EVALUATION BOARD
Input Coupling Options
Figures 10 and 11 show the schematics of the AD8316 MSOP and
LFCSP evaluation boards. Note that uninstalled components are
marked as open. The layout and silkscreen of the MSOP evalua-
tion board are shown in Figures 12 and 13. Apart from the slightly
smaller device footprint and number of pins, the LFCSP evalua-
tion board is identical to the MSOP board. The boards are
powered by a single supply in the 2.7 V to 5.5 V range. The power
supply is decoupled by a single 0.1 µF capacitor. Table II details
the various configuration options of the evaluation boards.
The internal 5 pF coupling capacitor of the AD8316, along with
the low frequency input impedance of 3 kΩ, result in a high-pass
input corner frequency of approximately 20 MHz. This sets the
minimum operating frequency. Figure 9 shows three options for
input coupling. A broadband resistive match can be implemented
by connecting a shunt resistor to ground at RFIN. This 52.3 Ω
resistor (other values can also be used to select different overall
input impedances) combines with the input impedance of the
AD8316 (3 kΩꢀ1 pF) to give a broadband input impedance of
50 Ω. While the input resistance and capacitance (CIN and RIN)
will vary by approximately 20% from device to device, the
dominance of the external shunt resistor means that the varia-
tion in the overall input impedance will be close to the tolerance
of the external resistor. This method of matching is most useful
in wideband applications or in multimode systems where there
is more than one operating frequency and those frequencies are
quite far apart.
For operation in controller mode, both jumpers, LK1 and LK2,
should be removed. OUT1 and OUT2 can be selected with SW3
in Position A and Position B, respectively. The setpoint voltage
is applied to VSET, RFIN is connected to the RF source (PA
output or directional coupler), and OUT1 or OUT2 is connected
to the gain control pins of each PA. When the AD8316 is used
in controller mode, a capacitor and a resistor must be installed
in C4, C6, and R10, R11 for loop stability. For GSM/DCS
handset power amplifiers, this capacitor should typically range
from 150 pF to 300 pF. The series resistor improves the system
phase margin at low power levels, which in turn improves the
step response in the circuit. Typically, this resistor value should
be about 1.5 kΩ.
A reactive match can also be implemented as shown in Figure 9b.
This is not recommended at low frequencies because device
tolerances will vary the quality of the match dramatically because
of the large input resistance. For low frequencies, Option 9a or
Option 9c is recommended.
A quasi-measurement mode (in which the AD8316 delivers an
output voltage that is proportional to the log of the input signal)
can be implemented to establish the relationship between VSET
and RFIN with the installation of two jumpers, LK1 and LK2.
This mimics an AGC loop. To establish the transfer function of
the log amp, the RF input should be swept while the voltage on
VSET is measured, that is, the SMA connector labeled VSET
acts as an output. This is the simplest method for validating
operation of the evaluation board. When operated in this
mode, a large capacitor (0.01 µF or greater) must be installed in
C4 or C6 (set R10/R11 to 0 Ω) to ensure loop stability.
In Figure 9b, the matching components are drawn as generic
reactances. Depending on the frequency, the input impedance
at that frequency, and the availability of standard value compo-
nents, either a capacitor or an inductor will be used. As in the
previous case, the input impedance at a particular frequency is
plotted on a Smith chart and matching components are chosen
(shunt or Series L, shunt or Series C) to move the impedance to
the center of the chart.
REV. C
–15–
AD8316
ANTENNA
AD8316
AD8316
AD8316
C
C
C
C
C
C
X1
RFIN
RFIN
RFIN
X2
STRIPLINE
PA
R
R
SHUNT
ATTN
52.3ꢀ
C
R
C
R
C
R
IN
IN
IN
IN
IN
IN
a. Broadband Resistive
b. Narrow-Band Reactive
c. Series Attenuation
Figure 9. Input Coupling Options
C1
0.1ꢁF
J1
R2
52.3ꢀ
R1
0ꢀ
INPUT
VPOS
AD8316
1
2
3
4
5
R3
0ꢀ
10
9
VPOS
OUT1
COMM
OUT2
FLT2
RFIN
ENBL
VSET
FLT1
BSEL
VPOS
J2
A
OUT1
C2
(OPEN)
R4
(OPEN)
SW1
R12
8
7
6
B
J3
J4
0ꢀ
OUT2
VSET
C4
(OPEN)
C7
(OPEN)
R9
(OPEN)
C6
(OPEN)
R10
OUT1 (A)
(OPEN)
R11
SW3
(OPEN)
VPOS
OUT1(A)
OUT2(B)
OUT2 (B)
SW2
VPOS
LK1
LK2
C3
0.1ꢁF
R7
16.2kꢀ
C5
0.1ꢁF
R8
10kꢀ
R6
17.8kꢀ
AD8031
R5
10kꢀ
Figure 10. Schematic of Evaluation Board (MSOP)
C1
0.1ꢁF
J1
R2
52.3ꢀ
NC NC
16 15 14 13
NC
R1
INPUT
VSET
0ꢀ
VPOS
A
1
2
3
4
12
11
R3
RFIN
VPOS
VPOS
J2
0ꢀ
ENBL
OUT1
OUT1
J4
C2
R4
B
AD8316
SW1
(OPEN)
(OPEN)
VSET
COMM 10
R12
J3
0ꢀ
FLT1
5
OUT2
8
9
OUT2
C7
R9
(OPEN)
C4
(OPEN)
6
7
(OPEN)
OUT1 (A)
OUT2 (B)
NC
NC
R10
(OPEN)
C6
NC = NO CONNECT
(OPEN)
SW3
VPOS
R11
(OPEN)
OUT1 (A)
OUT2 (B)
SW2
VPOS
LK1
LK2
C3
0.1ꢁF
R7
16.2kꢀ
C5
0.1ꢁF
R8
10kꢀ
R6
17.8kꢀ
AD8031
R5
10kꢀ
Figure 11. Schematic of Evaluation Board (LFCSP)
–16–
REV. C
AD8316
Table II. Evaluation Board Configuration Options
Component
Function
Default Condition
TP1, TP2
SW1
Supply and Ground Vector Pins.
Not Applicable
SW1 = A
Device Enable. When in Position A, the ENBL pin is connected to VPOS and
the AD8316 is in operating mode. In Position B, the ENBL pin is grounded,
putting the device into power-down mode.
SW2
Band Select. When in Position A (OUT1), the BSEL pin is connected to VPOS
and the AD8316 OUT1 is in operation mode. In Position B (OUT2), the
BSEL pin is grounded and the AD8316 OUT2 is in operation while OUT1 pin
is shut down.
SW2 = OUT1
R1, R2
Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8316’s
internal input impedance to provide a broadband input impedance of around
50 Ω. A reactive match can be implemented by replacing R2 with an inductor
and R1 (0 Ω) with a capacitor. In addition, the RF microstrip line has been
provided with a clean mask ground plane to provide additional matching. Note
that the AD8316’s RF input is internally ac-coupled.
R2 = 52.3 Ω (Size 0603)
R1 = 0 Ω (Size 0402)
R3, R4, R12,
R9, C2, C7
Output Interface. R4 and C2, R9 and C7 can be used to check the response
capacitive and resistive loading, respectively. R3/R4 and R12/R9 can be used to
reduce the slope of OUT1 and OUT2.
R4 = C2 = Open (Size 0603)
R9 = C7 = Open (Size 0603)
R3 = R12 = 0 Ω (Size 0603)
C1, C5
Power Supply Decoupling. The nominal supply decoupling consists of
a 0.1 µF capacitor.
C1 = C5 = 0.1 µF (Size 0603)
C4, C6, R10, Filter Capacitors/Resistors. The response time of OUT1, OUT2 can be modified C4 = C6 = Open (Size 0603)
R11
by placing the capacitors between FLT1, FLT2 and resistors R10, R11
to ground.
R10 = R11 = Open (Size 0603)
LK1, LK2
Measurement Mode. A quasi-measurement mode can be implemented by
installing LK1 and LK2 (connecting an inverted OUT1 or OUT2 to VSET) to
yield the nominal relationship between RFIN and VSET. In this mode, a large
capacitor (0.01 µF or greater) must be installed in C4 and C6 and a 0 Ω
resistors to ground in R10 and R11. To select OUT1 or OUT2, SW3 must
be in the OUT1 position or the OUT2 position, respectively.
LK1, LK2 = Installed
SW3
Measurement Mode Output Select. When in measurement mode, output 1
or output 2 can be selected by positioning SW3 to the OUT1 position or the
OUT2 position, respectively.
SW3 = OUT1
REV. C
–17–
AD8316
Figure 12. Silkscreen of Component Side (MSOP)
Figure 13. Layout of Component Side (MSOP)
–18–
REV. C
AD8316
OUTLINE DIMENSIONS
16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm ꢂ 3 mm Body
(CP-16-3)
Dimensions shown in millimeters
0.50
0.40
0.30
3.00
0.60 MAX
BSC SQ
PIN 1 INDICATOR
1.65
1.50 SQ
1.35
13
12
16
5
0.45
*
1
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
4
9
8
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
0.65TYP
12ꢃ MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
*
COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8ꢃ
0ꢃ
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
REV. C
–19–
AD8316
Revision History
Location
Page
1/04–Data Sheet changed from REV. B to REV. C.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
12/03–Data Sheet changed from REV. A to REV. B.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/03–Data Sheet changed from REV. 0 to REV. A.
Addition of LFCSP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TPC 9 replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to TPC 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Example section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Edits to Input Coupling Options section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Addition of new Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
–20–
REV. C
相关型号：
AD8317ACPZ-REEL7
IC LOG OR ANTILOG AMPLIFIER, 10000 MHz BAND WIDTH, QCC8, LEAD FREE, 2 X 3 MM, LFCSP-8, Analog Computational Function
ADI
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