AD8318ACPZ [ADI]
暂无描述;
| 型号： | AD8318ACPZ |
| 厂家： | 
ADI |
| 描述： | 暂无描述 功率控制 |
| 文件： | 总3页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Circuit Note
CN-0050
Devices Connected/Referenced in this Circuit Note
ADL5330 Variable Gain Amplifier (VGA)
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AD8318
70 dB Logarithmic Detector/Controller
Stable, Closed-Loop Automatic Power Control for RF Applications
with an automatic gain control (AGC) loop. Figure 1 shows the
ADL5330 operating in an AGC loop. The addition of the AD8318
log amp allows the AGC to have improved temperature stability
over a wide output power control range.
CIRCUIT FUNCTION AND BENEFITS
The circuit described in this document provides closed-loop, auto-
matic power control using a VGA (ADL5330) and a log detector
(AD8318). Due to the high temperature stability of the AD8318,
this circuit provides stability over temperature because the AD8318
RF detector ensures the same level of temperature stability at the
output of the ADL5330 VGA. The addition of the log amp detector
converts the ADL5330 from an open-loop variable gain amplifier
to a closed-loop output power control circuit. Because the AD8318,
like the ADL5330, has a linear-in-dB transfer function, the POUT vs.
setpoint transfer function also follows a linear-in-dB characteristic.
To operate the ADL5330 VGA in an AGC loop, a sample of the
output RF must be fed back to the detector (typically using a
directional coupler and additional attenuation). A setpoint voltage
is applied by a DAC to the VSET input of the detector while VOUT
is connected to the GAIN pin of the ADL5330. Based on the
detector’s defined linear-in-dB relationship between VOUT and the
RF input signal, the detector adjusts the voltage on the GAIN pin
(the detector’s VOUT pin is an error amplifier output) until the
level at the RF input corresponds to the applied setpoint voltage.
GAIN settles to a value that results in the correct balance between
the input signal level at the detector and the setpoint voltage.
CIRCUIT DESCRIPTION
Although the ADL5330 variable gain amplifier provides accurate
gain control, precise regulation of output power can be achieved
+5V
+5V
RF INPUT
SIGNAL
RF OUTPUT
SIGNAL
120nH
100pF
120nH
VPSx
INHI
COMx
OPHI
100pF
100pF
ADL5330
100pF
DIRECTIONAL
INLO
OPLO
COUPLER
GAIN
ETC1-1-13
(M/A-COM)
ETC1-1-13
(M/A-COM)
412Ω
+5V
ATTENUATOR
1kΩ
SETPOINT
VOLTAGE
VOUT
VPSx
1nF
VSET
INHI
DAC*
AD8318
LOG AMP
1nF
CLPF
INLO
220pF
CMxP
*SEE COMMON VARIATIONS SECTION
Figure 1. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318 (Simplified Schematic: Decoupling and
All Connections Not Shown)
Rev. B
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CN-0050
Circuit Note
T
T
The basic connections for operating the ADL5330 in an AGC
loop with the AD8318 are shown in Figure 1. The AD8318 is a
1 MHz to 8 GHz precision demodulating logarithmic amplifier.
It offers a large detection range of 60 dB with 0.5 dB
temperature stability. The gain control pin of the ADL5330 is
controlled by the output pin of the AD8318. This voltage,
VOUT, has a range of 0 V to near VPSx. To avoid overdrive
recovery issues, the AD8318 output voltage can be scaled down
using a resistive divider to interface with the 0 V to 1.4 V gain
control range of the ADL5330.
AM MODULATED INPUT
1
AD8318 OUTPUT
2
3
A coupler/attenuation of 23 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8318 (at approximately −5 dBm
at 900 MHz).
ADL5330 OUTPUT
CH1 250mV Ω CH2 200mV
CH3 250mV Ω
M2.00ms
T
0.00000s
Figure 3. Oscilloscope Showing an AM Modulated Input Signal
The detector’s error amplifier uses CLPF, a ground-referenced
capacitor pin, to integrate the error signal (in the form of a
current). A capacitor must be connected to CLPF to set the loop
bandwidth and to ensure loop stability.
For the AGC loop to remain in equilibrium, the AD8318 must
track the envelope of the ADL5330 output signal and provide
the necessary voltage levels to the ADL5330 gain control input.
Figure 3 shows an oscilloscope screen shot of the AGC loop
depicted in Figure 1. A 100 MHz sine wave with 50% AM
modulation is applied to the ADL5330. The output signal from
the ADL5330 is a constant envelope sine wave with amplitude
corresponding to a setpoint voltage at the AD8318 of 1.5 V.
Also shown is the gain control response of the AD8318 to the
changing input envelope.
30
4
20
3
10
2
0
1
–10
–20
–30
–40
–50
0
T
–1
–2
–3
–4
T
AD8318 WITH PULSED V
SET
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
SETPOINT VOLTAGE (V)
Figure 2. ADL5330 Output Power vs. AD8318 Setpoint Voltage,
PIN = −1.5 dBm
ADL5330 OUTPUT
Figure 2 shows the transfer function of the output power vs. the
VSET voltage over temperature for a 900 MHz sine wave with
an input power of −1.5 dBm. Note that the power control of the
AD8318 has a negative sense. Decreasing VSET, which corres-
ponds to demanding a higher signal from the ADL5330, tends
to increase GAIN.
2
CH1 2.00V CH2 50.0mVΩ
M10.0µs
20.2000µs
A
CH1
2.60V
T
Figure 4. Oscilloscope Showing the ADL5330 Output
The AGC loop is capable of controlling signals just under the
full 60 dB gain control range of the ADL5330. The performance
over temperature is most accurate over the highest power range,
where it is generally most critical. Across the top 40 dB range
of output power, the linear conformance error is well within
0.5 dB over temperature.
Figure 4 shows the response of the AGC RF output to a pulse on
VSET. As VSET decreases to 1 V, the AGC loop responds with
an RF burst. Response time and the amount of signal
integration are controlled by the capacitance at the AD8318
CLPF pin—a function analogous to the feedback capacitor
around an integrating amplifier. An increase in the capacitance
results in slower response time.
The broadband noise added by the logarithmic amplifier is
negligible.
The circuit must be constructed on a multilayer printed circuit
board with a large area ground plane. Proper layout, grounding,
and decoupling techniques must be used to achieve optimum
performance (see the MT-031 Tutorial and the MT-101 Tutorial
and the ADL5330 and ADL8318 evaluation board layouts).
Rev. B | Page 2 of 3
Circuit Note
CN-0050
On the underside of the ADL5330 and AD8318 chip scale
packages, there is an exposed compressed paddle. This paddle is
internally connected to the chip’s ground. Solder the paddle to
the low impedance ground plane on the printed circuit board to
ensure specified electrical performance and to provide thermal
relief. It is also recommended that the ground planes on all
layers under the paddle be stitched together with vias to reduce
thermal impedance.
LEARN MORE
Dana Whitlow, Design and Operation of Automatic Gain Control
Loops for Receivers in Modern Communications Systems, Analog
Devices Wireless Seminar, Chapter 7, 2006.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of “AGND” and “DGND,” Analog Devices.
MT-073 Tutorial, High Speed Variable Gain Amplifiers, Analog
Devices.
COMMON VARIATIONS
MT-077 Tutorial, Log Amp Basics, Analog Devices.
This circuit can be used to implement a constant power out
function (fixed setpoint with variable input power) or a variable
power out function (variable setpoint with fixed or variable
input power). If a lower output power control range is desired,
the AD8318 log amp (60 dB power detection range) can be
replaced with either the AD8317 (50 dB power detection range)
or the AD8319 (45 dB power detection range). For a constant
output power function, the lowest dynamic range detector
(AD8319) is adequate because the loop always servos the
detector input power to a constant level.
MT-078 Tutorial, High Speed Log Amps, Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Data Sheets
ADL5330
AD8318
AD8317
AD8319
ADL5330 Evaluation Board
AD8318 Evaluation Board
The ADL5330 VGA, which is optimized for transmit applications,
can be replaced by the AD8368 VGA. The AD8368 is optimized
for receive application low frequencies of up to 800 MHz and
provides 34 dB of linear-in-dB voltage-controlled variable gain.
REVISION HISTORY
9/10—Rev. A to Rev. B
There are a number of DACs suitable for this application. All of
the following DACs have internal references:
Changes to Figure 1 ..........................................................................1
Changes to Circuit Description Section.........................................1
Changes to Common Variations Section.......................................3
Single: AD5660/AD5640/AD5620 (16-bit/14-bit/12-bit),
Dual: AD5663R/AD5643R/AD5623R (16-bit/14-bit/12-bit)
Quad: AD5664R/AD5644R/AD5624R (16-bit/14-bit/12-bit)
11/09—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to Circuit Note Title..........................................................1
10/08—Revision 0: Initial Release
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CN08515-0-9/10(B)
Rev. B | Page 3 of 3
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