AD8318_06 [ADI]
1 MHz to 8 GHz, 60 dB Logarithmic Detector/Controller; 1 MHz至8 GHz的， 60分贝对数检测器/控制器
| 型号： | AD8318_06 |
| 厂家： | 
ADI |
| 描述： | 1 MHz to 8 GHz, 60 dB Logarithmic Detector/Controller |
| 文件： | 总24页 (文件大小：1942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MHz to 8 GHz, 60 dB Logarithmic
Detector/Controller
AD8318
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VPSI
ENBL
TADJ
VPSO
Wide bandwidth: 1 MHz to 8 GHz
High accuracy: 1.0 dB over 55 dB range (f < 5.8 GHz)
Stability over temperature: 0.5 dB
Low noise measurement/controller output (VOUT)
Pulse response time 10 ns/12 ns (fall/rise)
Integrated temperature sensor
TEMP
SENSOR
GAIN
BIAS
TEMP
SLOPE
VSET
I
I
V
V
VOUT
CLPF
DET
DET
DET
DET
Small footprint CSP package
INHI
Power-down feature: <1.5 mW at 5 V
Single-supply operation: 5 V @ 68 mA
Fabricated using high speed SiGe process
INLO
CMIP
CMOP
Figure 1.
APPLICATIONS
RF transmitter PA setpoint control and level monitoring
RSSI measurement in base stations, WLAN, WiMAX, and radar
GENERAL DESCRIPTION
The AD8318 is a demodulating logarithmic amplifier, capable of
accurately converting an RF input signal to a corresponding decibel-
scaled output voltage. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which is
equipped with a detector cell. The device is used in measurement or
controller mode. The AD8318 maintains accurate log conformance
for signals of 1 MHz to 6 GHz and provides useful operation to
8 GHz. The input range is typically 60 dB (re: 50 Ω) with error less
than 1 dB. The AD8318 has a 10 ns response time that enables RF
burst detection to beyond 45 MHz. The device provides unprece-
dented logarithmic intercept stability vs. ambient temperature
conditions. A 2 mV/°C slope temperature sensor output is also
provided for additional system monitoring. A single supply of 5 V is
required. Current consumption is typically 68 mA. Power
In this mode, the setpoint control voltage is applied to VSET.
The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the amplifier output to a magni-
tude corresponding to VSET. The AD8318 provides 0 V to 4.9 V
output capability at the VOUT pin, suitable for controller
applications. As a measurement device, Pin VOUT is externally
connected to VSET to produce an output voltage, VOUT, which is
a decreasing linear-in-dB function of the RF input signal
amplitude.
The logarithmic slope is nominally −25 mV/dB, but can be
adjusted by scaling the feedback voltage from VOUT to the
VSET interface. The intercept is +20 dBm (re: 50 Ω, CW input)
using the INHI input. These parameters are very stable against
supply and temperature variations.
consumption decreases to <1.5 mW when the device is disabled.
The AD8318 is fabricated on a SiGe bipolar IC process and is
available in a 4 mm × 4 mm, 16-lead LFCSP package, for the
operating temperature range of –40oC to +85oC.
The AD8318 can be configured to provide a control voltage to a
VGA, such as a power amplifier or a measurement output, from
Pin VOUT. Because the output can be used for controller
applications, wideband noise is minimal.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8318
TABLE OF CONTENTS
Features ...................................................................................................1
Temperature Compensation of Output Voltage..........................13
Temperature Sensor........................................................................14
Measurement Mode........................................................................14
Device Calibration and Error Calculation...................................15
Applications............................................................................................1
Functional Block Diagram ...................................................................1
General Description..............................................................................1
Revision History ....................................................................................2
Specifications..........................................................................................3
Absolute Maximum Ratings.................................................................6
ESD Caution.......................................................................................6
Pin Configuration and Function Descriptions..................................7
Typical Performance Characteristics ..................................................8
Theory of Operation .......................................................................... 11
Using the AD8318 .............................................................................. 12
Basic Connections.......................................................................... 12
Enable Interface .............................................................................. 12
Input Signal Coupling.................................................................... 12
Output Interface ............................................................................. 13
Setpoint Interface ........................................................................... 13
Selecting Calibration Points to Improve Accuracy over a
Reduced Range................................................................................16
Variation in Temperature Drift from Device to Device.............17
Temperature Drift at Different Temperatures.............................17
Setting the Output Slope in Measurement Mode .......................17
Response Time Capability .............................................................18
Output Filtering...............................................................................18
Controller Mode..............................................................................19
Characterization Setup and Methods...........................................21
Evaluation Board.................................................................................22
Outline Dimensions............................................................................24
Ordering Guide ...............................................................................24
REVISION HISTORY
1/06—Rev. 0 to Rev. A
Changed TADJ Resistor to RTADJ Resistor....................Universal
Changes to Applications .................................................................. 1
Changes to Table 1............................................................................ 3
Changes to Figure 5, Figure 6, and Figure 7 Captions................. 8
Changes to Figure 12 Caption......................................................... 9
Changes to Figure 15 Caption......................................................... 9
Changed General Description Heading to
Theory of Operation ...................................................................... 11
Changes to Enable Interface Section............................................ 12
Inserted Figure 24........................................................................... 12
Changes to Input Signal Coupling Section ................................. 12
Changes to Measurement Mode Section..................................... 14
Changes to Figure 36...................................................................... 17
Added Output Filtering Section ................................................... 19
Changes to Controller Mode Section........................................... 19
Changes to Response Time Capability Section .......................... 18
Changes to Table 6.......................................................................... 22
Changes to Figure 47, Figure 48, and Figure 49 ......................... 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
7/04—Rev. 0: Initial Version
Rev. A | Page 2 of 24
AD8318
SPECIFICATIONS
VPOS = 5 V, CLPF = 220 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
SIGNAL INPUT INTERFACE
Specified Frequency Range
DC Common-Mode Voltage
MEASUREMENT MODE
f = 900 MHz
INHI (Pin 14) and INLO (Pin 15)
0.001
8
GHz
V
VPOS – 1.8
VOUT (Pin 6) shorted to VSET (Pin 7), sinusoidal input signal
RTADJ = 500 Ω
Input Impedance
1 dꢀ Dynamic Range
957||0.71
57
Ω||pF
dꢀ
TA = +25°C
−40°C < TA < +85°C
1 dꢀ error
1 dꢀ error
48
−1
dꢀ
Maximum Input Level
Minimum Input Level
Slope
dꢀm
dꢀm
mV/dꢀ
dꢀm
V
−58
−24.5
22
0.78
1.52
−26
19.5
0.7
−23
24
0.86
1.62
Intercept
Output Voltage—High Power In PIN = −10 dꢀm
Output Voltage—Low Power In PIN = −40 dꢀm
1.42
V
Temperature Sensitivity
PIN = −10 dꢀm
25°C ≤ TA ≤85°C
−40°C ≤ TA ≤ +25°C
RTADJ = 500 Ω
0.0011
0.003
dꢀ/°C
dꢀ/°C
f = 1.9 GHz
Input Impedance
1 dꢀ Dynamic Range
523||0.68
57
Ω||pF
dꢀ
TA = +25°C
−40°C < TA < +85°C
1 dꢀ error
1 dꢀ error
50
−2
−59
−24.4
20.4
0.73
dꢀ
Maximum Input Level
Minimum Input Level
Slope
dꢀm
dꢀm
mV/dꢀ
dꢀm
V
−27
17
0.63
−22
24
0.83
Intercept
Output Voltage—High Power PIN = −10 dꢀm
In
Output Voltage—Low Power PIN = −35 dꢀm
In
1.2
1.35
1.5
V
Temperature Sensitivity
PIN = –10 dꢀm
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +5°C
RTADJ = 500 Ω
0.0011
0.0072
dꢀ/°C
dꢀ/°C
f = 2.2 GHz
Input Impedance
1 dꢀ Dynamic Range
391||0.66
58
Ω||pF
dꢀ
TA = +25°C
−40°C < TA < +85°C
1 dꢀ error
1 dꢀ error
50
−2
−60
−24.4
19.6
0.73
1.34
dꢀ
dꢀm
dꢀm
Maximum Input Level
Minimum Input Level
Slope
−28
15
0.63
1.2
−21.5 mV/dꢀ
Intercept
25
0.84
1.5
dꢀm
V
V
Output Voltage—High Power In PIN = −10 dꢀm
Output Voltage—Low Power In PIN = −35 dꢀm
Temperature Sensitivity
PIN = −10 dꢀm
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0005
0.0062
dꢀ/°C
dꢀ/°C
Rev. A | Page 3 of 24
AD8318
Parameter
Conditions
Min
Typ
Max
Unit
f = 3.6 GHz
RTADJ = 51 Ω
Input Impedance
1 dꢀ Dynamic Range
119||0.7
58
Ω||pF
dꢀ
TA = +25°C
−40°C < TA < +85°C
1 dꢀ error
1 dꢀ error
42
−2
–60
−24.3
19.8
0.717
1.46
dꢀ
Maximum Input Level
Minimum Input Level
Slope
dꢀm
dꢀm
mV/dꢀ
dꢀm
V
Intercept
Output Voltage—High Power In PIN = −10 dꢀm
Output Voltage—Low Power In PIN = −40 dꢀm
V
Temperature Sensitivity
PIN = −10 dꢀm
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
0.0022
0.004
dꢀ/°C
dꢀ/°C
f = 5.8 GHz
RTADJ = 1000 Ω
Input Impedance
1 dꢀ Dynamic Range
33||0.59
57
Ω||pF
dꢀ
TA = +25°C
−40°C < TA < +85°C
1 dꢀ error
1 dꢀ error
48
−1
−58
−24.3
25
dꢀ
Maximum Input Level
Minimum Input Level
Slope
dꢀm
dꢀm
mV/dꢀ
dꢀm
V
Intercept
Output Voltage—High Power In PIN = −10 dꢀm
Output Voltage—Low Power In PIN = −40 dꢀm
0.86
1.59
V
Temperature Sensitivity
PIN = −10 dꢀm
+25°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +25°C
0.0033
0.0069
dꢀ/°C
dꢀ/°C
f = 8.0 GHz
RTADJ = 500 Ω
TA = +25°C
3 dꢀ Dynamic Range
60
dꢀ
−40°C < TA < +85°C
3 dꢀ error
3 dꢀ error
58
3
−55
−23
dꢀ
Maximum Input Level
Minimum Input Level
Slope
dꢀm
dꢀm
mV/dꢀ
Intercept
37
dꢀm
V
V
Output Voltage—High Power In PIN = −10 dꢀm
Output Voltage—Low Power In PIN = −40 dꢀm
1.06
1.78
Temperature Sensitivity
PIN = −10 dꢀm
+25°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +25°C
0.028
dꢀ/°C
dꢀ/°C
−0.0085
OUTPUT INTERFACE
Voltage Swing
VOUT (Pin 6)
VSET = 0 V; PIN = −10 dꢀm, no load1
VSET = 2.1 V; PIN = −10 dꢀm, no load1
VSET = 1.5 V; PIN = −50 dꢀm
4.9
25
60
V
mV
mA
Output Current Drive
Small Signal ꢀandwidth
PIN = −10 dꢀm; from CLPF to VOUT
60
45
MHz
MHz
Video ꢀandwidth (or Envelope
ꢀandwidth)
Output Noise
Fall Time
Rise Time
PIN = 2.2 GHz; −10 dꢀm, fNOISE = 100 kHz, CLPF = 220 pF
PIN = Off to −10 dꢀm, 90% to 10%
PIN = −10 dꢀm to off, 10% to 90%
90
10
12
nV/√Hz
ns
ns
Rev. A | Page 4 of 24
AD8318
Parameter
Conditions
Min
Typ
Max
Unit
VSET INTERFACE
Nominal Input Range
VSET (Pin 7)
PIN = 0 dꢀm; measurement mode2
PIN = −65 dꢀm; measurement mode2
0.5
2.1
V
Logarithmic Scale Factor
ꢀias Current Source
−0.04
2.5
dꢀ/mV
μA
PIN = −10 dꢀm; VSET = 2.1 V
TEMP (Pin 13)
TA = 25°C, RLOAD = 10 kΩ
−40°C ≤ TA ≤ +85°C, RLOAD = 10 kΩ
TA = 25°C
TEMPERATURE REFERENCE
Output Voltage
Temperature Slope
0.57
0.6
2
0.63
V
mV/°C
mA
Current Source/Sink
10/0.1
POWER-DOWN INTERFACE
Logic Level to Enable Device
ENꢀL Current When Enabled
ENꢀL Current When Disabled
POWER INTERFACE
ENꢀL (Pin 16)
1.7
<1
15
V
μA
μA
ENꢀL = 5 V
ENꢀL = 0 V; sourcing
VPSI (Pin 3 and Pin 4), VPSO (Pin 9)
Supply Voltage
Quiescent Current
vs. Temperature
Supply Current when Disabled
vs. Temperature
4.5
50
5
68
150
260
350
5.5
82
V
ENꢀL = 5 V
−40°C ≤ TA ≤ +85°C
ENꢀL = 0 V, total currents for VPSI and VPSO
−40°C ≤ TA ≤ +85°C
mA
μA/°C
μA
μA
1 Controller mode.
2 Gain = 1. For other gains, see the Measurement Mode section.
Rev. A | Page 5 of 24
AD8318
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage: Pin VPSO, Pin VPSI
ENꢀL, VSET Voltage
Input Power (Single-Ended, re: 50 Ω)
Internal Power Dissipation
5.7 V
0 to VPOS
12 dꢀm
0.73 W
1
55°C/W
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature
125°C
−40°C to +85°C
−65°C to +150°C
260°C
1 With package die paddle soldered to thermal pads with vias connecting
to inner and bottom layers.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
AD8318
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
9
CMIP CMIP TADJ VPSO
13 TEMP
CMOP
VSET
VOUT
CLPF
8
7
6
5
14 INHI
AD8318
15 INLO
16 ENBL
CMIP CMIP VPSI VPSI
1
2
3
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 11, 12
3, 4
5
6
7
CMIP
VPSI
Device Common (Input System Ground).
Positive Supply Voltage (Input System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal.
Loop Filter Capacitor.
Measurement and Controller Output.
Setpoint Input for Controller Mode or Feedback Input for Measurement Mode.
Device Common (Output System Ground).
Positive Supply Voltage (Output System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal.
Temperature Compensation Adjustment.
Temperature Sensor Output.
RF Input. Nominal input range: −60 dꢀm to 0 dꢀm (re: 50 Ω), ac-coupled.
RF Common for INHI. AC-coupled RF common.
Device Enable. Connect to VPSI for normal operation. Connect pin to ground for disable mode.
Internally Connected to CMIP (Solder to Ground).
CLPF
VOUT
VSET
CMOP
VPSO
TADJ
TEMP
INHI
8
9
10
13
14
15
16
INLO
ENꢀL
Paddle
Rev. A | Page 7 of 24
AD8318
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS = 5 V, TA = +25°C, −40°C, +85°C; CLPF = 220 pF; RTADJ = 500 ꢀ; unless otherwise noted. Colors: +25°C ꢀ Black; −40°C ꢀ Blue; +85°C ꢀ Red.
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.6
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.4
–0.8
–1.2
–1.6
–2.0
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
P
(dBm)
IN
IN
Figure 3. VOUT and Log Conformance vs. Input Amplitude at 900 MHz,
Typical Device
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz,
Typical Device, RTADJ = 51 Ω
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.6
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.4
–0.8
–1.2
–1.6
–2.0
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
P
(dBm)
IN
IN
Figure 4. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz,
Typical Device
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz,
Typical Device, RTADJ = 1000 Ω
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
4.5
1.6
3.6
1.2
2.7
0.8
1.8
0.4
0.9
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.9
–1.8
–2.7
–3.6
–4.5
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
P
(dBm)
P
(dBm)
IN
IN
Figure 5. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz,
Typical Device
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 8 GHz,
Typical Device
Rev. A | Page 8 of 24
AD8318
2.0
1.6
2.0
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.4
–0.8
–1.2
–1.6
–2.0
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
P
(dBm)
IN
IN
Figure 9. Distribution of Error over Temperature After Ambient
Normalization vs. Input Amplitude at 900 MHz for at Least 70 Devices
Figure 12. Distribution of Error at Temperature After Ambient
Normalization vs. Input Amplitude at 3.6 GHz for at Least 70 Devices,
RTADJ = 51 Ω
2.0
1.6
2.0
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.4
–0.8
–1.2
–1.6
–2.0
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
P
(dBm)
IN
IN
Figure 10. Distribution of Error at Temperature After Ambient
Figure 13. Distribution of Error at Temperature After Ambient
Normalization vs. Input Amplitude at 1900 MHz for at Least 70 Devices
Normalization vs. Input Amplitude at 5.8 GHz for at Least 70 Devices,
R
TADJ = 1000 Ω
2.0
1.6
4.5
3.6
1.2
2.7
0.8
1.9
0.4
0.9
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.9
–1.8
–2.7
–3.6
–4.5
–65
–55
–45
–35
–25
–15
–5
5
15
–65
–55
–45
–35
–25
–15
–5
5
P
(dBm)
P
(dBm)
IN
IN
Figure 11. Distribution of Error at Temperature After Ambient
Normalization vs. Input Amplitude at 2.2 GHz for at Least 70 Devices
Figure 14. Distribution of Error at Temperature After Ambient
Normalization vs. Input Amplitude at 8 GHz for at Least 70 Devices
Rev. A | Page 9 of 24
AD8318
j1
j2
j0.5
10k
1k
RF OFF
j0.2
0
0.2
8GHz
0.5
1
2
–60dBm
–40dBm
0.1GHz
–20dBm
5.8GHz
0.9GHz
1.9GHz
100
–j0.2
–10dBm
0dBm
1k
3.6GHz
2.2GHz
–j2
–j0.5
10
1
3
10
30
100
300
3k
10k
START FREQUENCY = 0.1GHz
STOP FREQUENCY = 8GHz
–j1
FREQUENCY (kHz)
Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI,
Figure 18. Noise Spectral Density of Output; CLPF = Open
Z
O = 50 Ω
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
1k
DECREASING V
INCREASING V
ENBL
ENBL
100
1.4
1.5
1.6
1.7
1.8
10
1
3
10
30
100
300
1k
3k
10k
V
(V)
ENBL
FREQUENCY (kHz)
Figure 19. Noise Spectral Density of Output Buffer (from CLPF to VOUT);
LPF = 0.1 μF
Figure 16. Supply Current vs. Enable Voltage
C
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.6
VOUT
1.2
0.8
200mV/VERTICAL
DIVISION
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
PULSED RF INPUT 0.1GHz,
–10dBm
GND
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
IN
20ns PER HORIZONTAL DIVISION
Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz
When VP Varies by 10%, Multiple Devices
Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, –10 dBm;
CLPF = Open
Rev. A | Page 10 of 24
AD8318
THEORY OF OPERATION
CMIP, the input system common pin, provides a quality low
The AD8318 is a 9-stage demodulating logarithmic amplifier that
provides RF measurement and power amplifier control functions.
The design of the AD8318 is similar to the AD8313 logarithmic
detector/controller. However, the AD8318 input frequency range
extends to 8 GHz with 60 dB dynamic range. Other improvements
include: reduced intercept variability vs. temperature, increased
dynamic range at higher frequencies, low noise measurement and
controller output (VOUT), adjustable low-pass corner frequency
(CLPF), temperature sensor output (TEMP), negative transfer
function slope for higher accuracy, and 10 ns response time for RF
burst detection capability. A block diagram is shown in Figure 21.
impedance connection to the printed circuit board (PCB)
ground via four package pins. Ground the package paddle,
which is internally connected to the CMIP pin, to the PCB to
reduce thermal impedance from the die to the PCB.
The logarithmic function is approximated in a piecewise
fashion by nine cascaded gain stages. For a more complete
explanation of the logarithm approximation, refer to the
AD8307 data sheet, available at www.analog.com. The cells have
a nominal voltage gain of 8.7 dB each and a 3 dB bandwidth of
10.5 GHz.
VPSI
ENBL
TADJ
VPSO
Using precision biasing, the gain is stabilized over temperature
and supply variations. Since the cascaded gain stages are
dc-coupled, the overall dc gain is high. An offset compensation
loop is included to correct for offsets within the cascaded cells.
At the output of each of the gain stages, a square-law detector
cell rectifies the signal. The RF signal voltages are converted to a
fluctuating differential current with an average value that
increases with signal level. Along with the nine gain stages and
detector cells, an additional detector is included at the input of
the AD8318, altogether providing a 60 dB dynamic range. After
the detector currents are summed and filtered, the function
TEMP
SENSOR
GAIN
BIAS
TEMP
SLOPE
VSET
I
I
V
V
VOUT
CLPF
DET
DET
DET
DET
INHI
INLO
CMIP
CMOP
Figure 21. Block Diagram
ID × log10(VIN/VINTERCEPT
)
A fully differential design, using a proprietary high speed SiGe
process, extends high frequency performance. Input INHI receives
the signal with a low frequency impedance of nominally 1200 Ω in
parallel with 0.7 pF. The maximum input with 1 dB log confor-
mance error is typically 0 dBm (re: 50 Ω). The noise spectral density
referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage
of 118 μV rms in a 10.5 GHz bandwidth, or a noise power of
−66 dBm (re: 50 Ω). This noise spectral density sets the lower limit
of the dynamic range. However, the low end accuracy of the AD8318
is enhanced by specially shaping the demodulating transfer charac-
teristic to partially compensate for errors due to internal noise.
is formed at the summing node,
where:
ID is the internally set detector current.
IN is the input signal voltage.
INTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage would be 0 V if capable of going to 0 V).
V
V
Rev. A | Page 11 of 24
AD8318
VPSI
40kΩ
USING THE AD8318
BASIC CONNECTIONS
DISCHARGE
ENBL
2
× V
BE
200Ω
The AD8318 is specified for operation up to 8 GHz. As a result, low
impedance supply pins with adequate isolation between functions
are essential. In the AD8318, VPSI and VPSO, the two positive
supply pins, must be connected to the same positive potential. The
VPSI pin biases the input circuitry, while VPSO biases the low noise
output driver for VOUT. Separate commons are also included in the
device. CMOP is used as the common for the output drivers. Pins
CMIP and CMOP should be connected to a low impedance ground
plane.
40kΩ
2
× V
BE
ENABLE
CMIP
Figure 23. ENBL Interface
Δ: 2.07V
@: 2.07V
A power supply voltage of between 4.5 V and 5.5 V should be
applied to VPSO and VPSI. In addition, 100 pF and 0.1 μF power
supply decoupling capacitors connect close to each power supply
pin. The two adjacent VPSI pins can share a pair of decoupling
capacitors due to their proximity.
1
V
S
499Ω
(SEE TEXT)
C5
0.1μF
CH1 500mV
M400ns
A CH1
920mV
C6
100pF
T
425.200ns
12
11
10
9
Figure 24. ENBL Response Time; VPOS = 5.0 V;
Input AC-Coupling Caps = 18 pF; CLPF = Open
CMIP CMIP TADJ VPSO
TEMP
OUT
13 TEMP
CMOP
VSET
VOUT
CLPF
8
7
6
5
C1
1nF
RF
INPUT
14 INHI
R1
52.3Ω
C2
1nF
INPUT SIGNAL COUPLING
AD8318
15 INLO
16 ENBL
VOUT
(SEE TEXT)
The RF input to the AD8318 (INHI) is single-ended and must
be ac-coupled. INLO (input common) should be ac-coupled to
ground (see Figure 22). Suggested coupling capacitors are 1 nF
ceramic 0402 style capacitors for input frequencies of 1 MHz to
8 GHz. The coupling capacitors should be mounted close to the
INHI and INLO pins. These capacitor values can be increased
to lower the input stage high-pass cutoff frequency. The high-
pass corner is set by the input coupling capacitors and the
internal 10 pF capacitor. The dc voltage on INHI and INLO is
approximately one diode voltage drop below the voltage applied
to the VPSI pin.
CMIP CMIP VPSI VPSI
V
S
1
2
3
4
C7
100pF
C8
0.1μF
V
S
Figure 22. Basic Connections
The paddle of the AD8318 LFCSP package is internally connected to
CMIP. For optimum thermal and electrical performance, solder the
paddle to a low impedance ground plane.
The Smith chart in Figure 15 shows the AD8318 input
impedance vs. frequency. Table 4 lists the reflection coefficient
and impedance at select frequencies. For Figure 15 and Table 4,
the 52.3 ꢀ input termination resistor is removed. At dc, the
resistance is typically 2 kΩ. At frequencies up to 1 GHz, the
impedance is approximated as 1000 ꢀ||0.7 pF. The RF input
pins are coupled to a network as shown in the simplified
schematic in Figure 25.
ENABLE INTERFACE
To enable the AD8318, the ENBL pin must be pulled high. Taking
ENBL low puts the AD8318 in sleep mode, reducing current
consumption to 260 ꢁA at ambient. The voltage on ENBL must be
greater than 2 VBE (~1.7 V) to enable the device. When enabled, the
ENBL pin draws less than 1 ꢁA. When ENBL is pulled low, the pin
sources 15 ꢁA.
The enable interface has high input impedance. An internal 200 Ω
resistor is placed in series with the ENBL input for added protection.
Figure 23 depicts a simplified schematic of the enable interface. The
response time of the AD8318 ENBL interface is shown in Figure 24.
Rev. A | Page 12 of 24
AD8318
VPSO
CLPF
VPSI
10pF
CURRENT
10pF
10Ω
VOUT
+
0.2V
–
FIRST
GAIN
150Ω
200Ω
20kΩ
INHI
20kΩ
STAGE
2kΩ
A = 8.6dB
CMOP
INLO
Figure 26. Output Interface
Gm
STAGE
OFFSET
COMP
SETPOINT INTERFACE
The setpoint interface is shown in Figure 27. The VSET input
drives the high impedance (250 kΩ) input of an internal
operational amplifier. The VSET voltage appears across the
internal 3.13 kΩ resistor to generate ISET. When a portion of
Figure 25. Input Interface
While the input can be reactively matched, this is typically not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, see Figure 22) combines
with the relatively high input impedance to provide an adequate
broadband 50 Ω match.
VOUT is applied to VSET, the feedback loop forces
−ID × log10 (VIN/VINTERCEPT) = ISET
.
If
Table 4. Input Impedance for Select Frequency
S11
Frequency
MHz
Impedance Ω
(Series)
V
SET = VOUT/X,
Real
Imaginary
Then
100
450
900
1900
2200
3600
5300
5800
8000
0.918
0.905
0.834
0.605
0.524
0.070
−0.041
−0.183
−0.350
−0.595
−0.616
−0.601
927-j491
173-j430
61-j233
28-j117
28-j102
26-j49
20-j16
22-j16
22-j3
I
SET = VOUT/(X × 3.13 kΩ).
The result is
V
OUT = (−ID × 3.13 kꢀ × X) × log10(VIN/VINTERCEPT).
I
−0.369 −0.305
−0.326 −0.286
−0.390 −0.062
SET
VSET
The coupling time constant, 50 × CC/2, forms a high-pass corner
with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 = C2 =
CC. Using the typical value of 1 nF, this high-pass corner is
~3.2 MHz. In high frequency applications, fHP should be as large as
possible to minimize the coupling of unwanted low frequency
signals. Likewise, in low frequency applications, a simple RC
network forming a low-pass filter should be added. This should
generally be placed at the generator side of the coupling capacitors,
thereby lowering the required capacitance value for a given high-
pass corner frequency.
3.13kΩ
CMOP
Figure 27. VSET Interface
The slope is given by −ID × X × 3.13 kΩ = −500 mV × X. For
example, if a resistor divider to ground is used to generate a VSET
voltage of VOUT/2, then X = 2. The slope is set to −1 V/decade or
−50 mV/dB.
TEMPERATURE COMPENSATION OF OUTPUT
VOLTAGE
OUTPUT INTERFACE
The AD8318 functionality includes the capability to externally
trim the temperature drift. Attaching a ground-referenced
resistor to the TADJ pin alters an internal current, minimizing
intercept drift vs. temperature. As a result, the Resistor RTADJ can
be optimized for operation at different frequencies.
The logarithmic output interface is shown in Figure 26. The VOUT
pin is driven by a PNP output stage. An internal 10 ꢀ resistor is
placed in series with the emitter follower output and the VOUT pin.
The rise time of the output is limited mainly by the slew on CLPF.
The fall time is an RC limited slew provided by the load capacitance
and the pull-down resistance at VOUT. There is an internal pull-
down resistor of 350 ꢀ. Any resistive load at VOUT is placed in
parallel with the internal pull-down resistor and provides additional
discharge current.
I
COMP
2V
V
INTERNAL
~0.4V
2kΩ
TADJ
Figure 28. TADJ Interface
Rev. A | Page 13 of 24
AD8318
RTADJ, nominally 500 Ω for optimal temperature compensation at
2.2 GHz input frequency, is connected between the TADJ pin and
ground (see Figure 22). The value of this resistor partially deter-
mines the magnitude of an analog correction coefficient that is
employed to reduce intercept drift.
MEASUREMENT MODE
When the VOUT voltage, or a portion of the VOUT voltage, is fed
back to VSET, the device operates in measurement mode. As
shown in Figure 30, the AD8318 has an offset voltage, a
negative slope, and a VOUT measurement intercept greater than
its input signal range.
Table 5 lists recommended resistors for various frequencies. These
resistors provide the best overall temperature drift based on
measurements of a diverse population of devices.
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.0
1.5
1.0
0.5
0
V
25°C
OUT
ERROR 25°C
The relationship between output temperature drift and frequency is
nonlinear and is not easily modeled. Experimentation is required to
choose the correct RTADJ resistor at frequencies not listed in Table 5.
Table 5. Recommended RTADJ Resistors
Frequency
900 MHz
1.9 MHz
2.2 GHz
3.6 GHz
5.8 GHz
8 GHz
Recommended RTADJ
–0.5
–1.0
–1.5
RANGE OF
500 Ω
500 Ω
500 Ω
51 Ω
1 kΩ
500 Ω
CALCULATION
OF SLOPE AND
INTERCEPT
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15
INTERCEPT
P
(dBm)
IN
Figure 30. Typical Output Voltage vs. Input Signal
TEMPERATURE SENSOR
The output voltage vs. input signal voltage of the AD8318 is
linear-in-dB over a multidecade range. The equation for this
function is
The AD8318 internally generates a voltage that is proportional to
absolute-temperature (VPTAT). The VPTAT voltage is multiplied by a
factor of 5, resulting in a 2 mV/°C output at the TEMP pin. The
output voltage at 27°C is typically 600 mV. An emitter follower
drives the TEMP pin, as shown in Figure 29.
V
OUT = X × VSLOPE/DEC × log10(VIN/VINTERCEPT
)
(1)
(2)
= X × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT
)
where:
VPSI
X is the feedback factor in VSET = VOUT/X.
INTERNAL
V
V
V
INTERCEPT is expressed in Vrms
SLOPE/DEC is nominally −500 mV/decade or −25 mV/dB.
INTERCEPT, expressed in dBV, is the x-axis intercept of the linear-
.
TEMP
4kΩ
in-dB transfer function shown in Figure 30.
1kΩ
CMIP
V
INTERCEPT is 7 dBV (20 dBm, re: 50 Ω or 2.239 Vrms) for a
sinusoidal input signal.
Figure 29. Temp Sensor Interface
The slope of the transfer function can be increased to
accommodate various converter mV per dB (LSB per dB)
requirements. However, increasing the slope can reduce the
dynamic range. This is due to the limitation of the minimum
and maximum output voltages, determined by the chosen
scaling factor X.
The internal pull-down resistance is 5 kꢀ. The temperature sensor
has a slope of 2 mV/°C.
The temperature sensor output varies with output current due to
increased die temperature. Output loads less than 1 kꢀ draw enough
current from the output stage causing this increase to occur. An
output current of 10 mA results in the voltage on the temperature
sensor to increase by 1.5°C, or ~3 mV.
The minimum value for VOUT is X × VOFFSET. The offset voltage,
VOFFSET, is equal to 0.5 V and is internally added to the detector
output signal.
Best precision from the temperature sensor is obtained when the
supply current to AD8318 remains fairly constant, that is, no heavy
load drive.
V
OUT(MIN) = (X × VOFFSET)
Rev. A | Page 14 of 24
AD8318
DEVICE CALIBRATION AND ERROR CALCULATION
The maximum output voltage is 2.1 V × X, and cannot exceed
400 mV below the positive supply.
The measured transfer function of the AD8318 at 2.2 GHz is
shown in Figure 31. The figure shows plots of both output
voltage vs. input power and calculated log conformance error
vs. input power.
V
V
OUT(MAX) = (2.1 V × X) when X < (VPOS − 400 mV)/(2.1 V)
OUT(MAX) = (VPOS − 400 mV) when X ≥ (VPOS − 400 mV)/(2.1 V)
When X = 1, the typical output voltage swing is 0.5 V to 2.1 V. The
output voltage swing is modeled using the equations above and
restricted by the following equation:
As the input power varies from −65 dBm to 0 dBm, the output
voltage varies from 2 V to about 0.5 V.
V
V
V
+25°C
–40°C
+85°C
OUT
OUT
OUT
V
OUT(MIN) < VOUT < VOUT(MAX)
VOUT
IDEAL
SLOPE = (VOUT – VOUT )/(PIN – PIN )
INTERCEPT = PIN – (VOUT /SLOPE)
ERROR (dB) = (VOUT
= SLOPE
×
(P – INTERCEPT)
IN
1
2
1
2
ERROR +25°C
ERROR –40°C
ERROR +85°C
1
1
When X = 4 and VPOS = 5 V
(X × VOFFSET) < VOUT < (VPOS − 400 mV)
(4 × 0.5 V) < VOUT < (2.1 V × 4)
2 V < VOUT < 4.6 V
×
VOUT
)/SLOPE
IDEAL
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
2.0
1.5
1.0
0.5
0
VOUT
2
For X = 4, Slope = −100 mV/dB; VOUT can swing 2.6 V, and the
usable dynamic range is reduced to 26 dB from 0 dBm to –26 dBm.
–0.5
–1.0
–1.5
–2.0
The slope is very stable vs. process and temperature variation. When
base-10 logarithms are used, VSLOPE/DECADE represents the output
voltage per decade of input power. One decade is equal to 20 dB;
VOUT
1
VSLOPE/DECADE/20 = VSLOPE/dB represents the output voltage slope in
–65 –60 –55
PIN
–45 –40 –35 –30 –25 –20 –15
PIN
1
–5
0
5
volts/dB.
INTERCEPT
2
P
(dBm)
IN
As noted in the previous equations, the VOUT voltage has a negative
slope. This is the correct slope polarity to control the gain of many
power amplifiers and other VGAs in a negative feedback
configuration. Since both the slope and intercept vary slightly with
frequency, refer to Table 1 for application-specific values for slope
and intercept.
Figure 31. Transfer Function at 2.2 GHz
Because slope and intercept vary from device to device, board-
level calibration is performed to achieve high accuracy.
The equation can be rewritten for output voltage, from the
Measurement Mode section, using an intercept expressed
in dBm
Although demodulating log amps respond to input signal voltage,
not input signal power, it is customary to discuss the amplitude of
high frequency signals in terms of power. In this case, the charac-
teristic impedance of the system, Z0, must be known to convert
voltages to corresponding power levels. Beginning with the
definitions of dBm and dBV,
V
OUT = Slope × (PIN – Intercept)
(8)
In general, the calibration is performed by applying two known
signal levels to the AD8318 input and measuring the corre-
sponding output voltages. The calibration points are generally
chosen to be within the linear-in-dB operating range of the
device (see Figure 31). Calculation of slope and intercept is
done using the equations
P(dBm) = 10 × log10(Vrms2/(Z0 × 1 mW))
(3)
(4)
V(dBV) = 20 × log10(Vrms/1 Vrms
)
When Equation 3 is expanded
Slope = (VOUT1 − VOUT2)/(PIN1 − PIN2
Intercept = PIN1 − VOUT1/Slope
)
(9)
P(dBm) = 20 × log10(Vrms) − 10 × log10(Z0 × 1 mW)
(5)
(10)
and given Equation 4, Equation 5 can be rewritten as
Once slope and intercept are calculated, an equation can be
written to allow calculation of an (unknown) input power based
on the output voltage of the detector.
P(dBm) = V(dBV) − 10 × log10(Z0 × 1 mW)
(6)
For example, PINTERCEPT for a sinusoidal input signal, expressed in
terms of dBm (decibels referred to 1 mW), in a 50 ꢀ system is
PIN (unknown) = VOUT (measured)/Slope + Intercept
(11)
P
INTERCEPT(dBm) = VINTERCEPT (dBV)
− 10 × log10(Z0 × 1 mW) =
(7)
+7 dBV − 10 × log10(50 × 10-3) = +20 dBm
For further information on the intercept variation dependence upon
waveform, refer to the AD8313 and AD8307 data sheets.
Rev. A | Page 15 of 24
AD8318
Using the equation for the ideal output voltage (7) as a reference, the
log conformance error of the measured data can be calculated
Figure 33 shows how calibration points can be adjusted to
increase dynamic range, but at the expense of linearity. In this
case, the calibration points for slope and intercept are set at
−4 dBm and −60 dBm. These points are at the end of the linear
range of the device.
Error(dB) = (VOUT(MEASURED) − VOUT(IDEAL))/Slope
(12)
Figure 31 includes a plot of the error at 25°C, the temperature at
which the log amp is calibrated. Note that the error is not zero. This
is because the log amp does not perfectly follow the ideal VOUT vs. PIN
equation, even within its operating region. The error at the calibra-
tion points (−12 dBm and −52 dBm, in this case) is, however, equal
to zero by definition.
Once again, at 25°C, an error of 0 dB is seen at the calibration
points. Note also that the range over which the AD8318
maintains an error of < 1 dB is extended to 60 dB at 25°C and
58 dB over temperature. The disadvantage of this approach is
that linearity suffers, especially at the top end of the input range.
Figure 31 includes error plots for the output voltage at −40°C and
+85°C. These error plots are calculated using the slope and intercept
at 25°C. This method is consistent with a mass-production environ-
ment where calibration at temperature is not practical.
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
V
V
V
+25
°
C
°
C
ERROR +25
ERROR –40
ERROR +85
°
C
OUT
OUT
OUT
–40
°
°
C
2.0
+85
C
°
C
1.5
1.0
SELECTING CALIBRATION POINTS TO IMPROVE
ACCURACY OVER A REDUCED RANGE
0.5
0
In some applications, very high accuracy is required at just one
power level or over a reduced input range. For example, in a wireless
transmitter, the accuracy of the high power amplifier (HPA) is most
critical at, or close to, full power.
–0.5
–1.0
–1.5
–2.0
–2.5
58dB DYNAMIC RANGE (±1dB ERROR)
Figure 32 shows the same measured data as Figure 31. Note that
accuracy is very high from −10 dBm to −30 dBm. Below −30 dBm,
the error increases to about −1 dB. This is because the calibration
points have changed to −14 dBm and −26 dBm.
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
(dBm)
0
5
P
IN
Figure 33. Dynamic Range Extension by Choosing Calibration Points
Close to the End of the Linear Range
V
V
V
+25°C
–40°C
+85°C
ERROR +25°C
ERROR –40°C
ERROR +85°C
OUT
OUT
OUT
Another way of presenting the error function of a log amp
detector is shown in Figure 34. In this case, the dB error at hot
and cold temperatures is calculated with respect to the output
voltage at ambient. This is a key difference in comparison to the
plots in Figure 32 and Figure 33. Previously, all errors were
calculated with respect to the ideal transfer function at ambient.
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
2.0
1.5
1.0
0.5
0
When this alternative technique is used, the error at ambient
becomes, by definition, equal to 0 (see Figure 34). This is valid
if the device transfer function perfectly follows the ideal
VOUT = Slope × (Pin - Intercept) equation. However, because a
log amp in practice never perfectly follows this equation
(especially outside of its linear operating range), this plot tends
to artificially improve linearity and extend the dynamic range.
This plot is a useful tool for estimating temperature drift at a
particular power level with respect to the (nonideal) output
voltage at ambient. However, to achieve this level of accuracy in
an end application requires calibration at multiple points in the
operating range of the device.
V
V
OUT2
–0.5
–1.0
–1.5
–2.0
–2.5
OUT1
0.6
0.4
0.2
–65 –60 –55 –50 –45 –40 –35 –30
(dBm)
–20
–10 –5
0
5
P
IN
P
P
IN1
IN2
Figure 32. Output Voltage and Error vs. PIN with 2-Point Calibration at
−10 dBm and −30 dBm
Calibration points are chosen to suit the application at hand. In
general, the calibration points are never chosen in the nonlinear
portion of the transfer function of the log amp (above −5 dBm or
below −60 dBm, in this case).
Rev. A | Page 16 of 24
AD8318
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
reduced temperature range, higher measurement accuracy is
achievable for all frequencies.
V
V
V
+25
°
C
°
C
ERROR +25 C wrt V
ERROR –40 C wrt V
ERROR +85°C wrt V
°
°
OUT
OUT
OUT
OUT
OUT
OUT
–40
°
2.0
+85
C
1.5
V
V
+25°C
0°C
V
V
–40°C
+70°C
V
+85°C
OUT
OUT
OUT
OUT
ERROR +25°C
ERROR 0°C
OUT
1.0
ERROR –10°C
ERROR +70°C
ERROR –20°C
–10°C
V
V
–20°C
OUT
ERROR –40°C
OUT
ERROR +85°C
0.5
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
0
2.0
–0.5
–1.0
–1.5
–2.0
–2.5
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
(dBm)
0
5
P
IN
Figure 34. Error vs. Temperature with Respect to Output Voltage at 25°C
(Does Not Take Transfer Function Nonlinearities at 25°C into Account)
VARIATION IN TEMPERATURE DRIFT FROM DEVICE
TO DEVICE
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
(dBm)
0
5
P
IN
Figure 35 shows a plot of output voltage and error for multiple
AD8318 devices measured at 5.8 GHz. The concentration of black
error plots represents the performance of the population at 25°C
(slope and intercept are calculated for each device). The red and blue
curves indicate the measured behavior of a population of devices
over temperature. This suggests a range on the drift (from device to
device) of 1.2 dB.
Figure 36. Typical Drift at 5.8 GHz for Various Temperatures
SETTING THE OUTPUT SLOPE IN MEASUREMENT
MODE
To operate in measurement mode, VOUT is connected to VSET.
This yields the typical logarithmic slope of −25 mV/dB. The
output swing corresponding to the specified input range is then
approximately 0.5 V to 2.1 V. The slope and output swing can be
increased by placing a resistor divider between VOUT and
VSET (that is, one resistor from VOUT to VSET and one
resistor from VSET to common).
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.6
1.2
0.8
As an example, if two equal resistors, such as 10 kꢀ/10 kꢀ, are
used, the slope doubles to approximately −50 mV/dB. The input
impedance of VSET is approximately 500 kꢀ. Slope setting
resistors should be kept below ~50 kꢀ to prevent this input
impedance from affecting the resulting slope. When increasing
the slope, the new output voltage range cannot exceed the
output voltage swing capability of the output stage. Refer to the
Measurement Mode section for further details.
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
–65
–55
–45
–35
–25
–15
–5
5
15
P
(dBm)
IN
AD8318
VOUT
–50mV/dB
Figure 35. Output Voltage and Error vs. Temperature (+25°C, −40°C, and +85°C)
of a Population of Devices Measured at 5.8 GHz
10kΩ
10kΩ
VSET
TEMPERATURE DRIFT AT DIFFERENT TEMPERATURES
Figure 36 shows the log slope and error over temperature for a
5.8 GHz input signal. Error due to drift over temperature consis-
tently remains within 0.5 dB, and only begins to exceed this limit
when the ambient temperature drops below −20°C. When using a
Figure 37. Increasing the Slope
Rev. A | Page 17 of 24
AD8318
AD8318
OUTPUT
+5V
PULSED RF
INPUT
+5V
1nF
1nF
VPOS
40Ω
50Ω
50Ω
INHI
VOUT
52.3Ω
AD8318
ADCMP563
INLO
VSET
GND
100Ω
100Ω
50Ω 50Ω
COMPARATOR
OUTPUT
–5.2V
V
= 1.8V–1.2V
REF
–5.2V
Figure 38. AD8318 Operating with the High Speed ADCMP563 Comparator
Figure 39 shows the response of the AD8318 and the
comparator for a 500 MHz pulsed sine wave of varying
amplitudes. The output level of the AD8318 is the signal
strength of the input signal. For applications where these RF
bursts are very small, the output level does not change by a large
amount. Using a comparator is beneficial in this case because it
turns the output of the log amp into a limiter-like signal. While
this configuration does result in the loss of received signal
power level, it does allow for presence-only detection of low
power RF bursts.
RESPONSE TIME CAPABILITY
The AD8318 has a 10 ns rise/fall time capability (10% to 90%) for
input power switching between the noise floor and 0 dBm. This
capability enables RF burst measurements at repetition rates beyond
45 MHz. In most measurement applications, the AD8318 has an
external capacitor connected to CLPF to provide additional filtering
for VOUT. However, using the CLPF capacitor slows the response
time as does stray capacitance on VOUT. For an application
requiring maximum RF burst detection capability, the CLPF pin is
left unconnected. In this case, the integration function is provided by
the 1.5 pF on-chip capacitor.
OUTPUT FILTERING
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.
There is a 10 ꢀ internal resistor in series with the output driver.
Because of this resistor, it is necessary to add an external 40 ꢀ back-
terminating resistor in series with the output when driving a 50 ꢀ
load. Place the back-terminating resistor close to the VOUT pin. The
AD8318 has the drive capability to drive a 50 ꢀ load at the end of a
coaxial cable or transmission line when back terminated (see
Figure 38).
To reduce the nominal output video bandwidth of 45 MHz,
connect a ground-referenced capacitor (CFLT) to the CLPF pin,
as shown in Figure 40. Generally, this is done to reduce output
ripple (at twice the input frequency for a symmetric input
waveform, such as sinusoidal signals).
The circuit diagram in Figure 38 shows the AD8318 used with a
high speed comparator circuit. The 40 ꢀ series resistor at the output
of the AD8318 combines with an internal 10 ꢀ to properly match to
the 50 ꢀ input of the comparator.
AD8318
I
LOG
VOUT
CLPF
+4
PULSED RF
INPUT
–50dB
–30dB
–20dB
–10dB
3.13kΩ
1.5pF
C
FLT
Figure 40. Lowering the Postdemodulation Bandwidth
AD8318
OUTPUT
CFLT is selected using the following equation:
COMPARATOR
OUTPUT
1
(13)
− 1.5 pF
CFLT
=
(
π × 3.13 kΩ ×VideoBandwidth
)
Set the video bandwidth to a frequency equal to about one-
tenth the minimum input frequency. This ensures that the
0
100
200
300
400
500
600
700
800
TIME (ns)
output ripple of the demodulated log output, which is at twice
the input frequency, is well filtered.
Figure 39. Pulse Response of AD8318 and Comparator for RF Pulses
of Varying Amplitudes
Rev. A | Page 18 of 24
AD8318
In many log amp applications, it may be necessary to lower the
corner frequency of the postdemodulation filtering to achieve low
output ripple while maintaining a rapid response time to changes in
signal level. For an example of a 4-pole active filter, see the AD8307
data sheet.
The basic connections for operating the AD8318 as an analog
controller with the AD8367 are shown in Figure 42. The
AD8367 is a low frequency to 500 MHz VGA with 45 dB of
dynamic range. This configuration is very similar to the one
shown in Figure 41. For applications working at high input
frequencies, such as cellular bands or WLAN, or those
requiring large gain control ranges, the AD8318 can control the
ADL5330 10 MHz to 3 GHz RF VGA. For further details and an
application schematic, refer to the ADL5330 data sheet.
CONTROLLER MODE
The AD8318 provides a controller mode feature at the VOUT pin.
Using VSET for the setpoint voltage, it is possible for the AD8318 to
control subsystems, such as power amplifiers (PAs), variable gain
amplifiers (VGAs), or variable voltage attenuators (VVAs) that have
output power that increases monotonically with respect to their gain
control signal.
The voltage applied to the GAIN pin controls the gain of the
AD8367. This voltage, VGAIN, is scaled linear-in-dB with a slope
of 20 mV/dB and runs from 50 mV at −2.5 dB of gain, up to
1.0 V at +42.5 dB.
To operate in controller mode, the link between VSET and VOUT is
broken. A setpoint voltage is applied to the VSET input; VOUT is
connected to the gain control terminal of the VGA and the detector
RF input is connected to the output of the VGA (usually using a
directional coupler and some additional attenuation). Based on the
defined relationship between VOUT and the RF input signal when the
device is in measurement mode, the AD8318 adjusts the voltage on
VOUT (VOUT is now an error amplifier output) until the level at
The incoming RF signal to the AD8367 has a varying amplitude
level. Receiving and demodulating it with the lowest possible
error requires that the signal levels be optimized for the highest
signal-to-noise ratio (SNR) feeding into the analog-to-digital
converters (ADC). This is done by using an automatic gain
control (AGC) loop. In Figure 42, the voltage output of the
AD8318 modifies the gain of the AD8367 until the incoming
RF signal produces an output voltage that is equal to the
the RF input corresponds to the applied VSET
.
setpoint voltage VSET
.
When the AD8318 operates in controller mode, there is no defined
relationship between VSET and VOUT voltage; VOUT settles to a value
that results in the correct input signal level appearing at INHI/INLO.
+3V
RF INPUT SIGNAL
RF OUTPUT SIGNAL
VPOS GND
0.1μF
174Ω
AD8367
VGA
INPT
GAIN
VOUT
HPFL
In order for this output power control loop to be stable, a ground-
referenced capacitor is connected to the CLPF pin. This capacitor,
57.6Ω
C
HP
100pF
CFLT, integrates the error signal (in the form of a current) to set the
R2
261Ω
R
HP
100MHz
R1
1kΩ
loop bandwidth and ensure loop stability. For further details on
control loop dynamics, refer to the AD8315 data sheet.
100Ω
+5V
BANDPASS
FILTER
VOUT
VPOS
INHI
1nF
1nF
+V
SET
DAC
VSET
SETPOINT
VOLTAGE
AD8318
INLO
CLPF
VGA/VVA
GAIN
RFIN
GND
C
FLT
100pF
DIRECTIONAL
COUPLER
Figure 42. AD8318 Operating in Controller Mode to Provide Automatic Gain
Control Functionality in Combination with the AD8367
CONTROL
VOLTAGE
ATTENUATOR
1nF
1nF
VOUT
The AGC loop is capable of controlling signals over ~45 dB
dynamic range. The output of the AD8367 is designed to drive
loads ≥ 200 ꢀ. As a result, it is not necessary to use the 53.6 ꢀ
resistor at the input of the AD8318; the nominal input imped-
ance of 2 kꢀ is sufficient.
INHI
AD8318
52.3Ω
DAC
VSET
INLO
CLPF
C
FLT
If the AD8367 output drives a 50 ꢀ load, such as an oscilloscope
or spectrum analyzer, use a simple resistive divider network.
The divider used in Figure 42 has an insertion loss of 11.5 dB.
Figure 43 shows the transfer function of output power vs. VSET
voltage for a 100 MHz sine wave at −40 dBm into the AD8367.
Figure 41. AD8318 Controller Mode
Decreasing VSET, which corresponds to demanding a higher signal
from the VGA, tends to increase VOUT. The gain control voltage of
the VGA must have a positive sense. A positive control voltage to the
VGA increases the gain of the device.
Rev. A | Page 19 of 24
AD8318
0
1.2
10
0
–5
1.0
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
0.8
MAXIMUM INPUT LEVEL
–10
–20
–30
–40
–50
–60
–70
–80
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
MINIMUM INPUT LEVEL
–60
0.6
0.8
1.0
1.2
V
1.4
(V)
1.6
1.8
2.0
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.2
1.3
1.4
1.5
SET
V
(V)
SET
Figure 45. Setpoint Voltage vs. Input Power. Optimal signal levels must be
used to achieve the full 45 dB dynamic range capabilities of the AD8367.
Figure 43. AD8367 Output Power vs. AD8318 Setpoint Voltage
For the AGC loop to remain locked, the AD8318 must track the
envelope of the VGA output signal and provide the necessary voltage
levels to the AD8367 gain control input. Figure 44 shows an
oscilloscope screen image of the AGC loop depicted in Figure 42.
A 50 MHz sine wave with 50% AM modulation is applied to the
AD8367. The output signal from the VGA is a constant envelope
sine wave with an amplitude corresponding to a setpoint voltage at
the AD8318 of 1.0 V.
In some cases, if VGAIN is >1.0 V it can take an unusually long
time for the AGC loop to recover; that is, the output of the
AD8318 remains at an abnormally high value and the gain is set
to its maximum level. A voltage divider is placed between the
output of the AD8318 and the AD8367 GAIN pin to ensure that
VGAIN does not exceed 1.0 V.
In Figure 42, CHP and RHP are configured to reduce oscillation
and distortion due to harmonics at higher gain settings. Some
additional filtering is recommended between the output of the
AD8367 and the input of the AD8318. This helps to decrease
the output noise of the AD8367, which can reduce the dynamic
range of the loop at higher gain settings (smaller VSET).
AM MODULATED INPUT
1
AD8318 V
OUT
Response time and the amount of signal integration are
controlled by CFLT. This functionality is analogous to the
feedback capacitor around an integrating amplifier. Though it is
possible to use large capacitors for CFLT, in most applications,
values under 1 nF provide sufficient filtering.
2
3
AD8367 OUTPUT
Calibration in controller mode is similar to the method used in
measurement mode. Do a simple two-point calibration by
applying two known VSET voltages or DAC codes and measuring
the output power from the VGA. Slope and intercept are
calculated with the following equations:
CH1 50.0mV
CH3 20.0mV
CH2 200mV
M4.00ms
A
CH2
64.0mV
Figure 44. Oscilloscope Screen Image Showing an AM Modulated Input Signal to
the AD8367. The AD8318 tracks the envelope of this input signal and applies the
appropriate voltage to ensure a constant output from the AD8367.
Slope = (VSET1 − VSET2)/(POUT1 − POUT2
Intercept = POUT1 − VSET1/Slope
)
(14)
(15)
(16)
The 45 dB control range is constant for the range of VSET voltages.
The input power levels to the AD8367 must be optimized to achieve
this range. In Figure 45, the minimum and maximum input power
levels are shown vs. setpoint voltage.
V
SET = Slope × (Px − Intercept)
For more information on AGC applications, refer to the
AD8367 data sheet or ADL5330 data sheet.
Rev. A | Page 20 of 24
AD8318
R AND S SMT06
VIDEO RF OUT
TEKTRONIX
TDS51504
CHARACTERIZATION SETUP AND METHODS
OUT
–7dBm
5V
CH1* CH3* TRIGGER
The general hardware configuration used for the AD8318
3dB
SPLITTER
*50Ω
TERMINATION
VPOS
1nF
characterization is shown in Figure 46. The primary setup used for
characterization is measurement mode. The characterization board
is similar to the customer evaluation board with the exception that
the RF input has a Rosenberger SMA connector and R10 has
changed to a 1 kꢀ resistor to remove cable capacitance from the
bench characterization setup. Slope and intercept are calculated in
this data sheet and in the production environment using linear
regression from −50 dBm to −10 dBm. The slope and intercept
generate an ideal line. Log conformance error is the difference from
the ideal line and the measured output voltage for a given tempera-
ture in dB. For additional information on the error calculation, refer
to the Device Calibration and Error Calculation section.
40Ω
INHI
VOUT
52.3Ω
AD8318
INLO
VSET
1nF
GND
Figure 46. Pulse Response Measurement Test Setup
To measure noise spectral density, the 0 ꢀ resistor in series with
the VOUT pin is replaced with a 1 ꢁF dc blocking capacitor.
The capacitor is used because the Rohde & Schwarz FSEA
spectrum analyzer cannot handle dc voltages at its RF input.
The CLPF pin is left open for data collected for Figure 18. For
Figure 19, a 1 ꢁF capacitor is placed between CLPF and ground.
The large capacitor filters the noise from the detector stages of
the log amp. Noise spectral density measurements are taken
using the FSEA and the SMT06 signal generator. The signal
generator frequency is set to 2.2 GHz. The spectrum analyzer
has a span of 10 Hz, resolution bandwidth of 50 Hz, video
bandwidth of 50 Hz, and averages the signal 100 times. Data is
adjusted to account for the dc blocking capacitor impedance on
the output at lower frequencies.
The hardware configuration for pulse response measurement
replaces the 0 ꢀ series resistor at the VOUT pin with a 40 ꢀ resistor;
the CLPF pin remains open. Pulse response time is measured using a
Tektronix TDS51504 Digital Phosphor Oscilloscope. Both channels
on the scope are configured for 50 ꢀ termination. The 10 ꢀ internal
series resistance at VOUT, combined with the 40 ꢀ resistor,
attenuates the output voltage level by two. RF input frequency is set
to 100 MHz with −10 dBm at the input of the device. The RF burst is
generated using a Rohde & Schwarz SMT06 with the pulse option
with a period of 1.5 μs, a width of 0.1 ꢁs, and a pulse delay of 0.04 ꢁs.
The output response is triggered using the video output from the
SMT06. Refer to Figure 46 for an overview of the test setup.
Rev. A | Page 21 of 24
AD8318
EVALUATION BOARD
Table 6. Evaluation Board (Rev. A) Bill of Materials
Component
Function
Default Conditions
Not Applicable
VP, GND
Supply and Ground Connections
SW1, R3
Device Enable:
SW1 = A
When in Position A, the ENꢀL pin is connected to VP and the AD8318 is in
operating mode. In Position ꢀ, the ENꢀL pin is grounded through R3, putting
the device in power-down mode. The ENꢀL pin may be exercised by a pulse
generator connected to ENꢀL SMA and SW1 in Position ꢀ.
R3 = 10 ΚΩ (Size 0603)
R1, C1, C2
Input Interface:
R1 = 52.3 Ω (Size 0402)
C1 = 1 nF (Size 0402)
C2 = 1 nF (Size 0402)
The 52.3 Ω resistor (R1) combines with the AD8318 internal input impedance
to give a broadband input impedance of 50 Ω. C1 and C2 are dc-blocking
capacitors. A reactive impedance match can be implemented by replacing R1
with an inductor and C1 and C2 with appropriately-valued capacitors.
R2
R4
Temperature Sensor Interface:
The temperature sensor output voltage is available at the SMA labeled TEMP,
via the current limiting resistor, R2.
R2 = 1 ΚΩ (Size 0402)
R4 = 499 Ω (Size 0603)
Temperature Compensation Interface:
The internal temperature compensation resistor is optimized for an input
signal of 2.2 GHz when R4 is 500 Ω. This circuit can be adjusted to optimize
performance for other input frequencies by changing the value of Resistor R4.
See the Temperature Compensation of Output Voltage section.
R7, R8, R9, R10
R7, R8, R9, R10
Output Interface—Measurement Mode:
R7 = 0 Ω = (Size 0402)
R8 = open (Size 0402)
R9 = open (Size 0402
R10= 0 Ω (Size 0402)
In measurement mode, a portion of the output voltage is fed back to the VSET
pin via R7. The magnitude of the slope at VOUT can be increased by reducing
the portion of VOUT that is fed back to VSET. R10 can be used as a back-
terminating resistor or as part of a single-pole low-pass filter.
Output Interface—Controller Mode:
R7 = open (Size 0402)
R8 = open (Size 0402)
R9 = 0 Ω (Size 0402)
R10 = 0 Ω (Size 0402)
In this mode, R7 must be open. In controller mode, the AD8318 can control the
gain of an external component. A setpoint voltage is applied to the VSET pin,
the value of which corresponds to the desired RF input signal level applied to
the AD8318 RF input. The magnitude of the control voltage is optionally
attenuated, via the voltage divider comprised of R8 and R9, or a capacitor can
be installed in R8 to form a low-pass filter along with R9. See the Controller
Mode section for more details.
C5, C6, C7, C8, R5, R6
Power Supply Decoupling:
C5 = 0.1 ꢁF (Size 0603)
C6 = 100 pF (Size 0402)
C7 = 100 pF (Size 0402)
C8 = 0.1 ꢁF (Size 0603)
R5 = 0 Ω (Size 0603)
The nominal supply decoupling consists of a 100 pF filter capacitor placed
physically close to the AD8318, a 0 Ω series resistor, and a 0.1 ꢁF capacitor
placed closer to the power supply input pin.
R6 = 0 Ω (Size 0603)
C9
Loop Filter Capacitor:
C9 = open (Size 0603)
The low-pass corner frequency of the circuit that drives the VOUT pin can be
lowered by placing a capacitor between CLPF and ground. Increasing this
capacitor increases the overall rise/fall time of the AD8318 for pulsed input
signals. See the Output Filtering section for more details.
Rev. A | Page 22 of 24
AD8318
V
POS
R4
499Ω
(SEE TEXT)
C5
0.1μF
R5
0Ω
C6
100pF
12
11
10
9
CMIP CMIP TADJ VPSO
R2
1kΩ
13 TEMP
CMOP
VSET
VOUT
CLPF
8
7
6
5
R8
TEMP
RFIN
OPEN
C1 1nF
C2 1nF
14 INHI
VSET
VOUT
R1
52.3Ω
R7
0Ω
R9
AD8318
OPEN
15 INLO
16 ENBL
R10
0Ω
CMIP CMIP VPSI VPSI
A
B
V
C9
OPEN
(SEE TEXT)
1
2
3
4
ENBL
POS
R3
10kΩ
SW1
C7
100pF
R6
0Ω
GND
VP
C8
0.1μF
V
POS
Figure 47. Evaluation Board Schematic
Figure 49. Component Side Silkscreen
Figure 48. Component Side Layout
Rev. A | Page 23 of 24
AD8318
OUTLINE DIMENSIONS
4.00
0.60 MAX
16
BSC SQ
PIN 1
INDICATOR
0.60 MAX
0.65 BSC
13
12
1
PIN 1
2.25
TOP
VIEW
INDICATOR
EXPOSED
3.75
BSC SQ
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.75
0.60
0.50
4
9
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option Ordering Quantity
AD8318ACPZ-REEL71 −40°C to +85°C
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
Evaluation ꢀoard
1500
64
AD8318ACPZ-WP1, 2
AD8318-EVAL
−40°C to +85°C
1 Z = Pb-free part.
2 WP = waffle pack.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04853-0-1/06(A)
Rev. A | Page 24 of 24
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