AD8326ARE-REEL [ADI]
High Output Power Programmable CATV Line Driver; 高输出功率可编程CATV线路驱动器
| 型号： | AD8326ARE-REEL |
| 厂家： | 
ADI |
| 描述： | High Output Power Programmable CATV Line Driver |
| 文件： | 总24页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Output Power
Programmable CATV Line Driver
a
AD8326
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Supports DOCSIS Standard for Reverse Path
Transmission
V
CC
(7 PINS)
BYP
Gain Programmable in 0.75 dB Steps over a 53.5 dB Range
Low Distortion at 65 dBmV Output
–62 dBc SFDR at 21 MHz
–58 dBc SFDR at 65 MHz
1 dB Compression of 25 dBm at 10 MHz
Output Noise Level
AD8326
V
V
V
V
IN+
OUT+
DIFF OR
SINGLE
INPUT
AMP
POWER
AMP
ATTENUATION
CORE
VERNIER
IN–
OUT–
Z
DIFF =
OUT
75⍀
8
DECODE
–45 dBmV in 160 kHz
Z
Z
(SINGLE) = 800⍀
(DIFF) = 1.6k⍀
IN
IN
8
POWER-DOWN
LOGIC
Maintains 75 ⍀ Output Impedance
Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
Single or Dual Supply Operation
DATA LATCH
8
SHIFT
REGISTER
APPLICATIONS
Gain-Programmable Line Driver
CATV Telephony Modems
TXEN
GND
DATEN DATA CLK
V
EE
(10 PINS)
SLEEP
CATV Terminal Devices
General-Purpose Digitally Controlled Variable Gain Block
–40
–45
–50
–55
–60
–65
–70
–75
–80
ARP(V = +12V)
S
ARE(V = ؎5V)
S
ARP(V = 69dBmV)
O
ARP(V = 67dBmV)
O
GENERAL D ESCRIP TIO N
The AD8326 is a high-output power, digitally controlled, vari-
able gain amplifier optimized for coaxial line driving applications
such as data and telephony cable modems that are designed to
the MCNS-DOCSIS upstream standard. An 8-bit serial word
determines the desired output gain over a 53.5 dB range result-
ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in
two models, each optimized to support the desired output power
and resulting performance.
ARE(V = 65dBmV)
O
ARE(V = 62dBmV)
O
5
15
25
35
45
55
65
FREQUENCY – MHz
The AD8326 comprises a digitally controlled variable attenuator
of 0 dB to –54 dB, that is preceded by a low noise, fixed-gain
buffer and is followed by a low distortion high-power amplifier.
The AD8326 accepts a differential or single-ended input signal.
The output is designed to drive a 75 Ω load, such as coaxial
cable, although the AD8326 is capable of driving other loads.
Figure 1. Worst Harmonic Distortion vs. Frequency
The differential output of the AD8326 is compliant with DOCSIS
paragraph 4.2.10.2 for “Spurious Emissions During Burst On/Off
Transients.” In addition, this device has a sleep mode function
that reduces the quiescent current to 4 mA.
When driving 67 dBm into a 75 Ω load, the AD8326ARP
provides a worst harmonic of only –59 dBc at 21 MHz and
–57 dBc at 42 MHz. When driving 65 dBmV into a 75 Ω load,
the AD8326ARE provides a worst harmonic of only –62 dBc at
21 MHz and –60 dBc at 42 MHz.
The AD8326 is packaged in a low-cost 28-lead TSSOP and a
28-lead P (power) SOIC. Both devices have an operational tem-
perature range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(T = 25؇C, V = 12 V, R = R = 75 ⍀, V = 259 mV p-p, V measured through a 1:1
A
S
L
IN
IN
OUT
transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.)
AD8326–SPECIFICATIONS
AD 8326ARP
P aram eter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Output = 67 dBmV, Max Gain
Max Gain, f = 10 MHz
Differential Input
259
16.6
1600
800
2
mV p-p
dB
Ω
Ω
pF
Input Resistance
Single-Ended Input
Input Capacitance
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
52.5
26.5
–27
53.5
27.5
–26
54.5
28.5
–25
dB
dB
dB
Gain Code = 71 Dec
Gain Code = 0 Dec
Minimum Gain
Gain Scaling Factor
Gain Linearity Error
0.7526
±0.2
dB/LSB
dB
f = 10 MHz, Code-to-Code
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
All Gain Codes
f = 65 MHz
f = 65 MHz
100
1.2
0
MHz
dB
dB
Bandwidth Peaking
Output Noise Spectral Density
Max Gain, f = 10 MHz
–28
dBmV in
160 kHz
dBmV in
160 kHz
dBmV in
160 kHz
dBm
Min Gain, f = 10 MHz
–45.5
–65
Transmit Disable Mode, f = 10 MHz
1 dB Compression Point
Max Gain, f = 10 MHz
26.5
Differential Output Impedance
Transmit Enable and Transmit Disable Mode
75 ± 20%
Ω
OVERALL PERFORMANCE
Worst Harmonic Distortion
f = 14 MHz, VOUT = 67 dBmV @ Max Gain
f = 21 MHz, VOUT = 67 dBmV @ Max Gain
f = 42 MHz, VOUT = 67 dBmV @ Max Gain
f = 65 MHz, VOUT = 67 dBmV @ Max Gain
16 QAM, VOUT = 67 dBmV
–59
–59
–57
–55
–56
dBc
dBc
dBc
dBc
dBc
Adjacent Channel Power
Output Settling
Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC
Due to Gain Change (TGS
)
Min to Max Gain
60
ns
Due to Input Step Change
Signal Isolation
Max Gain, VIN = 0 V to 0.25 V p-p
30
ns
Min Gain, TXEN = 0, 65 MHz, VIN = 0.25 V p-p
Max Gain, TXEN = 0, 42 MHz, VIN = 0.25 V p-p
Max Gain, TXEN = 0, 65 MHz, VIN = 0.25 V p-p
All Gains, SLEEP, 65 MHz, VIN = 0.25 V p-p
–85
–31
–28
–85
dBc
dBc
dBc
dBc
POWER CONTROL
Transmit Enable Response Time (tON
)
Max Gain, VIN = 0
Max Gain, VIN = 0
Equivalent Output = 31 dBmV
Equivalent Output = 61 dBmV
250
40
5
ns
ns
mV p-p
mV p-p
Transmit Disable Response Time (tOFF
)
Between Burst Transients1
60
POWER SUPPLY
Operating Range
Quiescent Current
11.4
147
38
12
157
44
12.6
167
50
V
Transmit Enable Mode (TXEN = 1)
Transmit Disable Mode (TXEN = 0)
Sleep Mode
mA
mA
mA
1.5
4.5
7.5
OPERATING TEMPERATURE
RANGE
–40
+85
°C
NOTES
1Between Burst Transients measured at the output of diplexer.
Specifications subject to change without notice.
–2–
REV. 0
AD8326
SPECIFICATIONS (tTran=sf2o5r؇mCe,rVwi=th؎an5iVn,sRert=ionR lo=ss7o5f⍀0.5, VdB=@21006MVHpz-,pu,nVlessmoetahseurwreisdethnrootuegdh.)a 1:1
A
S
L
IN
IN
OUT
AD 8326ARE
P aram eter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Output = 65 dBmV, Max Gain
Max Gain, f = 10 MHz
Differential Input
206
16.6
1600
800
2
mV p-p
dB
Ω
Ω
pF
Input Resistance
Single-Ended Input
Input Capacitance
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
52.5
26.5
–27
53.5
27.5
–26
54.5
28.5
–25
dB
dB
dB
Gain Code = 71 Dec
Gain Code = 0 Dec
Minimum Gain
Gain Scaling Factor
Gain Linearity Error
0.7526
±0.2
dB/LSB
dB
f = 10 MHz, Code-to-Code
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
All Gain Codes
f = 65 MHz
f = 65 MHz
100
1.1
0
MHz
dB
dB
Bandwidth Peaking
Output Noise Spectral Density
Max Gain, f = 10 MHz
–28
dBmV in
160 kHz
dBmV in
160 kHz
dBmV in
160 kHz
dBm
Min Gain, f = 10 MHz
–45.5
–65
Transmit Disable Mode, f = 10 MHz
1 dB Compression Point
Max Gain, f = 10 MHz
25.0
Differential Output Impedance
Transmit Enable and Transmit Disable Mode
75 ± 20%
Ω
OVERALL PERFORMANCE
Worst Harmonic Distortion
f = 14 MHz, VOUT = 65 dBmV @ Max Gain
f = 21 MHz, VOUT = 65 dBmV @ Max Gain
f = 42 MHz, VOUT = 65 dBmV @ Max Gain
f = 65 MHz, VOUT = 65 dBmV @ Max Gain
16 QAM, VOUT = 65 dBmV
–62
–62
–60
–58
–58
dBc
dBc
dBc
dBc
dBc
Adjacent Channel Power
Output Settling
Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC
Due to Gain Change (TGS
)
Min to Max Gain
60
ns
Due to Input Step Change
Signal Isolation
Max Gain, VIN = 0 V to 0.19 V p-p
30
ns
Min Gain, TXEN = 0, 65 MHz, VIN = 0.19 V p-p
Max Gain, TXEN = 0, 42 MHz, VIN = 0.19 V p-p
Max Gain, TXEN = 0, 65 MHz, VIN = 0.19 V p-p
All Gains, SLEEP, 65 MHz, VIN = 0.19 V p-p
–85
–31
–28
–85
dBc
dBc
dBc
dBc
POWER CONTROL
Transmit Enable Response Time (tON
)
Max Gain, VIN = 0
Max Gain, VIN = 0
Equivalent Output = 31 dBmV
Equivalent Output = 61 dBmV
250
40
5
ns
ns
mV p-p
mV p-p
Transmit Disable Response Time (tOFF
)
Between Burst Transients1
60
POWER SUPPLY
Operating Range
Quiescent Current
±4.75 ±5.0
±5.25
160
48
V
Transmit Enable Mode (TXEN = 1)
Transmit Disable Mode (TXEN = 0)
Sleep Mode
140
36
1
150
42
4
mA
mA
mA
7
OPERATING TEMPERATURE
RANGE
–40
+85
°C
NOTES
1Between Burst Transients measured at the output of diplexer.
Specifications subject to change without notice.
REV. 0
–3–
AD8326
LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V = 12 V: Full Temperature Range)
CC
P aram eter
Min
Typ
Max
Unit
Logic “1” Voltage
Logic “0” Voltage
2.1
0
5.0
0.8
V
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) TXEN
Logic “0” Current (VINL = 0 V) TXEN
Logic “1” Current (VINH = 5 V) SLEEP
Logic “0” Current (VINL = 0 V) SLEEP
0
–600
50
–250
50
20
nA
nA
µA
µA
µA
µA
–100
190
–30
190
–30
–250
Specifications subject to change without notice.
TIMING REQUIREMENTS (Full Temperature Range, V = 12 V, tR = tF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
CC
P aram eter
Min
Typ
Max
Unit
Clock Pulsewidth (tWH
Clock Period (tC)
Setup Time SDATA vs. Clock (tDS
Setup Time DATEN vs. Clock (tES
Hold Time SDATA vs. Clock (tDH
Hold Time DATEN vs. Clock (tEH
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
)
16.0
32.0
5.0
15.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
3.0
10
Specifications subject to change without notice.
tDS
VALID DATA WORD G1
VALID DATA WORD G2
SDATA
CLK
MSB. . . .LSB
tC
tWH
tEH
tES
8 CLOCK CYCLES
DATEN
GAIN TRANSFER (G1)
tOFF
GAIN TRANSFER (G2)
TXEN
tGS
tON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
MSB-2
tDH
tDS
CLK
Figure 3. SDATA Timing
–4–
REV. 0
AD8326
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage VCC
Pins 5, 9, 10, 19, 20, 23, 27 . For ARP, Max VCC = VEE + 13 V;
. . . . . . . . . . . . . . . . . . . . . . . For ARE, Max VCC = VEE + 11 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP EPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
PSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
JA
P ackage O ption
AD8326ARP
–40°C to +85°C
28-Lead Power SOIC with Slug
23°C/W*
RP-28
AD8326ARP-REEL
AD8326ARP-EVAL
AD8326ARE
Evaluation Board
28-Lead TSSOP with Exposed Pad
–40°C to +85°C
39°C/W*
RE-28
AD8326ARE-REEL
AD8326ARE-EVAL
Evaluation Board
*Thermal Resistance measured on SEMI standard 4-layer board.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8326 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD8326
P IN CO NFIGURATIO N
1
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DATEN
SDATA
CLK
2
3
V
CC
V
IN–
4
GND
V
IN+
5
V
V
CC
EE
6
V
TXEN
CC
AD8326
7
V
SLEEP
EE
TOP VIEW
(Not to Scale)
8
NC
BYP
9
V
V
CC
CC
10
11
12
13
14
V
V
CC
CC
V
V
EE
EE
NC
NC
V
V
EE
EE
OUT–
OUT+
NC = NO CONNECT
P IN FUNCTIO N D ESCRIP TIO NS
P in No.
Mnem onic
D escription
1
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
2
3
SDATA
CLK
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first and ignored.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
4, 28
5, 9, 10, 19,
20, 23, 27
GND
VCC
Common External Ground Reference
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
6
7
TXEN
SLEEP
Transmit Enable pin. Logic 1 powers up the part.
Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A
Logic 0 powers down the part (High ZOUT State) and a Logic 1 powers up the part.
8, 12, 17
NC
No Connection to these pins.
11, 13, 16, 18, VEE
22, 24
Common Negative External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
14
15
21
25
OUT–
OUT+
BYP
Negative Output Signal
Positive Output Signal
Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a
VIN+
0.1 µF capacitor.
26
VIN–
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
–6–
REV. 0
Typical Performance Characteristics–AD8326
V
CC
10F
0.1F
V
0.1F
CC
75⍀
75⍀
0.1F
0.1F
V
V
IN+
OUT+
+
+1/2 V
IN
C
AD8326
165⍀
75⍀
L
V
O
–
OUT–
1:1
IN–
TOKO
617DB-A0070
0.1F
V
–1/2 V
BYP
EE
IN
0.1F
0.1F
10F
V
EE
TPC 1. Test Circuit
32.0
1.0
0.5
V
P
= 12V
S
= 67dBmV@ MAX GAIN
V
= 12V
O
S
30.5
29.0
27.5
26.0
24.5
23.0
21.5
P
= 67dBmV @ MAX GAIN
OUT
10MHz
C
= 0pF
L
5MHz
C
= 10pF
0
L
42MHz
–0.5
–1.0
–1.5
C
= 20pF
L
C
= 50pF
L
65MHz
1
10
FREQUENCY – MHz
100
0
9
18
27
36
45
54
63
72
GAIN CONTROL – Decimal
TPC 2. Gain Error vs. Gain Control
TPC 4. AC Response for Various Capacitor Loads
40
30
–26
V
V
= 12V
S
= 67dBmV @ MAX GAIN
O
f = 10MHz
TXEN = 1
–30
71D
46D
V
= 12V
S
20
–34
–38
–42
–46
–50
10
0
–10
–20
–30
–40
23D
00D
0.1
1
10
100
1000
0
8
16
24
32
40
48
56
64
72
FREQUENCY – MHz
GAIN CONTROL – Decimal
TPC 3. AC Response
TPC 5. Output Referred Noise vs. Gain Control
REV. 0
–7–
AD8326
0
–50
–55
–60
–65
–70
–75
–80
–85
RBW 500Hz RF ATT 30dB
–10 VBW 5kHz
SWT 20s UNIT dBm
CH PWR +12.27dBm
ACP UP –56.72dB
ACP LOW –56.71dB
V
= 12V
S
f
= 42MHz
= 67dBmV @ MAX GAIN
–20
–30
–40
–50
–60
–70
–80
–90
–100
P
O
HD3
HD2
–90
CENTER 21MHz
100kHz/
SPAN 1MHz
0
9
18
27
36
45
54
63
72
GAIN CODE – Decimal
TPC 6. Harmonic Distortion vs. Gain Code for
AD8326-ARP
TPC 9. Adjacent Channel Power for AD8326-ARP
–50
190
180
170
V
= 12V(ARP)
S
–55
–60
–65
–70
–75
–80
–85
–90
V
= 69dBmV @ MAX GAIN
O
V
= 68dBmV @ MAX GAIN
O
SLEEP
160
150
140
130
120
110
POWER-UP
POWER-DOWN
V
= 67dBmV @ MAX GAIN
O
V
= 65dBmV @ MAX GAIN
O
5
15
25
35
45
55
65
1
10
100
FREQUENCY – MHz
1000
FREQUENCY – MHz
TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 10. Input Impedance vs. Frequency (Inputs
Shunted with 165 Ω)
1000
–35
V
= +12V(ARP)
S
–40
–45
–50
–55
–60
–65
–70
–75
SLEEP
POWER-DOWN
100
V
= 69dBmV @ MAX GAIN
= 67dBmV @ MAX GAIN
O
V
= 68dBmV @ MAX GAIN
O
POWER-UP
10
V
O
V
= 65dBmV @ MAX GAIN
O
1
0.1
5
15
25
35
45
55
65
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 8. Third Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 11. Output Impedance vs. Frequency
–8–
REV. 0
AD8326
0
–50
–55
–60
–65
–70
–75
–80
–85
–90
RBW 500Hz RF ATT 30dB
–10 VBW 5kHz
SWT 20s UNIT dBm
CH PWR +10.41dBm
ACP UP –58.83dB
ACP LOW –59.06dB
V
= ؎5V
S
f
= 42MHz
= 65dBmV @ MAX GAIN
–20
–30
–40
–50
–60
–70
–80
–90
–100
P
O
HD3
HD2
CENTER 21MHz
100kHz/
SPAN 1MHz
0
9
18
27
36
45
54
63
72
DEC CODE
TPC 12. Harmonic Distortion vs. Gain Control for
AD8326-ARE
TPC 15. Adjacent Channel Power for AD8326-ARE
0
–50
V
= 12V
V
= ؎5V(ARE)
S
S
–55
–60
–65
–70
–75
–80
–85
–90
–20
–40
TXEN = 1
V
= 65dBmV @ MAX GAIN
O
V
= 66dBmV @ MAX GAIN
O
–60
V
= 64dBmV @ MAX GAIN
O
–80
TXEN = 0
V
= 62dBmV @ MAX GAIN
O
–100
–120
SLEEP
5
15
25
35
45
55
65
0
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Second Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 16. Signal Isolation vs. Frequency
200
180
160
140
120
100
80
–40
V
= 12V(ARP)
S
V
= ؎5V(ARE)
S
–45
–50
–55
–60
–65
–70
–75
–80
TRANSMIT ENABLE
V
= 66dBmV @ MAX GAIN
O
V
= 65dBmV @ MAX GAIN
O
V
= 64dBmV @ MAX GAIN
O
60
TRANSMIT DISABLE
V
= 62dBmV @ MAX GAIN
O
40
20
5
15
25
35
45
55
65
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
FREQUENCY – MHz
TEMPERATURE – ؇C
TPC 14. Third Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 17. Quiescent Current vs. Temperature
REV. 0
–9–
AD8326
AP P LICATIO NS
SP I P r ogr am m ing
Gener al Applications
The AD8326 is controlled through a serial peripheral interface
(SPI) of three digital data lines, CLK, DATEN, and SDATA.
Changing the gain requires 8 bits of data to be streamed into the
SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register, Most Significant Bit
(MSB) first, on the rising edge of the CLK pulses. Since a 7-bit
shift register is used in the AD8326, the MSB of the 8-bit word
is a “don’t care” bit and is shifted out of the register on the eighth
clock pulse. The data is latched into the attenuator core on the
rising edge of the DATEN line. This provides control over the
changes in the output signal level. The serial interface timing for
the AD8326 is shown in Figures 2 and 3. The programmable
gain range of the AD8326 is –25.75 dB to +27.5 dB with steps
of 0.75 dB. This provides a total gain range of 53.25 dB. The
AD8326 was characterized with a TOKO transformer (TOKO
#617DB-A0070), and the stated gain values include the losses
due to the transformer.
The AD8326 is primarily intended for use as the upstream
power amplifier (PA), also known as a line driver, in DOCSIS
(Data Over Cable Service Interface Specification) certified
cable modems, cable telephony systems, and CATV set-top
boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal. Due to the
varying distances between the cable modem and the headend,
the upstream PA must be capable of varying the output power
by applying gain or attenuation. The varying output power of
the AD8326 ensures that the signal from the cable modem will
have the proper level once it arrives at the headend. The upstream
signal path also contains a transformer, a diplexer, and cable split-
ters. The AD8326 has been designed to overcome losses associated
with these passive components in the upstream cable path, particu-
larly in modems that support cable telephony.
AD 8326ARP Applications
For gain codes from 0 through 71 the gain transfer function is:
The AD8326ARP is in a thermally enhanced PSOP2 package,
and designed for single 12 V supply and output power applica-
tions up to +69 dBmV. The AD8326ARP will provide maximum
performance in 12 V systems.
AV = 27.5 dB –(0.75 dB ×(71– CODE)
[
]
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word. Gain codes 0 to 71 provide linear changes in
gain. Figure 4 shows the gain characteristics of the AD8326 for
all possible values in an 8-bit word. Note that maximum gain is
achieved at Code 71. From Code 72 through 127 the 5.25 dB
of attenuation from the vernier stage is being applied over every
eight codes, resulting in the saw tooth characteristic at the top
of the gain range. Because the eighth bit is shifted out of the
register, the gain characteristics for Codes 128 through 255 are
identical to Codes 0 through 127, as depicted in Figure 4.
AD 8326ARE Applications
The AD8326ARE is in a TSSOP package with an exposed ther-
mal pad. It is designed for dual ±5 V or single 10 V supplies. For
applications requiring up to 65 dBmV of output power, lower
cost, smaller package, and lower power dissipation, the TSSOP
package is most appropriate.
O per ational D escr iption
The AD8326 consists of four analog functions in the transmit
enable or forward mode. The input amplifier (preamp) can be
used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals be
180 degrees out of phase and of equal amplitudes. This will
ensure proper gain accuracy and harmonic performance. The
preamp stage drives a vernier stage that provides the fine tune
gain adjustment. The approximate step resolution of 0.75 dB is
implemented in this stage and provides a total of approximately
5.25 dB of accumulated attenuation. After the vernier stage, a
DAC provides the bulk of the AD8326’s attenuation (8 bits or
48 dB). The signals in the preamp and vernier gain blocks are
differential to improve the PSRR and linearity. A differential
current is fed from the DAC into the output stage, which
amplifies these currents to the appropriate levels necessary to
drive a 75 Ω load.
28
21
14
7
0
–7
–14
–21
–28
0
32
64
96
128
160
192
224
256
GAIN CODE – Decimal
Figure 4. Gain Code vs. Gain
The output stage utilizes negative feedback to implement a
differential 75 Ω output impedance, which eliminates the need
for external matching resistors needed in typical video (or
video filter) termination requirements.
–10–
REV. 0
AD8326
V
EE
10F
10F
V
CC
0.1F
AD8326
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IN–
1
2
GND
DATEN
SDATA
CLK
DATEN
SDATA
CLK
V
0.1F
CC
Z
= 150⍀
3
IN
V
V
IN–
165⍀
4
GND1
IN+
5
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
V
V
V
CC
EE
CC
6
TXEN
TXEN
SLEEP
GND
V
IN+
7
V
SLEEP
EE
0.1F
8
BYP
9
V
V
V
V
V
CC
CC
EE
CC
10
11
12
13
14
0.1F
0.1F
CC
V
EE
GND
GND
0.1F
V
V
V
0.1F
EE
EE
V
OUT–
OUT+
TOKO 617DB-A0070
TO DIPLEXER
Z
= 75⍀
IN
Figure 5. Typical Applications Circuit
Input Bias, Im pedance, and Ter m ination
Toko 1:1 transformer is included on the board for this purpose
(T3). Enabling the evaluation board for single to differential
input conversion requires R15–R17 to be removed, and 0 Ω
jumpers must be installed on the placeholders for R13, R14, and
R18. For a 75 Ω input impedance, R12 should be 78.7 Ω. Refer
to Figure 11 for evaluation board schematic. In this configuration,
the input signal must be applied to VIN–. Other input imped-
ances may be calculated using the equation in Figure 7.
The VIN+ and VIN– inputs have a dc bias level of approxi-
mately 1.47 V below VCC/2, therefore the input signal should
be ac-coupled using 0.1 µF capacitors as seen in the typical
application circuit (see Figure 5).
The differential input impedance of the AD8326 is approxi-
mately 1600 Ω, while the single-ended input is 800 Ω.
Single-Ended Inver ting Input
When operating the AD8326 in a single-ended input mode VIN+
and VIN– should be terminated as illustrated in Figure 6. On the
AD8326 evaluation boards, this termination method requires the
removal of R12, R13, R14, R16, R17, and R18. Install a 0 Ω
jumper at R15, an 82.5 Ω resistor at R10 for a 75 Ω system, and a
39.2 Ω resistor at R11 to balance the inputs of the AD8326
evaluation board (Figure 11). Other input impedance configura-
tions may be calculated using the equations in Figure 6.
DESIRED IMPEDANCE = R12||1600
V
–
IN
AD8326
R12
Figure 7. Differential Signal from Single-Ended Source
D iffer ential Signal Sour ce
The AD8326 evaluation board is also capable of accepting a
differential input signal. This requires the installation of a 165 Ω
resistor in R12, the removal of R13–R14, R17–R18, and the
installation of 0 Ω jumpers for R15–R16. This configuration
results in a differential input impedance of 150 Ω. Other differ-
ential input impedance configurations may be calculated with
the equation in Figure 8.
Z
= R10||800
IN
R11 = Z ||R10
IN
V
–
–
IN
R10
AD8326
+
R11
DESIRED IMPEDANCE = R12||1600
Figure 6. Single-Ended Input Impedance
V
V
+
IN
The inverting and noninverting inputs of the AD8326 must be
balanced for all input configurations.
R12
AD8326
–
IN
D iffer ential Input fr om Single-Ended Sour ce
The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. A
Figure 8. Differential Input
REV. 0
–11–
AD8326
at +65 dBmV with ±5 V supplies. The AD8326ARP draws a
O utput Bias, Im pedance, and Ter m ination
maximum of 2 W at +67 dBmV with a +12 V supply.
The outputs have a dc bias level of approximately VCC/2, there-
fore they should be ac-coupled before being applied to the load.
The following guidelines should be used for both the AD8326ARE
and AD8326ARP.
The differential output impedance of the AD8326 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
transmit enable mode or transmit disable mode, eliminating the
need for external back termination resistors. A 1:1 transformer
is used to couple the amplifier’s differential output to the coaxial
cable while maintaining a proper impedance match. If the out-
put signal is being evaluated on standard 50 Ω test equipment, a
minimum loss 75 Ω–50 Ω pad must be used to provide the test
circuit with proper impedance match.
First and foremost, the exposed thermal pad should be soldered
directly to a substantial ground plane that adequately absorbs
heat away from the AD8326 package. This is the simplest, and
most important step in thermally managing the power dissipated in
the AD8326. Increasing the area of copper beneath the AD8326
will lower the thermal resistance in the PCB and more effectively
allow air to remove the heat from the PCB, and consequently,
from the AD8326.
Single Supply O per ation
Secondly, thermal stitching is a method for increasing thermal
capacity of the PCB. Additionally, thermal stitching can be used
to provide a thermally efficient area onto which the AD8326
may be soldered. Thermal stitching is accomplished by using a
number of plated through holes (or vias) densely populated in
the solder pad area (but not confined to the size of the TSSOP
or PSOP2 exposed thermal pad). This technique maximizes the
copper area where the package is attached to the PCB increas-
ing the thermal mass or capacity by utilizing more than one
copper plane. This method of thermal management should be
applied in close proximity to the exposed thermal pad.
The 12 V supply should be delivered to each of the VCC pins via
a low impedance power bus to ensure that each pin is at the
same potential. The power bus should be decoupled to ground using
a 10 µF tantalum capacitor located close to the AD8326ARP.
In addition to the 10 µF capacitor, each VCC pin should be
individually decoupled to ground with 0.1 µF ceramic chip
capacitors located close to the pins. The pin labeled BYP (Pin
21) should also be decoupled with a 0.1 µF capacitor. The PCB
should have a low-impedance ground plane covering all unused
portions of the board, except in the area of the input and output
traces in close proximity to the AD8326 and output transformer. All
ground and VEE pins of the AD8326ARP must be connected to
the ground plane to ensure proper grounding of all internal nodes.
Pin 28 and the exposed pad should be connected to ground.
Another important guideline is to utilize a multilayer PCB with
the AD8326. Lowering the PCB thermal resistance using several
layers will generally increase thermal mass resulting in cooler
junction temperatures.
D ual Supply O per ation
Using the techniques described above and dedicating 2.9 square
inches of thermally enhanced PCB area, the AD8326 in either
package can operate at safe junction temperatures. Figures 12-17
show the above practices in use on the AD8326ARE-EVAL board.
The +5 V supply power should be delivered to each of the VCC
pins via a low impedance power bus to ensure that each pin is at
the same potential. The –5 V supply should also be delivered to
each of the VEE pins with a low impedance bus. The power buses
should be decoupled to ground with a 10 µF tantalum capacitor
located close to the AD8326ARE. In addition to the 10 µF capaci-
tor, all VCC, VEE and BYP pins should be individually decoupled to
ground with 0.1 µF ceramic chip capacitors located close to the
pins. The PCB should have a low-impedance ground plane
covering all unused portions of the board, except in the area of
the input and output traces in close proximity to the AD8326
and output transformer. All ground pins of the AD8326ARE must
be connected to the ground plane to ensure proper grounding of
all internal nodes. Pin 28 and the exposed thermal pad should
both be tied to ground.
Initial P ower -Up
When the supply is first applied to the AD8326, the gain setting
of the amplifier is indeterminate. Therefore, as power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0), preventing forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the desired
level by following the procedure in the SPI Programming and
Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.
Asynchr onous P ower -D own
Signal Integr ity Layout Consider ations
The asynchronous TXEN pin is used to place the AD8326 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying Logic 0 to the TXEN pin acti-
vates the on-chip reverse amplifier, providing a 72% reduction
in consumed power. For 12 V operation, the supply current is
typically reduced from 159 mA to 44 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition
to the TXEN pin, the AD8326 also incorporates an asynchro-
nous SLEEP pin, which may be used to further reduce the supply current
to approximately 4 mA. Applying Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the
output of the amplifier.
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
technique is mandatory. The differential input and output traces
should be kept as short as possible. It is also critical to make
sure that all differential signal paths are symmetrical in length
and width. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8326 in all applications.
Ther m al Layout Consider ations
As integrated circuits become denser, smaller, and more power-
ful, they often produce more heat. Therefore when designing PC
boards, the layout must be able to draw heat away from the higher
power devices. The AD8326ARE draws up to 1.5 W when running
–12–
REV. 0
AD8326
D istor tion, Adjacent Channel P ower , and D O CSIS
rate than the noise, resulting in a signal to noise ratio that improves
with gain. In transmit disable mode, the output noise spectral
density is 1.4 nV/√Hz, which results in –65 dBmV when computed
In order to deliver +58 dBmV of high fidelity output power
required by DOCSIS, the PA is required to deliver up to
+67 dBmV. This added power is required to compensate for
losses associated with the transformer, diplexer, directional
coupler, and splitters that may be included in the upstream
path of the cable telephony. It should be noted that the AD8326
was characterized with the TOKO 617DB-A0070 transformer.
TPC 7, TPC 8, TPC 13, and TPC 14 show the AD8326 second
and third harmonic distortion performance versus fundamental
frequency for various output power levels. These figures are
useful for determining the in band harmonic levels from 5 MHz
to 65 MHz. Harmonics higher in frequency will be sharply
attenuated by the low-pass filter function of the diplexer.
over 160KSYM/SECOND
.
The noise power was measured directly at the output of the
transformer. In a typical cable telephony application there will
be a 6 dB pad, or splitter, which will further attenuate the noise
by 6 dB.
Evaluation Boar d Featur es and O per ation
The AD8326 evaluation boards (Part # AD8326ARE-EVAL
and AD8326ARP-EVAL) and control software can be used to
control the AD8326 upstream cable driver via the parallel port
of a PC. A standard printer cable connected between the paral-
lel port and the evaluation board is used to feed all the necessary
data to the AD8326 by means of the Windows 9X-based control
software. This package provides a means of evaluating the amplifier
by providing a convenient way to program the gain/attenuation
as well as offering easy control of the asynchronous TXEN and
SLEEP pins. With this evaluation kit, the AD8326 can be evalu-
ated in either a single-ended or differential input configuration.
The amplifier can also be evaluated with or without the PULSE
diplexer in the output signal path. A schematic of the evaluation
board is provided in Figure 11.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS section 4.2.10.1.1
states, “Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates.” TPC 9 shows the mea-
sured ACP for a +67 dBmV 16 QAM signal taken at the output
of the AD8326 evaluation board, through a 75 Ω to 50 Ω
matching pad (5.7 dB of loss). The transmit channel width
and adjacent channel width in TPC 9 correspond to symbol
rates of 160 KSYM/SEC. Table I shows the ACP results for
the AD8326 for all conditions in DOCSIS Table 4-7 “Adjacent
Channel Spurious Emissions.”
O utput Tr ansfor m er and D iplexer
A 1:1 transformer is needed to couple the differential outputs of
the AD8326 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070); however, M/A-COM part # ETC-1-1T may
also be used. The evaluation board is equipped with the TOKO
transformer, but is also designed to accept the M/A-COM trans-
former. The PULSE diplexer included on the evaluation board
provides a high-order low-pass filter function, typically used in the
upstream path. To remove the diplexer from the signal path,
remove the 0 Ω chip resistors at R7 and R19, and install a 0 Ω
chip resistor at R6 so the output signal is directed away from
the diplexer and toward the CABLE port of the evaluation
board (Figure 11). The ability of the PULSE diplexer to achieve
DOCSIS compliance is neither expressed nor implied by Analog
Devices Inc. Data on the diplexer should be obtained from
PULSE. When using the diplexer, be sure to properly terminate
the cable port (75 Ω) so that the AD8326 draws minimal current.
Table I. Adjacent Channel P ower
Adjacent Channel Sym bol Rate
Transm it
Sym bol
Rate
160K/s
ACP
(dBc)
320K/s 640K/s 1280K/s 2560K/s
ACP
ACP
ACP
ACP
(dBc)
(dBc)
(dBc)
(dBc)
160K/s
320K/s
640K/s
1280K/s
2560K/s
–57
–57
–55
–55
–53
–59
–58
–58
–57
–56
–62
–60
–58
–58
–57
–63
–62
–60
–58
–57
–64
–64
–62
–60
–57
Noise and D O CSIS
At minimum gain, the AD8326 output noise spectral density is
13.3 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spuri-
ous Emissions in 5 MHz to 42 MHz,” specifies the output noise
for various symbol rates. The calculated noise power in dBmV
for 160 KSYM/SECOND is:
O ver shoot on P C P r inter P or ts
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre-
sented to the CLK pin of the AD8326. The evaluation board
was designed to accommodate a series resistor and shunt capaci-
tor (R2 and C2 in Figure 11) to filter the CLK signal if required.
2
13.3 nV
20 × log
× 160 kHz + 60 = – 45.5 dBmV
Hz
Installing Visual Basic Contr ol Softwar e
Install the “CabDrive_26” software by running “setup.exe” on
disk one of the AD8326 Evaluation Software. Follow on-screen
directions and insert disk two when prompted. Choose instal-
lation directory, and then select the icon in the upper left to
complete installation.
Comparing the computed noise power of –45.5 dBmV to the
+8 dBmV signal yields –53.5 dBc, which meets the required level
set forth in DOCSIS Table 4-8. As the AD8326 gain is increased
from this minimum value, the output signal increases at a faster
REV. 0
–13–
AD8326
Running AD 8326 Softwar e
Mem or y Functions
To load the control software, go to START, PROGRAMS,
CABDRIVE_26, or select the AD8326.exe from the installed
directory. Once loaded, select the proper parallel port to com-
municate with the AD8326 (Figure 9).
The MEMORY section of the software provides a way to alter-
nate between two gain settings. The “X->M1” button stores
the current value of the gain slide bar into memory while the
“RM1” button recalls the stored value, returning the gain slide
bar to the stored level. The same applies to the “X->M2” and
“RM2” buttons.
Figure 9. Parallel Port Selection
Contr olling Gain/Attenuation of the AD 8326
The slide bar controls the gain/attenuation of the AD8326,
which is displayed in dB and in V/V. The gain scales 0.75 dB
per LSB with valid codes from 0 to 71. The gain code from the
position of the slide bar is displayed in decimal, binary, and
hexadecimal (Figure 10).
Figure 10. Control Software Interface
Tr ansm it Enable and Sleep Mode
The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8326 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmis-
sion while maintaining a 75 Ω back termination. The Transmit
Enable button applies Logic 1 to the TXEN pin, enabling the
AD8326 for forward transmission. Checking the “Enable SLEEP
Mode” checkbox applies logic “0” to the asynchronous SLEEP
pin, setting the AD8326 for SLEEP mode.
–14–
REV. 0
AD8326
Figure 11. Evaluation Board Schematic
–15–
REV. 0
AD8326
Figure 12. Evaluation Board Layout (Component Side)
–16–
REV. 0
AD8326
Figure 13. Evaluation Board Layout (Silkscreen Top)
REV. 0
–17–
AD8326
Figure 14. Evaluation Board Layout (Circuit Side)
–18–
REV. 0
AD8326
Figure 15. Evaluation Board Layout (Silkscreen Bottom)
REV. 0
–19–
AD8326
Figure 16. Evaluation Board Layout (Internal Ground Plane)
–20–
REV. 0
AD8326
Figure 17. Evaluation Board Layout (Internal Power Planes)
REV. 0
–21–
AD8326
AD 8326 Evaluation Board Rev. B – Revised - Novem ber 22, 2000
Vendor
Qty.
D escription
Ref D escription
2
4
14
9
10 µF 16 V. B Size Tantalum Chip Capacitor
ADS# 4-7-24
ADS# 4-5-18
ADS# 4-12-8
ADS# 3-18- 88
C7, C19
C20–23
C4–C6, C8–C18
R1–R3, R7, R8, R13, R14,
0.1 µF 50 V. 1206 Size Ceramic Chip Capacitor
0.1 µF 25 V. 603 Size Ceramic Chip Capacitor
0 Ω 1/8 W. 1206 Size Chip Resistor
R18, R19
1
2
6
1
1
3
4
78.7 Ω 1% 1/8 W. 1206 Size Chip Resistor
Yellow Test Point [INPUTS] (Bisco TP104-01-04)
White Test Point [DATA] (Bisco TP104-0 -09)
Red Test Point [VCC] (Bisco TP104-01-02)
Blue Test Point [VEE] (Bisco TP104-01-06)
Black Test Point [AGND] (Bisco TP104-01-00)
End Launch SMA Connector
ADS# 3-18-194
ADS# 12-18-32
ADS# 12-18-42
ADS# 12-18-43
ADS# 12-18-62
ADS# 12-18-44
ADS# 12-1-31
R12
TP13, TP14
TP1–TP6
TP15
TP7
TP16–TP18
VIN–, VIN+, CABLE,
HPF
1
1
1
1
1
1
4
4
2
2
2
2
Centronics Type 36 Pin Right-Angle Connector
3 Terminal Power Block (Green)
1:1 Transformer TOKO # 617DB – A0070
Pulse # CX 6002 Diplexer
AD 8326ARE (TSSOP ePad) UPSTREAM Cable Driver
AD 8326ARE REV. B Evaluation PC Board
#4–40 × 1/4 Inch STAINLESS Panhead Machine Screw
#4–40 × 3/4 Inch Long Aluminum Round Standoff
# 2–56 × 3/8 inch STAINLESS Panhead Machine Screw
# 2 Steel Flat Washer
ADS# 12-3-50
ADS# 12-19-14
TOKO
P1
TB1
T3, T1
Z2
Z1
PULSE
ADI# AD8326XRE
ADI# AD8326XRE-EVAL
ADS# 30-1-1
ADS# 30-16-3
ADS# 30-1-17
ADS# 30-6-6
ADS# 30-5-2
ADS# 30-7-6
EVAL PCB
(p1 hardware)
(p1 Hardware)
(p1 Hardware)
(p1 Hardware)
# 2 Steel Internal Tooth Lockwasher
# 2 STAINLESS STEEL Hex. Machine Nut
Do not install C1–C3, R4–R6, R10, R11, R15–R17, T2, T4, TP8–TP12, W1–W2.
–22–
REV. 0
AD8326
O UTLINE D IMENSIO NS
Dimensions shown in inches and (mm).
28-Lead P SO P
(RP -28)
0.711 (18.06)
0.701 (17.81)
28
15
0.299 (7.59)
0.292 (7.42)
0.189 (4.80)
0.179 (4.55)
HEAT SLUG
ON BOTTOM
0.410 (10.41)
0.400 (10.16)
14
1
PIN 1
0.539 (13.69)
0.098 (2.49)
0.016 (0.41)
0.010 (0.25)
0.529 (13.44)
45°
0.090 (2.29)
8؇
0؇
0.050 (1.27)
0.019 (0.48)
0.004 (0.10)
0.000 (0.00)
STANDOFF
0.040 (1.27)
0.024 (0.61)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
BSC
0.014 (0.36)
28-Lead H TSSO P
(RE-28)
0.386 (9.80)
0.382 (9.70)
0.378 (9.60)
15
28
0.119 (3.05)
0.117 (3.00)
0.115 (2.95)
0.177 (4.50)
0.173 (4.40)
0.169 (4.30)
0.252
(6.40)
BSC
EXPOSED
PAD
ON BOTTOM
1
14
PIN 1
0.138 (3.55)
0.136 (3.50)
0.134 (3.45)
0.041 (1.05)
0.039 (1.00)
0.031 (0.80)
0.047
(1.20)
MAX
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.030 (0.75)
0.024 (0.60)
0.177 (0.45)
0.0256
(0.65)
BSC
0.006 (0.15)
0.000 (0.00)
SEATING 0.0079 (0.20)
PLANE
0.0035 (0.09)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm)
REV. 0
–23–
–24–
相关型号：
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