AD8335-EVAL [ADI]
Quad Low Noise, Low Cost Variable Gain Amplifier; 四通道，低噪声，低成本可变增益放大器
| 型号： | AD8335-EVAL |
| 厂家： | 
ADI |
| 描述： | Quad Low Noise, Low Cost Variable Gain Amplifier |
| 文件： | 总24页 (文件大小：887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Low Noise, Low Cost
Variable Gain Amplifier
AD8335
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low noise preamplifier (PrA)
Voltage noise = 1.3 nV/√Hz typical
Current noise = 2.4 pA/√Hz typical
NF = 7 dB (RS = RIN = 50 Ω)
Single-ended input; VIN max = 625 mV p-p
Active input match
Input SNR (noise bandwidth = 20 MHz) = 92 dB
VGA
Differential output
61 60
59 58
53 55
52
51
49
47
VOH1
PIP1 63
ATTEN
–48dB TO
0dB
20dB
TO
28dB
VMD1
18dB
PMD1 64
46
VOL1
VGN1
SL12
VGN2
PMD2
PIP2
1
2
4
5
6
7
INTERPOLATOR GAIN INT 56
50
VMD2
18dB
PON2
POP2
VIP2
INTERPOLATOR GAIN INT 54
VOUT max = 5 V p-p, RL = 500 Ω differential
43
VOL2
Gain range (8 dB output gain step)
−10 dB to +38 dB—LO gain mode
−2 dB to +46 dB—HI gain mode
Accurate linear-in-dB gain control
PrA + VGA performance
−3 dB bandwidth of 70 MHz
Excellent overload performance
Supply: 5 V
ATTEN
–48dB TO
0dB
20dB
TO
28dB
VIN2
42
39
VOH2
VOH3
AD8335
VIN3 10
VIP3 11
ATTEN
–48dB TO
0dB
20dB
TO
28dB
38
VOL3
VGN3
POP3 12
PON3 13
GAIN INT 27
31
INTERPOLATOR
INTERPOLATOR
Power consumption
SL34
VGN4
VOL4
PIP3 15
95 mW/channel (380 mW total)
65 mW/channel (PrA off; 260 mW total)
Power-down
VMD3
VMD4
18dB
18dB
25
35
GAIN INT
PMD3 16
PMD4 17
PIP4 18
ATTEN
–48dB TO
0dB
20dB
TO
28dB
34
VOH4
APPLICATIONS
Medical imaging (ultrasound, gamma cameras)
20 21
22
23 28 26
29
30
32
Sonar
Test and measurement
Figure 1.
Precise, stable wideband gain control
GENERAL DESCRIPTION
The AD8335 is a quad variable gain amplifier (VGA) with low
noise preamplifier intended for cost and power sensitive
applications. Each channel features a gain range 48 dB, fully
differential signal paths, active input preamplifier matching, and
user-selectable maximum gains of 46 dB and 38 dB. Individual
gain controls are provided for each channel.
Assuming a 20 MHz noise bandwidth (NBW), the Nyquist
frequency for a 40 MHz ADC, the input SNR is 92 dB. The
HILO pin optimizes the output SNR for 10-bit and 12-bit
ADCs with 1 V p-p or 2 V p-p full-scale (FS) inputs.
Channels 1 and 2 are enabled through the EN12 pin while
Channels 3 and 4 are enabled through the EN34 pin. For VGA
only applications, the PrAs can be powered down, significantly
reducing power consumption.
The preamplifier (PrA) has a single-ended to differential gain
of ×8 (18.06 dB) and accepts input signals ≤ 625 mV p-p. PrA
noise is 1.2 nV/√Hz and the combined input referred voltage
noise of the PrA and VGA is 1.3 nV/√Hz at maximum gain.
The AD8335 is available in a 64-lead lead frame chip scale
(9 mm × 9 mm) package for the industrial temperature range
of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8335
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Stage ........................................................................... 19
VGA Noise .............................................................................. 19
Applications..................................................................................... 20
Ultrasound................................................................................... 20
Basic Connections...................................................................... 21
Preamp Connections.................................................................. 21
Input Overdrive .......................................................................... 23
Input Overload Protection.................................................... 23
Logic Inputs................................................................................. 23
Common-Mode Pins ................................................................. 23
Driving ADCs............................................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide........................................................................... 24
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 15
Theory of Operation ...................................................................... 16
Enable Summary......................................................................... 16
Preamp......................................................................................... 17
Noise......................................................................................... 17
VGA.............................................................................................. 18
Optimizing the System Dynamic Range ............................. 18
Attenuator................................................................................ 18
Gain Control ........................................................................... 19
REVISION HISTORY
9/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8335
SPECIFICATIONS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, dBm (50 Ω), unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
PrA CHARACTERISTICS
Gain
Single-ended input to differential output
Single-ended input to single-ended output
PrA output limited to 5 V p-p differential
RFB = 249 Ω
18
12
625
50
dB
dB
mV p-p
Ω
Input Voltage Range
Input Resistance
RFB = 374 Ω
75
Ω
RFB = 499 Ω
RFB = ∞, low frequency value into PIPx
PIPx (Pins 2, 15, 18, 63)
With RFB = 249 Ω
RS = 0 Ω, RFB = ∞
100
14.7
1.5
110
1.15
2.4
Ω
kΩ
pF
MHz
nV/√Hz
pA/√Hz
Input Capacitance
−3 dB Small Signal Bandwidth
Input Voltage Noise
Input Current Noise
Noise Figure
Active Termination Match
Unterminated
RS = RIN = 50 Ω, RFB = 249 Ω
RS = 50 Ω, RFB = ∞
7
4.4
dB
dB
PrA + VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth
Unterminated: RS = 50 Ω, RFB = ∞
Matched: RS = RIN = 50 Ω
LO gain, VGN = 3 V, VOUT = 2 V p-p
HI gain, VGN = 3 V, VOUT = 2 V p-p
Pins VGNx = 3 V, RS = 0 Ω, RFB = ∞
Pins VGNx = 3 V, f = 1 MHz to 10 MHz
RS = RIN = 50 Ω
70
85
250
350
1.3
MHz
MHz
V/µs
V/µs
Slew Rate
Input Voltage Noise
Noise Figure
Active Termination Match
nV/√Hz
7
dB
RS = RIN = 100 Ω
RS = 50 Ω, RFB = ∞
RS = 500 Ω, RFB = ∞
LO gain; VGN < 2 V
4.5
5.0
1.3
33
80
5
1.2
VS/2
5
dB
dB
dB
nV/√Hz
nV/√Hz
V p-p
Ω
V
mV
Unterminated
Output Referred Noise
HI gain; VGN < 2 V
Peak Output Voltage
Output Resistance
Common-Mode Level
Output Offset Voltage
Differential, RL ≥ 500 Ω
f < 1 MHz, Pins VOHx, VOLx
Set to midsupply for PrA and VGA
Differential (VOHx−VOLx) full gain range
Common-mode (VOHx−VCMx, VOLx−VCMx)
VOUT = 1 V p-p, LO gain, VGN = 2 V
f = 1 MHz
f = 1 MHz
f = 10 MHz
f = 10 MHz
−25
−20
35
20
0
mV
Harmonic Distortion
HD2
HD3
HD2
−69
−57
−57
−55
dBc
dBc
dBc
dBc
HD3
Harmonic Distortion
HD2
VOUT = 1 V p-p, HI gain, VGN = 2 V
f = 1 MHz
−58
−70
−55
−55
18
dBc
dBc
dBc
dBc
dBm
dBVpk
HD3
HD2
HD3
f = 1 MHz
f = 10 MHz
f = 10 MHz
VGN = 3 V
Output 1 dB Compression (OP1dB)
VGN = 3 V
8
Rev. 0 | Page 3 of 24
AD8335
Parameter
Conditions
Min
Typ
Max
Unit
Two-Tone IMD3 Distortion
VOUT = 1 V p-p, VGN = 3 V
f1 = 1 MHz, f2 = 1.05 MHz
f1 = 10 MHz, f2 = 10.05 MHz
VOUT = 1 V p-p, VGN = 3 V
f = 1 MHz
−69
−65
dBc
dBc
Output IP3 (OIP3)
33
31
−80
10
dBm
dBm
dBc
ns
f = 10 MHz
Channel-to-Channel Crosstalk
Overload Recovery
VOUT = 1 V p-p, f = 1 to 10 MHz
Pra or VGA
Group Delay Variation
GAIN CONTROL INTERFACE
Normal Operating Range
Maximum Range
Full gain range, f = 1 MHz to 10 MHz
Pins VGNx
3.0
ns
0
0
3
VS
V
V
No gain foldover
Gain Range
LO gain mode; (Pins HLxx = 0 V)
HI gain mode; (Pins HLxx = VS)
Nominal (Pins SL12 and SL34 = 2.5 V)
−10 to +38
−2 to +46
20.0
−0.3
5
dB
dB
dB/V
µA
MHz
ns
Scale Factor
Bias Current
Response Bandwidth
Response Time
GAIN ACCURACY
Absolute Gain Error
19.0
21.0
48 dB gain change
350
Pins VGNx
0 ≤ VGN ≤ 0.4 V
1.25
7.5
dB
−1.25
−7.5
0.2
+1.25 dB
0.4 ≤ VGN ≤ 2.6 V, 1σ
2.6 ≤ VGN ≤ 3 V
−1.25 dB
Gain Law Conformance Over Temperature
Intercept
0.4 ≤ VGN ≤ 2.6 V; −40°C < TA < +85°C
LO gain mode; PrA matched to 50 Ω
HI gain mode; PrA matched to 50 Ω
0.4 ≤ VGN ≤ 2.6 V
0.75
−16.1
−8.1
dB
dB
dB
dB
Channel-to-Channel Matching
0.15
LOGIC LEVEL—HILO, SHUTDOWN PREAMP,
and ENABLE INTERFACES
Pins HLxx, SPxx, and ENxx
Logic Level High
Logic Level Low
2.75
0
5
1
V
V
BIAS CURRENT—HILO, ENABLE
Logic high
Logic low
80
−12
50
µA
µA
kΩ
INPUT RESISTANCE—HILO, ENABLE
BIAS CURRENT – SHUTDOWN PREAMP
Logic high
20
0
µA
µA
kΩ
µs
Logic low
INPUT RESISTANCE—SHUTDOWN PREAMP
HILO Response Time
Enable Response Time
POWER SUPPLY
500
0.6
100
µs
Pins VPPx and VPVx
Supply Voltage
4.5
16
5
19
5.5
V
Quiescent Current
Over Temperature
Quiescent Power
Quiescent Current
Quiescent Power
Quiescent Current
Disable Current
PSRR
Per channel—PrA and VGA enabled
−40°C < TA < +85°C
Per channel—PrA and VGA enabled
Per channel—PrA disabled, VGA enabled
Per channel—PrA disabled, VGA enabled
All channels enabled
mA
mA
mW
mA
mW
mA
mA
dB
22.8
95
13
65
76
0.8
−60
All channels disabled
VGN = 0 V, all bypass capacitors removed, 1 MHz
Rev. 0 | Page 4 of 24
AD8335
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Voltage
Supply VS
Preamp Input
VGA Inputs
Enable, Shutdown Preamp, and HILO
Interfaces
6 V
VS
VS
VS
Gain
VS
Power Dissipation (4-layer JEDEC Board (2S2P)) 2.46 W
θJA
26.4°C/W
θJC
6.8°C/W
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 s)
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 24
AD8335
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
IDENTIFIER
PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3 10
VIP3 11
POP3 12
PON3 13
VPP3 14
PIP3 15
1
2
3
4
5
6
7
8
9
48 GND1
47 VOH1
46 VOL1
45 VPV1
44 VPV2
43 VOL2
42 VOH2
41 GND2
40 GND3
39 VOH3
38 VOL3
37 VPV3
36 VPV4
35 VOL4
34 VOH4
33 GND4
AD8335
TOP VIEW
(Not to Scale)
PMD3 16
Figure 2. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
Pin No. Mnemonic Function
1
2
3
4
5
6
7
8
PMD2
PIP2
VPP2
PON2
POP2
VIP2
Preamp input common—Ch2
Preamp input—Ch2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND4
VOH4
VOL4
VPV4
VPV3
VOL3
VOH3
GND3
GND2
VOH2
VOL2
VPV2
VPV1
VOL1
VOH1
GND1
HL12
SL12
Ground VGA—Ch4
VGA output positive—Ch4
VGA output negative—Ch4
Positive supply VGA—Ch4
Positive supply VGA—Ch3
VGA output negative—Ch3
VGA output positive—Ch3
Ground VGA —Ch3
Positive supply preamp—Ch2
Preamp output negative—Ch2
Preamp output positive—Ch2
VGA input positive—Ch2
VGA input negative—Ch2
Ground preamp—Ch2
VIN2
COM2
COM3
VIN3
9
Ground preamp—Ch3
Ground VGA — Ch2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VGA input negative—Ch3
VGA input positive—Ch3
Preamp output positive—Ch3
Preamp output negative—Ch3
Positive supply preamp—Ch3
Preamp input—Ch3
Preamp input common—Ch3
Preamp input common—Ch4
Preamp input—Ch4
Positive supply preamp—Ch4
Preamp output negative—Ch4
Preamp output positive—Ch4
VGA input positive—Ch4
VGA input negative—Ch4
Ground preamp—Ch4
Gain control—Ch4
Common-mode decoupling pin—Ch4
Gain control—Ch3
Common-mode decoupling pin—Ch3
Enable—Ch3 and Ch4
Shutdown—preamp3 and preamp4
Slope decoupling pin—Ch3 and Ch4
HILO pin—Ch3 and Ch4
VGA output positive—Ch2
VGA output negative—Ch2
Positive supply VGA—Ch2
Positive supply VGA—Ch1
VGA output negative—Ch1
VGA output positive—Ch1
Ground VGA — Ch1
VIP3
POP3
PON3
VPP3
PIP3
PMD3
PMD4
PIP4
VPP4
PON4
POP4
VIP4
HILO pin—Ch1 and Ch2
Slope decoupling pin—Ch1 and Ch2
Shutdown—preamp1 and preamp2
Enable—Ch1 and Ch2
Common-mode decoupling pin—Ch2
Gain control—Ch2
Common-mode decoupling pin—Ch1
Gain control—Ch1
Ground preamp—Ch1
VGA input negative—Ch1
VGA input positive—Ch1
Preamp output positive—Ch1
Preamp output negative—Ch1
Positive supply preamp—Ch1
Preamp input—Ch1
SP12
EN12
VCM2
VGN2
VCM1
VGN1
COM1
VIN1
VIN4
COM4
VGN4
VCM4
VGN3
VCM3
EN34
SP34
SL34
VIP1
POP1
PON1
VPP1
PIP1
HL34
PMD1
Preamp input common—Ch1
Rev. 0 | Page 6 of 24
AD8335
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, unless otherwise noted.
50
40
20
18
16
14
12
10
8
420 CHANNELS
(105 UNITS)
GAIN
+85°C
V
= 1.5V
HI GAIN
30
20
LO GAIN
+25°C
10
–40°C
6
0
4
–10
–20
2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
–0.6 –0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5 0.6
GAIN ERROR (dB)
V
(V)
GAIN
Figure 3. Gain vs. VGAIN at Three Temperatures (See Figure 49)
Figure 6. Gain Error Histogram
2.0
1.5
25
420 CHANNELS
(105 UNITS)
= 1.0V
20
15
10
5
V
GAIN
1.0
+85°C, LO GAIN
+85°C, HI GAIN
0.5
0
+25°C, LO GAIN
0
25
20
15
10
5
–40°C, LO GAIN
+25°C, HI GAIN
–0.5
–1.0
–1.5
–2.0
V
= 2.0V
GAIN
CH1 TO CH2
CH1 TO CH4
CH1 TO CH3
–40°C, HI GAIN
0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
GAIN
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
Figure 4. Gain Error vs. VGAIN at Three Temperatures (See Figure 49)
Figure 7. Gain Match Histogram for VGAIN = 1 V and 2 V
45
40
35
30
25
20
15
10
5
6.0
4.0
420 CHANNELS
(105 UNITS)
0.5V < V
< 2.5V
GAIN
2.0
0
5MHz
1MHz
20MHz
10MHz
–2.0
–4.0
–6.0
0
19.9
20.0
20.1
20.2
20.3
20.4
0
0.5
1.0
1.5
2.0
2.5
3.0
GAIN SCALING FACTOR
V
(V)
GAIN
Figure 8. Gain Scaling Factor Histogram for 0.5 V < VGAIN < 2.5 V
Figure 5. Gain Error vs. VGAIN at Various Frequencies (See Figure 49)
Rev. 0 | Page 7 of 24
AD8335
25
30
25
20
15
10
5
420 CHANNELS
(105 UNITS)
0.5V < V
< 2.5V
GAIN
R
= ∞
FB
20
15
10
5
R = 249Ω
FB
R
= 50Ω
= 10mV p-p
S
V
IN
0
–5
–10
0
–16.7 –16.6 –16.5 –16.4 –16.3 –16.2 –16.1 –16.0 –15.9 –15.8 –15.7 –15.6 –15.5
INTERCEPT (dB)
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 9. Intercept Histogram
Figure 12. Frequency Response for a Terminated and Unterminated
50 Ω Source (See Figure 49)
50
40
–10
V
= 1V p-p
OUT
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 3.0V
GAIN
V
V
= 2.5V
= 2.0V
GAIN
30
GAIN
20
V
= 1.5V
= 1.0V
GAIN
V
= 2V
GAIN
10
V
= 1V
GAIN
V
= 1V
V
GAIN
GAIN
V
= 3V
GAIN
0
V
V
= 0.5V
= 0V
GAIN
V
= 3V
GAIN
–10
V
= 2V
GAIN
GAIN
–20
100k
1M
10M
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
Figure 10. Frequency Response for Various Values of VGAIN (See Figure 49)
Figure 13. Channel-to-Channel Crosstalk vs. Frequency for
Various Values of VGAIN
50
80
70
60
50
40
30
20
10
0
V
= 3.0V
GAIN
40
30
V
V
= 2.5V
= 2.0V
GAIN
GAIN
V
= 1.5V
= 1.0V
GAIN
20
V
GAIN
GAIN
10
V
= 0.5V
= 0V
0
V
GAIN
–10
–20
100k
1M
10M
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
Figure 11. Frequency Response vs. Frequency for Various Values of VGAIN
,
Figure 14. Group Delay vs. Frequency
HILO = HI (See Figure 49)
Rev. 0 | Page 8 of 24
AD8335
25
20
1k
100
10
R
= 2.5kΩ
FB
+85°C, HI
+85°C, LO
15
R
R
= 1kΩ
10
FB
5
= 499Ω
FB
0
–5
–40°C, LO
–40°C, HI
–10
–15
–20
–25
+25°C, HI
+25°C, LO
R
= 249Ω
FB
R
= ∞, C = 0pF
SH
SH
R
= 49Ω, C = 22pF
SH
SH
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
1M
10M
1G
V
FREQUENCY (Hz)
GAIN
Figure 15. Differential Output Offset Voltage vs. VGAIN at Three Temperatures
Figure 18. Preamp Input Resistance vs. Frequency for
Various Values of RFB
25
20
50j
–V= 10mV p-p
IN
25j
100j
–20
–30
–40
–50
15
10
STOP
1GHz
5
0
17Ω
50Ω
150Ω
0Ω
–60
–5
–70
–80
–90
–10
–15
–20
–25
START
100kHz
100MHz
–75j
–100
–25j
0
0.5
1.0
1.5
2.0
2.5
3.0
100k
1M
10M
100M
V
(V)
–50j
FREQUENCY (Hz)
GAIN
Figure 16. Absolute Offset vs. VGAIN at Pins VOHx and VOLx
Relative to Pins VCMx
Figure 19. Smith Chart S11 vs. Frequency, 100 kHz to 1 GHz
100
10
1
250
200
150
V
= 10mV p-p
IN
R
R
= 0Ω
= ∞
S
VOHx
FB
VOLx
HILO = HI
HILO = LO
1.5
100
50
0
0.1
100k
0
0.5
1.0
2.0
2.5
3.0
1M
10M
FREQUENCY (Hz)
1G
V
(V)
GAIN
Figure 17. Output Resistance at Pins VOHx and VOLx vs. Frequency
Figure 20. Output Referred Noise vs. VGAIN (See Figure 50)
Rev. 0 | Page 9 of 24
AD8335
1.4
60
55
50
45
40
35
30
25
20
15
10
5
f = 10MHz
1.2
V
R
R
= 3.0V
= 0Ω
= ∞
GAIN
1.0
S
FB
0.8
0.6
0.4
0.2
0
0.1
0
1
10
FREQUENCY (MHz)
100
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
GAIN
Figure 21. Short-Circuit Input Referred Noise vs. Frequency at Maximum Gain
(See Figure 50)
Figure 24. Noise Figure vs. VGAIN for RS = RIN = 50 Ω
1k
–35
–40
–45
–50
–55
–60
–65
–70
f = 10MHz
V
V
= 1V p-p
= 1.5V
T = +85°C
OUT
GAIN
100
HILO = LO
HD2 HD3
10
T = +25°C
HILO = HI
HD2 HD3
1.0
T = –40°C
0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
200
400
600
800
1.0k 1.2k 1.4k 1.6k 1.8k 2.0k
(Ω)
V
(V)
GAIN
R
LOAD
Figure 22. Input Referred Noise vs. VGAIN at Three Temperatures
(See Figure 50)
Figure 25. Harmonic Distortion vs. RLOAD (See Figure 50)
10
–20
f = 1MHz, V
= 3V
GAIN
f = 10MHz
V
= 1V p-p
OUT
–30
–40
–50
–60
–70
–80
HILO = LO
HD3
HILO = HI,
HD3
1.0
R
THERMAL NOISE
ALONE
S
HILO = HI,
HD2
HILO = LO,
HD2
0.1
1
10
100
1k
0
10
20
30
(pF)
40
50
SOURCE RESISTANCE (Ω)
C
LOAD
Figure 23. Input Referred Noise vs. RS
Figure 26. Harmonic Distortion vs. CLOAD (See Figure 53)
Rev. 0 | Page 10 of 24
AD8335
–20
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
LO GAIN
= 1V p-p
HI GAIN
V = 1V p-p
OUT
V
OUT
f = 10MHz
f = 10MHz
f = 5MHz
f = 5MHz
f = 1MHz
f = 1MHz
1.5
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
2.0
2.5
3.0
V
(V)
V
(V)
GAIN
GAIN
Figure 27. HD2 vs. VGAIN at Three Frequencies, LO Gain (See Figure 53)
Figure 30. HD3 vs. VGAIN at Three Frequencies, HI Gain (See Figure 53)
–20
–35
LO GAIN
V
= 1V p-p
f = 1MHz
OUT
–40
–30
–40
–50
–60
–70
–80
–45
–50
f = 10MHz
2V p-p
–55
–60
–65
f = 5MHz
–70
1V p-p
0.5V p-p
–75
f = 1MHz
2.5
–80
0.5
0.5
1.0
1.5
2.0
3.0
1.0
1.5
2.0
2.5
3.0
V
(V)
GAIN
V
(V)
GAIN
Figure 28. HD3 vs. VGAIN at Three Frequencies, LO Gain (See Figure 53)
Figure 31. HD2 vs. VGAIN at Three Output Voltages, LO Gain (See Figure 53)
–20
–20
HI GAIN
f = 1MHz
V
= 1V p-p
OUT
–30
–30
–40
–50
–60
–70
–80
2V p-p
–40
f = 10MHz
1V p-p
–50
–60
–70
–80
–90
f = 5MHz
0.5V p-p
f = 1MHz
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
V
2.0
2.5
3.0
V
(V)
(V)
GAIN
GAIN
Figure 29. HD2 vs. VGAIN at Three Frequencies, HI Gain (See Figure 53)
Figure 32. HD3 vs. VGAIN, at Three Output Voltages, LO Gain (See Figure 53)
Rev. 0 | Page 11 of 24
AD8335
40
35
30
25
20
15
10
5
–35
–40
–45
–50
–55
–60
–65
V
= 1Vp-p
OUT
f = 1MHz
5MHz (HI)
5MHz (LO)
2V p-p
1V p-p
0.5V p-p
0
–70
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
V
(V)
GAIN
GAIN
Figure 33. HD2 vs. VGAIN at Three Output Voltages, HI Gain, f = 1 MHz
(See Figure 53)
Figure 36. Output Referred IP3 (OIP3) vs. VGAIN
–20
5
0
f = 1MHz
–30
f = 10MHz
HILO = LO
–40
–5
HILO = HI
–50
–10
–15
–20
–25
–30
2V p-p
–60
1V p-p
–70
0.5V p-p
–80
–90
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
V
(V)
GAIN
GAIN
Figure 34. HD3 vs. VGAIN at Three Output Voltages, HI Gain (See Figure 53)
Figure 37. Input P1dB (IP1dB) vs. VGAIN
0
V
V
= 1V p-p
= 3V
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
GAIN
10mV
100
90
IMD3 (HI)
IMD3 (LO)
10
0
10ns
50mV
1
10
100
FREQUENCY (MHz)
Figure 35. IMD3 vs. Frequency
Figure 38. Small Signal Pulse Response, LO Gain (See Figure 51)
Rev. 0 | Page 12 of 24
AD8335
2V
10mV
100
90
100
90
10
0
10
0
10ns
50mV
100mV
100µs
Figure 42. Small Signal Enable Response (See Figure 51)
Figure 39. Large Signal Pulse Response, LO Gain (See Figure 51)
2
C
= 47pF
= 22pF
V
= 2V
L
GAIN
C
C
2V
L
= 10pF
L
INPUT
100
1
0
90
C
= 0pF
L
–1
–2
10
0
INPUT IS NOT TO SCALE
10 20 30 40
1V
100µs
0
50
60
70
80
90
100
TIME (ns)
Figure 43. Large Signal Enable Response (See Figure 51)
Figure 40. Large Signal Pulse Response for Various Capacitive Loads,
CL = 0 pF, 10 pF, 20 pF, 47 pF Each Output (See Figure 51)
2V
1V
100
90
100
90
10
0
10
0
1µs
400ns
500mV
Figure 41. Gain Response, VGAIN Stepped from 0 V to3 V, VOUT = 2 V p-p
(See Figure 51)
Figure 44. Preamp Overdrive Recovery,
50 mV p-p to 1.5 V p-p at Preamp Input (Measured at Preamp Output)
Rev. 0 | Page 13 of 24
AD8335
95
90
85
80
75
70
65
60
1V
V
= 2.5V
GAIN
100
90
10
0
1µs
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 45. VGA Overdrive Recovery, 40 mV to 500 mV Input, VGAIN = 2.5 V
Figure 47. Quiescent Supply Current vs. Temperature
0
2V
–10
V
= 2.5V
GAIN
100
V
= 1.5V
GAIN
–20
–30
–40
–50
–60
–70
–80
90
V
= 0.5V
GAIN
10
0
V
= 0V
GAIN
500mV
1µs
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 48 HILO Response Time
Figure 46. PSRR vs. Frequency (All Bypass Capacitors Removed)
Rev. 0 | Page 14 of 24
AD8335
TEST CIRCUITS
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
SPECTRUM
ANALYZER
18nF
249Ω
237Ω
AD8335
0.1µF
0.1µF
AD8335
50Ω
0.1µF
0.1µF
0.1µF
28Ω
237Ω
28Ω
IN
1:1
49.9Ω
1:1
0.1µF
49Ω
22pF
0.1µF
0.1µF
22pF
Figure 49. Test Circuit for Gain and Bandwidth Measurements
Figure 50. Test Circuit Used for Noise Measurements
NETWORK ANALYZER
50Ω
50Ω
IN
OUT
50Ω
OSCILLOSCOPE
18nF
249Ω
18nF
249Ω
237Ω
28Ω
50Ω
AD8335
0.1µF
0.1µF
0.1µF
237Ω
AD8335
IN
0.1µF
0.1µF
1:1
49.9Ω
28Ω
237Ω
28Ω
50Ω
1:1
237Ω
28Ω
49.9Ω
50Ω
0.1µF
22pF
0.1µF
22pF
0.1µF
Figure 51. Test Circuit for Transient Measurements
Figure 52. Test Circuit Used for S11 Measurements
SPECTRUM
ANALYZER
18nF
249Ω
237Ω
50Ω
SIGNAL
AD8335
0.1µF
0.1µF
0.1µF
GENERATOR
IN
28Ω
237Ω
28Ω
LPF
1:1
50Ω
50Ω
0.1µF
22pF
Figure 53. Test Circuit Used for Distortion Measurements
Rev. 0 | Page 15 of 24
AD8335
THEORY OF OPERATION
Figure 54 is a simplified block diagram of a single channel. Each
channel consists of a low noise preamplifier (PrA) followed by a
VGA with a user-selectable gain of 20 dB or 28 dB. Channels are
enabled in pairs, Channels 1 and 2 and Channels 3 and 4. The
preamps are enabled by grounding Pins SPxx and powered
down by connecting them to the positive supply. The ENxx pins
are connected to the positive supply to enable the VGAs and the
overall channel. HILO configures VGA for a fixed gain of 20 dB
or 28 dB, with 0 V or 5 V applied to the HLxx pins, respectively.
Channels 1 and 2 share Pin HL12, and Channels 3 and 4 share
Pin HL34. The HLxx pins are typically hardwired to adjust the
VGA gain according to an ADC resolution of 12 bits for LO
gain and 10 bits for HI gain.
In the remainder of this document, the gain values are
rounded to −10 dB to +38 dB for LO gain mode and to
−2 dB to +46 dB for HI gain mode. If desired, Equation 1
can be used to calculate the gain at value of VGAIN
:
dB
(1)
Gain(dB) = 20 VGN + ICPT
V
where ICPT = −16.1 dB for LO gain mode with the preamp
input matched to 50 Ω (RFB = 250 Ω) and −10.1 dB for the
unmatched input case. For HI gain mode, these numbers
are −8.1 dB and −2.1 dB, respectively.
Power consumption is 95 mW/channel from a 5 V supply,
or 380 mW for all four channels. Power is distributed 35%
for the PrA, and 65% for the remainder of the circuit. The
preamps can be shut down via the SP12 and SP34 pins if a
user wants to use the VGAs only. However, to avoid
feedthrough around the preamp, feedback resistors should
not be installed.
The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the
preamplifiers are designed to be driven from a single-ended
signal source. Gain values are referenced from the single-ended
PrA input to the differential output of either the PrA or the
VGA. Again referring to Figure 54, the system gain is
distributed as listed in Table 4.
ENABLE SUMMARY
Table 5 summarizes the enable/shutdown logic and
resulting supply current.
Table 4. Channel Gain Distribution
LO Nominal Gain
(dB)
HI Nominal Gain
(dB)
Section
PrA
18.06
18.06
Attenuator
Output Amp 20
Aggregate −10.1 to +38.6
0 to −48.16
0 to −48.16
27.96
−2.14 to +46.02
Table 5. Control Pin Logic and Power Consumption
EN12
SP12
L
H
L
H
EN34
SP34
L
H
L
H
PrA12
On
Off
Off
Off
VGA12
On
On
Off
Off
PrA34
On
Off
Off
Off
VGA34
On
On
Off
Off
IS
H
H
L
H
H
L
76 mA
52 mA
0.8 mA
0.8 mA
L
L
+1
+1
VINx
PONx
INTERPOLATOR
OUTPUT AMP
20dB TO 28dB
VOHx
RFB
ATTENx
–48dB TO 0dB
PrA
18dB
PIPx
R
S
PMDx
+1
+1
VOLx
BIAS
+1
GAIN INTERFACE
VGNx SLxx
HILO
HLxx
POPx
VCMx
VIPx
ENxx
Figure 54. Simplified Block Diagram of Single Channel
Rev. 0 | Page 16 of 24
AD8335
PREAMP
the lower frequency limit is determined by the size of the ac-
coupling capacitors, and the upper limit is determined by the
preamplifier BW. Furthermore, the input capacitance and RS
limits the BW at higher frequencies.
Although the preamp signal path is fully differential, the design
is optimized for single-ended input drive and signal source
resistance matching. Thus, the negative input to the differential
preamplifier Pins PMDx must be ac-grounded to provide a
balanced differential signal at the PrA outputs. Detailed
information regarding the preamplifier architecture is found in
the LNA section of the AD8331/AD8332 data sheet.
1k
R
=
∞, C = 0pF
SH
SH
R
= 500Ω, R = 2.5kΩ
FB
IN
The preamplifier consists of a fixed gain amplifier with differen-
tial outputs. With the negative output available and a fixed gain
of 8 (18.06 dB), an active input termination is synthesized by
connecting a feedback resistor between the negative output and
the positive input, Pin PIPx. This technique is well known and
results in the input resistance shown in Equation 2.
R
= 200Ω, R = 1kΩ
FB
IN
R
= 50Ω, C = 22pF
SH
SH
100
R
= 100Ω, R = 499Ω
FB
IN
R
= 50Ω, R = 249Ω
IN
FB
R
=
∞, C = 0pF
SH
SH
R
= 50Ω, C = 22pF
SH
SH
RFB
RIN
=
(2)
10
100k
A
(1 +
)
1M
10M
50M
2
FREQUENCY (Hz)
where A/2 is the single-ended gain, or the gain from the PIPx
Figure 55. RIN vs. Frequency for Various Values of RFB
.
inputs to the PONx outputs. Since the amplifier has a gain of ×8
from its input to its differential output, it is important to note
that the gain A/2 is the gain from Pin PIPx to Pin PONx, which
is 6 dB lower, or 12.04 dB (×4). The input resistance is reduced
by an internal bias resistor of 14.7 kΩ in parallel with the source
resistance connected to Pin PIPx, with Pin PMDx ac-grounded.
Equation 3 can be used to calculate the needed RFB for a desired
RIN, and is used for higher values of RIN.
Effects of RSH and CSH are also shown.
Figure 55 shows RIN vs. frequency for various values of RFB. Note
that at the lowest value, 50 Ω, RIN peaks at frequencies greater
than 10 MHz. This is due to the BW roll-off of the PrA as
mentioned earlier. The RSH and CSH network shown in Figure 58
reduces this peaking.
However, as can be seen for larger RIN values, parasitic
capacitance starts rolling off the signal BW before the PrA can
produce peaking and the RSH/CSH network further degrades the
match. Therefore RSH and CSH should not be used for values of
RIN greater than 50 Ω.
RFB
(1+ 4)
RIN
=
||14.7kΩ
(3)
For example, to set RIN = 200 Ω, the value of RFB is 1.013 kΩ. If the
simplified Equation 2 is used to calculate RIN, the value is 197 Ω,
resulting in a less than 0.1 dB gain error. Factors such as a
widely varying source resistance might influence the absolute
gain accuracy more significantly. At higher frequencies, the
input capacitance of the PrA needs to be considered. The user
must determine the level of matching accuracy and adjust RFB
accordingly.
Noise
The total input referred noise (IRN) is approximately 1.3
nV/√Hz. Allowing for a gain of ×8 in the preamp, the VGA
noise is 0.46 nV/√Hz referred to the PrA input. The preamp
noise is 1.2 nV/√Hz. It is important to note that these noise
values include all amplifier noise sources, including the VGA
and the preamplifier gain resistors. Frequently, manufacturer
noise specifications exclude gain setting resistors, and the
voltage noise spectral density of an op amp might be presented
as 1 nV/√Hz. Including the gain resistors results in a much
higher noise specification.
The bandwidths (BW) of the preamplifier and VGA are
approximately 110 MHz each, resulting in a cascaded BW of
approximately 80 MHz. Ultimately the BW of the PrA limits the
accuracy of the synthesized RIN. For RIN = RS up to approximately
200 Ω, the best match is between 100 kHz and 10 MHz, where
Rev. 0 | Page 17 of 24
AD8335
Optimizing the System Dynamic Range
Figure 56 shows the simulated noise figure (NF) vs. source
resistance, and various values of preamplifier RIN from 50 Ω, to
14.7 kΩ, the value seen looking into Pins PIPx when RFB = ∞. As
shown in the figure, the minimum NF for RIN = 50 Ω is slightly
less than 7 dB. Note that, for this preamplifier, the NF is
optimized for the RIN from 50 Ω to 200 Ω; for RFB = ∞, the
minimum NF is at approximately 480 Ω. This optimum noise
resistance can also be calculated by dividing the input referred
voltage noise by the current noise.
The VGA output gain switch of 8 dB (×2.5) optimizes the VGA
noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC
input voltage of 1 V p-p.
At low gain the ADC SNR should limit the system noise per-
formance, while at high gains the noise is defined by the source
and preamplifier. The maximum voltage swing is bounded by
the full-scale peak-to-peak ADC input voltage (typically 1 V p-p
to 2 V p-p). The noise performance is optimized by adjusting
the noise floor of the VGA according to the ADC resolution.
The SNR of a 12-bit converter is theoretically 12 dB better than
a 10-bit; however, approximately 8 dB is typical in practice,
accounting for the 8 dB gain option of the AD8335. The IRN
and the power consumption of the VGA are unaffected by
either gain setting; therefore, only the output referred noise
(ORN) changes (by 8 dB) without affecting any other
parameters.
16
R
R
= 50Ω
FB
INCLUDES NOISE OF VGA
f = 1MHz
IN
= 250Ω
14
12
10
8
R
R
= 75Ω
= 375Ω
IN
FB
R
R
= 100Ω
= 500Ω
IN
FB
6
Attenuator
4
R
= 200Ω
= 1kΩ
IN
The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB – 6.02 dB per tap. The effective input
resistance per side is 320 Ω nominally for a total differential
resistance of 640 Ω. The common-mode voltage of the attenuator
and the VGA is controlled by an amplifier that uses the same
midsupply voltage derived in the preamplifier, permitting dc
coupling of the PrA to the VGA without introducing large
offsets due to common-mode differences. However, when dc
coupling between the PrA and VGA, any offset from the PrA
are amplified as the gain is increased, producing an exponentially
increasing VGA output offset. When the PrA and the VGA are
ac-coupled, the output offset is unchanged with changes in gain
(see Figure 15). As a result, ac coupling is recommended for
most applications. As can be seen from Figure 54, Pins VCMx
connect to the respective midpoints on each channel and are
used to ac decouple the common-mode node at high frequencies.
It is very important that at least a 0.1 µF capacitor be used, with
better decoupling at higher frequencies when another smaller
capacitor (10 nF) is connected in parallel. The internal +1 buffer
provides correct common-mode bias levels and any dynamic
currents have to be absorbed by the external decoupling
capacitors.
R
FB
2
R
R
= 14.7kΩ
= ∞
IN
SIMULATION
FB
0
10
100
1k
R
(Ω)
S
Figure 56. Simulated Noise Figure vs. RS for
Various Fixed Values of RIN, Actively Matched
VGA
As seen in Figure 54, the basic architecture, an X-AMPTM,
consists of a ladder attenuator, followed by a fixed-gain
amplifier with selectable input stages. Earlier examples of this
architecture are to be found in the AD60x series, AD8331/
AD8332, and AD8367 VGAs. Through a proprietary, tempera-
ture-compensated interpolator design, the bias currents to the
input gm stages are continuously steered from right to left
(decreasing attenuation) resulting in increasing gain.
The HILO (HL12 and HL34) gain pins select one of two output
amplifier networks consisting of the feedback resistors, amplifier
stages, and buffers.
Rev. 0 | Page 18 of 24
AD8335
dynamic range, and the common-mode level is maintained
Gain Control
automatically at half the supply voltage for maximum signal
swing. The differential signal has the added benefit of suppress-
ing the even order harmonics.
The gain control interface has two inputs, VGAIN (Pins VGNx)
and VSLP (Pins SLxx). The slope input is intended only as a
decoupling pin, and the only guaranteed gain slope is the
20 dB/V default. However, if a voltage is applied to the VSLP
inputs, the gain slope can be increased by reducing the slope
voltage. For example, if a voltage of 1.67 V is applied to Pins SLxx,
the gain slope changes to 30 dB/V. Use Equation 4 to calculate
the gain slope.
The output amplifier is designed to drive a nominal differential
load of 500 Ω or greater; the signal swing can be as large as
5 V p-p differential before clipping occurs. However, that distor-
tion increases before reaching the clipping level. Distortion is
shown in Figure 25 through Figure 34 for typical values of
1 V p-p or 2 V p-p (full-scale inputs for many ADCs). The
output is ac-coupled to a differential anti-alias filter driving a
differential ADC. Most modern ADCs have differential inputs
and achieve optimum performance when driven differentially.
For more information, see the Applications section.
VGA Noise
2.5 V× 20 dB/V
VSLP =
(4)
Slope
VGAIN varies the gain of the VGA through the interpolator by
selecting the appropriate input stages connected to the input
attenuator. The nominal VGAIN range for 20 dB/V is 0 V to 3 V,
with the best gain-linearity from approximately 0.5 V to 2.5 V,
where the error is typically less than 0.2 dB. For VGAIN voltages
above 2.5 V and less than 0.5 V, the error increases (see Figure 4).
The value of the VGAIN voltage can be increased to that of the
supply voltage, without gain foldover.
As with all X-AMPs, the output noise of the VGA is constant
with gain. This causes the input referred noise to increase as the
gain is decreased. This characteristic is desirable in receiver
applications where wide dynamic range input signals are com-
pressed with a fixed ceiling and noise floor into an ADC. The
VGA output noise is approximately 33 nV/√Hz in LO gain
mode and 2.5 times higher than this, 83 nV/√Hz, in HI gain
mode. As the gain increases, the noise of the preamplifier prevails
and, at the maximum VGA gain, the output noise is approxi-
mately 90 nV/√Hz and 225 nV/√Hz for LO and HI gain modes,
respectively.
Each channel has separate gain control pins that can be
connected to a common voltage-source such as found in most
ultrasound applications. For control of individual channels,
connect the appropriate gain control signal to each channel.
Output Stage
Duplicate output stages of the VGA provide an 8 dB (×2.5) gain
switch. The gain switch is intended to optimize the output noise
floor for either a 10-bit or 12-bit ADC. The VGA gain is 20 dB
(×10) in LO gain mode and 28 dB (×25) in HI gain mode. The
logic setting of the HILO (Pins HLxx) selects between output
amplifiers including the gain resistors and feedback buffers.
The output SNR is determined by the noise floor and the largest
signal level, typically limited by the FS of the ADC. Modulation
noise, essentially the noise introduced by the gain control input,
can be troublesome. Normally one tends to look at the main
amplifier signal path for noise, but a VGA is really a multiplier
with the following function
V
GAIN ×VIN
VREF
100 MHz bandwidth is maintained between the amplifiers by
changing the compensation capacitance as the gain switches gain
settings. Power consumption is the same for either level of gain.
VOUT
=
(4)
where VREF (bias) and VGAIN (gain control interface) are both
In certain applications, power consumption can be reduced by
lowering the supply voltage as much as possible; however, the
output dynamic range is affected by the more limited swing. The
fully differential signal path of the AD8335 restores 6 dB of
noise contributors under certain conditions. It is therefore
important that the gain control signals be kept clean, especially
at higher gain control slopes.
Rev. 0 | Page 19 of 24
AD8335
APPLICATIONS
ULTRASOUND
Most modern machines use digital beamforming. In this
technique, the signal is converted to digital format immediately
following the TGC amplifier; beamforming is done digitally.
The primary application for the AD8335 is medical ultrasound.
Figure 57 shows a simplified block diagram of an ultrasound
system. The most critical function of an ultrasound system is
the time gain control (TGC) compensation for physiological
signal attenuation. Because the attenuation of ultrasound signals
is exponential with respect to distance (time), a linear-in-dB
VGA is the optimal solution.
Typical ADC resolution in general purpose machines is 10 bits
with sampling rates greater than 40 MSPS, while high end
systems use 12 bits.
Power consumption and low cost are of primary importance in
low-end and portable ultrasound machines, and the AD8335 is
designed for these criteria.
Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low
power, and differential drive to an ADC. Because ultrasound
machines use beamforming techniques requiring large binary
weighted numbers (for example, 32 to 512) of channels, the
lowest power at the lowest possible noise is of key importance.
For additional information regarding ultrasound systems, refer
to “How Ultrasound System Considerations Influence Front-
End Component Choice”, Analog Dialogue, Vol. 36, No. 3,
May–July 2003.
(http://www.analog.com/library/analogDialogue/archives/36-
03/ultrasound/index.html)
TX HV AMPs
BEAMFORMER
CENTRAL CONTROL
TX BEAMFORMER
MULTICHANNEL
TGC USES MANY VGAs
VGAs
AD8335
HV
Rx BEAMFORMER
(B AND F MODES)
T/R
MUX/
LNAs
SWITCHES
DEMUX
TGC
TRANSDUCER
TIME GAIN COMPENSATION
ARRAY
128, 256 ETC.
ELEMENTS
CW (ANALOG)
BEAMFORMER
IMAGE AND
MOTION
PROCESSING
(B MODE)
SPECTRAL
DOPPLER
PROCESSING
MODE
COLOR
BIDIRECTIONAL
CABLE
DOPPLER (PW)
PROCESSING
(F MODE)
AUDIO
OUTPUT
DISPLAY
Figure 57. Simplified Ultrasound System Block Diagram
Rev. 0 | Page 20 of 24
AD8335
BASIC CONNECTIONS
Figure 58 shows the basic connections for the AD8335. Input
signals enter from the left and output signals exit from the right,
providing straight-line signal paths. Of course, a device with
four differential VGAs such as this requires a multilayer printed
circuit board. Power supply isolation is shown for the preamps,
and for the VGA sections. If components are mounted to both
sides of the board, those in the signal path should be located on
the top, with power-supply decoupling components on the
wiring side.
Table 6. Feedback Resistor Values for Various Input Resistances
RIN (Ω)
Exact RFB Value (Ω)
Nearest Standard 1% Value (Ω)
200
500
1000
1014
2588
5365
1.02k
2.61k
5.36k
5× RIN
RFB (Ω) =
(5)
RIN
1 −
14.7 k
PREAMP CONNECTIONS
To configure the AD8335 for input matching a feedback resistor
(RFB) is ac-coupled between Pin PONx and Pin PIPx. AC coupling
accommodates dissimilar common-mode voltages at the input
and output ports. For values of RSOURCE between 50 Ω and 200 Ω,
RFB is simply 5 × RSOURCE. Table 6 lists a few larger values of source
resistor (or RIN), along with the exact value and nearest standard
1% feedback resistor. For values other those than listed in Table 6,
RFB can be calculated using Equation 5. For values larger than
1 kΩ, it may be advantageous to simply remove RFB.
Rev. 0 | Page 21 of 24
AD8335
+5V
0.1µF
VGN1
VGN2
SL12
0.1µF
H
R
1
FB
PIP1
0.1µF
0.1µF
0.1µF 249Ω
R
1
1nF* 0.1µF 1nF* 0.1µF
SH
49.9Ω
C
1
L
SH
22pF
0.1µF
VPP
+5V
51 50
0.1µF
0.1µF
0.1µF
PIP2
57
49
VOH1
VOL1
64 63
62 61
60 59
58
56 55
54 53
52
R
2
SH
49.9
Ω
0.1µF
0.1µF
1
48
47
46
45
C
2
SH
PMD2
PIP2
GND1
VOH1
VOL1
VPV1
VPV2
VOL2
VOH2
GND2
GND3
VOH3
VOL3
VPV3
VPV4
VOL4
VOH4
GND4
R
2
+5V
FB
249Ω
22pF
2
3
120nH FB
VPP2
PON2
POP2
VIP2
VPP
4
VPV
0.1µF
5
44
43
42
41
40
39
38
37
36
35
34
33
0.1µF
0.1µF
6
0.1µF
0.1µF
VOL2
VOH2
7
VIN2
120nH FB
8
+5V
VPP
COM2
COM3
VIN3
AD8335
0.1µF
9
0.1µF
0.1µF
10
11
12
13
14
15
16
VOH3
VOL3
0.1µF
VIP3
0.1µF
POP3
PON3
VPP3
PIP3
VPV
R
3
FB
249Ω
0.1µF
0.1µF
VPP
0.1µF
VOL4
VOH4
0.1µF
PIP3
R
3
SH
49.9Ω
+5V
PMD3
0.1µF
C
3
SH
22pF
H
23
30
17
0.1µF
18
19 20
21 22
0.1µF
24 25 26 27 28
29
31 32
0.1µF
0.1µF
VPP
0.1µF
L
0.1µF
+5V
1nF*
1nF*
PIP4
0.1µF
R
4
SH
49.9Ω
R
4
FB
249Ω
0.1µF
VGN4
VGN3
SL34
C
4
SH
22pF
*SEE TEXT
Figure 58. Basic Connections for RIN = 50 Ω
The preamp PMD pins must be capacitively coupled to ground.
Although the preamplifier is a differential design, the PMD pins
are the internal input bias nodes and are made available for
bypassing only. These pins may not be used as signal inputs.
When synthesizing low values of RIN, the bandwidth of the
preamplifier produces some peaking at the high end of the
frequency response. The optional series RSHx/CSHx network
shown in Figure 58 flattens the response (see Figure 55). With a
50 Ω source, the resistor and capacitor values should be 49.9 Ω
and 22 pF. For RS values greater than 100 Ω, the network is not
needed. The circuit is stable in either scenario.
The PIPx inputs must be capacitively coupled from the signal
source because they have a nominal dc level of more than half
the supply voltage. AC coupling capacitors throughout the
circuit should be as large as possible for the application. Although
0.1 µF capacitors are shown in Figure 58 (and used in most
positions in the evaluation board), values of these capacitors
should be determined by the application. Capacitors used for
coupling PMDx and PIPx pins should be the same value.
The starred capacitors in Figure 58 (*) on the VGNx pins may
be removed when faster gain control signals are required.
Rev. 0 | Page 22 of 24
AD8335
LOGIC INPUTS
INPUT OVERDRIVE
The enable Pins EN12 and EN34, the preamp shutdown Pins SP12
and SP34, and the HILO Pins HL12 and HL34 are all logic inputs
of the AD8335. The enable inputs turn on and off each of the
corresponding pairs of channels; the preamp shutdown pins do
the same for the preamplifiers only; inputs HL12 and HL34 set
the HILO gain for Channels 1 and 2, and Channels 3 and 4,
respectively.
Excellent overload behavior is of primary importance in ultra-
sound. Both the preamplifier and VGA have built-in overdrive
protection and quickly recover after an overload event.
Input Overload Protection
As with any amplifier, voltage clamping prior to the inputs is
highly recommended if the application is subject to high
transient voltages.
Shutting down the preamplifiers allows use of the VGAs alone,
while reducing power consumption. The VGAs cannot be shut
down independently. The SPxx (shutdown preamp) pins are
logic high; thus the pins are grounded to enable the preamplifiers.
A block diagram of a simplified ultrasound transducer interface
is shown in Figure 59. A common transducer element serves the
dual functions of transmit and receive of ultrasound energy.
During the transmit phase, high voltage pulses are applied to
the ceramic elements. A typical T/R (transmit/receive) switch
may consist of four high voltage diodes in a bridge configuration.
Although they ideally block transmit pulses from the sensitive
receiver input, diode characteristics are not ideal, and resulting
leakage transients impinging on the PIPx inputs can be
problematic.
The pins can be enabled by connecting to the supply or to
ground for fixed enable or disable, or to the output of a logic
device. Be sure to check the data sheet of the device for voltage
and current requirements.
COMMON-MODE PINS
The common-mode Pins VCMx are provided for bypassing the
internal common-mode reference for each channel to ground.
They require a capacitor at each of the four pins and can neither
be connected together nor driven by an external source.
Since ultrasound is a pulse system, and time-of-flight is used to
determine depth, quick recovery from input overloads is essential.
Overload can occur in the preamp and the VGA. Immediately
following a transmit pulse, the typical VGA gains are low, and
the PrA is subject to overload from T/R switch leakage. With
increasing gain, the VGA can become overloaded from strong
echoes that occur with near field echoes and acoustically dense
materials, such as bone.
DRIVING ADCs
The AD8335 VGA is designed to drive 10-bit and 12-bit ADCs
with minimal extra components. Because the AD8335 is a single
supply 5 V part and many of the newest ADCs operate from a
3 V supply, dissimilar common-mode voltages exist between the
VGA output and the ADC input. This level shift is most easily
accommodated by ac coupling, especially if the signal is filtered,
as is the case in most ultrasound and communications
applications.
Figure 59 illustrates an external overload protection scheme. A
pair of back-to-back Schottky diodes is installed prior to installing
the ac-coupling capacitors. Although the BAS40 is shown, many
types are available and merit investigation by the user. With such
diodes, clamping levels of 0.5 V or less greatly enhance the
system overload performance.
When an anti-aliasing filter (AAF) is called for, it is advantageous
to implement a differential configuration. A fully differential
AAF requires approximately 1.5 times the number of components
than a single-ended filter, because the components that in the
single-ended case are tied to ground, now connect across the
differential signal path. Although the series components double,
the component count for the differential filter is more economical
when compared to simply building a pair of single-ended filters
requiring twice as many components.
+HV
RFB
PONx
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
Rs
PrA
18dB
PIPx
PMDx
3
POPx
2
1
TRANSDUCER
–HV
BAS40-04
Figure 59. Input Overload Protection
Rev. 0 | Page 23 of 24
AD8335
OUTLINE DIMENSIONS
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
4.85
4.70 SQ
4.55
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
(BOTTOM VIEW)
*
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-64)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8335ACPZ1
AD8335ACPZ-REEL1
AD8335ACPZ-REEL71
AD8335-EVAL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-64
CP-64
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Evaluation Board with AD8335ACP
CP-64
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04976–0–9/04(0)
Rev. 0 | Page 24 of 24
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