AD8337-EVALZ-SS [ADI]
General-Purpose, Low Cost, DC-Coupled VGA;
| 型号： | AD8337-EVALZ-SS |
| 厂家： | 
ADI |
| 描述： | General-Purpose, Low Cost, DC-Coupled VGA |
| 文件： | 总28页 (文件大小：954K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
General-Purpose, Low Cost,
DC-Coupled VGA
Data Sheet
AD8337
FEATURES
GENERAL DESCRIPTION
Low noise
Voltage noise = 2.2 nV/√Hz
Current noise = 4.8 pA/√Hz (positive input)
Wide bandwidth (−3 dB) = 280 MHz
Nominal gain range: 0 dB to 24 dB (preamp gain = 6 dB)
Gain scaling: 19.7 dB/V
The AD8337 is a low noise, single-ended, linear-in-dB, general-
purpose, variable gain amplifier (VGA) usable at frequencies
from dc to 100 MHz; the −3 dB bandwidth is 280 MHz.
Excellent bandwidth uniformity across the entire gain range
and low output referred noise make the AD8337 ideal for
gain trim applications and for driving high speed analog-to-
digital converters (ADCs).
DC-coupled
Single-ended input and output
High speed uncommitted op amp input
Supplies: +5 V, 2.5 V, or 5 V
Low power: 78 mW with 2.5 V supplies
Excellent dc characteristics combined with high speed make the
AD8337 particularly suited for industrial ultrasound, PET
scanners, and video applications. Dual-supply operation enables
gain control of negative going pulses, such as those generated
by photodiodes or photomultiplier tubes.
APPLICATIONS
Gain trim
PET scanners
The AD8337 uses the Analog Devices, Inc., exclusive X-AMP®
architecture with 24 dB gain range scaled to 19.7 dB/V,
referenced to VCOM.
High performance AGC systems
I/Q signal processing
Video
Industrial and medical ultrasound
Radar receivers
The AD8337 preamplifier is configured in a current feedback
architecture optimized for gains of 6 dB to 24 dB. The AD8337
is characterized by a noninverting preamplifier gain of 2× using a
pair of 100 Ω resistors. The attenuator has a range of 24 dB, and
the output amplifier has a fixed gain of 8× (18.06 dB). The lowest
nominal gain range is 0 dB to 24 dB and can be shifted up or down
by adjusting the preamplifier gain. Series connected AD8337
devices provide larger gain ranges, interstage filtering to suppress
noise and distortion, and nulling of offset voltages.
FUNCTIONAL BLOCK DIAGRAM
GAIN CONTROL
INTERFACE
GAIN
EIGHT SECTIONS
PREAMP
INPP
INPN
18dB
VOUT
PRAO
VCOM
Figure 1
Rev. D
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Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8337
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Single-Supply Operation and AC Coupling ........................... 19
Noise ............................................................................................ 19
Applications Information.............................................................. 20
Preamplifier Connections ......................................................... 20
Driving Capacitive Loads.......................................................... 20
Gain Control Considerations ................................................... 21
Thermal Considerations............................................................ 22
PSI (Ψ) ......................................................................................... 22
Board Layout............................................................................... 22
Evaluation Boards........................................................................... 23
Circuit Options........................................................................... 24
Output Protection ...................................................................... 24
Measurement Setup.................................................................... 25
Board Layout Considerations................................................... 25
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 14
Theory of Operation ...................................................................... 18
Overview...................................................................................... 18
Preamplifier................................................................................. 18
VGA.............................................................................................. 18
Gain Control ............................................................................... 18
Output Stage................................................................................ 19
Attenuator.................................................................................... 19
REVISION HISTORY
10/2016—Rev. C to Rev. D
2/2007—Rev. A to Rev. B
Changes to General Description Section and Figure 1 ............... 1
Change to Input Voltage Noise Parameter, Table 1...................... 3
Changes to Figure 2.......................................................................... 6
Changes to Typical Performance Characteristics Section........... 7
Changes to Preamplifier Section .................................................. 18
Deleted Bill of Materials Section, Table 5, and Table 6;
Renumbered Sequentially.............................................................. 27
Deleted Table 7................................................................................ 28
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 28
Changes to Figure 30, Figure 31, and Figure 32......................... 11
Changes to Single-Supply Operation and
AC Coupling Section ..................................................................... 19
Moved Noise Section to Page........................................................ 19
Changes to Ordering Guide.......................................................... 24
6/2006—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 3.............................................................................6
Changes to Figure 22, Figure 25, and Figure 26......................... 10
Changes to Figure 39 and Figure 40............................................. 13
Changes to Figure 74 and Figure 75............................................. 23
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide.......................................................... 25
9/2008—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Added Exposed Pad Note to Figure 2 and Table 3....................... 6
Changes to Figure 49...................................................................... 14
Changes to Evaluation Boards Section........................................ 23
Changes to Circuit Options Section............................................. 24
Changes to Output Protection Section........................................ 24
Changes to Measurement Setup Section ..................................... 25
Changes to Board Layout Considerations Section..................... 25
Changes to Bill of Materials Section ............................................ 27
Updated Outline Dimensions, Changes to Ordering Guide .... 29
9/2005—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
AD8337
SPECIFICATIONS
VS = ±±2. V, TA = ±.°C, preamplifier gain = +±, VCOM = GND, f = 10 MHz, CL = . pF, RL = .00 Ω, including a ±0 Ω snubbing resistor,
unless otherwise specified2
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
GENERAL PARAMETERS
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
VOUT = 10 mV p-p
VOUT = 1 V p-p
VOUT = 2 V p-p
VOUT = 1 V p-p
f = 10 MHz
f = 10 MHz
VGAIN = 0.7 V, RS = 50 Ω, unterminated
VGAIN = 0.7 V, RS = 50 Ω, shunt terminated with 50 Ω
VGAIN = 0.7 V (gain = 24 dB)
VGAIN = −0.7 V (gain = 0 dB)
DC to 10 MHz
280
100
625
490
2.2
4.8
8.5
14
MHz
MHz
V/μs
V/μs
nV/√Hz
pA/√Hz
dB
Input Voltage Noise
Input Current Noise
Noise Figure
dB
Output Referred Noise
34
21
1
nV/√Hz
nV/√Hz
Ω
Output Impedance
Output Signal Range
V
RL ≥ 500 Ω, VS = 2.5 V, +5 V
RL ≥ 500 Ω, VS = 5 V
VGAIN = 0.7 V (gain = 24 dB)
VCOM 1.3
VCOM 2.4
5
V
Output Offset Voltage
−25
+25
mV
DYNAMIC PERFORMANCE
Harmonic Distortion
HD2
VGAIN = 0 V, VOUT = 1 V p-p
f = 1 MHz
−72
−66
−62
−63
−58
−56
8.2
−9.4
−71
−57
−58
−45
34
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
ns
HD3
HD2
HD3
HD2
f = 10 MHz
f = 45 MHz
HD3
Input 1 dB Compression Point
VGAIN = −0.7 V, f = 10 MHz (preamp limited)
VGAIN = +0.7 V, f = 10 MHz (VGA limited)
Two-Tone Intermodulation Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz
VGAIN = 0 V, VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz
Output Third-Order Intercept
VGAIN = 0 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0 V, VOUT = 1 V p-p, f = 45 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f = 45 MHz
VGAIN = 0.75 V, VIN = 50 mV p-p to 500 mV p-p
1 MHz < f < 100 MHz, full gain range
28
35
26
50
Overload Recovery
Group Delay Variation
1
ns
Rev. D | Page 3 of 28
AD8337
Data Sheet
Parameter
Test Conditions/Comments
VS = ±± V
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Harmonic Distortion
HD2
VGAIN = 0 V, VOUT = 1 V p-p
f = 1 MHz
−8±
−7±
−90
−80
−7±
−76
14.±
−1.7
−74
−60
−64
−49
3±
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
ns
HD3
HD2
HD3
HD2
f = 10 MHz
f = 3± MHz
HD3
Input 1 dB Compression Point
VGAIN = −0.7 V, f = 10 MHz
VGAIN = +0.7 V, f = 10 MHz
Two-Tone Intermodulation Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz
VGAIN = 0 V, VOUT = 1 V p-p, f1 = 4± MHz, f2 = 46 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f1 = 4± MHz, f2 = 46 MHz
Output Third-Order Intercept
VGAIN = 0 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0 V, VOUT = 1 V p-p, f = 4± MHz
VGAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz
VGAIN = 0 V, VOUT = 2 V p-p, f = 4± MHz
VGAIN = 0.7 V, VIN = 0.1 V p-p to 1 V p-p
28
36
28
±0
Overload Recovery
ACCURACY
Absolute Gain Error
−0.7 V < VGAIN < −0.6 V
−0.6 V < VGAIN < −0.± V
−0.± V < VGAIN < +0.± V
0.± V < VGAIN < 0.6 V
0.6 V < VGAIN < 0.7 V
0.7 to 3.±
dB
−1.2± ±0.3±
−1.0 ±0.2±
−1.2± ±0.3±
−0.7 to −3.±
+1.2± dB
+1.0 dB
+1.2± dB
dB
GAIN CONTROL INTERFACE
Gain Scaling Factor
Gain Range
−0.6 V < VGAIN < +0.6 V
19.7
24
12.6±
dB/V
dB
dB
V
MΩ
μA
ns
Intercept
VGAIN = 0 V
No foldover
Input Voltage (VGAIN) Range
Input Impedance
Bias Current
Response Time
POWER SUPPLY
Supply Voltage
VS = ±2.± V
−VS
+VS
70
0.3
200
−0.7 V < VGAIN < +0.7 V
24 dB gain change
VPOS to VNEG (dual- or single-supply operation)
4.±
±
10
V
Quiescent Current
Power Dissipation
PSRR
Each supply (VPOS and VNEG)
No signal, VPOS to VNEG = ± V
VGAIN = 0.7 V, f = 1 MHz
10.±
1±.±
78
−40
23.±
mA
mW
dB
VS = ±± V
Quiescent Current
Power Dissipation
PSRR
Each supply (VPOS and VNEG)
No signal, VPOS to VNEG = 10 V
VGAIN = 0.7 V, f = 1 MHz
13.±
18.±
18±
−40
2±.±
mA
mW
dB
Rev. D | Page 4 of 28
Data Sheet
AD8337
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 2.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Voltage
Supply Voltage (VPOS, VNEG)
Input Voltage (INPx)
GAIN Voltage
±± V
VPOS, VNEG
VPOS, VNEG
8±± mW
Power Dissipation
(Exposed Pad Soldered to PCB)
Temperature
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, ±0 sec)
−40°C to +85°C
−±5°C to +150°C
300°C
Thermal Data, 4-Layer JEDEC Board
No Air Flow Exposed Pad Soldered to PCB
θJA
θJB
θJC
ΨJT
ΨJB
75.4°C/W
47.5°C/W
17.9°C/W
2.2°C/W
4±.2°C/W
Rev. D | Page 5 of 28
AD8337
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT 1
VCOM 2
INPP 3
INPN 4
8
7
6
5
VPOS
GAIN
VNEG
PRAO
AD8337
TOP VIEW
(Not to Scale)
NOTES
1. FOR BEST THERMAL PERFORMANCE,
EXPOSED PAD MUST BE SOLDERED
TO PCB.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
VGA Output.
1
2
VOUT
VCOM
Common Ground When Using Plus and Minus Supply Voltages. For single-supply operation, provide half the
positive supply voltage at the VPOS pin to VCOM pin.
3
INPP
Positive Input to Preamplifier.
4
INPN
Negative Input to Preamplifier.
5
PRAO
Preamplifier Output.
±
7
8
VNEG
GAIN
VPOS
Negative Supply (−VPOS for Dual Supply; GND for Single Supply).
Gain Control Input Centered at VCOM.
Positive Supply.
EP
Exposed Pad
For best thermal performance, exposed pad must be soldered to PCB.
Rev. D | Page ± of 28
Data Sheet
AD8337
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 2.5 V, TA = 25C, RL = 500 Ω, including a 20 Ω snubbing resistor, f = 10 MHz, CL = 2 pF, VIN = 10 mV p-p, preamp gain = 2× (6 dB),
noninverting configuration, unless otherwise noted.
60
50
40
30
20
10
0
30
25
20
15
10
5
500 UNITS
+85°C
+25°C
–40°C
V
V
V
= –0.4V
GAIN
GAIN
GAIN
= 0V
= +0.4V
0
–5
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
GAIN ERROR (dB)
Figure 6. Gain Error Histogram for Three Values of VGAIN
Figure 3. Gain vs. VGAIN at Three Temperatures
(See Figure 44)
50
40
30
20
10
0
2.0
1.5
500 UNITS
+85°C
–0.4V ≤ V
≤ +0.4V
GAIN
+25°C
–40°C
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0 20.1
GAIN SCALING (dB/V)
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
Figure 7. Gain Scaling Histogram
Figure 4. Gain Error vs. VGAIN at Three Temperatures
(See Figure 44)
50
40
30
20
10
0
2.0
1.5
f = 1MHz
f = 10MHz
f = 70MHz
f = 100MHz
f = 150MHz
500 UNITS
RELATIVE TO BEST FIT
LINE FOR 10MHz
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–800
12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13.0
INTERCEPT (dB)
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
Figure 5. Gain Error vs. VGAIN at Five Frequencies
(See Figure 44)
Figure 8. Intercept Histogram
Rev. D | Page 7 of 28
AD8337
Data Sheet
30
25
20
15
10
5
30
25
20
15
10
5
V
= 0V
GAIN
e
= 10mV p-p
IN
V
= +0.7
GAIN
V
V
= +0.5
= +0.2
GAIN
GAIN
V
= 0
GAIN
V
V
= –0.2
GAIN
GAIN
= –0.5
= –0.7
C
= 47pF
L
C
C
C
= 22pF
= 10pF
= 0pF
L
L
L
0
0
V
GAIN
–5
100k
–5
100k
1M
10M
FREQUENCY (Hz)
100M
500M
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 9. Frequency Response for Various Values of VGAIN
(See Figure 45)
Figure 12. Frequency Response for Three Values of CL
with a 20 Ω Snubbing Resistor (See Figure 45)
20
15
10
5
10
8
V
= +0.7
V
V
= ±2.5V
= ±5V
GAIN
S
S
V
V
= +0.5
= +0.2
GAIN
GAIN
V
= 0
GAIN
6
V
= –0.2
GAIN
0
4
V
= –0.5
= –0.7
GAIN
–5
–10
–15
V
GAIN
2
e
= 10mV p-p
1M
IN
0
100k
100k
10M
FREQUENCY (Hz)
100M
500M
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 10. Frequency Response for Various Values of VGAIN—Inverting Input
(See Figure 58)
Figure 13. Frequency Response—Preamp
(See Figure 46)
30
25
20
15
10
5
V
= 0V
GAIN
= 10mV p-p
e
IN
25
20
15
10
5
0
C
C
C
C
= 47pF
= 22pF
= 10pF
= 0pF
L
L
L
L
0
–5
–5
100k
–10
1M
1M
10M
100M
500M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Frequency Response for Three Values of CL
(See Figure 45)
Figure 14. Group Delay vs. Frequency
(See Figure 47)
Rev. D | Page 8 of 28
Data Sheet
AD8337
10
8
40
35
30
25
20
15
+85°C
+25°C
–40°C
V
= ±5V
S
6
4
2
0
–2
–4
–6
V
= ±2.5V
S
+85°C
–8
+25°C
–40°C
–10
–800
–600
–400
–200
0
200
400
600
800
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
V
(mV)
GAIN
GAIN
Figure 15. Offset Voltage vs. VGAIN at Three Temperatures
(See Figure 48)
Figure 18. Output Referred Noise vs. VGAIN at Three Temperatures
(See Figure 50)
80
25
500 UNITS
+85°C
+25°C
–40°C
V
V
V
= –0.4V
GAIN
GAIN
GAIN
70
60
= 0V
20
15
10
5
= +0.4V
50
40
30
20
10
0
0
–800
–15
–10
–5
0
5
10
15
20
25
–600
–400
–200
0
200
400
600
800
OUTPUT OFFSET VOLTAGE (mV)
V
(mV)
GAIN
Figure 16. Output Offset Voltage Histogram for Three Values of VGAIN
Figure 19. Short-Circuit, Input Referred Noise at Three Temperatures
(See Figure 50)
1k
7
V
R
= 0.7V
FB2
GAIN
= R
V
V
= ±2.5V
= ±5V
S
S
= 100Ω
FB1
6
5
4
3
2
1
0
100
10
1
PREAMP GAIN = –1
PREAMP GAIN = +2
0.1
1M
10M
FREQUENCY (Hz)
100M
500M
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 17. VGA Output Impedance vs. Frequency
(See Figure 49)
Figure 20. Short-Circuit, Input Referred Noise vs. Frequency at Maximum
Gain—Inverting and Noninverting Preamp Gain = −1 and +2
(See Figure 50)
Rev. D | Page 9 of 28
AD8337
Data Sheet
–40
–50
–60
–70
–80
10
f = 10MHz,
= 0.7V
HD3
HD2
V
GAIN
INPUT-REFERRED NOISE
1
R
THERMAL NOISE ALONE
S
0.1
0
5
10
15
20
25
30
35
40
45
50
1
10
100
1k
SOURCE RESISTANCE (Ω)
LOAD CAPACITANCE (pF)
Figure 21. Input Referred Noise vs. RS
(See Figure 61)
Figure 24. Harmonic Distortion vs. Load Capacitance
(See Figure 52)
35
30
25
20
15
10
5
–30
–40
–50
–60
–70
–80
50Ω SOURCE
WITH 50Ω SHUNT
TERMINATION AT INPUT
UNTERMINATED
1MHz
10MHz
35MHz
100MHz
–800
–600
–400
–200
0
200
400
600
800
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
V
(mV)
GAIN
GAIN
Figure 25. HD2 vs. VGAIN at Four Frequencies
(See Figure 52)
Figure 22. Noise Figure vs. VGAIN
(See Figure 51)
–30
–40
–50
–60
–70
–80
–40
1MHz
10MHz
35MHz
HD3 V = ±2.5V
V
V
= 1V p-p
S
OUT
HD3 V = ±5V
S
= 0V
GAIN
HD2 V = ±2.5V
S
100MHz
HD2 V = ±5V
S
–50
–60
–70
–80
–800
–600
–400
–200
0
200
400
600
800
0
200 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k
V
(mV)
GAIN
LOAD RESISTANCE (Ω)
Figure 26. HD3 vs. VGAIN at Four Frequencies
(See Figure 52)
Figure 23. Harmonic Distortion vs. RL and Supply Voltage
(See Figure 52)
Rev. D | Page 10 of 28
Data Sheet
AD8337
–30
50
40
30
20
10
0
V
V
V
= 2V p-p
= 1V p-p
= 0.5V p-p
OUT
OUT
OUT
–40
–50
–60
–70
–80
–90
LIMITED BY
MAXIMUM PREAMP
OUTPUT SWING
1MHz
10MHz
45MHz
70MHz
100MHz
V
= 1V p-p
OUT
TONES SEPARATED BY 100kHz
–800
–600
–400
–200
0
200
400
600
800
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
V
(mV)
GAIN
GAIN
Figure 27. HD2 vs. VGAIN for Three Levels of Output Voltage
(See Figure 52)
Figure 30. Output Referred IP3 (OIP3) vs. VGAIN
at Five Frequencies (See Figure 64)
–30
–40
–50
–60
–70
–80
–90
50
40
30
20
10
0
V
V
V
= 2V p-p
= 1V p-p
= 0.5V p-p
OUT
OUT
OUT
LIMITED BY
MAXIMUM PREAMP
OUTPUT SWING
1MHz
10MHz
45MHz
70MHz
V
V
= ±5V
S
= 1V p-p
OUT
100MHz
TONES SEPARATED BY 100kHz
–800
–600
–400
–200
0
200
400
600
800
–800
–600
–400
–200
0
200
400
600 800
V
(mV)
V
(mV)
GAIN
GAIN
Figure 28. HD3 vs. VGAIN for Three Levels of Output Voltage
(See Figure 52)
Figure 31. Output Referred IP3 (OIP3) vs. VGAIN, VS = 5 V
at Five Frequencies (See Figure 64)
20
15
10
5
–20
–30
–40
–50
–60
–70
–80
V
V
= 1V p-p
= 0V
OUT
V
V
= ±2.5V
= ±5V
S
S
PREAMP LIMITED
GAIN
TONES SEPARATED BY 100kHz
0
–5
–10
–15
V
V
= ±2.5V
= ±5V
S
S
1M
10M
100M
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
FREQUENCY (Hz)
Figure 29. IMD3 vs. Frequency
(See Figure 64)
Figure 32. Input Referred P1dB (IP1dB) vs. VGAIN
(See Figure 63)
Rev. D | Page 11 of 28
AD8337
Data Sheet
80
V
8
800
600
400
200
0
80
C
C
C
C
= 0pF
= 0.7V
L
L
L
L
GAIN
= 10pF
= 22pF
= 47pF
60
40
6
60
40
4
20
20
2
0
0
0
–200
–400
–20
–40
–60
–80
–20
–40
–2
–4
–6
–8
INPUT
INPUT
OUTPUT
OUTPUT
–600
–800
–60
–80
V
V
= ±2.5V
S
= 0.7V
GAIN
–20
–10
0
10
20
30
40
50
60
70
–20
–10
0
10
20
30
40
50
60
70
TIME (ns)
TIME (ns)
Figure 33. Small Signal Pulse Response
(See Figure 53)
Figure 36. Large Signal Pulse Response for Three Capacitive Loads
(See Figure 53)
800
600
400
200
0
80
80
60
8
C
C
C
C
= 0pF
V
= 0.7V
L
L
L
L
GAIN
= 10pF
= 22pF
= 47pF
60
6
INPUT
40
40
4
20
20
2
0
0
0
–200
–400
–20
–40
–60
–80
–20
–40
–2
–4
–6
–8
INPUT
OUTPUT
OUTPUT
–10
–600
–800
–60
–80
V
V
= ±5V
S
= 0.7V
GAIN
–20
–10
0
10
20
30
40
50
60
70
–20
0
10
20
30
40
50
60
70
TIME (ns)
TIME (ns)
Figure 34. Small Signal Pulse Response—Inverting Feedback
(See Figure 59)
Figure 37. Large Signal Pulse Response for Three Capacitive Loads, VS = 5 V
(See Figure 53)
800
600
400
200
0
80
0.8
0.6
V
= 0.7V
GAIN
60
V
OUT
40
0.4
0.2
20
0
0
–200
–400
–20
–40
–60
–80
–0.2
–0.4
–0.6
–0.8
INPUT
OUTPUT
–600
–800
V
GAIN
–20
–10
0
10
20
30
40
50
60
70
–0.5
0
0.5
1.0
1.5
2.0
TIME (ns)
TIME (µs)
Figure 38. Gain Response
(See Figure 54)
Figure 35. Large Signal Pulse Response
(See Figure 53)
Rev. D | Page 12 of 28
Data Sheet
AD8337
1.5
10
0
V
V
(V)
(V)
V
V
V
V
V
V
= +0.7V, V = ±2.5V
S
IN
OUT
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
V
= 0.7V
GAIN
= +0.7V, V = ±5V
S
= 0V, V = ±2.5V
S
1.0
0.5
= 0V, V = ±5V
S
–10
–20
–30
–40
–50
–60
–70
–80
= –0.7V, V = ±2.5V
S
= –0.7V, V = ±5V
S
0
–0.5
–1.0
–1.5
–0.3 –0.1 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
100k
1M
10M
100M
FREQUENCY (Hz)
TIME (µs)
Figure 39. Preamp Overdrive Recovery
(See Figure 55)
Figure 42. PSRR vs. Frequency of Negative Supply
(See Figure 60)
1.5
1.0
24
22
20
18
16
14
12
V
V
(V)
V
= 0.7V
IN
V
V
= ±5V
= ±2.5V
GAIN
S
S
(V)
OUT
0.5
0
–0.5
–1.0
–1.5
–0.3 –0.1 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
–50
–30
–10
10
30
50
70
90
TEMPERATURE (°C)
TIME (µs)
Figure 40. VGA Overdrive Recovery
(See Figure 56)
Figure 43. Quiescent Supply Current vs. Temperature
(See Figure 57)
10
0
V
V
V
V
V
V
= +0.7V, V = ±2.5V
S
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
= +0.7V, V = ±5V
S
= 0V, V = ±2.5V
S
= 0V, V = ±5V
S
–10
–20
–30
–40
–50
–60
–70
–80
= –0.7V, V = ±2.5V
S
= –0.7V, V = ±5V
S
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 41. PSRR vs. Frequency of Positive Supply
(See Figure 60)
Rev. D | Page 13 of 28
AD8337
Data Sheet
TEST CIRCUITS
NETWORK ANALYZER
NETWORK ANALYZER
OUT
IN
OUT
IN
50Ω
50Ω
50Ω
50Ω
AD8337
AD8337
3
4
+
453Ω
20Ω 453Ω
PrA
1
+
PrA
–
3
4
20Ω
49.9Ω
–
1
49.9Ω
56.2Ω
56.2Ω
5
7
100Ω
5
7
V
100Ω
GAIN
100Ω
100Ω
Figure 47. Group Delay
Figure 44. Gain and Gain Error vs. VGAIN
NETWORK ANALYZER
OSCILLOSCOPE
FUNCTION
GENERATOR
OUT
IN
OUT
CH1
CH2
50Ω
50Ω
50Ω
50Ω
50Ω
V
GAIN
DIFFERENTIAL
FET PROBE
7
453Ω
AD8337
AD8337
453Ω
50Ω
3
20Ω
3
4
+
PrA
–
+
PrA
–
49.9Ω
1
1
4
5
7
5
OPTIONAL
POSITIONS FOR
100Ω
100Ω
C
L
V
GAIN
100Ω
100Ω
Figure 45. Frequency Response
Figure 48. Offset Voltage
NETWORK ANALYZER
NETWORK ANALYZER
CONFIGURE TO
MEASURE Z
CONVERTED S11
IN
OUT
IN
50Ω
50Ω
50Ω
0Ω
AD8337
NC
AD8337
NC
20Ω 453Ω
3
3
4
+
PrA
–
0Ω
+
–
PrA
1
1
49.9Ω
49.9Ω
4
5
7
5
7
100Ω
100Ω
NC
453Ω
NC
100Ω
100Ω
Figure 49. Output Impedance vs. Frequency
Figure 46. Frequency Response—Preamp
Rev. D | Page 14 of 28
Data Sheet
AD8337
OSCILLOSCOPE
PULSE
GENERATOR
SPECTRUM ANALYZER
POWER
SPLITTER
OUT
CH1
CH2
IN
50Ω
50Ω
50Ω
0Ω
AD8337
AD8337
3
4
+
20Ω 453Ω
56.2Ω
PrA
1
3
4
+
PrA
–
0Ω
–
1
49.9Ω
49.9Ω
5
7
100Ω
5
7
0.7V
100Ω
100Ω
V
GAIN
100Ω
Figure 53. Pulse Response
Figure 50. Input Referred and Output Referred Noise
DUAL
FUNCTION
GENERATOR
OSCILLOSCOPE
POWER
SPLITTER
NOISE FIGURE METER
NOISE
SINE
WAVE
SQUARE
WAVE
CH1
CH2
INPUT
SOURCE
DRIVE
50Ω
50Ω
NOISE
SOURCE
V
GAIN
DIFFERENTIAL
FET PROBE
0Ω
7
AD8337
AD8337
3
20Ω 453Ω
3
4
+
PrA
–
+
0Ω
49.9Ω
(OR ∞)
NC
1
PrA
1
49.9Ω
4
–
5
5
7
100Ω
100Ω
V
GAIN
100Ω
100Ω
Figure 51. Noise Figure vs. VGAIN
Figure 54. Gain Response
SPECTRUM ANALYZER
INPUT
FUNCTION
GENERATOR
OSCILLOSCOPE
R
L
SIGNAL
GENERATOR
50Ω
CH2
OUTPUT
CH1
LOW-
50Ω
PASS
FILTER
NC
7
AD8337
AD8337
3
20Ω
+
PrA
49.9Ω
1
4
–
3
4
+
PrA
–
C
L
1
NC
49.9Ω
5
7
100Ω
5
V
GAIN
100Ω
100Ω
100Ω
100Ω
Figure 52. Harmonic Distortion
Figure 55. Preamp Overdrive Recovery
Rev. D | Page 15 of 28
AD8337
Data Sheet
FUNCTION
OSCILLOSCOPE
GENERATOR
POWER
SPLITTER
OSCILLOSCOPE
PULSE
GENERATOR
POWER
SPLITTER
OUTPUT
CH1
CH2
OUT
CH1
CH2
50Ω
50Ω
50Ω
50Ω
AD8337
AD8337
3
+
PrA
–
20Ω 453Ω
NC
1
20Ω 453Ω
3
4
+
PrA
–
49.9Ω
4
1
100Ω
56.2Ω
100Ω
5
100Ω
5
7
100Ω
100Ω
0.7V
Figure 56. VGA Overdrive Recovery
Figure 59. Pulse Response—Inverting Feedback
+SUPPLY TO NETWORK
ANALYZER BIAS PORT
NETWORK ANALYZER
BENCH
POWER SUPPLY
DMM
(+I)
OUT
50Ω
IN
50Ω
8
BYPASS
CAPACITORS
REMOVED FOR
MEASUREMENT
AD8337
VPOS
3
4
+
PrA
–
AD8337
DMM
(V)
1
3
4
+
PrA
1
DIFFERENTIAL
FET PROBE
49.9Ω
–
5
7
6
100Ω
5
7
DMM
(–I)
100Ω
100Ω
V
GAIN
100Ω
Figure 57. Supply Current
Figure 60. PSRR
SPECTRUM ANALYZER
NETWORK ANALYZER
IN
OUT
IN
50Ω
50Ω
50Ω
453Ω
AD8337
AD8337
3
4
+
PrA
–
3
4
+
PrA
–
20Ω
1
1
100Ω
100Ω
5
7
5
7
100Ω
100Ω
V
GAIN
V
100Ω
GAIN
Figure 58. Frequency Response—Inverting Feedback
Figure 61. Input Referred Noise vs. RS
Rev. D | Page 1± of 28
Data Sheet
AD8337
NETWORK ANALYZER
POWER SWEEP
SPECTRUM ANALYZER
22dB
OUT
IN
IN
50Ω
50Ω
50Ω
453Ω
AD8337
AD8337
3
+
PrA
–
20Ω
3
4
+
PrA
–
1
1
49.9Ω
4
5
7
5
7
100Ω
100Ω
V
0.7V
GAIN
100Ω
100Ω
Figure 63. IP1dB vs. VGAIN
Figure 62. Short-Circuit Input Noise vs. Frequency
SPECTRUM ANALYZER
INPUT
50Ω
+22dB
+22dB
–6dB
–6dB
–6dB
SIGNAL
GENERATOR
COMBINER
–6dB
AD8337
453Ω
3
4
+
PrA
–
20Ω
1
49.9Ω
SIGNAL
GENERATOR
5
7
100Ω
V
GAIN
100Ω
Figure 64. IMD and OIP3
Rev. D | Page 17 of 28
AD8337
Data Sheet
THEORY OF OPERATION
VPOS
8
R
= R
= 100Ω
FB1
FB2
INPP
INPN
+
+
+
3
4
5
18dB
(8x)
–
PrA
6dB
–
ATTENUATOR
–24dB TO 0dB
–
1
VOUT
R
G
749Ω
PRAO
FB2
R
GAIN
INTERFACE
INTERPOLATOR
BIAS
R
FB1
107Ω
2
6
7
VCOM
VNEG
GAIN
Figure 65. Circuit Block Diagram
the negative supply. For ease of adjustment, a trimmer network
can be used.
OVERVIEW
The AD8337 is a low noise, single-ended, linear-in-dB, general-
purpose variable gain amplifier (VGA) usable at frequencies up
to 100 MHz. It is fabricated using a proprietary Analog Devices
dielectrically isolated, complementary bipolar process. The
bandwidth is dc to 280 MHz and features low dc offset voltage
and an ideal nominal gain range of 0 dB to 24 dB. Requiring
about 15.5 mA, the power consumption is only 78 mW from
either a single +5 V or a dual 2.5 V supply. Figure 65 is the
circuit block diagram of the AD8337.
For larger gains, the overall noise is reduced if a low value of
RFB1 is selected. For values of RFB1 = 20 Ω and RFB2 = 301 Ω, the
preamp gain is 16× (24.1 dB), and the input referred noise is
approximately 1.5 nV/√Hz. For this value of gain, the overall
gain range increases by 18 dB; therefore, the gain range is 18 dB
to 42 dB.
VGA
This X-AMP, with its linear-in-dB gain characteristic
architecture, yields the optimum dynamic range for receiver
applications. Referring to Figure 65, the signal path consists of
a −24 dB variable attenuator followed by a fixed gain amplifier of
18 dB, for a total VGA gain range of −6 dB to +18 dB. With the
preamplifier configured for a gain of 6 dB, the composite gain
range is 0 dB to 24 dB.
PREAMPLIFIER
The uncommitted current feedback op amp included in the
AD8337 is used as a preamplifier to buffer the ladder network
attenuator of the X-AMP. As with any op amp, the gain is
established using external resistors, and the preamplifier is
specified with a noninverting gain of 6 dB (2×) and gain resistor
values of 100 Ω. Current feedback amplifiers exhibit many
properties dissimilar from more familiar voltage feedback
amplifiers. One of the more significant differences is the
asymmetrical input impedances between inverting and non-
inverting inputs where the noninverting input impedance is
much higher. The practical effects of this difference are that
current feedback amplifiers are more commonly used in
noninverting gain applications and applications requiring
higher slew rates or bandwidths. For a description of these
current vs voltage feedback amplifiers properties, refer to
Section 1 of the Op Amp Applications Handbook, 2005.
The VGA plus preamp, with 6 dB of gain, implements the
following exact gain law:
dB
V
Gain(dB) 19.7
V
GAIN
ICPT(dB)
where the nominal intercept (ICPT) = 12.65 dB.
The ICPT increases as the gain of the preamp is increased. For
example, if the gain of the preamp is increased by 6 dB, ICPT
increases to 18.65 dB. Although the previous equation shows
the exact gain law as based on statistical data, a quick estimation
of signal levels can be made using the default slope of 20 dB/V
for a particular gain setting. For example, the change in gain for
a VGAIN change of 0.3 V is 6 dB using a slope of 20 dB/V and
5.91 dB using the exact slope of 19.6 dB/V. This is a difference
of only 0.09 dB.
The preamplifier gain is increased using larger values of RFB2
,
trading off bandwidth and offset voltage. The value of RFB2 is to
be ≥100 Ω because the value and an internal compensation
capacitor determine the 3 dB bandwidth, and smaller values can
compromise preamplifier stability.
GAIN CONTROL
The gain control interface provides a high impedance input and is
referenced to the VCOM pin (in a single-supply application to
midsupply at [VPOS + VNEG]/2 for optimum swing). When dual
supplies are used, VCOM is connected to ground. The voltage on the
VCOM pin determines the midpoint of the gain range. For a ground
Because the AD8337 is dc-coupled, larger preamp gains increase
the offset voltage. The offset voltage can be compensated by
connecting a resistor between the INPN input and the supply
voltage. If the offset is negative, the resistor value connects to
Rev. D | Page 18 of 28
Data Sheet
AD8337
referenced design, the VGAIN range is from −0.7 V to +0.7 V with the
most linear-in-dB section of the gain control between −0.6 V and +0.6
V. In the center 80% of the VGAIN range, the gain error is typically less
than 0.2 dB. The gain control voltage can be increased or decreased to
the positive or negative rails without gain foldover.
e gain scaling factor (gain slope) is designed for 20 dB/V. This relatively
low slope ensures that noise on the GAIN input is not unduly
amplified. Because a VGA functions as a multiplier, it is important that
the GAIN input does not inadvertently modulate the output signal with
unwanted noise. Because of its high input impedance, a simple low-
pass filter can be added to the GAIN input to filter unwanted noise.
NOISE
The total input referred voltage and current noise of the positive
input of the preamplifier are about 2.2 nV/Hz and 4.8 pA/Hz. The
VGA output referred noise is about 21 nV/Hz at low gains. This
result is divided by the VGA fixed gain amplifier gain of 8× and
results in a voltage noise density of 2.6 nV/Hz referred to the
VGA input. This value includes the noise of the VGA gain setting
resistors as well. If this voltage is again divided by the preamp gain
of 2, the VGA noise referred all the way to the preamp input is
about 1.3 nV/Hz. From this, it is determined that the preamplifier,
including the 100 Ω gain setting resistors, contributes about 1.8
nV/Hz. The two 100 Ω resistors contribute 1.29 nV/Hz each at the
output of the preamp. With the gain resistor noise subtracted, the
preamplifier noise is approximately 1.55 nV/Hz.
OUTPUT STAGE
The output stage is a Class AB, voltage-feedback, complementary emitter-
follower with a fixed gain of 18 dB, similar to the preamplifier in speed
and bandwidth. Because of the ac-beta roll-off of the output devices
and the inherent reduction in feedback beyond the −3 dB bandwidth,
the impedance looking into the output pin of the preamp and output
stages appears to be inductive (increasing impedance with increasing
frequency). The high speed output amplifier used in the AD8337 can
drive large currents, but its stability is susceptible to capacitive
loading. A small series resistor mitigates the effects of capacitive
loading (see the Applications Information section).
Equation 2 shows the calculation that determines the output
referred noise at maximum gain (24 dB or 16×).
where:
At is the total gain from preamp input to VGA output.
RS is the source resistance.
en − PrA is the input referred voltage noise of the preamp.
in − PrA is the current noise of the preamp at the INPP pin.
ATTENUATOR
en −
is the voltage noise of RFB1.
The input resistance of the VGA attenuator is nominally 265 Ω. For
example, if the default preamplifier feedback network RFB1 + RFB2 is
200 Ω, the effective preamplifier load is approximately 114 Ω. The
attenuator is composed of eight 3.01 dB sections for a total
attenuation range of −24.08 dB. Following the attenuator is a fixed
gain amplifier with 8× (18.06 dB) gain. Because of this relatively low
gain, the output offset is kept well below 20 mV over temperature; the
offset is largest at maximum gain when the preamplifier offset is
amplified. The VCOM pin defines the common-mode reference for
the output, as shown in Figure 65.
R
R
FB1
en −
is the voltage noise of RFB2
.
FB2
e
n − VGA is the input referred voltage noise of the VGA (low gain,
output referred noise divided by a fixed gain of 8×).
Assuming RS = 0 Ω, RFB1 = RFB2 = 100 Ω, At = 16×, and AVGA
8×, the noise simplifies to
=
en − out
=
(1.7516)2 2(1.298)2 (1.98)2 35nV Hz (1)
Dividing the result by 16 gives the total input referred noise with
a short-circuited input as 2.2 nV/Hz. When the preamplifier is
SINGLE-SUPPLY OPERATION AND AC COUPLING
If the AD8337 is to be operated from a single 5 V supply, the bias
supply for VCOM must be a very low impedance 2.5 V reference,
especially if dc coupling is used. If the device is dc-coupled, the VCOM
source must be able to handle the preamplifier and VGA dynamic load
currents in addition to the bias currents.
used in the inverting configuration with the same RFB1 and RFB2
100 Ω as previously noted, en − out does not change. However,
because the gain dropped by 6 dB, the input referred noise
increases by a factor of 2 to about 4.4 nV/Hz. The reason for this
increase is that the noise gain to the output of the noise generators
stays the same, yet the preamp in the inverting configuration has a
gain of −1 compared to the +2 in the noninverting configuration;
this increases the input referred noise by 2.
=
When ac coupling the preamplifier input, a bias network and
bypass capacitor must be connected to the opposite polarity input
pin. The bias generator for the VCOM pin must provide the
dynamic current to the preamplifier feedback network and the
VGA attenuator. For many single 5 V applications, a reference, such
as the ADR391, and a good op amp provide an adequate VCOM
source if a 2.5 V supply is unavailable.
R
2
2
2
2
2
2
FB2
(2)
e
(e R A ) (en PrA A ) (in PrA R ) (e
n R
A
VGA
)
(e
n R
A
FB2
)
(en VGA A
VGA
)
n out
t
t
FB1
n
S
S
VGA
R
FB1
Rev. D | Page 19 of 28
AD8337
Data Sheet
APPLICATIONS INFORMATION
PREAMPLIFIER CONNECTIONS
Noninverting Gain Configuration
DRIVING CAPACITIVE LOADS
Because of the large bandwidth of the AD8337, stray capacitance at
the output pin can induce peaking in the frequency response as the
gain of the amplifier begins to roll off. Figure 68 shows peaking
with two values of load capacitance using 2.5 V supplies and
The AD8337 preamplifier is an uncommitted current feedback
op amp that is stable for values of RFB2 ≥ 100 Ω. See Figure 66
for the noninverting feedback connections.
VGAIN = 0 V.
PREAMPLIFIER
INPP
25
V
= 0V
GAIN
3
4
5
+
C
C
C
= 0pF
= 10pF
= 22pF
L
L
L
R
INPN
G
20
15
10
5
–
NO SNUBBING RESISTOR
PRAO
FB2
R
R
FB1
Figure 66. AD8337 Preamplifier Configured for Noninverting Gain
Two surface-mount resistors establish the preamplifier gain.
Equal values of 100 Ω configure the preamplifier for a 6 dB gain
and the device for a default gain range of 0 dB to 24 dB.
0
–5
100k
1M
10M
100M
500M
FREQUENCY (Hz)
For preamplifier gains ≥2, select a value of RFB2 ≥ 100 Ω and
Figure 68. Peaking in the Frequency Response for Two Values of Output
Capacitance with 2.5 V Supplies and No Snubbing Resistor
R
FB1 ≤ 100 Ω. Higher values of RFB2 reduce the bandwidth and
increase the offset voltage, but smaller values compromise
stability. If RFB1 ≤ 100 Ω, the gain increases and the input
referred noise decreases.
25
V
= 0V
GAIN
C
C
C
= 0pF
= 10pF
= 22pF
L
L
L
20
15
10
5
WITH 20Ω SNUBBING RESISTOR
Inverting Gain Configuration
For applications requiring polarity inversion of negative pulses, or
for waveforms that require current sinking, the preamplifier can
be configured as an inverting gain amplifier. When configured
with bipolar supplies, the preamplifier amplifies positive or
negative input voltages with no level shifting of the common-
mode input voltage required. Figure 67 shows the AD8337
configured for inverting gain operation.
0
Because the AD8337 is a very high frequency device, stability
issues can occur unless the circuit board on which it is used is
carefully laid out. The stability of the preamp is affected by
parasitic capacitance around the INPN pin. To minimize stray
capacitance position the preamp gain resistors, RFB1 and RFB2, as
close as possible to the INPN pin.
–5
100k
1M
10M
FREQUENCY (Hz)
100M
500M
Figure 69. Frequency Response for Two Values of Output Capacitance
with a 20 Ω Snubbing Resistor
In the time domain, stray capacitance at the output pin can
induce overshoot on the edges of transient signals, as shown in
Figure 70 and Figure 72. The amplitude of the overshoot is also a
function of the slewing of the transient (not shown in Figure 70
and Figure 72). The transition time of the input pulses used for
Figure 70 and Figure 72 is deliberately set high at 300 ps to demon-
strate the fast response time of the amplifier. Signals with longer
transition times generate less overshoot.
PREAMPLIFIER
INPP
3
4
5
+
R
INPN
FB1
–
PRAO
R
FB2
Figure 67. The AD8337 Preamplifier Configured for Inverting Gain
Rev. D | Page 20 of 28
Data Sheet
AD8337
800
80
800
600
80
V
= ±5V
S
600
60
60
400
200
40
400
200
40
20
20
C
C
C
= 0pF
= 10pF
= 22pF
L
L
L
0
0
0
0
NO SNUBBING RESISTOR
–200
–20
–40
–60
–80
INPUT
–200
–20
–40
–60
INPUT
–400
–600
–800
OUTPUT
–400 OUTPUT
–600
C
C
C
= 0pF
= 10pF
= 22pF
L
L
L
WITH 20Ω SNUBBING RESISTOR
–20 –10
0
10
20
30
40
50
60
70
80
–800
–80
80
TIME (ns)
–20 –10
0
10
20
30
40
50
60
70
TIME (ns)
Figure 70. Pulse Response for Two Values of Output Capacitance
with 2.5 V Supplies and No Snubbing Resistor
Figure 73. Pulse Response for Two Values of Output Capacitance
with 5 V Supplies and a 20 Ω Snubbing Resistor
800
80
The effects of stray output capacitance are mitigated with a
small value snubbing resistor, RSNUB, placed in series with, and
as near as possible to, the VOUT pin. Figure 69, Figure 71, and
Figure 73 show the improvement in dynamic performance with
a 20 ꢀ snubbing resistor. RSNUB reduces the gain slightly by the
ratio of RL/(RSNUB + RL), a very small loss when used with high
impedance loads, such as ADCs. For other loads, alternate values
of RSNUB can be determined empirically. The data for the curves in
the Typical Performance Characteristics section are derived using
a 20 Ω snubbing resistor.
600
60
400
200
40
20
0
0
–200
–20
–40
–60
–80
INPUT
–400 OUTPUT
–600
C
C
C
= 0pF
= 10pF
= 22pF
L
L
L
The best way to avoid the effects of stray capacitance is to
exercise care in the PCB layout. Locate the passive components
or devices connected to the AD8337 output pins as close as
possible to the package.
WITH 20Ω SNUBBING RESISTOR
–800
–20 –10
0
10
20
30
40
50
60
70
80
TIME (ns)
Figure 71. Pulse Response for Two Values of Output Capacitance
with 2.5 V Supplies and a 20 Ω Snubbing Resistor
Although a nonissue, the preamplifier output is also sensitive to
load capacitance. However, the series connection of RFB1 and
800
80
V
= ±5V
S
600
60
RFB2 is typically the only load connected to the preamplifier. If
overshoot appears, it can be mitigated by inserting a snubbing
resistor, the same way as the VGA output.
400
200
40
20
GAIN CONTROL CONSIDERATIONS
0
–200
–400
–600
–800
0
In typical applications, voltages applied to the GAIN input are dc
or relatively low frequency signals. The high input impedance of
the AD8337 enables several devices to be connected in parallel.
This is useful for arrays of VGAs, such as those used for calibra-
tion adjustments.
–20
–40
–60
–80
INPUT
OUTPUT
C
= 0pF
L
C = 10pF
L
C
= 22pF
L
WITH NO SNUBBING RESISTOR
Under dc or slowly changing ramp conditions, the gain tracks
the gain control voltage, as shown in Figure 3. However, it is often
necessary to consider other effects influenced by the VGAIN input.
–20 –10
0
10
20
30
40
50
60
70
80
TIME (ns)
Figure 72. Large Signal Pulse Response for Two Values of Output
Capacitance with 5 V Supplies and No Snubbing Resistor
Rev. D | Page 21 of 28
AD8337
Data Sheet
The offset voltage effect of the AD8337, as with all VGAs, can
appear as a complex waveform when observed across the range
of VGAIN voltage. Generated by multiple sources, each device has
a unique offset voltage (VOS) profile while the GAIN input is
swept through its voltage range. The offset voltage profile seen
in Figure 15 is a typical example. If the VGAIN input voltage is
modulated, the output is the product of the VGAIN and the dc
profile of the offset voltage. This is observed on a scope as a
small ac signal, as shown in Figure 74. In Figure 74, the signal
applied to the VGAIN input is a 1 kHz ramp, and the output voltage
signal is slightly less than 4 mV p-p.
Under certain circumstances, the product of VGAIN and the
offset profile plus spikes is a coherent spurious signal within the
signal band of interest and indistinguishable from desired
signals. In general, the slower the ramp applied to the GAIN
Pin, the smaller the spikes are. In most applications, these
effects are benign and not an issue.
THERMAL CONSIDERATIONS
The thermal performance of LFCSPs, such as the AD8337,
departs significantly from that of leaded devices such as the
larger TSSOP or QFSP. In larger packages, heat is conducted
away from the die by the path provided by the bond wires and
the device leads. In LFCSPs, the heat transfer mechanisms are
surface-to-air radiation from the top and side surfaces of the
package and conduction through the metal solder pad on the
mounting surface of the device.
10
V
= ±2.5V
INPUT
OUTPUT
S
8
6
4
2
θJC is the traditional thermal metric used for integrated circuits.
0
Heat transfer away from the die is a three-dimensional dynamic,
and the path is through the bond wires, leads, and the six
surfaces of the package. Because of the small size of LFCSPs, the
θJC is not measured conventionally. Instead, it is calculated using
thermodynamic rules.
–2
–4
–6
–8
–10
The θJC value of the AD8837 listed in Table 2 assumes that the
tab is soldered to the board and that there are three additional
ground layers beneath the device connected by at least four vias.
For a device with an unsoldered pad, the θJC nearly doubles,
becoming 138°C/W.
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
Figure 74. Offset Voltage vs. VGAIN for a 1 kHz Ramp
The profile of the waveform shown in Figure 74 is consistent
over a wide range of signals from dc to about 20 kHz. Above
20 kHz, secondary artifacts can be generated due to the effects
of minor internal circuit tolerances, as shown in Figure 75.
These artifacts are caused by settling and time constants of the
interpolator circuit and appear at the output as the voltage
spikes, as shown in Figure 75.
PSI (Ψ)
Table 2 lists a subset of the classic theta specification, ΨJT (Psi
junction to top). θJC is the metric of heat transfer from the die to
the case, involving the six outside surfaces of the package. Ψ(XY)
is a subset of the theta value and the thermal gradient from the
junction (die) to each of the six surfaces. Ψ can be different for
each of the surfaces, but since the top of the package is a fraction of
a millimeter from the die, the surface temperature of the package is
very close to the die temperature. The die temperature is calculated
as the product of the power dissipation and ΨJT. Since the top
surface temperature and power dissipation are easily measured, it
follows that the die temperature is easily calculated. For example,
for a dissipation of 180 mW and a ΨJT of 5.3°C/W, the die
temperature is slightly less than 1°C higher than the surface
temperature.
10
V
= ±2.5V
INPUT
S
8
6
OUTPUT
4
SPIKE
2
0
–2
–4
–6
–8
–10
SPIKE
BOARD LAYOUT
Because the AD8337 is a high frequency device, board layout is
critical. It is very important to have a good ground plane
connection to the VCOM pin. Coupling through the ground
plane, from the output to the input, can cause peaking at higher
frequencies.
–800
–600
–400
–200
0
200
400
600
800
V
(mV)
GAIN
Figure 75. VOS Profile for a 50 kHz Ramp
Rev. D | Page 22 of 28
Data Sheet
AD8337
EVALUATION BOARDS
The AD8337 evaluation boards provide a family of platforms for
testing and evaluating the AD8337 VGA. Three circuit configu-
rations are available:
AD8337-EVALZ, dc-coupled, with noninverting gain and
dual power supplies
AD8337-EVALZ-INV, dc-coupled, with inverting gain and
dual power supplies
AD8337-EVALZ-SS, ac-coupled, with noninverting gain
configuration and a single supply
These fully assembled and tested boards are ready to use. Only
the appropriate power supply and signal source connections
need to be made. SMA connectors are provided for the pream-
plifier and VGA outputs. Photos of fully assembled boards are
shown in Figure 76 and Figure 77. The board component side
layouts are shown in Figure 78 and Figure 79.
Figure 78. Assembly, Dual-Supply Evaluation Board
Figure 76. AD8337 Evaluation Board for Dual Supplies
Figure 79. Assembly, Single-Supply Evaluation Board
Schematic diagrams of the dual-supply board for noninverting
and inverting configurations are shown in Figure 80 and Figure 81.
The dual-supply boards require ±±.ꢀ V to ±ꢀ V supplies capable of
supplying ±0 mA or greater. A schematic diagram of the single-
supply board is shown in Figure 8±. The single-supply version
accepts a +ꢀ V to +10 V supply with ±0 mA or greater capability.
Figure 77. AD8337 Evaluation Board for Single Supply
Rev. D | Page 23 of 28
AD8337
Data Sheet
+V
–V
S
S
GND1 GND2 GND3 GND4
CIRCUIT OPTIONS
Part numbers for fully assembled boards are listed in Table 4.
+
C1
10µF
C2
RVO1
VOUT
+ 10µF
453Ω
Table 4. AD8337 Evaluation Board Variations
L2
120nH
L1
120nH
Part Number
Configuration
AD8337-EVALZ
AD8337-EVALZ-INV
AD8337-EVALZ-SS
Dual-supply noninverting
Dual-supply inverting
Single-supply noninverting
C3
TP1
1
2
3
4
8
7
6
5
VOUT
U1 VPOS
0.1µF
RVO3
GAIN
AD8337
VCOM
0Ω
GAIN
CG
1nF
R1
J1
49.9Ω
Figure 80, Figure 81, and Figure 82 are schematics for the
various circuit configurations. Within limits, the AD8337
preamplifier gain is controlled by Resistor RFB1 and Resistor
INPP
VNEG
PRAO
R4
IN
0Ω
INPN
C4
0.1µF
R2
49.9Ω
RFB2. For simple guidelines applying to the current feedback
RPO2
453Ω
R
FB2
100Ω
R5
100Ω
preamplifier, see the Theory of Operation section.
PRAO
R
100Ω
FB1
OUTPUT PROTECTION
DO NOT INSTALL PARTS IN GRAY
The AD8337 VGA output stage is specified for driving loads of
500 Ω or greater. To protect the stage from an accidental
overload, a 453 Ω resistor is provided, which when connected to
50 Ω test equipment inputs, enables safe operation. In certain
high load impedance situations, the value of this resistor can be
reduced. However, if load capacitance values greater than
approximately 20 pF are anticipated, such as a BNC cable, the
minimum series resistor value is not to be less than 20 Ω.
Figure 80. Schematic—AD8337-EVALZ Noninverting Configuration
+V
–V
S
S
GND1 GND2 GND3 GND4
+
+
C2
10µF
C1
10µF
RVO1
453Ω
VOUT
L2
120nH
L1
120nH
C3
TP1
1
2
3
4
8
7
6
5
VOUT
U1 VPOS
0.1µF
An alternate test pin is also provided for direct access to the
output of the AD8337 VGA. The pin is typically used for a
probe, and a 0 Ω resistor is provided between the test loop and
the output pin. If the test loop is connected to loads ≤500 Ω,
then the 0 Ω resistor is to be changed to an appropriate value.
RVO3
GAIN
AD8337
0Ω
VCOM
INPP
INPN
R
GAIN
CG
1nF
R1
49.9Ω
100Ω
IN
J1
R4
VNEG
PRAO
0Ω
C4
0.1µF
R2
49.9Ω
RPO2
453Ω
FB2
R5
100Ω
100Ω
PRAO
R
FB1
100Ω
DO NOT INSTALL PARTS IN GRAY
Figure 81. Schematic—AD8337-EVALZ-INV Inverting Configuration
L1
120nH FB
+V
S
+
C1
10µF
10V
C3
0.1µF
8
GND1 GND2 GND3 GND4
C6
0.1µF
RVO1
453Ω
IN
VPOS
INPP
VOUT
GAIN
3
1
7
VOUT
GAIN
C4
0.1µF
ADU81337
CG
1nF
INPN
4
PRAO VCOM VNEG
R1
49.9Ω
C10
0.1µF
5
2
6
2
1
R
100Ω
FB2
C7
AD8541AR
3
R
100Ω
VIN SHDN
VOUT
U2
FB1
0.1µF
R6
3
4
7
100Ω
6
U3
2
+
4
C2
C5
0.1µF
1µF
16V
GND
5
C9
0.1µF
C8
0.22µF
R4
10kΩ
ADR391AUJZ-R2
Figure 82. Evaluation Board Schematic—Single-Supply Version
Rev. D | Page 24 of 28
Data Sheet
AD8337
TOP:
SIGNAL GENERATOR 10.05MHz, 500mV p-p
BOTTOM:
SIGNAL GENERATOR 9.95MHz, 500mV p-p
POWER
AMPLIFIERS
SPECTRUM
ANALYZER
POWER
SPLITTER
SIGNAL
INPUT
PREAMP
OUTPUT
VGAIN
+5V
–5V
POWER SUPPLY
Figure 83. Typical Board Test Connections
For ease of assembly, all board components are located on the
primary side and are 0603 size surface mounts. Higher density
applications may require components on both sides of the board
and present no problem to the AD8337, as demonstrated in
unreleased versions of the board that featured secondary-side
components and vias. Not evident in the figures are thermal
vias within the pad that solder to the mating pad of the AD8337
chip-scale package. These vias serve as a thermal path and are
the primary means of removing heat from the device. The thermal
specifications for the AD8337 are predicated on the use of multi-
layer board construction with these thermal vias to enable heat
conductivity from the die.
MEASUREMENT SETUP
Figure 83 shows board connections for two generators. In this
example, the experiment illustrates IMD measurements using
standard off-the-shelf test equipment used by Analog Devices.
However, any equivalent equipment can be used.
BOARD LAYOUT CONSIDERATIONS
The AD8337 evaluation board is designed using four layers.
Interconnecting circuitry is located on the component and
wiring sides, with the inner layers dedicated to power and
ground planes. Figure 84 through Figure 88 show the copper
layouts.
Rev. D | Page 25 of 28
AD8337
Data Sheet
Figure 84. Dual-Supply Component Side Copper
Figure 88. Dual-Supply Power Plane
Figure 89. Single-Supply Component Side Copper
Figure 85. Dual-Supply Wiring Side Copper
Figure 86. Dual-Supply Component Side Silk-Screen
Figure 90. Single-Supply Wiring Side Copper
Figure 91. Single-Supply Component Side Silkscreen
Figure 87. Dual-Supply Ground Plane
Rev. D | Page 2± of 28
Data Sheet
AD8337
Figure 93. Single-Supply Power Plane
Figure 92. Single-Supply Ground Plane
Rev. D | Page 27 of 28
AD8337
Data Sheet
OUTLINE DIMENSIONS
1.84
1.74
1.64
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
EXPOSED
PAD
1.55
1.45
1.35
AREA
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 94. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option Branding
AD8337BCPZ-R2
AD8337BCPZ-REEL
AD8337BCPZ-REEL7
AD8337BCPZ-WP
AD8337-EVALZ
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board with Noninverting Gain Configuration
Evaluation Board with Inverting Gain Configuration
Evaluation Board with Single-Supply Operation
CP-8-13
CP-8-13
CP-8-13
CP-8-13
HVB
HVB
HVB
HVB
AD8337-EVALZ-INV
AD8337-EVALZ-SS
1 Z = RoHS Compliant Part.
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05575-0-10/16(D)
Rev. D | Page 28 of 28
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