AD8352ACPZ-R7 [ADI]
2 GHz Ultralow Distortion Differential RF/IF Amplifier; 2 GHz的超低失真差分RF / IF放大器
| 型号： | AD8352ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 2 GHz Ultralow Distortion Differential RF/IF Amplifier |
| 文件： | 总20页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz Ultralow Distortion
Differential RF/IF Amplifier
AD8352
FEATURES
FUNCTIONAL BLOCK DIAGRAM
−3 dB bandwidth of 2.2 GHz (AV = 10 dB)
Single resistor gain adjust 3 dB ≤ AV ≤ 21 dB
Single resistor and capacitor distortion adjust
Input resistance 3 kΩ, independent of gain (AV)
Differential or single-ended input to differential output
Low noise input stage 2.7 nV/√Hz RTI @ AV = 10 dB
Low broadband distortion
10 MHz: −86 dBc HD2, −82 dBc HD3
70 MHz: −84 dBc HD2, −82 dBc HD3
190 MHz: −81 dBc HD2, −87 dBc HD3
OIP3 of 41 dBm @ 150 MHz
VCM
VCC
ENB
RGP
RDP
BIAS CELL
+
–
VOP
VON
VIP
VIN
C
D
R
R
D
G
RDN
RGN
GND
Slew rate 8 V/ns
AD8352
Fast settling and overdrive recovery of 2 ns
Single-supply operation: 3 V to 5.0 V
Low power dissipation: 37 mA @ 5 V
Power down capability: 5 mA @ 5 V
Figure 1.
–60
44
42
40
38
36
34
32
30
28
–65
–70
–75
–80
–85
–90
–95
Fabricated using the high speed XFCB3 SiGe process
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
–100
20
40
60
80
100 120 140 160 180 200 220
FREQUENCY (MHz)
Figure 2. IP3 and Third Harmonic Distortion vs. Frequency,
Measured Differentially
GENERAL DESCRIPTION
The AD8352 is a high performance differential amplifier
optimized for RF and IF applications. It achieves better than
80 dB SFDR performance at frequencies up to 200 MHz, and
65 dB beyond 500 MHz, making it an ideal driver for high
speed 12- to 16-bit analog-to-digital converters (ADCs).
The device is optimized for wide band, low distortion
performance at frequencies beyond 500 MHz. These attributes,
together with its wide gain adjust capability, make this device
the amplifier of choice for general-purpose IF and broadband
applications where low distortion, noise, and power are critical.
In particular, it is ideally suited for driving not only ADCs, but
also mixers, pin diode attenuators, SAW filters, and multielement
discrete devices. The device comes in a compact 3 mm × 3 mm,
16-lead LFCSP package and operates over a temperature range of
−40°C to +85°C.
Unlike other wideband differential amplifiers, the AD8352 has
buffers that isolate the Gain Setting Resistor RG from the signal
inputs. As a result, the AD8352 maintains a constant 3 kΩ input
resistance for gains of 3 dB to 24 dB, easing matching and input
drive requirements. The AD8352 has a nominal 100 Ω differential
output resistance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8352
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications..................................................................................... 11
Gain and Distortion Adjustment (Differential Input) .......... 11
Single-Ended Input Operation ................................................. 12
Narrow-Band, Third-Order Intermodulation Cancellation. 13
High Performance ADC Driving............................................. 14
Layout and Transmission Line Effects..................................... 15
Evaluation Board ............................................................................ 16
Evaluation Board Loading Schemes ........................................ 17
Evaluation Board Schematics ................................................... 18
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Noise Distortion Specifications .................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0| Page 2 of 20
AD8352
SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 6 and Table 7).
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
AV = 6 dB, VOUT ≤ 1.0 V p-p
AV = 10 dB, VOUT ≤ 1.0 V p-p
AV = 14 dB, VOUT ≤ 1.0 V p-p
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB
VS 5%
2500
2200
1800
190
300
1
.06
4
9
MHz
MHz
MHz
MHz
MHz
dB
dB/V
mdB/°C
V/ns
V/ns
ns
Bandwidth for 0.1 dB Flatness
Bandwidth for 0.2 dB Flatness
Gain Accuracy
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
−40°C to +85°C
RL = 1 kΩ, VOUT = 2 V step
RL = 200 Ω, VOUT = 2 V step
2 V step to 1%
8
<2
Settling Time
Overdrive Recovery Time
Reverse Isolation (S12)
INPUT/OUTPUT CHARACTERISTICS
Common-Mode Nominal
Voltage Adjustment Range
Maximum Output Voltage Swing
Output Common-Mode Offset
Output Common-Mode Drift
Output Differential Offset Voltage
CMRR
VIN = 4 V to 0 V step, VOUT
≤
10 mV
<3
−80
ns
dB
VCC/2
1.2 to 3.8
6
V
V
1 dB compressed
Referenced to VCC/2
−40°C to +85°C
V p-p
mV
mV/°C
mV
dB
−100
−20
+20
+20
.25
57
.15
5
Output Differential Offset Drift
Input Bias Current
−40°C to +85°C
mV/°C
μA
Input Resistance
3
kΩ
Input Capacitance (Single-Ended)
Output Resistance
Output Capacitance
0.9
100
3
pF
Ω
pF
POWER INTERFACE
Supply Voltage
ENB Threshold
ENB Input Bias Current
3
5
1.5
75
−125
37
5.3
5.5
39
V
V
nA
μA
mA
mA
ENB at 3 V
ENB at 0.6 V
ENB at 3 V
ENB at 0.6 V
Quiescent Current
35
Rev. 0| Page 3 of 20
AD8352
NOISE DISTORTION SPECIFICATIONS
VS = 5 V, RL=200 Ω differential, RG=118 Ω (AV = 10 dB), VOUT = 2 V p-p composite, T = 25°C; parameters specified differentially, unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 6 and Table 7).
Table 2.
Parameter
Conditions
Min Typ
−88/−95
Max Unit
10 MHz
Second/Third Harmonic Distortion1 RL = 1 kΩ, VOUT = 2 V p-p
dBc
dBc
dBm
dBc
dBc
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz
RL = 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite
−86/−82
+38
−86
Output Third-Order Intercept
Third-Order IMD
−81
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
+2.7
+15.7
nV/√Hz
dBm
70 MHz
Second/Third HarmonicDistortion1
RL = 1 kΩ, RG = 178 Ω, VOUT = 2 V p-p
RL = 200 Ω, RG = 115 Ω, VOUT = 2 V p-p
RL = 200 Ω f1 = 69.5 MHz, f2 = 70.5 MHz
RL = 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite
−83/−84
−84/−82
+40
−91
−83
dBc
dBc
dBm
dBc
dBc
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
100 MHz
+2.7
+15.7
nV/√Hz
dBm
Second/Third Harmonic Distortion
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 99.5 MHz, f2 = 100.5 MHz
RL = 1 kΩ, f1 = 99.5 MHz, f2 = 100.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 99.5 MHz, f2 = 100.5 MHz, VOUT = 2 V p-p composite
−83/−83
−84/−82
+40
−91
−84
dBc
dBc
dBm
dBc
dBc
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
140 MHz
+2.7
+15.6
nV/√Hz
dBm
Second/Third Harmonic Distortion2 RL = 1 kΩ, VOUT = 2 V p-p
−83/−82
−82/−84
+41
−89
−85
dBc
dBc
dBm
dBc
dBc
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz
RL = 1 kΩ, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2V p-p
Output Third-Order Intercept
Third-Order IMD
composite
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
+2.7
+15.5
nV/√Hz
dBm
1 When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini-Circuits® ADT1-1WT to obtain the low
frequency balance required for differential HD2 cancellation.
2 CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required.
Rev. 0| Page 4 of 20
AD8352
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), VOUT = 2 V p-p composite, T = 25°C; parameters specified differentially, unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 6 and Table 7). See the Applications section for
single-ended to differential performance characteristics.
Table 3.
Parameter
Conditions
Min Typ
−82/−85
Max Unit
190 MHz
Second/Third Harmonic Distortion1
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 180.5 MHz, f2 = 190.5 MHz
RL = 1 kΩ, f1 = 180.5 MHz, f2 = 190.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 180.5 MHz, f2 = 190.5 MHz, VOUT = 2 V p-p composite
dBc
dBc
dBm
dBc
dBc
−81/−87
+39
−83
Output Third-Order Intercept
Third-Order IMD
−81
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
240 MHz
+2.7
+15.4
nV/√Hz
dBm
Second/Third Harmonic Distortion1 RL = 1 kΩ, VOUT = 2 V p-p
−82/−76
−80/−73
+36
−85
−77
dBc
dBc
dBm
dBc
dBc
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz
RL = 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
+2.7
+15.3
nV/√Hz
dBm
380 MHz
Second/Third Harmonic Distortion RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
−72/−68
−74/−69
+33
−74
−70
dBc
dBc
dBm
dBc
dBc
Output Third-Order Intercept
Third-Order IMD
RL = 200 Ω, f1 = 379.5 MHz, f2 = 380.5 MHz
RL = 1 kΩ, f1 = 379.5 MHz, f2 = 380.5 MHz, VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 379.5 MHz, f2 = 380.5 MHz, VOUT = 2 V p-p composite
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
+2.7
+14.6
nV/√Hz
dBm
500 MHz
Second/Third Harmonic Distortion2
Output Third-Order Intercept
Third-Order IMD
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 499.5 MHz, f2 = 500.5 MHz
RL = 200 Ω, f1 = 499.5 MHz, f2 = 500.5 MHz, VOUT = 2 V p-p composite
−71/−64
+28
−61
dBc
dBm
dBc
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
+2.7
+13.9
nV/√Hz
dBm
1 When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini-Circuits ADT1-1WT to obtain the low
frequency balance required for differential HD2 cancellation.
2 CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required.
Rev. 0| Page 5 of 20
AD8352
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage VCC
5.5 V
VIP, VIN
5 V
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
210 mW
91.4°C/W
104°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0| Page 6 of 20
AD8352
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 GND
11 VOP
10 VON
RDP
RGP
RGN
RDN
1
2
3
4
AD8352
TOP VIEW
(Not to Scale)
9
GND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
RDP
RGP
RGN
RDN
VIN
GND
VCC
VON
VOP
VCM
Positive Distortion Adjust.
Positive Gain Adjust.
Negative Gain Adjust.
Negative Distortion Adjust.
Balanced Differential Input. Biased to VCM, typically ac-coupled.
Ground. Connect to low impedance GND.
5
6, 7, 9, 12
8, 13
10
11
14
Positive Supply.
Balanced Differential Output. Biased to VCM, typically ac-coupled.
Balanced Differential Output. Biased to VCM, typically ac-coupled.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output.
Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and output common
mode floats to midsupply = VCC/2.
15
16
ENB
VIP
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device.
Balanced Differential Input. Biased to VCM, typically ac-coupled.
Rev. 0| Page 7 of 20
AD8352
TYPICAL PERFORMANCE CHARACTERISTICS
25
30
25
20
15
10
5
R
= 20Ω
G
20
R
= 43Ω
G
15
10
5
R
= 100Ω
G
R
= 100Ω
= 182Ω
= 383Ω
G
R
G
G
R
= 520Ω
G
R
R
= 715Ω
G
0
0
–5
10
–5
10
100
1k
10k
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency for a 200 Ω Differential Load with Baluns,
AV = 18 dB, 12 dB, and 6 dB
Figure 7. Gain vs. Frequency for a 1 kΩ Differential Load Without Baluns,
RD/CD Open, AV = 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB
25
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
11.0
10.5
10.0
9.5
R
R
T
= 1kΩ
= 182Ω
= 0.002dB/°C
L
G
C
–40°C
20
R
= 62Ω
= 190Ω
= 3kΩ
G
+85°C
+25°C
15
10
5
R
G
9.0
8.5
–40°C
R
G
8.0
+85°C
7.5
+25°C
R
R
T
= 200Ω
= 118Ω
= 0.004dBc
L
G
C
9.0
7.0
0
8.5
6.5
6.0
–5
10
8.0
10
100
1k
10k
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Gain vs. Frequency for a 1 kΩ Differential Load with Baluns,
AV = 18 dB, 12 dB, and 6 dB
Figure 8. Gain vs. Frequency over Temperature (−40°C, +25°C, +85°C)
Without Baluns, AV = 10 dB, RL = 200 Ω and 1 kΩ
25
50
45
40
R
= 19Ω
G
G
20
15
10
5
A
= 10dB
V
R
= 64Ω
= 118Ω
= 232Ω
A
= 15dB
35
30
25
20
15
10
V
R
G
R
R
A
= 6dB
G
G
V
= 392Ω
0
–5
10
100
1k
10k
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency for a 200 Ω Differential Load Without Baluns,
RD/CD Open, AV = 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB
Figure 9. OIP3 vs. Frequency in dB, 2 V p-p Composite, RL = 200 Ω
AV = 15 dB, 10 dB, and 6 dB
Rev. 0| Page 8 of 20
AD8352
–60
–65
–70
–75
–80
–85
–90
0.6
0.5
0.4
0.3
0.2
0.1
0
0
> 300MHz NO C OR R USED
D
D
–20
–40
–60
–80
HD3
2V p-p
HD2
2V p-p
HD3
1V p-p
–100
–120
220
260
300
340
380
420
460
500
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Third-Order Harmonic Distortion HD3 vs. Frequency,
AV = 10 dB, RL = 200 Ω
Figure 13. Phase and Group Delay vs. Frequency, AV = 10 dB, RL = 200 Ω
–60
–65
3500
3000
2500
2000
1500
1000
500
7
6
5
4
3
2
1
HD3
–70
–75
–80
–85
HD2
–90
–95
–100
–105
–110
0
10
0
1000
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 11. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 200 Ω,
Figure 14. S11 Magnitude and Phase
A
V = 10 dB, RG = 115 Ω, RD = 4.3 kΩ, CD = 0.2 pF
–50
120
118
116
114
112
110
108
106
104
102
100
0
–10
–60
–20
–30
–40
–50
–60
–70
–80
–90
–100
–70
HD3
HD2
–80
–90
–100
–110
0
50
100
150
200
250
300
350
400
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Harmonic Distortion vs. Frequency for 2 V p-p into RL =1 kΩ,
AV = 10 dB, 5 V Supply, RG = 180 Ω, RD = 6.8 kΩ, CD = 0.1 pF
Figure 15. S22 Magnitude and Phase
Rev. 0| Page 9 of 20
AD8352
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
T
T
(10/90) = 215psec
(10/90) = 210psec
RISE
FALL
–0.5
–1.0
–1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
0
50
100 150 200 250 300 350 400 450 500
TIME (nsec)
FREQUENCY (MHz)
Figure 16 Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB
Figure 18. Noise Figure and Noise Spectral Density RTI vs. Frequency,
AV = 10 dB, RL = 200 Ω and 1 kΩ
5
4
80
70
3
R
= 200Ω
= 1kΩ
L
60
50
40
30
20
10
2
1
R
L
0
–1
–2
–3
–4
–5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10
100
1000
TIME (nsec)
FREQUENCY (MHz)
Figure 17. 1% Settling Time for a 2 V p-p Step Response,
AV = 10 dB, RL = 200 Ω
Figure 19. CMRR vs. Frequency, RL = 200 Ω and 1 kΩ,
Differential Source Resistance
Rev. 0| Page 10 of 20
AD8352
APPLICATIONS
Table 7. Broadband Selection of RG, CD, and RD: 1 kΩ Load
GAIN AND DISTORTION ADJUSTMENT
(DIFFERENTIAL INPUT)
AV (dB)
RG (Ω)
750
360
210
180
130
82
CD (pF)
0 (DNP)
0 (DNP)
0 (DNP)
0.05
RD (kΩ)
3
6
9
10
12
15
18
6.8
6.8
6.8
6.8
6.8
6.8
Table 6 and Table 7 show the required value of RG for the gains
specified at 200 Ω and 1 kΩ loads. Figure 20 and Figure 22 plot
RG vs. gain up to 18 dB for both load conditions. For other
output loads (RL), use Equation 1 to compute gain vs. RG.
0.1
0.3
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
R + 500
G
A
=
R
(1)
VDifferential
L
54
0.5
6.8
(
R + 5)(R + 53
)
+ 430
G
L
20
18
16
14
12
10
8
where:
RL = single-ended load.
RG = gain setting resistor.
The third-order harmonic distortion can be reduced by using
external components RD and CD. Table 6 and Table 7 show the
required values for RD and CD vs. the specified gains to achieve
(single tone) third-order distortion reduction at 180 MHz.
Figure 21 and Figure 23 show CD vs. any gain (up to 18 dB) for
200 Ω and 1 kΩ loads, respectively. When these values are
selected, they result in minimum single tone, third-order
distortion at 180 MHz. This frequency point provides the best
overall broadband distortion for the specified frequencies below
and above this value. For applications above approximately
300 MHz, CD and RD are not required. See the Specifications
section and third-order harmonic plots in the Typical
6
4
2
0
0
50
100
150
200
(Ω)
250
300
350
400
R
G
Figure 20. RG vs. Gain, RL = 200 Ω
20
18
16
14
12
10
8
Performance Characteristics section for more details.
CD can be further optimized for narrow-band tuning
requirements below 180 MHz that result in relatively lower
third-order (in-band) intermodulation distortion terms. See the
Narrow-Band, Third-Order Intermodulation Cancellation
section for more information. Though not shown, single tone,
third-order optimization can also be improved for narrow-band
frequency applications below 180 MHz with the proper
selection of CD, and 3 dB to 6 dB of relative third-order
improvement can be realized at frequencies below
approximately 140 MHz.
6
4
2
0
0
0.1
0.2
0.3
0.4
0.5
(pF)
0.6
0.7
0.8
0.9
1.0
Using the information listed in Table 6 and Table 7, an
extrapolated value for RD can be determined for loads between
200 Ω and 1 kΩ. For loads above 1 kΩ, use the 1 kΩ RD values
listed in Table 7.
C
D
Figure 21. CD vs. Gain, RL = 200 Ω
Table 6. Broadband Selection of RG, CD, and RD: 200 Ω Load
AV (dB)
RG (Ω)
390
220
140
115
86
CD (pF)
0 (DNP)
0 (DNP)
0.1
0.2
0.3
RD (kΩ)
3
6
9
10
12
15
18
6.8
4.3
4.3
4.3
4.3
4.3
4.3
56
35
0.6
1
Rev. 0| Page 11 of 20
AD8352
20
18
16
14
12
10
8
0.1µF
0.1µF
0.1µF
VIP
RGP
65Ω
25Ω
50Ω
C
R
R
G
AD8352
RGN
D
D
AC
0.1µF
R
200Ω
N
6
Figure 24. Single-Ended Schematic
4
40
35
30
25
20
15
10
5
2
0
0
100
200
300
400
(Ω)
500
600
700
800
R
G
Figure 22. RG vs. Gain, RL = 1 kΩ
GAIN, R = 1kΩ
L
20
18
16
14
12
10
8
GAIN, R = 200Ω
L
0
1
10
100
1k
10k
R
(Ω)
G
6
Figure 25. Gain vs. RG
4
–60
–70
2
0
0
0.1
0.2
0.3
0.4
0.5
2NDS, 2V p-p OUT
C
(pF)
D
Figure 23. CD vs. Gain, RL = 1 kΩ
–80
2NDS, 1V p-p OUT
SINGLE-ENDED INPUT OPERATION
–90
The AD8352 can be configured as a single-ended to differential
amplifier as shown in Figure 24. To balance the outputs when
driving only the VIP input, an external resistor (RN) of 200 Ω is
added between VIP and RGN. See Equation 2 to determine the
single-ended input gain (AVSingle-ended) for a given RG or RL.
–100
–110
10
70
140
FREQUENCY (MHz)
190
240
⎛
⎞
RG + 500
RL
(2)
⎜
⎜
⎟
⎟
AVSingle−ended
=
RL +
Figure 26. Single-Ended, Second-Order Harmonic Distortion,
200 Ω Load
(
RG + 5)(RL + 53
)
+ 430
RL + 30
⎝
⎠
where:
RL = single-ended load.
RG = gain setting resistor.
This broadband optimization was also performed at 180 MHz.
As with differential input drive, the resulting distortion levels
at lower frequencies are based on the CD and RD specified in
Table 8 and Table 9. As with differential input drive, relative
third-order reduction improvement at frequencies below
140 MHz are realized with proper selection of CD and RD.
Figure 25 plots gain vs. RG for 200 Ω and 1 kΩ loads. Table 8
and Table 9 show the values of CD and RD required (for 180 MHz
broadband third-order, single tone optimization) for 200 Ω and
1 kΩ loads, respectively. This single-ended configuration
provides −3 dB bandwidths similar to input differential drive.
Figure 26 through Figure 28 show distortion levels at a gain of
12 dB for both 200 Ω and 1 kΩ loads. Gains from 3 dB to 18 dB,
using optimized CD and RD values, obtain similar distortion
levels.
Rev. 0| Page 12 of 20
AD8352
–60
–70
Table 9. Distortion Cancellation Selection Components
(RD and CD) for Required Gain, 1 kΩ Load
AV (dB)
RG (Ω)
CD (pF)
0 (DNP)
0 (DNP)
0.2
RD (kΩ)
6
9
12
15
18
3 k
4.3
4.3
4.3
3RDS, 2V p-p OUT
470
210
120
68
–80
0.3
4.3
–90
0.5
4.3
3RDS, 1V p-p OUT
–100
–110
NARROW-BAND, THIRD-ORDER
INTERMODULATION CANCELLATION
Broadband, single tone, third-order harmonic optimization
does not necessarily result in optimum (minimum) two tone,
third-order intermodulation levels. The specified values for CD
and RD in Table 6 and Table 7 were determined for minimizing
broadband single tone, third-order levels.
10
70
140
FREQUENCY (MHz)
190
240
Figure 27. Single-Ended, Third-Order Harmonic Distortion, 200 Ω Load
–60
Due to phase-related distortion coefficients, optimizing single
tone, third-order distortion does not result in optimum in band
(2f1 − f2 and 2f2 − f1), third-order distortion levels. By proper
selection of CD (using a fixed 4.3 kΩ RD), IP3s of better than
45 dBm are achieved. This results in degraded out-of-band,
third-order frequencies (f2 + 2f1, f1 + 2f2, 3f1 and 3f2). Thus,
careful frequency planning is required to determine the
tradeoffs.
–70
–80
2NDS, 2V p-p OUT
–90
2NDS, 1V p-p OUT
–100
Figure 30 shows narrow band (2 MHz spacing) OIP3 levels
optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using
the CD values specified in Figure 31. These four data points (the
CD value and associated IP3 levels) are extrapolated to provide
close estimates of IP3 levels for any specific frequency between
30 MHz and 180 MHz. For frequencies below approximately
140 MHz, narrow-band tuning of IP3 results in relatively higher
IP3s (vs. the broadband results shown in Table 2 specifications).
Though not shown, frequencies below 30 MHz also result in
improved IP3s when using proper values for CD.
–110
10
70
140
190
240
FREQUENCY (MHz)
Figure 28. Single-Ended, Second-Order Harmonic Distortion, 1 kΩ Load
–60
–70
–80
–90
3RDS, 2V p-p OUT
48
R
R
C
= 200Ω
= 4.3kΩ
= 0.3pF
L
47
46
45
44
43
42
41
40
39
38
D
D
–100
–110
3RDS, 1V p-p OUT
A
=
6db
V
10
70
140
190
240
10db
15db
18dB
FREQUENCY (MHz)
Figure 29. Single-Ended, Third-Order Harmonic Distortion, 1 kΩ Load
Table 8. Distortion Cancellation Selection Components
(RD and CD) for Required Gain, 200 Ω Load
AV (dB)
RG (Ω)
4.3 k
540
220
120
68
CD (pF)
0 (DNP)
0 (DNP)
0.1
0.3
0.6
RD (kΩ)
0
50
100
FREQUENCY (MHz)
150
200
3
6
9
12
15
18
4.3
4.3
4.3
4.3
4.3
4.3
Figure 30. Third-Order Intermodulation Distortion vs. Frequency for
Various Gain Settings
43
0.9
Rev. 0 | Page 13 of 20
AD8352
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
These AD8352 simplified circuits provide the gain, isolation,
and distortion performance necessary for efficiently driving
high linearity converters such as the AD9445. This device also
provides balanced outputs whether driven differentially or
single-ended, thereby maintaining excellent second-order
distortion levels. Though at frequencies above approximately
100 MHz, due to phase related errors, single-ended, second-
order distortion is relatively higher. The output of the amplifier
is ac-coupled to allow for an optimum common-mode setting at
the ADC input. Input ac-coupling can be required if the source
also requires a common-mode voltage that is outside the
optimum range of the AD8352. A VCM common-mode pin is
provided on the AD8352 that equally shifts both input and
output common-mode levels. Increasing the gain of the
AD8352 increases the system noise and, thus, decreases the
SNR (3.5 dB at 100 MHz input for Av=10 dB) of the AD9445
when no filtering is used. Note that amplifier gains from 3 dB to
18 dB, with proper selection of CD and RD, do not appreciably
affect distortion levels. These circuits, when configured
properly, can result in SFDR performance of better than 87 dBc
at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive,
with appropriate CD and RD, give similar results for SFDR and
third-order intermodulation levels shown in these figures.
R
R
= 200Ω
= 4.3kΩ
L
D
A
=
6db
V
10db
15db
18dB
0
30
50
70
90
110
130
150
170
190
FREQUENCY (MHz)
Figure 31. Narrow-Band CD vs. Frequency for Various Gain Settings
HIGH PERFORMANCE ADC DRIVING
The AD8352 provides the gain, isolation, and balanced low
distortion output levels for efficiently driving wideband ADCs
such as the AD9445.
Figure 32 and Figure 33 (single and differential input drive)
illustrate the typical front-end circuit interface for the AD8352
differentially driving the AD9445 14-bit ADC at 105 MSPS. The
AD8352, when used in the single-ended configuration shows
little or no degradation in overall third-order harmonic
performance (vs. differential drive). See the Single-Ended Input
Operation section. The 100 MHz FFT plots shown in Figure 34
and Figure 35 display the results for the differential
configuration. Though not shown, the single-ended third-order
levels are similar.
Placing antialiasing filters between the ADC and the amplifier
is a common approach for improving overall noise and broadband
distortion performance for both band-pass and low-pass appli-
cations. For high frequency filtering, matching to the filter is
required. The AD8352 maintains a 100 Ω output impedance
well beyond most applications and is well-suited to drive most
filter configurations with little or no degradation in distortion.
V
CC
The 50 Ω resistor shown in Figure 32 provides a 50 Ω
differential input impedance to the source for matching
considerations. When the driver is less than one eighth of the
wavelength from the AD8352, impedance matching is not
required thereby negating the need for this termination resistor.
The output 24 Ω resistors provide isolation from the analog-to-
digital input. Refer to the Layout and Transmission Line Effects
section for more information. The circuit in Figure 33
0.1µF
0.1µF
0Ω
16
1
IF/RF INPUT
8, 11
2
0.1µF
0.1µF
11
10
24Ω
24Ω
AD8352
AD9445
R
R
G
50Ω
D
C
D
3
4
5
ADT1-1WT
14
0Ω
0.1µF
0.1µF
represents a single-ended input to differential output configura-
tion for driving the AD9445. In this case, the input 50 Ω resistor
with RN (typically 200 Ω) provide the input impedance match
for a 50 Ω system. Again, if input reflections are minimal, this
impedance match is not required. A fixed 200 Ω resistor (RN) is
required to balance the output voltages that are required for
second-order distortion cancellation. RG is the gain-setting
resistor for the AD8352 with the RD and CD components
providing distortion cancellation. The AD9445 presents
approximately 2 kΩ in parallel with 5 pF/differential load to the
AD8352 and requires a 2.0 V p-p differential signal (VREF = 1 V)
between VIN+ and VIN− for a full-scale output operation.
Figure 32. Differential Input to the AD8352 Driving the AD9445
0.1µF
0.1µF
33Ω
VIP
VOP
50Ω
50Ω
VIN+
AD9445
VIN–
AC
C
R
R
G
AD8352
D
D
VIN
33Ω
VON
0.1µF
0.1µF
25Ω
R
N
200Ω
Figure 33. Single-Ended Input to the AD8352 Driving the AD9445
Rev. 0| Page 14 of 20
AD8352
0
–10
LAYOUT AND TRANSMISSION LINE EFFECTS
SNR = 67.26dBc
SFDR = 83.18dBc
NOISE FLOOR = –110.5dB
FUND = –1.074dBFS
SECOND = –83.14dBc
THIRD = –85.39dBc
–20
High Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies resulting
in excessive gain peaking or possible oscillation. If RF transmis-
sion lines connecting the input or output are used, they should
be designed such that stray capacitance at the I/O pins is
minimized. In many board designs, the signal trace widths
should be minimal where the driver/receiver is less than one-
eighth of the wavelength from the AD8352. This non-transmission
line configuration requires that underlying and adjacent ground
and low impedance planes be far removed from the signal lines.
In a similar fashion, stray capacitance should be minimized
near the RG, CD, and RD components and associated traces. This
also requires not placing low impedance planes near these
components. Refer to the evaluation board layout (Figure 37
and Figure 38) for more information. Excessive stray capacitance
at these nodes results in unwanted high frequency distortion.
The 0.1 μF supply decoupling capacitors need to be close to the
amplifier. This includes Signal Capacitor C2 through Signal
Capacitor C5.
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 34. Single Tone Distortion AD8352 Driving AD9445, Encode Clock @
105 MHz with Fc @ 100 MHz (AV = 10 dB), See Figure 32
0
SNR = 61.98dBc
NOISE FLOOR = –111.2dB
FUND1 = –7.072
FUND2 = –7.043
IMD (2F2-F1) = –89dBc
IMD (2F1-F2) = –88dBc
–10
–20
–30
–40
–50
–60
–70
Parasitic suppressing resistors (R5, R6, R7, and R11) can be
used at the device I/O pins. Use 25 Ω series resistors (Size 0402)
to adequately de-Q the input and output system from most
parasitics without a significant decrease in gain. In general,
if proper board layout techniques are used, the suppression
resistors may not be required. Output Parasitic Suppression
Resistor R7 and Output Parasitic Suppression Resistor R11 may
be required for driving some switch cap ADCs. These
–80
–90
–100
–110
–120
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
suppressors, with Input C of the converter (and possibly added
External Shunt C), help provide charge kickback isolation and
improve overall distortion at high encode rates.
Figure 35. Two Tone Distortion AD8352 Driving AD9445,
Encode Clock @ 105 MHz with Fc @ 100 MHz (AV = 10 dB),
Analog In = 98 MHz and 101 MHz, See Figure 32
Rev. 0 | Page 15 of 20
AD8352
EVALUATION BOARD
An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output
network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are
presented in Figure 36, Figure 37, and Figure 38. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B).
Table 10. Evaluation Board Circuit Components and Functions
Additional
Information
Component
Name
Function
Pin 8 and Pin 13 VCC
Supply VCC = +5 V.
Connect to Low Impedance GND.
Pin 6, Pin 7,
Pin 9, Pin 12
GND
Pin 14, C9
VCM, Capacitor Common-Mode Offset Pin. Allows for monitoring or adjustment of the
output common-mode voltage. C9 is a bypass capacitor.
C9 = 0.1 μF
RD/CD
Distortion
Tuning
Distortion Adjustment Components. Allows for third-order distortion
adjustment HD3.
Typically, both are open
above 300 MHz
Components
CD = 0.2 pF, RD = 4.32 kΩ
CD is Panasonic High Q
(microwave) Multilayer
Chip 402 capacitor
Pin 15, C8
ENB, Capacitor
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. Pull
down to disable. Can be bypassed and float high (1.8 V) for on state. C8 is
a bypass capacitor.
Floats to 1.8 V to
maintain device in
power-up mode
C8 = 0.1 μF
R1, R2, R3, R4,
R5, R6, T2, C2,
C3
Resistors,
Transformer,
Capacitors
Input Interface. R1 and R4 ground one side of the differential drive
interface for single-ended applications. T2 is a 1-to-1 impedance ratio
balun to transform a single-ended input into a balanced differential
signal. R2 and R3 provide a differential 50 Ω input termination. R5 and R6
can be increased to reduce gain peaking when driving from a high source
impedance. The 50 Ω termination provides an insertion loss of 6 dB. C2
and C3 provide ac-coupling.
T2 = Macom™ ETC1-1-13
R1 = open, R2 = 25 Ω,
R3 = 25 Ω, R4 = 0 Ω,
R5 = 0 Ω, R6 = 0 Ω,
C2 = 0.1 μF, C3 = 0.1 μF
R7, R8, R9, R11,
R12, R13, R14,
T1, C4, C5
Resistors,
Transformer,
Capacitors
Output Interface. R13 and R14 ground one side of the differential output
interface for single-ended applications. T1 is a 1-to-1 impedance ratio
balun to transform a balanced differential signal to a single-ended signal.
R8, R9, and R12 are provided for generic placement of matching
components. R7 and R11 allow additional output series resistance when
driving capacitive loads. The evaluation board is configured to provide a
150 Ω to 50 Ω impedance transformation with an insertion loss of 11.6 dB.
C4 and C5 provide ac-coupling. R7 and R11 provide additional series
resistance when driving capacitive loads.
T1= Macom ETC1-1-13
R7 = 0 Ω, R8 = 86.6 Ω,
R9 = 57.6 Ω,
R11 = 0 Ω, R12 = 86.6 Ω,
R13 = 0 Ω, R14 = open
C4 = 0.1 μF, C5 = 0.1 μF
RG
Resistor
Gain Setting Resistor. Resistor RG is used to set the gain of the device.
Refer to Table 6 and Table 7 when selecting the gain resistor.
RG = 115 Ω (Size 0402)
for a gain of 10 dB
C1, C6, C7
Capacitors
Power Supply Decoupling. The supply decoupling consists of a 10 μF
capacitor to ground. C6 and C7 are bypass capacitors.
C1 = 10 μF
C6, C7 = 0.1 μF
Pin 14
VCM
Common-Mode Offset Adjustment. Use Pin 14 to trim common-mode
Typically decoupled to
input/output levels. By applying a voltage to Pin 14, the input and output, ground using a 0.1 μF
common-mode voltage can be directly adjusted.
capacitor with
ac-coupled
input/output ports
Rev. 0| Page 16 of 20
AD8352
Table 11. Values Used for 200 Ω and 1000 Ω Loads
EVALUATION BOARD LOADING SCHEMES
Component
200 Ω Load
1000 Ω Load
The AD8352 evaluation board is characterized with two load
configurations representing the most common ADC input
resistance. The loads chosen are 200 Ω and 1000 Ω using a
broadband resistive match. The loading can be changed via R8,
R9, and R12 giving the flexibility to characterize the AD8352
evaluation board for the load in any given application. These
loads are inherently lossy and thus must be accounted for in
overall gain/loss for the entire evaluation board. Measure the
gain of the AD8352 with an oscilloscope using the following
procedure to determine the actual gain:
R8
86.6
487
51.1
487
R9
57.6
R12
86.6
1. Measure the peak-to-peak voltage at the input node
(C2 or C3), and
2. Measure the peak-to-peak voltage at the output node
(C4 or C5), then
3. Compute gain using the formula
Gain = 20log VOUT/VIN
Rev. 0 | Page 17 of 20
AD8352
EVALUATION BOARD SCHEMATICS
C
V C
M V C
E N
C
D
D
V C
G N
G N
B
Figure 36. Preliminary Characterization Board v.A01212A
Rev. 0| Page 18 of 20
AD8352
Figure 37. Component Side Silk Screen
Figure 38. Far Side Showing Ground Plane Pull Back Around Critical Features
Rev. 0 | Page 19 of 20
AD8352
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.65
13
12
16
1
0.45
1.50 SQ
1.35
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
(BOTTOM VIEW)
4
9
8
5
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8352ACPZ-WP1
AD8352ACPZ-R71
AD8352-EVAL
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-16-3
CP-16-3
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ, 7”Tape and Reel
Evaluation Board
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05728-0-1/06(0)
Rev. 0| Page 20 of 20
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