AD835ANZ [ADI]
250 MHz, Voltage Output,4-Quadrant Multiplier; 250兆赫，电压输出， 4象限乘法器
| 型号： | AD835ANZ |
| 厂家： | 
ADI |
| 描述： | 250 MHz, Voltage Output,4-Quadrant Multiplier |
| 文件： | 总16页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 MHz, Voltage Output,
4-Quadrant Multiplier
AD835
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Simple: basic function is W = XY + Z
AD835
X = X1 – X2
X1
X2
Complete: minimal external components required
Very fast: Settles to 0.1% of full scale (FS) in 20 ns
DC-coupled voltage output simplifies use
High differential input impedance X, Y, and Z inputs
Low multiplier noise: 50 nV/√Hz
XY
+
+
XY + Z
X1
W OUTPUT
Y1
Y2
Y = Y1 – Y2
Z INPUT
APPLICATIONS
Figure 1.
Very fast multiplication, division, squaring
Wideband modulation and demodulation
Phase detection and measurement
Sinusoidal frequency doubling
Video gain control and keying
Voltage-controlled amplifiers and filters
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. The AD835 is the first monolithic 250 MHz, four-quadrant
voltage output multiplier.
2. Minimal external components are required to apply the
AD835 to a variety of signal processing applications.
3. High input impedances (100 kΩ||2 pF) make signal source
loading negligible.
4. High output current capability allows low impedance loads
to be driven.
5. State-of-the-art noise levels achieved through careful
device optimization and the use of a special low noise,
band gap voltage reference.
The AD835 is a complete four-quadrant, voltage output analog
multiplier, fabricated on an advanced dielectrically isolated
complementary bipolar process. It generates the linear product
of its X and Y voltage inputs with a −3 dB output bandwidth of
250 MHz (a small signal rise time of 1 ns). Full-scale (−1 V to
+1 V) rise to fall times are 2.5 ns (with a standard RL of 150 Ω),
and the settling time to 0.1% under the same conditions is
typically 20 ns.
Its differential multiplication inputs (X, Y) and its summing
input (Z) are at high impedance. The low impedance output
voltage (W) can provide up to 2.5 V and drive loads as low as
25 Ω. Normal operation is from 5 V supplies.
6. Designed to be easy to use and cost effective in applications
that require the use of hybrid or board-level solutions.
Though providing state-of-the-art speed, the AD835 is simple
to use and versatile. For example, as well as permitting the
addition of a signal at the output, the Z input provides the
means to operate the AD835 with voltage gains up to about ×10.
In this capacity, the very low product noise of this multiplier
(50 nV/√Hz) makes it much more useful than earlier products.
The AD835 is available in an 8-lead PDIP package (N) and an
8-lead SOIC package (R) and is specified to operate over the
−40°C to +85°C industrial temperature range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.
AD835
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 10
Basic Theory ............................................................................... 10
Scaling Adjustment .................................................................... 10
Applications Information.............................................................. 11
Multiplier Connections ............................................................. 11
Wideband Voltage-Controlled Amplifier ............................... 11
Amplitude Modulator................................................................ 11
Squaring and Frequency Doubling.......................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
12/10—Rev. C to Rev. D
Changes to Figure 1.......................................................................... 1
Changes to Absolute Maximum Ratings and Table 2.................. 5
Added Figure 19, Renumbered Subsequent Tables.................... 10
Added Figure 23.............................................................................. 11
10/09—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 22...................................................................... 11
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 14
6/03—Rev. A to Rev. B
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 10
Rev. D | Page 2 of 16
AD835
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 150 Ω, CL ≤ 5 pF, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
TRANSFER FUNCTION
(
X1− X2)(Y1−Y2)
W =
+ Z
U
INPUT CHARACTERISTICS (X, Y)
Differential Voltage Range
Differential Clipping Level
Low Frequency Nonlinearity
VCM = 0 V
1
1.ꢀ
0.3
0.1
V
V
% FS
% FS
1.21
X = 1 V, Y = 1 V
Y = 1 V, X = 1 V
TMIN to TMAX
0.51
0.31
2
vs. Temperature
X = 1 V, Y = 1 V
Y = 1 V, X = 1 V
0.7
0.5
+3
% FS
% FS
V
mV
mV
dB
Common-Mode Voltage Range
Offset Voltage
vs. Temperature
−2.5
701
3
201
2
TMIN to TMAX
25
CMRR
Bias Current
vs. Temperature
f ≤ 100 kHz; 1 V p-p
10
201
27
μA
μA
μA
kΩ
pF
2
TMIN to TMAX
Offset Bias Current
2
100
2
Differential Resistance
Single-Sided Capacitance
Feedthrough, X
X = 1 V, Y = 0 V
Y = 1 V, X = 0 V
−ꢀ61
−601
dB
dB
Feedthrough, Y
DYNAMIC CHARACTERISTICS
−3 dB Small Signal Bandwidth
−0.1 dB Gain Flatness Frequency
Slew Rate
Differential Gain Error, X
Differential Phase Error, X
Differential Gain Error, Y
Differential Phase Error, Y
Harmonic Distortion
150
250
15
1000
0.3
0.2
0.1
MHz
MHz
V/μs
%
Degrees
%
W = −2.5 V to +2.5 V
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
X or Y = 10 dBm, second and third harmonic
Fund = 10 MHz
Fund = 50 MHz
0.1
Degrees
−70
−ꢀ0
20
dB
dB
ns
Settling Time, X or Y
SUMMING INPUT (Z)
Gain
−3 dB Small Signal Bandwidth
Differential Input Resistance
Single-Sided Capacitance
Maximum Gain
To 0.1%, W = 2 V p-p
From Z to W, f ≤ 10 MHz
0.990
0.995
250
60
2
50
MHz
kΩ
pF
X, Y to W, Z shorted to W, f = 1 kHz
dB
Bias Current
50
μA
Rev. D | Page 3 of 16
AD835
Parameter
Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Voltage Swing
2.2
2.0
2.5
V
V
2
vs. Temperature
TMIN to TMAX
Voltage Noise Spectral Density
Offset Voltage
vs. Temperature3
X = Y = 0 V, f < 10 MHz
50
25
nV/√Hz
mV
mV
751
10
2
TMIN to TMAX
Short-Circuit Current
Scale Factor Error
vs. Temperature
Linearity (Relative Error)ꢀ
75
5
mA
81
9
1.01
1.25
% FS
% FS
% FS
% FS
2
TMIN to TMAX
0.5
2
vs. Temperature
TMIN to TMAX
POWER SUPPLIES
Supply Voltage
For Specified Performance
Quiescent Supply Current
vs. Temperature
PSRR at Output vs. VP
PSRR at Output vs. VN
ꢀ.5
5
16
5.5
251
26
V
mA
mA
%/V
%/V
2
TMIN to TMAX
+ꢀ.5 V to +5.5 V
−ꢀ.5 V to −5.5 V
0.51
0.5
1 All minimum and maximum specifications are guaranteed. These specifications are tested on all production units at final electrical test.
2 TMIN = −ꢀ0°C, TMAX = 85°C.
3 Normalized to zero at 25°C.
ꢀ Linearity is defined as residual error after compensating for input offset, output voltage offset, and scale factor errors.
Rev. D | Page ꢀ of 16
AD835
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Parameter
Rating
Table 3.
Supply Voltage
6 V
300 mW
−ꢀ0°C to +85°C
−65°C to +150°C
300°C
Package Type
8-Lead PDIP (N)
8-Lead SOIC (R)
θJA
90
115
θJC
35
ꢀ5
Unit
°C/W
°C/W
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature, Soldering 60 sec
ESD Rating
ESD CAUTION
HBM
CDM
1500 V
250 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For more information, see the Analog Devices, Inc., Tutorial
MT-092, Electrostatic Discharge.
Rev. D | Page 5 of 16
AD835
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Y1
Y2
VN
Z
1
2
3
4
8
7
6
5
X1
X2
VP
W
AD835
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
ꢀ
5
6
7
8
Y1
Y2
VN
Z
Noninverting Y Multiplicand Input
Inverting Y Multiplicand Input
Negative Supply Voltage
Summing Input
W
Product
VP
X2
X1
Positive Supply Voltage
Inverting X Multiplicand Input
Noninverting X Multiplicand Input
Rev. D | Page 6 of 16
AD835
TYPICAL PERFORMANCE CHARACTERISTICS
COMPOSITE
0.19 0.20
DG DP (NTSC)
FIELD = 1 LINE = 18
Wfm → FCC
0.16
0
0.06
0.11
X, Y CH = 0dBm
0.4
0.2
R
C
= 150Ω
≤ 5pF
L
L
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
MIN = 0
MAX = 0.2
p-p/MAX = 0.2
0
–0.2
–0.4
1ST
0
2ND
0.02
3RD
0.02
4TH
0.03
5TH
0.03
6TH
0.06
0.3
0.2
0.1
0
MIN = 0
MAX = 0.06
p-p = 0.06
–0.1
–0.2
–0.3
300k
1M
10M
100M
1G
1ST
2ND
3RD
4TH
5TH
6TH
FREQUENCY (Hz)
Figure 6. Gain Flatness to 0.1 dB
Figure 3. Typical Composite Output Differential Gain and Phase,
NTSC for X Channel; f = 3.58 MHz, RL = 150 Ω
COMPOSITE
–0.01 –0.20
DG DP (NTSC)
FIELD = 1 LINE = 18
Wfm → FCC
0
0.01
0
0
X, Y CH = 5dBm
0.3
0.2
R
C
= 150Ω
< 5pF
L
L
MIN = –0.02
MAX = 0.01
p-p/MAX = 0.03
0.1
–10
–20
–30
–40
–50
–60
0
–0.1
–0.2
–0.3
Y FEEDTHROUGH
1ST
0
2ND
0.03
3RD
0.04
4TH
0.07
5TH
0.10
6TH
0.16
X FEEDTHROUGH
0.20
0.10
0
X FEEDTHROUGH
Y FEEDTHROUGH
10M
MIN = 0
MAX = 0.16
p-p = 0.16
–0.10
–0.20
1M
100M
1G
FREQUENCY (Hz)
1ST
2ND
3RD
4TH
5TH
6TH
Figure 4. Typical Composite Output Differential Gain and Phase,
NTSC for Y Channel; f = 3.58 MHz, RL = 150 Ω
Figure 7. X and Y Feedthrough vs. Frequency
X, Y, Z CH = 0dBm
R
C
= 150Ω
≤ 5pF
L
L
2
0
180
90
+0.2V
GAIN
–2
–4
–6
–8
–10
0
GND
PHASE
–90
–180
–0.2V
100mV
10ns
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 8. Small Signal Pulse Response at W Output, RL = 150 Ω, CL ≤ 5 pF,
X Channel = 0.2 V, Y Channel = 1.0 V
Figure 5. Gain and Phase vs. Frequency of X, Y, Z Inputs
Rev. D | Page 7 of 16
AD835
10MHz
+1V
GND
10dB/DIV
–1V
30MHz
20MHz
500mV
10ns
Figure 9. Large Signal Pulse Response at W Output, RL = 150 Ω, CL ≤ 5 pF,
X Channel = 1.0 V, Y Channel = 1.0 V
Figure 12. Harmonic Distortion at 10 MHz; 10 dBm Input to X or Y Channels,
RL = 150 Ω, CL = ≤ 5 pF
50MHz
0
20
40
60
80
10dB/DIV
100MHz
150MHz
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 13. Harmonic Distortion at 50 MHz, 10 dBm Input to X or Y Channel,
RL = 150 Ω, CL ≤ 5 pF
Figure 10. CMRR vs. Frequency for X or Y Channel, RL = 150 Ω, CL ≤ 5 pF
0dBm ON SUPPLY
X, Y = 1V
100MHz
PSSR ON V+
–10
–20
–30
–40
200MHz
300MHz
10dB/DIV
–50
PSSR ON V–
–60
300k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 11. PSRR vs. Frequency for V+ and V– Supply
Figure 14. Harmonic Distortion at 100 MHz, 10 dBm Input to X or Y Channel,
RL = 150 Ω, CL ≤ 5 pF
Rev. D | Page 8 of 16
AD835
35
30
25
20
15
10
5
X CH = 6dBm
Y CH = 10dBm
R
= 100Ω
L
+2.5V
10dB/DIV
–2.5V
1V
10ns
0
0
20
40
60
80
100 120 140 160 180 200
RF FREQUENCY INPUT TO X CHANNEL (MHz)
Figure 17. Fixed LO on Y Channel vs. RF Frequency Input to X Channel
Figure 15. Maximum Output Voltage Swing, RL = 50 Ω, CL ≤ 5 pF
35
15
OUTPUT OFFSET DRIFT WILL
TYPICALLY BE WITHIN SHADED AREA
X CH = 6dBm
Y CH = 10dBm
= 100Ω
30
25
20
15
10
5
10
5
R
L
0
–5
–10
OUTPUT V DRIFT, NORMALIZED TO 0 AT 25°C
OS
0
–15
–55
0
20
40
60
80
100 120 140 160 180 200
–35
–15
5
25
45
65
85
105
125
LO FREQUENCY ON Y CHANNEL (MHz)
TEMPERATURE (°C)
Figure 18. Fixed IF vs. LO Frequency on Y Channel
Figure 16. VOS Output Drift vs. Temperature
Rev. D | Page 9 of 16
AD835
THEORY OF OPERATION
The AD835 is a four-quadrant, voltage output analog multiplier,
fabricated on an advanced dielectrically isolated complementary
bipolar process. In its basic mode, it provides the linear product
of its X and Y voltage inputs. In this mode, the −3 dB output
voltage bandwidth is 250 MHz (with small signal rise time of 1 ns).
Full-scale (−1 V to +1 V) rise to fall times are 2.5 ns (with a
standard RL of 150 Ω), and the settling time to 0.1% under the
same conditions is typically 20 ns.
avoid the needless use of less intuitive subscripted variables
(such as, VX1). All variables as being normalized to 1 V.
For example, the input X can either be stated as being in the −1 V
to +1 V range or simply –1 to +1. The latter representation is found
to facilitate the development of new functions using the AD835.
The explicit inclusion of the denominator, U, is also less helpful, as
in the case of the AD835, if it is not an electrical input variable.
SCALING ADJUSTMENT
As in earlier multipliers from Analog Devices a unique
summing feature is provided at the Z input. As well as providing
independent ground references for the input and the output and
enhanced versatility, this feature allows the AD835 to operate
with voltage gain. Its X-, Y-, and Z-input voltages are all
nominally 1 V FS, with an overrange of at least 20%. The
inputs are fully differential at high impedance (100 kΩ||2 pF)
and provide a 70 dB CMRR (f ≤ 1 MHz).
The basic value of U in Equation 1 is nominally 1.05 V. Figure 20,
which shows the basic multiplier connections, also shows how
the effective value of U can be adjusted to have any lower
voltage (usually 1 V) through the use of a resistive divider
between W (Pin 5) and Z (Pin 4). Using the general resistor
values shown, Equation 1can be rewritten as
XY
U
W =
+ kW +
(1− k
)Z'
(3)
The low impedance output is capable of driving loads as small
as 25 Ω. The peak output can be as large as 2.2 V minimum
for RL = 150 Ω, or 2.0 V minimum into RL = 50 Ω. The AD835
has much lower noise than the AD534 or AD734, making it
attractive in low level, signal processing applications, for
example, as a wideband gain control element or modulator.
where Z' is distinguished from the signal Z at Pin 4. It follows that
XY
1 − k)U
W =
+ Z'
(4)
(
In this way, the effective value of U can be modified to
U’ = (1 − k)U
(5)
BASIC THEORY
without altering the scaling of the Z' input, which is expected because
the only ground reference for the output is through the Z' input.
The multiplier is based on a classic form, having a translinear core,
supported by three (X, Y, and Z) linearized voltage-to-current
converters, and the load driving output amplifier. The scaling
voltage (the denominator U in the equations) is provided by a
band gap reference of novel design, optimized for ultralow noise.
Figure 19 shows the functional block diagram.
Therefore, to set U' to 1 V, remembering that the basic value of
U is 1.05 V, R1 must have a nominal value of 20 × R2. The values
shown allow U to be adjusted through the nominal range of
0.95 V to 1.05 V. That is, R2 provides a 5% gain adjustment.
In general terms, the AD835 provides the function
In many applications, the exact gain of the multiplier may not
be very important; in which case, this network may be omitted
entirely, or R2 fixed at 100 Ω.
(
X1 − X2)(Y1−Y2)
W =
+ Z
(1)
U
+5V
where the variables W, U, X, Y, and Z are all voltages. Connected as
a simple multiplier, with X = X1 − X2, Y = Y1 − Y2, and Z = 0
and with a scale factor adjustment (see Figure 19) that sets U = 1 V,
the output can be expressed as
FB
4.7μF TANTALUM
W = XY
(2)
0.01μF CERAMIC
X
W
AD835
X = X1 – X2
XY
X1
X2
8
7
6
5
X1
X2
VP
W
R1 = (1–k) R
2kΩ
AD835
XY + Z
X1
W OUTPUT
Y1
1
Y2
2
VN
3
Z
4
+
+
Y1
Y2
Y
Y = Y1 – Y2
R2 = kR
200Ω
4.7μF TANTALUM
0.01μF CERAMIC
Z INPUT
1
Z
FB
Figure 19. Functional Block Diagram
Simplified representations of this sort, where all signals are
presumed expressed in V, are used throughout this data sheet to
–5V
Figure 20. Multiplier Connections
Rev. D | Page 10 of 16
AD835
APPLICATIONS INFORMATION
The AD835 is easy to use and versatile. The capability for adding
another signal to the output at the Z input is frequently valuable.
Three applications of this feature are presented here: a wideband
voltage-controlled amplifier, an amplitude modulator, and a
frequency doubler. Of course, the AD835 may also be used as a
square law detector (with its X inputs and Y inputs connected in
parallel). In this mode, it is useful at input frequencies to well
over 250 MHz because that is the bandwidth limitation of the
output amplifier only.
The ac response of this amplifier for gains of 0 dB (VG = 0.25 V),
6 dB (VG = 0.5 V), and 12 dB (VG = 1 V) is shown in Figure 22.
In this application, the resistor values have been slightly adjusted to
reflect the nominal value of U = 1.05 V. The overall sign of the
gain may be controlled by the sign of VG.
21
18
15
12dB
G
(V = 1V)
12
9
MULTIPLIER CONNECTIONS
6dB
(V = 0.5V)
G
Figure 20 shows the basic connections for multiplication. The
inputs are often single sided, in which case the X2 and Y2 inputs
are normally grounded. Note that by assigning Pin 7 (X2) and
Pin 2 (Y2), respectively, to these (inverting) inputs, an extra
measure of isolation between inputs and output is provided.
The X and Y inputs may be reversed to achieve some desired
overall sign with inputs of a particular polarity, or they may be
driven fully differentially.
6
3
0dB
(V = 0.25V)
G
0
–3
–6
–9
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 22. AC Response of VCA
Power supply decoupling and careful board layout are always
important in applying wideband circuits. The decoupling
recommendations shown in Figure 20 should be followed
closely. In Figure 21, Figure 23, and Figure 24, these power
supply decoupling components are omitted for clarity but should
be used wherever optimal performance with high speed inputs
is required. However, if the full, high frequency capabilities of the
AD835 are not being exploited, these components can be
omitted.
AMPLITUDE MODULATOR
Figure 23 shows a simple modulator. The carrier is applied to the
Y input and the Z input, while the modulating signal is applied to
the X input. For zero modulation, there is no product term so the
carrier input is simply replicated at unity gain by the voltage
follower action from the Z input. At X = 1 V, the RF output is
doubled, while for X = –1 V, it is fully suppressed. That is, an
X input of approximately 1 V (actually U or about 1.05 V)
corresponds to a modulation index of 100%. Carrier and
modulation frequencies can be up to 300 MHz, somewhat
beyond the nominal −3 dB bandwidth.
WIDEBAND VOLTAGE-CONTROLLED AMPLIFIER
Figure 21 shows the AD835 configured to provide a gain of
nominally 0 dB to 12 dB. (In fact, the control range extends from
well under –12 dB to about +14 dB.) R1 and R2 set the gain to
be nominally ×4. The attendant bandwidth reduction that comes
with this increased gain can be partially offset by the addition of
the peaking capacitor C1. Although this circuit shows the use of
dual supplies, the AD835 can operate from a single 9 V supply
with a slight revision.
Of course, a suppressed carrier modulator can be implemented
by omitting the feedforward to the Z input, grounding that
pin instead.
+5V
MODULATION
MODULATED
CARRIER
OUTPUT
8
7
6
5
SOURCE
X1
X2
VP
W
+5V
AD835
V
VOLTAGE
OUTPUT
G
Y1
1
Y2
2
VN
3
Z
4
(GAIN CONTROL)
8
7
6
5
R1
97.6Ω
X1
X2
VP
W
AD835
–5V
C1
Y1
1
Y2
2
VN
3
Z
4
33pF
CARRIER
SOURCE
V
IN
(SIGNAL)
R2
301Ω
Figure 23. Simple Amplitude Modulator Using the AD835
–5V
Figure 21. Voltage-Controlled 50 MHz Amplifier Using the AD835
Rev. D | Page 11 of 16
AD835
+5V
V
SQUARING AND FREQUENCY DOUBLING
G
C1
VOLTAGE
OUTPUT
Amplitude domain squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E2/U. The input can have either polarity, but the
output in this case is always positive. The output polarity can be
reversed by interchanging either the X or Y inputs.
8
7
6
5
X1
X2
VP
W
R2
97.6Ω
AD835
Y1
1
Y2
2
VN
3
Z
4
When the input is a sine wave E sin ωt, a signal squarer behaves
as a frequency doubler because
R3
301Ω
R1
–5V
2
(
Esinωt
)
E2
2U
Figure 24. Broadband Zero-Bounce Frequency Doubler
=
(
1− cos2ωt
)
(6)
U
This circuit is based on the identity
While useful, Equation 6 shows a dc term at the output, which
varies strongly with the amplitude of the input, E.
1
cosθsinθ = sin2θ
(7)
2
Figure 24 shows a frequency doubler that overcomes this
limitation and provides a relatively constant output over a
moderately wide frequency range, determined by the time
constant R1C1. The voltage applied to the X and Y inputs is
exactly in quadrature at a frequency f = ½πC1R1, and their
amplitudes are equal. At higher frequencies, the X input becomes
smaller while the Y input increases in amplitude; the opposite
happens at lower frequencies. The result is a double frequency
output centered on ground whose amplitude of 1 V for a 1 V
input varies by only 0.5% over a frequency range of 10%.
Because there is no squared dc component at the output, sudden
changes in the input amplitude do not cause a bounce in the dc level.
At ωO = 1/C1R1, the X input leads the input signal by 45° (and is
attenuated by √2, while the Y input lags the input signal by 45°
and is also attenuated by √2. Because the X and Y inputs are 90°
out of phase, the response of the circuit is
1 E
E
2
E2
2U
W =
(
sinωt − 45°
)
(
sinωt + 45°
)
=
(sin2ωt
)
(8)
U
2
which has no dc component, R2 and R3 are included to restore
the output to 1 V for an input amplitude of 1 V (the same gain
adjustment as previously mentioned). Because the voltage across
the capacitor (C1) decreases with frequency, while that across
the resistor (R1) increases, the amplitude of the output varies
only slightly with frequency. In fact, it is only 0.5% below its full
value (at its center frequency ωO = 1/C1R1) at 90% and 110% of
this frequency.
Rev. D | Page 12 of 16
AD835
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 25. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 13 of 16
AD835
ORDERING GUIDE
Model1
AD835AN
AD835ANZ
AD835AR
AD835AR-REEL
AD835AR-REEL7
AD835ARZ
AD835ARZ-REEL
AD835ARZ-REEL7
Temperature Range
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
−ꢀ0°C to +85°C
Package Description
Package Option
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. D | Page 1ꢀ of 16
AD835
NOTES
Rev. D | Page 15 of 16
AD835
NOTES
©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00883-0-12/10(D)
Rev. D | Page 16 of 16
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