AD8361ART-REEL7_技术文档

LF to 2.5 GHz

™

a

TruPwr Detector

AD8361

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Calibrated RMS Response

Excellent Temperature Stability

Up to 30 dB Input Range at 2.5 GHz

700 mV rms, 10 dBm re 50 ⍀ Maximum Input

؎0.25 dB Linear Response Up to 2.5 GHz

Single Supply Operation: 2.7 V to 5.5 V

Low Power: 3.3 mW at 3 V Supply

Rapid Power-Down to Less than 1 ␮A

micro_SOIC

VPOS

FLTR

INTERNAL FILTER

i

2

␹

RFIN

TRANS-

AD8361

CONDUCTANCE

CELLS

ERROR

AMP

2

؋

7.5

BUFFER

␹

VRMS

APPLICATIONS

Measurement of CDMA, W-CDMA, QAM, Other

Complex Modulation Waveforms

RF Transmitter or Receiver Power Measurement

ADD

OFFSET

BAND-GAP

REFERENCE

SREF

PWDN

COMM

IREF

PRODUCT DESCRIPTION

SOT-23-6L

The AD8361 is a mean-responding power detector for use in high-

frequency receiver and transmitter signal chains, up to 2.5 GHz.

It is very easy to apply. It requires only a single supply between

2.7 V and 5.5 V, power supply decoupling capacitor and an

input coupling capacitor in most applications. The output is a

linear-responding dc voltage with a conversion gain of 7.5 V/V rms.

An external ﬁlter capacitor can be added to increase the averag-

ing time constant.

VPOS

FLTR

INTERNAL FILTER

i

2

␹

RFIN

AD8361

TRANS-

CONDUCTANCE

CELLS

ERROR

AMP

2

؋

7.5

BUFFER

␹

VRMS

3.0

BAND-GAP

REFERENCE

PWDN

2.8

SUPPLY

REFERENCE MODE

2.6

COMM

2.4

2.2

INTERNAL

REFERENCE MODE

2.0

The AD8361 is intended for true power measurement of simple

and complex waveforms. The device is particularly useful for

measuring high crest-factor (high peak-to-rms ratio) signals, such

as CDMA and W-CDMA.

1.8

1.6

1.4

GROUND

REFERENCE MODE

1.2

1.0

0.8

0.6

The AD8361 has three operating modes to accommodate a

variety of analog-to-digital converter requirements:

0.4

0.2

0.0

1. Ground referenced mode, in which the origin is zero;

2. Internal reference mode, which offsets the output 350 mV

above ground;

0

0.1

0.2

0.3

0.4

0.5

RFIN – V rms

3. Supply reference mode, which offsets the output to V_S/7.5.

Figure 1. Output in the Three Reference Modes, Supply 3 V,

Frequency 1.9 GHz (SOT-23-6L Package Ground Reference

Mode Only)

The AD8361 is speciﬁed for operation from –40°C to +85°C and

is available in 8-lead micro_SOIC and 6-lead SOT packages.

It is fabricated on a proprietary high f_Tsilicon bipolar process.

TruPwr is a trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(T_A= 25؇C, V_S= 3 V, f_RF= 900 MHz, ground reference output mode, unless otherwise

AD8361–SPECIFICATIONS _noted.)

Parameter

Condition

Min

Typ

Max

Unit

SIGNAL INPUT INTERFACE

Frequency Range¹

(Input RFIN)

2.5

GHz

Linear Response Upper Limit

V_S= 3 V

Equivalent dBm re 50 Ω

V_S= 5 V

390

4.9

660

9.4

mV rms

dBm

mV rms

dBm

Equivalent dBm re 50 Ω

Input Impedance²

225ʈ1

ΩʈpF

RMS CONVERSION

Conversion Gain

(Input RFIN to Output V rms)

7.5

V/V rms

f

_RF= 100 MHz, V_S= 5 V

6.5

8.5

Dynamic Range

0.25 dB Error⁴

1 dB Error

Error Referred to Best Fit Line³

CW Input, –40°C < T_A< +85°C

14

23

26

30

1

dB

CW Input, –40°C < T_A< +85°C

2 dB Error

CW Input, –40°C < T_A< +85°C

CW Input, V_S= 5 V, –40°C < T_A< +85°C

Internal Reference Mode

Intercept-Induced Dynamic

Range Reduction^{5, 6}

Supply Reference Mode, V_S= 3.0 V

Supply Reference Mode, V_S= 5.0 V

5.5 dB Peak-to-Average Ratio (IS95 Reverse Link)

12 dB Peak-to-Average Ratio (W-CDMA 4 Channels)

18 dB Peak-to-Average Ratio (W-CDMA 15 Channels)

1

1.5

0.2

1.0

1.2

Deviation from CW Response

OUTPUT INTERCEPT⁵

Ground Reference Mode (GRM)

Inferred from Best Fit Line³

0 V at SREF, V_Sat IREF

0

V

f

_RF= 100 MHz, V_S= 5 V

–50

300

590

+150

500

mV

V

Internal Reference Mode (IRM)

Supply Reference Mode (SRM)

0 V at SREF, IREF Open

f_RF= 100 MHz, V_S= 5 V

0 V at IREF, 3 V at SREF

f_RF= 100 MHz, V_S= 5 V

0 V at IREF, V_Sat SREF

350

400

V_S/7.5

750

POWER-DOWN INTERFACE

PWDN HI Threshold

PWDN LO Threshold

2.7

≤

V_S

≤

5.5 V, –40°C < T_A< +85°C

V_S– 0.5

V

µs

µA

0.1

5.5

Power-Up Response Time

2 pF at FLTR Pin, 224 mV rms at RFIN

100 nF at FLTR Pin, 224 mV rms at RFIN

5

320

<1

PWDN Bias Current

POWER SUPPLIES

Operating Range

Quiescent Current

Power-Down Current

–40°C < T_A< +85°C

2.7

V

0 mV rms at RFIN, PWDN Input LO⁷

GRM or IRM, 0 mV rms at RFIN, PWDN Input HI

SRM, 0 mV rms at RFIN, PWDN Input HI

1.1

<1

10 × V_S

mA

µA

NOTES

¹Operation at arbitrarily low frequencies is possible; see Applications section.

²Figure 13 and Figure 40 show impedance vs. frequency for the micro_SOIC and SOT respectively.

³Calculated using linear regression.

⁴Compensated for output reference temperature drift; see Applications section.

⁵SOT-23-6L operates in ground reference mode only.

⁶The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figures 35 and 36.

⁷Supply current is input level dependant; see Figure 12.

Speciﬁcations subject to change without notice.

REV. A

–2–

AD8361

PIN FUNCTION DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS¹

Supply Voltage V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

SREF, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V_S

IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V_S– 0.3 V, V_S

RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V rms

Equivalent Power re 50 Ω . . . . . . . . . . . . . . . . . . . 13 dBm

Internal Power Dissipation². . . . . . . . . . . . . . . . . . . . 200 mW

SOT-23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mW

micro_SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

Micro SOT Name

Description

1

6

VPOS

Supply Voltage Pin. Operational range

2.7 V to 5.5 V.

2

IREF

Output Reference Control Pin. Inter-

nal reference mode enabled when pin

is left open. Otherwise, this pin should

be tied to VPOS. DO NOT ground this

pin.

Signal Input Pin. Must be driven from

an ac-coupled source. The low frequency

real input impedance is 225 Ω.

3

4

5

4

RFIN

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²Specification is for the device in free air.

PWDN Power-Down Pin. For the device to

operate as a detector it needs a logical

low input (less than 100 mV). When

a logic high (greater than V_S– 0.5 V)

is applied, the device is turned off and

the supply current goes to nearly zero

(ground and internal reference mode

less than 1 µA, supply reference mode

V_Sdivided by 100 kΩ).

SOT-23-6L: θ_JA= 230°C/W; θ_JC= 92°C/W.

micro_SOIC: θ_JA= 200°C/W; θ_JC= 44°C/W.

PIN CONFIGURATIONS

micro_SOIC

5

6

2

3

COMM Device Ground Pin.

FLTR

By placing a capacitor between this pin

and VPOS, the corner frequency of the

modulation ﬁlter is lowered. The on-

chip ﬁlter is formed with 27 pFʈ2 kΩ

for small input signals.

VPOS

IREF

1

2

3

4

8

7

6

5

SREF

VRMS

FLTR

AD8361

RFIN

PWDN

COMM

7

8

1

VRMS Output Pin. Near-rail-to-rail voltage

output with limited current drive capa-

bilities. Expected load >10 kΩ to ground.

SOT-23-6L

SREF

Supply Reference Control Pin. To en-

able supply reference mode this pin

must be connected to VPOS, other-

wise it should be connected to COMM

(ground).

VRMS

COMM

FLTR

1

2

3

6

5

4

VPOS

RFIN

AD8361

PWDN

ORDERING GUIDE

Package Description

Model

Temperature Range

Package Option

AD8361ARM*

–40°C to +85°C

Tube, 8-Lead micro_SOIC

13" Tape and Reel

7" Tape and Reel

13" Tape and Reel

7" Tape and Reel

RM-8

AD8361ARM-REEL

AD8361ARM-REEL7

AD8361ART-REEL

AD8361ART-REEL7

AD8361-EVAL

RT-6

Evaluation Board micro_SOIC

AD8361ART-EVAL

Evaluation Board SOT-23-6L

*Device branded as J3A.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD8361 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

AD8361–Typical Performance Characteristics

2.8

3.0

2.5

900MHz

2.6

2.4

2.0

1.5

2.2

2.0

1.8

100MHz

1900MHz

1.0

0.5

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.5GHz

0

–0.5

–1.0

–1.5

–2.0

MEAN ؎3 SIGMA

–2.5

–3.0

0

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

0.1

0.2

0.3

0.4

0.5

INPUT – V rms

Figure 2. Output vs. Input Level, Frequencies 100 MHz,

900 MHz, 1900 MHz, and 2500 MHz, Supply 2.7 V, Ground

Reference Mode, micro_SOIC

Figure 5. Error from Linear Reference vs. Input Level,

3 Sigma to Either Side of Mean, Sine Wave, Supply 3.0 V,

Frequency 900 MHz

5.5

3.0

2.5

5.5V

5.0

2.0

1.5

1.0

0.5

0

4.5

5.0V

4.0

3.0V

3.5

3.0

2.5

–0.5

2.0

2.7V

–1.0

MEAN ؎3 SIGMA

–1.5

1.5

1.0

–2.0

0.5

0.0

–2.5

–3.0

0

0.01

0.02

(–21dBm)

0.1

0.6

(+8.6dBm)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

(–7dBm)

INPUT – V rms

Figure 3. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V,

and 5.5 V, Frequency 900 MHz

Figure 6. Error from Linear Reference vs. Input Level,

3 Sigma to Either Side of Mean, Sine-Wave, Supply 5.0 V,

Frequency 900 MHz

5.0

3.0

2.5

2.0

CW

IS95

REVERSE LINK

4.5

4.0

1.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

IS95

REVERSE LINK

1.0

0.5

0.0

CW

WCDMA

–0.5

–1.0

–1.5

–2.0

4-CHANNEL

4- AND 15-CHANNEL

15-CHANNEL

–2.5

–3.0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.01

0.02

0.1

0.2

0.6

1.0

INPUT – V rms

Figure 7. Error from CW Linear Reference vs. Input with

Different Waveforms Sine Wave (CW), IS95 Reverse Link,

W-CDMA 4-Channel and W-CDMA 15-Channel, Supply

3.0 V, Frequency 900 MHz

Figure 4. Output vs. Input Level with Different Waveforms

Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel

and W-CDMA 15-Channel, Supply 5.0 V

REV. A

–4–

AD8361

3.0

2.5

2.0

3.0

2.5

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

+85

؇

C

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

MEAN ؎3 SIGMA

–40

؇

–2.5

–3.0

–2.5

–3.0

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

INPUT – V rms

Figure 8. Error from CW Linear Reference vs. Input,

3 Sigma to Either Side of Mean, IS95 Reverse Link Signal,

Supply 3.0 V, Frequency 900 MHz

Figure 11. Output Delta from +25°C vs. Input Level,

3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V,

Frequency 1900 MHz, Temperature –40°C to +85°C

11

3.0

2.5

V

= 5V

S

10

INPUT OUT

OF RANGE

2.0

1.5

1.0

0.5

0

9

8

7

6

5

4

+25؇C

–40؇C

V

= 3V

S

INPUT OUT

OF RANGE

+85؇C

+25

؇C

–0.5

–1.0

+85

؇

C

MEAN ؎3 SIGMA

–1.5

3

2

–2.0

1

0

–2.5

–3.0

–40؇C

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.6

(+8.6dBm)

INPUT – V rms

Figure 9. Error from CW Linear Reference vs. Input Level,

3 Sigma to Either Side of Mean, IS95 Reverse Link Signal,

Supply 5.0 V, Frequency 900 MHz

Figure 12. Supply Current vs. Input Level, Supplies 3.0 V,

and 5.0 V, Temperatures –40°C, +25°C, and +85°C

3.0

2.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

250

200

150

+25؇C

+85؇C

1.5

–40؇C

+85؇C

1.0

0.5

+85؇C

0

–0.5

–1.0

–1.5

–2.0

100

50

0

+25؇C

–40؇C

–2.5

–3.0

0.4

2500

0.01

0.02

(–21dBm)

0.1

(–7dBm)

INPUT – V rms

0.4

(+5dBm)

0

500

1000

1500

2000

FREQUENCY – MHz

Figure 10. Output Delta from +25°C vs. Input Level,

3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V,

Frequency 900 MHz, Temperature –40°C to +85°C

Figure 13. Input Impedance vs. Frequency, Supply 3 V,

Temperatures –40°C, +25°C, and +85°C, micro_SOIC (See

Applications for SOT-23-6L Data)

REV. A

–5–

AD8361

0.03

0.02

0.01

0.18

0.16

0.14

0.12

0.10

MEAN ؎3 SIGMA

0.00

–0.01

–0.02

–0.03

–0.04

–0.05

0.08

0.06

0.04

0.02

0.00

MEAN ؎3 SIGMA

–0.02

–0.04

–0.06

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE –

؇

C

TEMPERATURE – ؇C

Figure 14. Output Reference Change vs. Temperature,

Supply 3 V, Ground Reference Mode

Figure 17. Conversion Gain Change vs. Temperature,

Supply 3 V, Ground Reference Mode, Frequency 900 MHz

0.02

0.01

0.00

0.18

0.16

0.14

0.12

0.10

MEAN ؎3 SIGMA

0.08

0.06

0.04

–0.01

0.02

0.00

MEAN ؎3 SIGMA

–0.02

–0.03

–0.02

–0.04

–0.06

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE – ؇C

TEMPERATURE –

؇

C

Figure 15. Output Reference Change vs. Temperature,

Supply 3 V, Internal Reference Mode (micro_SOIC Only)

Figure 18. Conversion Gain Change vs. Temperature,

Supply 3 V, Internal Reference Mode, Frequency 900 MHz

(micro_SOIC Only)

0.03

0.02

0.18

0.16

0.14

0.12

0.01

0.00

0.10

MEAN ؎3 SIGMA

0.08

–0.01

0.06

0.04

–0.02

MEAN ؎3 SIGMA

–0.03

0.02

0.00

–0.02

–0.04

–0.06

–0.04

–0.05

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE – ؇C

Figure 16. Output Reference Change vs. Temperature,

Supply 3 V, Supply Reference Mode (micro_SOIC Only)

Figure 19. Conversion Gain Change vs. Temperature,

Supply 3 V, Supply Reference Mode, Frequency 900 MHz

(micro_SOIC Only)

REV. A

–6–

AD8361

GATE PULSE FOR

900MHz RF TONE

PWDN INPUT

500mV PER

VERTICAL

DIVISION

370mV

270mV

370mV

270mV

500mV PER

VERTICAL

DIVISION

RF INPUT

67mV

25mV

5␮s PER HORIZONTAL DIVISION

2␮s PER HORIZONTAL DIVISION

Figure 23. Output Response Using Power-Down Mode

for Various RF Input Levels, Supply 3 V, Frequency

900 MHz, No Filter Capacitor

Figure 20. Output Response to Modulated Pulse Input

for Various RF Input Levels, Supply 3 V, Modulation

Frequency 900 MHz, No Filter Capacitor

GATE PULSE FOR

900MHz RF TONE

PWDN INPUT

370mV

500mV PER

VERTICAL

DIVISION

370mV

270mV

500mV PER

VERTICAL

DIVISION

RF INPUT

67mV

25mV

50␮s PER HORIZONTAL DIVISION

20␮s PER HORIZONTAL DIVISION

Figure 21. Output Response to Modulated Pulse Input

for Various RF Input Levels, Supply 3 V, Modulation

Frequency 900 MHz, 0.01 µF Filter Capacitor

Figure 24. Output Response Using Power-Down Mode

for Various RF Input Levels, Supply 3 V, Frequency

900 MHz, 0.01 µF Filter Capacitor

HPE3631A

POWER SUPPLY

HPE3631A

POWER SUPPLY

TEK TDS784C

SCOPE

TEK TDS784C

SCOPE

C2

100pF

C4

0.01␮F

AD8361

C2

100pF

C4

0.01␮F

AD8361

SREF

VPOS

SREF

VPOS

TEK P6204

FET PROBE

TEK P6204

VRMS

FLTR

IREF

VRMS

FLTR

FET PROBE

C1

0.1␮F

C3

C1

C3

C5

100pF

RFIN

100pF

R1

75⍀

R1

75⍀

0.1␮F

COMM

PWDN

COMM

PWDN

HP8648B

SIGNAL

HP8110A

PULSE

GENERATOR

Figure 22. Hardware Conﬁguration for Output Response

to Modulated Pulse Input

Figure 25. Hardware Conﬁguration for Output Response

Using Power-Down Mode

REV. A

–7–

AD8361

7.8

7.6

7.4

7.2

7.0

6.8

6.6

6.4

6.2

16

14

12

10

8

V

= 3V

S

6

4

6.0

5.8

2

0

6.9

5.6

100

7.0

7.2

7.4

7.6

7.8

1000

CARRIER FREQUENCY – MHz

CONVERSION GAIN – V/V rms

Figure 29. Conversion Gain Distribution Frequency

100 MHz, Supply 5 V, Sample Size 3000

Figure 26. Conversion Gain Change vs. Frequency, Supply

3 V, Ground Reference Mode, Frequency 100 MHz to

2500 MHz, Representative Device

12

RF

INPUT

SUPPLY

370mV

500mV PER

VERTICAL

DIVISION

10

8

270mV

6

67mV

25mV

4

2

20␮s PER HORIZONTAL DIVISION

0

0.32

0.34

0.36

0.38

0.40

0.42

0.44

IREF MODE INTERCEPT – Volts

Figure 27. Output Response to Gating On Power Supply,

for Various RF Input Levels, Supply 3 V, Modulation

Frequency 900 MHz, 0.01 µF Filter Capacitor

Figure 30. Output Reference, Internal Reference Mode,

Supply 5 V, Sample Size 3000 (micro_SOIC Only)

12

HP8110A

AD811

PULSE

GENERATOR

50⍀

10

8

TEK TDS784C

SCOPE

732⍀

C2

100pF

C4

AD8361

0.01␮F

6

4

2

0

SREF

VPOS

TEK P6204

VRMS

FLTR

IREF

FET PROBE

C1

0.1␮F

C3

C5

RFIN

100pF

R1

75⍀

COMM

PWDN

HP8648B

SIGNAL

0.64

0.66

0.68

0.70

0.72

0.74

0.76

SREF MODE INTERCEPT – Volts

GENERATOR

Figure 31. Output Reference, Supply Reference Mode,

Supply 5 V, Sample Size 3000 (micro_SOIC Only)

Figure 28. Hardware Conﬁguration for Output Response

to Power Supply Gating Measurements

REV. A

–8–

AD8361

eventual loss of square-law conformance. Consequently, the top

end of their response range occurs at a fairly large input level

(about 700 mV rms) while preserving a reasonably accurate

square-law response. The maximum usable range is, in practice,

limited by the output swing. The rail-to-rail output stage can

swing from a few millivolts above ground to less than 100 mV

below the supply. An example of the output induced limit: given

a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V

supply; the maximum input is (2.9 V rms)/7.5 or 390 mV rms.

CIRCUIT DESCRIPTION

The AD8361 is an rms-responding (mean power) detector pro-

viding an approach to the exact measurement of RF power that

is basically independent of waveform. It achieves this function

through the use of a proprietary technique in which the outputs

of two identical squaring cells are balanced by the action of a

high-gain error ampliﬁer.

The signal to be measured is applied to the input of the ﬁrst

squaring cell, which presents a nominal (LF) resistance of 225 Ω

between the pin RFIN and COMM (connected to the ground

plane). Since the input pin is at a bias voltage of about 0.8 V

above ground, a coupling capacitor is required. By making this

an external component, the measurement range may be extended

to arbitrarily low frequencies.

Filtering

An important aspect of rms-dc conversion is the need for

averaging (the function is root-MEAN-square). For complex RF

waveforms such as occur in CDMA, the ﬁltering provided by

the on-chip low-pass ﬁlter, while satisfactory for CW signals above

100 MHz, will be inadequate when the signal has modulation

components that extend down into the kilohertz region. For this

reason, the FLTR pin is provided: a capacitor attached between

this pin and VPOS can extend the averaging time to very low

frequencies.

The AD8361 responds to the voltage, V_IN, at its input, by squaring

this voltage to generate a current proportional to V_INsquared.

This is applied to an internal load resistor, across which is con-

nected a capacitor. These form a low-pass ﬁlter, which extracts

the mean of V_INsquared. Although essentially voltage-responding,

the associated input impedance calibrates this port in terms of

equivalent power. Thus 1 mW corresponds to a voltage input of

447 mV rms. In the Application section it is shown how to match

this input to 50 Ω.

Offset

An offset voltage can be added to the output (when using the

micro_SOIC version) to allow the use of A/D converters whose

range does not extend down to ground. However, accuracy at

the low end will be degraded because of the inherent error in this

added voltage. This requires that the pin IREF (internal reference)

should be tied to VPOS and SREF (supply reference) to ground.

The voltage across the low-pass ﬁlter, whose frequency may

be arbitrarily low, is applied to one input of an error-sensing

ampliﬁer. A second identical voltage-squaring cell is used to

close a negative feedback loop around this error ampliﬁer.

This second cell is driven by a fraction of the quasi-dc output

voltage of the AD8361. When the voltage at the input of the

second squaring cell is equal to the rms value of V_IN, the loop

is in a stable state, and the output then represents the rms value of

the input. The feedback ratio is nominally 0.133, making the

rms-dc conversion gain ×7.5, that is

In the IREF mode, the intercept is generated by an internal

reference cell, and is a ﬁxed 350 mV, independent of the supply

voltage. To enable this intercept, IREF should be open-circuited,

and SREF should be grounded.

In the SREF mode, the voltage is provided by the supply. To

implement this mode, tie IREF to VPOS and SREF to VPOS. The

offset is then proportional to the supply voltage, and is 400 mV

for a 3 V supply and 667 mV for a 5 V supply.

V_OUT= 7.5 × V_INrms

By completing the feedback path through a second squaring cell,

identical to the one receiving the signal to be measured, several

beneﬁts arise. First, scaling effects in these cells cancel; thus, the

overall calibration may be accurate, even though the open-loop

response of the squaring cells taken separately need not be.

Note that in implementing rms-dc conversion, no reference

voltage enters into the closed-loop scaling. Second, the tracking

in the responses of the dual cells remains very close over tempera-

ture, leading to excellent stability of calibration.

USING THE AD8361

Basic Connections

Figures 32, 33, and 34 show the basic connections for the

micro_SOIC version AD8361 in its three operating modes. In all

modes, the device is powered by a single supply of between 2.7 V

and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01 µF

capacitors. The quiescent current of 1.1 mA in operating mode

can be reduced to 1 µA by pulling the PWDN pin up to VPOS.

A 75 Ω external shunt resistance combines with the ac-coupled

input to give an overall broadband input impedance near 50 Ω.

Note that the coupling capacitor must be placed between the in-

put and the shunt impedance. Input impedance and input coupling

are discussed in more detail below.

The squaring cells have very wide bandwidth with an intrinsic

response from dc to microwave. However, the dynamic range

of such a system is fairly small, due in part to the much larger

dynamic range at the output of the squaring cells. There are

practical limitations to the accuracy with which very small error

signals can be sensed at the bottom end of the dynamic range,

arising from small random offsets; these set the limit to the

attainable accuracy at small inputs.

The input coupling capacitor combines with the internal input

resistance (Figure 13) to give a high-pass corner frequency

given by the equation

On the other hand, the squaring cells in the AD8361 have

a “Class-AB” aspect; the peak input is not limited by their

quiescent bias condition, but is determined mainly by the

1

f_{3 dB}

=

2 π × C_C× R_IN

REV. A

–9–

AD8361

With the 100 pF capacitor shown in Figures 32–34, the high-

pass corner frequency is about 8 MHz.

the output headroom decreases. The response for lower supply

voltages is similar (in the supply referenced mode, the offset is

smaller), but the dynamic range will be reduced further, as head-

room decreases. Figure 36 shows the response of the AD8361 to

a CW input for various supply voltages.

+V 2.7 – 5.5V

S

100pF

5.0

0.01␮F

SUPPLY REF

AD8361

4.5

1

2

3

4

SREF

8

7

6

5

VPOS

V rms

4.0

INTERNAL REF

C

IREF

VRMS

FLTR

C

100pF

3.5

RFIN

GROUND REF

3.0

R1

75⍀

CFLTR

COMM

PWDN

2.5

2.0

Figure 32. Basic Connections for Ground Referenced Mode

1.5

1.0

0.5

0.0

+V 2.7 – 5.5V

S

100pF

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.01␮F

AD8361

INPUT – V rms

1

2

3

4

SREF

VRMS

FLTR

8

7

6

5

VPOS

Figure 35. Output Swing for Ground, Internal and Supply

Referenced Mode. VPOS = 5 V (micro_SOIC Only)

V rms

IREF

C

RFIN

R1

75⍀

5.5

CFLTR

100pF

5.5V

COMM

PWDN

5.0

4.5

5.0V

Figure 33. Basic Connections for Internal Reference Mode

4.0

3.0V

3.5

+V 2.7 – 5.5V

S

3.0

2.5

100pF

2.0

2.7V

0.01␮F

AD8361

1.5

1.0

1

2

3

4

SREF

VRMS

FLTR

8

7

6

5

VPOS

V rms

IREF

0.5

0.0

C

RFIN

R1

75⍀

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

CFLTR

100pF

COMM

PWDN

INPUT – V rms

Figure 36. Output Swing for Supply Voltages of 2.7 V,

3.0 V, 5.0 V and 5.5 V (micro_SOIC Only)

Figure 34. Basic Connections for Supply Referenced Mode

Dynamic Range

The output voltage is nominally 7.5 times the input rms voltage

(a conversion gain of 7.5 V/V rms). Three different modes of

operation are set by the pins SREF and IREF. In addition to the

ground referenced mode shown in Figure 32, where the output

voltage swings from around near ground to 4.9 V on a 5.0 V

supply, two additional modes allow an offset voltage to be added to

the output. In the internal reference mode, (Figure 33), the

output voltage swing is shifted upward by an internal reference

voltage of 350 mV. In supply referenced mode (Figure 34), an

offset voltage of V_S/7.5 is added to the output voltage. Table I

summarizes the connections, output transfer function and mini-

mum output voltage (i.e., zero signal) for each mode.

Because the AD8361 is a linear responding device with a nomi-

nal transfer function of 7.5 V/V rms, the dynamic range in dB is

not clear from plots such as Figure 35. As the input level is

increased in constant dB steps, the output step size (per dB)

will also increase. Figure 37 shows the relationship between the

output step size (i.e., mV/dB) and input voltage for a nominal

transfer function of 7.5 V/V rms.

Table I. Connections and Nominal Transfer Function for

Ground, Internal, and Supply Reference Modes

Output

Intercept

(No Signal)

Output Swing

Reference

Mode

Figure 35 shows the output swing of the AD8361 for a 5 V supply

voltage for each of the three modes. It is clear from Figure 35,

that operating the device in either internal reference mode or

supply referenced mode, will reduce the effective dynamic range as

IREF

SREF

Output

Ground

Internal

Supply

VPOS

OPEN COMM

VPOS VPOS

COMM

Zero

0.350 V

V_S/7.5

7.5 V_IN

7.5 V_IN+ 0.350 V

7.5 V_IN+ V_S/7.5

REV. A

–10–

AD8361

A number of options exist for input matching. For operation at

multiple frequencies, a 75 Ω shunt to ground, as shown in Figure

39a, will provide the best overall match. For use at a single fre-

quency, a resistive or a reactive match can be used. By plotting the

input impedance on a Smith Chart, the best value for a

resistive match can be calculated. The VSWR can be held below

1.5 at frequencies up to 1 GHz, even as the input impedance

varies from part to part. (Both input impedance and input

capacitance can vary by up to 20% around their nominal values.)

At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt

resistor will not be sufﬁcient to reduce the VSWR below 1.5.

Where VSWR is critical, remove shunt component and insert

an inductor in series with the coupling capacitor as shown in

Figure 39b.

700

600

500

400

300

200

100

0

100

200

300

400

500

600

700

800

INPUT – mV

Table II gives recommended shunt resistor values for various

frequencies and series inductor values for high frequencies. The

coupling capacitor, C_C, essentially acts as an ac-short and plays

no intentional part in the matching.

Figure 37. Idealized Output Step Size as Function of Input

Voltage

Plots of output voltage vs. input voltage result in a straight line. It

may sometimes be more useful to plot the error on a logarith-

mic scale, as shown in Figure 38. The deviation of the plot for

the ideal straight line characteristic is caused by output clipping

at the high end and by signal offsets at the low end. It should

however be noted that offsets at the low end can be either posi-

tive or negative, so that this plot could also trend upwards at the

low end. Figures 5, 6, 8, and 9 show a 3 sigma distribution of

device error for a large population of devices.

C

RFIN

R

SH

AD8361

a. Broadband Resistor Match

L

C

M

RFIN

2.0

1.5

AD8361

b. Series Inductor Match

1.0

2.5GHz

0.5

C

M

100MHz

RFIN

0.0

1.9GHz

L

M

AD8361

–0.5

100MHz

–1.0

c. Narrowband Reactive Match

–1.5

900MHz

–2.0

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

1.0

C

R

SERIES

C

RFIN

INPUT – V rms

Figure 38. Representative Unit, Error in dB vs. Input Level,

V_S= 2.7 V

AD8361

d. Attenuating the Input Signal

It is also apparent in Figure 38 that the error plot tends to

shift to the right with increasing frequency. Because the input

impedance decreases with frequency, the voltage actually applied

to the input will also tend to decrease (assuming a constant source

impedance over frequency). The dynamic range is almost con-

stant over frequency, but with a small decrease in conversion gain

at high frequency.

Figure 39. Input Coupling/Matching Options

Table II. Recommended Component Values for Resistive or

Inductive Input Matching (Figures 39a and 39b)

Frequency

Matching Component

100 MHz

800 MHz

900 MHz

1800 MHz

1900 MHz

2500 MHz

63.4 Ω Shunt

Input Coupling and Matching

75 Ω Shunt

The input impedance of the AD8361 decreases with increasing

frequency in both its resistive and capacitive components (Figure

13). The resistive component varies from 225 Ω at 100 MHz

down to about 95 Ω at 2.5 GHz.

75 Ω Shunt

150 Ω Shunt or 4.7 nH Series

150 Ω Shunt or 2.7 nH Series

REV. A

–11–

AD8361

Alternatively, a reactive match can be implemented using a shunt

inductor to ground and a series capacitor as shown in Figure

39c. A method for hand calculating the appropriate matching

components is shown on page 12 of the AD8306 data sheet.

provides adequate ﬁltering for all frequencies above 240 MHz

(i.e., ten times the frequency at the output of the squarer, which

is twice the input frequency). However, signals with high peak-

to-average ratios, such as CDMA or W-CDMA signals, and

with low frequency components, require additional ﬁltering.

TDMA signals, such as GSM, PDC, or PHS have a peak-to-

average ratio that is close to that of a sinusoid, and the internal

ﬁlter is adequate.

Matching in this manner results in very small values for C_M,

especially at high frequencies. As a result, a stray capacitance as

small as 1 pF can signiﬁcantly degrade the quality of the match.

The main advantage of a reactive match is the increase in sensi-

tivity that results from the input voltage being “gained up” (by

the square root of the impedance ratio) by the matching network.

Table III shows recommended values for reactive matching.

The ﬁlter capacitance of the AD8361 can be augmented by

connecting a capacitor between Pin 6 (FLTR) and VPOS.

Table IV shows the effect of several capacitor values for various

communications standards with high peak-to-average ratios along

with the residual ripple at the output, in peak-to-peak and rms

volts. Note that large ﬁlter capacitors will increase the enable

and pulse response times, as discussed below.

Table III. Recommended Values for a Reactive Input Match

(Figure 39c)

Frequency

MHz

C_M

pF

L_M

nH

Table IV. Effect of Waveform and C_FILTon Residual AC

100

800

900

16

2

180

15

12

Output

V dc

Residual AC

mV p-p mV rms

Waveform

C_FILT

1800

1900

2500

1.5

4.7

3.3

IS95 Reverse Link Open

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

550

1000

2000

40

160

430

20

100

180

360

6

20

60

3

0.01 µF

Input Coupling Using a Series Resistor

Figure 39d shows a technique for coupling the input signal

into the AD8361, which may be applicable where the input signal

is much larger than the input range of the AD8361. A series

resistor combines with the input impedance of the AD8361 to

attenuate the input signal. Since this series resistor forms a

divider with the frequency-dependent input impedance, the

apparent gain changes greatly with frequency. However, this

method has the advantage of very little power being “tapped

off” in RF power transmission applications. If the resistor is large

compared to the transmission line’s impedance then the VSWR of

the system is relatively unaffected.

0.1 µF

0.01 µF

0.1 µF

0.01 µF

0.1 µF

40

6

110

290

975

2600

50

190

670

225

940

2500

45

18

40

150

430

7

30

95

35

135

390

6

IS95 8-Channel

Forward Link

W-CDMA 15

Channel

1.7

250

165

550

25

80

1.4

1.1

0.8

200

150

100

Operation at Low Frequencies

Although the AD8361 is speciﬁed for operation up to 2.5 GHz,

there is no lower limit on the operating frequency. It is only nec-

essary to increase the input coupling capacitor to reduce the

corner frequency of the input high-pass ﬁlter (use an input resis-

tance of 225 Ω for frequencies below 100 MHz). It is also

necessary to increase the ﬁlter capacitor so that the signal at the

output of the squaring circuit is free of ripple. The corner fre-

quency will be set by the combination of the internal resistance of

2 kΩ and the external ﬁlter capacitance.

0.5

0.2

50

0

500

1000

1500

2000

2500

3000

3500

FREQUENCY – MHz

Power Consumption, Enable and Power-On

Figure 40. Input Impedance vs. Frequency, Supply 3 V,

SOT-23-6L

The quiescent current consumption of the AD8361 varies with

the size of the input signal from about 1 mA for no signal up to

7 mA at an input level of 0.66 V rms (9.4 dBm re 50 Ω). If the

input is driven beyond this point, the supply current increases

steeply (see Figure 12). There is little variation in quiescent

current with power supply voltage.

Selecting the Filter Capacitor

The AD8361’s internal 27 pF ﬁlter capacitor is connected in

parallel with an internal resistance that varies with signal level

from 2 kΩ for small signals to 500 Ω for large signals. The

resulting low-pass corner frequency between 3 MHz and 12 MHz

REV. A

–12–

AD8361

The AD8361 can be disabled either by pulling the PWDN (Pin 4)

to VPOS or by simply turning off the power to the device. While

turning off the device obviously eliminates the current consump-

tion, disabling the device reduces the leakage current to less

than 1 µA. Figures 23 and 24 show the response of the output of

the AD8361 to a pulse on the PWDN pin, with no capacitance and

with a ﬁlter capacitance of 0.01 µF respectively; the turn-on time is

a function of the ﬁlter capacitor. Figure 27 shows a plot of the

output response to the supply being turned on (i.e., PWDN is

grounded and VPOS is pulsed) with a ﬁlter capacitor of 0.01 µF

Again, the turn-on time is strongly influenced by the size of the

ﬁlter capacitor.

current is required (>10 mA), the AD8051, which also has rail-

to-rail capability, can be used, down to a supply voltage of 3 V. It

can deliver up to 45 mA of output current.

5V

100pF

0.01␮F

VPOS

VOUT

AD8031

15V/V rms

AD8361

COMM PWDN

5k⍀

If the input of the AD8361 is driven while the device is disabled

(PWDN = VPOS), the leakage current of less than 1 µA will

increase as a function of input level. When the device is dis-

abled, the output impedance increases to around 16 kΩ.

5k⍀

a. Slope of 15 V/V rms

Volts to dBm Conversion

5V

In many of the plots, the horizontal axis is scaled in both rms

volts and dBm. In all cases, dBm are calculated relative to an

impedance of 50 Ω. To convert between dBm and volts in a

50 Ω. system, the following equations can be used. Figure 40

shows this conversion in graphical form.

100pF

0.01␮F

10k⍀

VPOS

VOUT

0.01␮F

5k⍀

AD8361

AD8031

3.75V/V rms

2

COMM PWDN









(V rms)

50 Ω

Power (dBm) = 10log

= 10 log (20 (V rms)²)

b. Slope of 3.75 V/V rms

0.001W









5V

100pF

0.01␮F

log^–1dBm/10

0.01␮F





(

)

dBm

VPOS

V rms = 0.001W × 50 Ω × log^–1

=





VOUT

10

20





AD8031

7.5V/V rms

AD8361

COMM PWDN

V rms

dBm

+20

1

+10

c. Slope of 7.5 V/V rms

0

Figure 42. Output Buffering Options

0.1

–10

–20

–30

–40

OUTPUT REFERENCE TEMPERATURE DRIFT

COMPENSATION

The error due to low temperature drift of the AD8361 can be

reduced if the temperature is known. Many systems incorporate

a temperature sensor; the output of the sensor is typically digi-

tized, facilitating a software correction. Using this information,

only a two-point calibration at ambient is required.

0.01

0.001

Figure 41. Conversion from dBm to rms Volts

The output voltage of the AD8361 at ambient (25°C) can be

expressed by the equation:

Output Drive Capability and Buffering

The AD8361 is capable of sourcing an output current of approxi-

mately 3 mA. If additional current is required, a simple buffering

circuit can be used as shown in Figure 42c. Similar circuits

can be used to increase or decrease the nominal conversion gain of

7.5 V/V rms (Figure 42a and 42b). In Figure 42b, the AD8031

buffers a resistive divider to give a slope of 3.75 V/V rms. In Figure

42a, the op amp’s gain of two increases the slope to 15 V/V rms.

Using other resistor values, the slope can be changed to an

arbitrary value. The AD8031 rail-to-rail op amp, used in these

examples can swing from 50 mV to 4.95 V on a single 5 V supply

and operate at supply voltages down to 2.7 V. If high output

V_OUT= GAIN ×V_IN+V_OS

(

)

where GAIN is the conversion gain in V/V rms and V_OSis the

extrapolated output voltage for an input level of 0 V. GAIN and

V_OS(also referred to as Intercept and Output Reference) can be

calculated at ambient using a simple two-point calibration;

that is, by measuring the output voltages for two specific input

levels. Calibration at roughly 35 mV rms (–16 dBm) and

250 mV rms (+1 dBm) is recommended for maximum linear

dynamic range. However, alternative levels and ranges can be

REV. A

–13–

AD8361

chosen to suit the application. GAIN and V_OSare then calculated

using the equations:

V_OUT= GAIN ×V_IN+V_OS+ DRIFT_VOS× TEMP − 25°C

(

)

(

)

The equation can be rewritten to yield a temperature compen-

sated value for V_IN.

V_OUT2−V_OUT1

(

)

GAIN =

V

−V

(

IN2

IN1

)

V_OUT−V_OS− DRIFT_VOS× TEMP − 25°C

(

)

(

V_IN

=

GAIN

V_OS=V_OUT1− GAIN ×V_IN1

(

)

Both GAIN and V_OSdrift over temperature. However, the drift

of V_OShas a bigger influence on the error relative to the output.

This can be seen by inserting data from Figures 14 and 17 (con-

version gain and intercept drift) into the equation for V_OUT. These

plots are consistent with Figures 10 and 11 which show that the

error due to temperature drift decreases with increasing input

level. This results from the offset error having a diminishing

influence with increasing level on the overall measurement error.

EVALUATION BOARD

Figures 43 and 46 show the schematic of the AD8361 evalua-

tion board. Note that uninstalled components are drawn in as

dashed. The layout and silkscreen of the component side are

shown in Figures 44, 45, 47, and 48. The board is powered by a

single supply in the range, 2.7 V to 5.5 V. The power supply

is decoupled by 100 pF and 0.01 µF capacitors. Additional

decoupling, in the form of a series resistor or inductor in R6,

can also be added. Table V details the various conﬁguration

options of the evaluation board.

From Figure 14, the average Intercept drift is 0.43 mV/°C from

–40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a

less rigorous compensation scheme, the average drift over the

complete temperature range can be calculated:





0.010V − −0.028V

(

)

DRIFT

V/°C

=

(

)

VOS





+85°C − −40°C

(

)





= 0.000304 V/°C

With the drift of V_OSincluded, the equation for V_OUTbecomes:

Table V. Evaluation Board Conﬁguration Options

Component

Function

Default Condition

TP1, TP2

SW1

Ground and Supply Vector Pins.

Not Applicable

SW1 = B

Device Enable. When in Position A, the PWDN pin is connected to +V_Sand

the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded,

putting the device in operating mode.

SW2/SW3

C1, R2

Operating Mode. Selects either Ground Referenced Mode, Internal Reference

Mode or Supply Reference Mode. See Table I for more details.

Input Coupling. The 75 Ω resistor in position R2 combines with the AD8361’s

internal input impedance to give a broadband input impedance of around 50 Ω.

For more precise matching at a particular frequency, R2 can be replaced by a

different value (see Input Matching and Figure 39).

SW2 = A, SW3 = B

(Ground Reference Mode)

R2 = 75 Ω (Size 0402)

C1 = 100 pF (Size 0402)

Capacitor C1 ac-couples the input signal and creates a high-pass input ﬁlter

whose corner frequency is equal to approximately 8 MHz. C1 can be increased

for operation at lower frequencies. If resistive attenuation is desired at the input,

series resistor R1, which is nominally 0 Ω, can be replaced by an appropriate value.

C2, C3, R6

Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and

100 pF. A series inductor or small resistor can be placed in R6 for additional

decoupling.

C2 = 0.01 µF (Size 0402)

C3 = 100 pF (Size 0402)

R6 = 0 Ω (Size 0402)

C5

Filter Capacitor. The internal 50 pF averaging capacitor can be augmented

by placing a capacitance in C5.

C5 = 1 nF (Size 0603)

C4, R5

Output Loading. Resistors and capacitors can be placed in C4 and R5 to

load test V rms.

C4 = R5 = Open

(Size 0603)

REV. A

–14–

AD8361

VPOS

R6

C3

100pF

C2

0.01␮F

TP2

R4

C2

C3

V

AD8361

S

J2

0⍀

0.01␮F

100pF

0⍀

VPOS

1

2

3

VRMS

6

5

VPOS

TP2

SW3

V

S

A

B

AD8361

J1

C4

R5

OPEN

SW2

COMM RFIN

1

2

3

4

SREF

VRMS

FLTR

8

7

6

5

VPOS

A

B

R4

C1

100pF

R2

75⍀

0⍀

C1

100pF

V

rms

IREF

4

PWDN

J3

FLTR

R5

(OPEN

C4

(OPEN

C5

)

RFIN

VPOS

TP1

RFIN

1nF

3

2

R2

75⍀

1nF

1

TP1

PWDN

COMM

SW1

VPOS

R7

50⍀

A

B

SW1

Figure 43. Evaluation Board Schematic micro_SOIC

Figure 44. Layout of Component Side micro_SOIC

Figure 45. Silkscreen of Component Side micro_SOIC

Figure 46. Evaluation Board Schematic, SOT-23-6L

Figure 47. Layout of the Component Side, SOT-23-6L

Figure 48. Silkscreen of the Component Side, SOT-23-6L

REV. A

–15–

AD8361

The Error from Linear Response to CW waveform is the difference

in output from the ideal output deﬁned by the conversion gain

and output reference. This is a measure of both the linearity of

the device response to both CW and modulated waveforms. The

error in dB uses the conversion gain multiplied times the input

as its reference. Error from Linear Response to CW waveform is not a

measure of absolute accuracy, since it is calculated using the

gain and output reference of each device. But it does show the

linearity and effect of modulation on the device response.

Error from 25°C performance uses the performance of a given

device and waveform type as the reference; it is predomi-

nantly a measure of output variation with temperature.

Problems caused by impedance mismatch may arise using the

evaluation board to examine the AD8361 performance. One

way to reduce these problems is to put a coaxial 3 dB attenuator

on the RFIN SMA connector. Mismatches at the source, cable,

and cable interconnection, as well as those occurring on the

evaluation board can cause these problems.

A simple (and common) example of such problem is triple travel

due to mismatch at both the source and the evaluation board.

Here the signal from the source reaches the evaluation board

and mismatch causes a reflection. When that reflection reaches

the source mismatch, it causes a new reflection, which travels

back to the evaluation board adding to the original signal inci-

dent at the board. The resultant voltage will vary with both

cable length and frequency dependent upon the relative phase of

the initial and reflected signals. Placing the 3 dB pad at the

input of the board improves the match at the board and thus

reduces the sensitivity to mismatches at the source. When such

precautions are taken, measurements will be less sensitive to

cable length and other fixturing issues. In an actual application

when the distance between AD8361 and source is short and well

defined, this 3 dB attenuator is not needed.

C4

C2

0.1␮F 100pF

AD8361

1

2

3

4

SREF

8

7

6

5

SREF

VRMS

VPOS

IREF

RFIN

IREF

VRMS

FLTR

C3

RFIN

R1

75⍀

C1

0.1␮F

COMM

PWDN

CHARACTERIZATION SETUPS

Equipment

Figure 49. Characterization Board

The primary characterization setup is shown in Figure 50. The

signal source used was a Rohde & Schwarz SMIQ03B, version

3.90HX. The modulated waveforms used for IS95 reverse link,

IS95 nine active channels forward (Forward Link 18 setting),

W-CDMA 4- and 15-channel were generated using the default

settings coding and ﬁltering. Signal levels were calibrated into a

50 Ω impedance.

AD8361

CHARACTERIZATION

BOARD

DC OUTPUT

RF SIGNAL

SMIQ038B

RF SOURCE

RFIN

VRMS

3dB

ATTENUATOR

PRUP +V

SREF IREF

S

Analysis

DC SOURCES

The conversion gain and output reference are derived using the

coefﬁcients of a linear regression performed on data collected in

its central operating range (35 mV rms to 250 mV rms). This

range was chosen to avoid areas of operation where offset distorts

the linear response. Error is stated in two forms Error from Linear

Response to CW waveform and Output Delta from 25°C performance.

IEEE BUS

PC CONTROLLER

DC MATRIX / DC SUPPLIES / DMM

Figure 50. Characterization Setup

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

6-Lead SOT-23-6L Package

(RT-6)

8-Lead micro_SOIC Package

(RM-8)

0.122 (3.10)

0.106 (2.70)

0.122 (3.10)

0.114 (2.90)

8

5

4

6

1

5

2

4

3

0.071 (1.80)

0.059 (1.50)

0.118 (3.00)

0.098 (2.50)

0.193

(4.90)

BSC

0.122 (3.10)

0.114 (2.90)

1

PIN 1

0.037 (0.95) BSC

PIN 1

0.0256 (0.65) BSC

0.037 (0.95)

0.030 (0.75)

0.075 (1.90)

BSC

0.043

(1.10)

MAX

0.006 (0.15)

0.002 (0.05)

0.051 (1.30)

6؇

0؇

0.057 (1.45)

0.035 (0.90)

0.016 (0.40)

0.035 (0.90)

0.028 (0.70)

0.016 (0.40)

SEATING

PLANE

0.009 (0.23)

0.005 (0.13)

0.010 (0.25)

10؇

0؇

0.020 (0.50)

0.010 (0.25)

0.006 (0.15)

0.000 (0.00)

0.022 (0.55)

0.014 (0.35)

SEATING

PLANE

0.009 (0.23)

0.003 (0.08)

–16–

REV. A


型号：	AD8361ART-REEL7
厂家：	ADI
描述：	LF to 2.5 GHz TruPwr⑩ Detector LF至2.5 GHz TruPwr ？探测器模拟IC 信号电路光电二极管
文件：	总16页 (文件大小：307K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8361ART-REEL7 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E