AD8361_15_技术文档

LF to 2.5 GHz

TruPwr™ Detector

AD8361

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Calibrated rms response

Excellent temperature stability

VPOS

FLTR

INTERNAL FILTER

i

2

χ

RFIN

Up to 30 dB input range at 2.5 GHz

700 mV rms, 10 dBm, re 50 Ω maximum input

0.25 dB linear response up to 2.5 GHz

Single-supply operation: 2.7 V to 5.5 V

Low power: 3.3 mW at 3 V supply

Rapid power-down to less than 1 µA

TRANS-

CONDUCTANCE

CELLS

AD8361

ERROR

AMP

i

2

× 7.5

BUFFER

χ

VRMS

ADD

OFFSET

BAND-GAP

REFERENCE

SREF

PWDN

COMM

APPLICATIONS

IREF

Measurement of CDMA, W-CDMA, QAM, other complex

modulation waveforms

RF transmitter or receiver power measurement

Figure 2. 8-Lead MSOP

VPOS

FLTR

INTERNAL FILTER

i

2

χ

RFIN

GENERAL DESCRIPTION

TRANS-

AD8361

CONDUCTANCE

CELLS

The AD8361 is a mean-responding power detector for use in

high frequency receiver and transmitter signal chains, up to

2.5 GHz. It is very easy to apply. It requires a single supply only

between 2.7 V and 5.5 V, a power supply decoupling capacitor,

and an input coupling capacitor in most applications. The

output is a linear-responding dc voltage with a conversion gain

of 7.5 V/V rms. An external filter capacitor can be added to

increase the averaging time constant.

ERROR

AMP

2

× 7.5

BUFFER

χ

VRMS

COMM

BAND-GAP

REFERENCE

PWDN

IREF

Figure 3. 6-Lead SOT-23

3.0

2.8

The AD8361 is intended for true power measurement of simple

and complex waveforms. The device is particularly useful for

measuring high crest-factor (high peak-to-rms ratio) signals,

such as CDMA and W-CDMA.

SUPPLY

REFERENCE MODE

2.6

2.4

2.2

2.0

1.8

1.6

INTERNAL

REFERENCE MODE

The AD8361 has three operating modes to accommodate a

variety of analog-to-digital converter requirements:

1.4

1.2

1.0

0.8

0.6

GROUND

REFERENCE MODE

1. Ground reference mode, in which the origin is zero.

2. Internal reference mode, which offsets the output 350 mV

above ground.

0.4

0.2

0.0

3. Supply reference mode, which offsets the output to V_S/7.5.

The AD8361 is specified for operation from −40°C to +85°C

and is available in 8-lead MSOP and 6-lead SOT-23 packages. It

is fabricated on a proprietary high f_Tsilicon bipolar process.

0

0.1

0.2

0.3

0.4

0.5

RFIN (V rms)

Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz

(6-Lead SOT-23 Package Ground Reference Mode Only)

Rev. F

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Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD8361

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ..............................................6

Circuit Description......................................................................... 11

Application Information................................................................ 12

Output Reference Temperature Drift Compensation ........... 16

Evaluation Board ............................................................................ 19

Characterization Setups............................................................. 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

REVISION HISTORY

7/15—Rev. E to Rev. F

8/04—Rev. B to Rev. C

Change to Ordering Guide............................................................ 22

Changed Trimpots to Trimmable Potentiometers.........Universal

Changes to Specifications.................................................................3

Changed Using the AD8361 Section Title to Applications....... 12

Changes to Figure 43...................................................................... 14

Changes to Ordering Guide.......................................................... 24

Updated Outline Dimensions....................................................... 24

5/15—Rev. D to Rev. E

Deleted Dynamic Range Extension for the AD8361 Section,

Figure 60, Renumbered Sequentially........................................... 19

Deleted Figure 61, Figure 62, Figure 63, and Figure 64 ............ 20

3/14—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 24

Updated Outline Dimensions....................................................... 24

Rev. F | Page 2 of 22

Data Sheet

AD8361

SPECIFICATIONS

T_A= 25°C, V_S= 3 V, f_RF= 900 MHz, ground reference output mode, unless otherwise noted.

Table 1.

Parameter

Condition

Min

Typ

Max

Unit

SIGNAL INPUT INTERFACE

Frequency Range¹

(Input RFIN)

2.5

GHz

Linear Response Upper Limit

V_S= 3 V

Equivalent dBm, re 50 Ω

V_S= 5 V

390

4.9

660

9.4

mV rms

dBm

mV rms

dBm

Equivalent dBm, re 50 Ω

Input Impedance²

RMS CONVERSION

Conversion Gain

225||1

Ω||pF

(Input RFIN to Output V rms)

7.5

V/V rms

f_RF= 100 MHz, V_S= 5 V

6.5

8.5

Dynamic Range

0.25 dB Error⁴

1 dB Error

Error Referred to Best Fit Line³

CW Input, −40°C < T_A< +85°C

CW Input, V_S= 5 V, −40°C < T_A< +85°C

Internal Reference Mode

Supply Reference Mode, V_S= 3.0 V

Supply Reference Mode, V_S= 5.0 V

5.5 dB Peak-to-Average Ratio (IS95 Reverse Link)

12 dB Peak-to-Average Ratio (W-CDMA 4 Channels)

18 dB Peak-to-Average Ratio (W-CDMA 15 Channels)

Inferred from Best Fit Line³

14

23

26

30

1

dB

2 dB Error

Intercept-Induced Dynamic

Range Reduction^{5, 6}

1

1.5

0.2

1.0

1.2

Deviation from CW Response

OUTPUT INTERCEPT⁵

Ground Reference Mode (GRM)

0 V at SREF, V_Sat IREF

0

V

f_RF= 100 MHz, V_S= 5 V

0 V at SREF, IREF Open

f_RF= 100 MHz, V_S= 5 V

3 V at IREF, 3 V at SREF

V_Sat IREF, V_Sat SREF

f_RF= 100 MHz, V_S= 5 V

−50

300

+150 mV

mV

Internal Reference Mode (IRM)

Supply Reference Mode (SRM)

350

500

750

0.1

mV

V

400

V_S/7.5

590

mV

POWER-DOWN INTERFACE

PWDN HI Threshold

PWDN LO Threshold

2.7 ≤ V_S≤ 5.5 V, −40°C < T_A< +85°C

2 pF at FLTR Pin, 224 mV rms at RFIN

100 nF at FLTR Pin, 224 mV rms at RFIN

V_S− 0.5

V

Power-Up Response Time

5

320

<1

μs

μA

PWDN Bias Current

POWER SUPPLIES

Operating Range

Quiescent Current

Power-Down Current

−40°C < T_A< +85°C

2.7

5.5

V

0 mV rms at RFIN, PWDN Input LO⁷

GRM or IRM, 0 mV rms at RFIN, PWDN Input HI

SRM, 0 mV rms at RFIN, PWDN Input HI

1.1

<1

10 × V_S

mA

μA

¹Operation at arbitrarily low frequencies is possible; see Application Information section.

²Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively.

³Calculated using linear regression.

⁴Compensated for output reference temperature drift; see Application Information section.

⁵SOT-23-6L operates in ground reference mode only.

⁶The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40.

⁷Supply current is input level dependent; see Figure 16.

Rev. F | Page 3 of 22

AD8361

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

Parameter

Rating

5.5 V

0 V, V_S

Supply Voltage V_S

SREF, PWDN

IREF

RFIN

V_S− 0.3 V, V_S

1 V rms

13 dBm

200 mW

170 mW

200 mW

Equivalent Power, re 50 Ω

Internal Power Dissipation¹

6-Lead SOT-23

8-Lead MSOP

ESD CAUTION

Maximum Junction Temperature 125°C

Operating Temperature Range

Storage Temperature Range

Lead Temperature Range

(Soldering 60 sec)

−40°C to +85°C

−65°C to +150°C

300°C

¹Specification is for the device in free air.

6-Lead SOT-23: θ_JA= 230°C/W; θ_JC= 92°C/W.

8-Lead MSOP: θ_JA= 200°C/W; θ_JC= 44°C/W.

Rev. F | Page 4 of 22

Data Sheet

AD8361

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VRMS

COMM

FLTR

1

2

3

6

5

4

VPOS

RFIN

VPOS

IREF

1

2

3

4

8

7

6

5

SREF

VRMS

FLTR

AD8361

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

RFIN

PWDN

COMM

PWDN

Figure 4. 8-Lead MSOP

Figure 5. 6-Lead SOT-23

Table 3. Pin Function Descriptions

Pin No.

MSOP

Pin No.

SOT-23 Mnemonic Description

1

2

6

N/A

VPOS

IREF

Supply Voltage Pin. Operational range 2.7 V to 5.5 V.

Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this

pin should be tied to VPOS. Do not ground this pin.

3

4

5

4

RFIN

Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance is

225 Ω.

Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than

100 mV). When a logic high (greater than V_S− 0.5 V) is applied, the device is turned off and the supply

current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference

mode V_Sdivided by 100 kΩ).

PWDN

5

6

2

3

COMM

FLTR

Device Ground Pin.

By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is

lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals.

7

8

1

VRMS

SREF

Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load

>10 kΩ to ground.

Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;

otherwise, it should be connected to COMM (ground).

N/A

Rev. F | Page 5 of 22

AD8361

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

2.8

3.0

2.5

900MHz

2.6

2.4

2.0

1.5

2.2

2.0

1.8

100MHz

1900MHz

1.0

0.5

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.5GHz

0

–0.5

–1.0

–1.5

–2.0

MEAN ±3 SIGMA

–2.5

–3.0

0

0.1

0.2

0.3

0.4

0.5

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

INPUT (V rms)

Figure 6. Output vs. Input Level, Frequencies 100 MHz, 900 MHz,

1900 MHz, and 2500 MHz, Supply 2.7 V, Ground Reference Mode, MSOP

Figure 9. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of

Mean, Sine Wave, Supply 3.0 V, Frequency 900 MHz

5.5

3.0

2.5

5.5V

5.0

2.0

1.5

1.0

0.5

0

4.5

5.0V

4.0

3.5

3.0V

3.0

2.5

–0.5

2.0

2.7V

–1.0

MEAN ±3 SIGMA

1.5

1.0

–1.5

–2.0

0.5

0.0

–2.5

–3.0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.6

(+8.6dBm)

INPUT (V rms)

Figure 10. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side

of Mean, Sine Wave, Supply 5.0 V, Frequency 900 MHz

Figure 7. Output vs. Input Level,

Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz

3.0

2.5

2.0

5.0

4.5

CW

IS95

REVERSE LINK

4.0

1.5

IS95

REVERSE LINK

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.0

0.5

0.0

CW

WCDMA

4- AND 15-CHANNEL

–0.5

–1.0

–1.5

–2.0

4-CHANNEL

15-CHANNEL

–2.5

–3.0

0

0.01

0.02

0.1

0.2

0.6

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

INPUT (V rms)

Figure 11. Error from CW Linear Reference vs. Input with Different

Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and

W-CDMA 15-Channel, Supply 3.0 V, Frequency 900 MHz

Figure 8. Output vs. Input Level with

Different Waveforms Sine Wave (CW), IS95 Reverse Link,

W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 5.0 V

Rev. F | Page 6 of 22

Data Sheet

AD8361

3.0

2.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

+85°C

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

MEAN 3 SIGMA

–40°C

–2.5

–3.0

2.5

–3.0

0.01

0.02

(–21dBm)

0.1

(–7dBm)

INPUT (V rms)

0.4

(+5dBm)

0.02

(–21dBm)

0.1

(–7dBm)

INPUT (V rms)

0.4

(+5dBm)

Figure 15. Output Delta from +25°C vs. Input Level, 3 Sigma to Either

Side of Mean Sine Wave, Supply 3.0 V, Frequency 1900 MHz,

Temperature −40°C to +85°C

Figure 12. Error from CW Linear Reference vs. Input, 3 Sigma to Either Side of

Mean, IS95 Reverse Link Signal, Supply 3.0 V, Frequency 900 MHz

11

3.0

2.5

V

= 5V

S

10

INPUT OUT

OF RANGE

2.0

1.5

1.0

0.5

0

9

8

7

6

5

4

+25°C

–40°C

V

= 3V

S

INPUT OUT

OF RANGE

+85°C

–0.5

+25°C

+85°C

–1.0

MEAN 3 SIGMA

3

2

–1.5

–2.0

1

0

–2.5

–3.0

–40°C

0.2

0

0.01

0.02

0.1

0.6

0.1

0.3

0.4

0.5

0.6

0.7

0.8

(–21dBm)

(–7dBm)

INPUT (V rms)

(+8.6dBm)

INPUT (V rms)

Figure 13. Error from CW Linear Reference vs. Input Level, 3 Sigma to Either

Side of Mean, IS95 Reverse Link Signal, Supply 5.0 V, Frequency 900 MHz

Figure 16. Supply Current vs. Input Level, Supplies 3.0 V, and 5.0 V,

Temperatures −40°C, +25°C, and +85°C

1.8

3.0

2.5

2.0

250

+25°C

–40°C

+85°C

1.6

1.4

1.2

1.0

0.8

0.6

200

150

1.5

+85°C

1.0

0.5

0

–0.5

–1.0

100

50

0

+25°C

–40°C

–1.5

–2.0

–2.5

–3.0

0.4

2500

0.01

0.02

(–21dBm)

0.1

0.4

(+5dBm)

0

500

1000

1500

2000

(–7dBm)

FREQUENCY (MHz)

INPUT (V rms)

Figure 14. Output Delta from +25°C vs. Input Level, 3 Sigma to

Either Side of Mean Sine Wave, Supply 3.0 V,

Figure 17. Input Impedance vs. Frequency, Supply 3 V,

Temperatures −40°C, +25°C, and +85°C, MSOP

(See the Application Information Section for SOT-23 Data)

Frequency 900 MHz, Temperature −40°C to +85°C

Rev. F | Page 7 of 22

AD8361

Data Sheet

0.03

0.02

0.01

0.18

0.16

0.14

0.12

0.10

MEAN ±3 SIGMA

0.00

–0.01

–0.02

–0.03

–0.04

–0.05

0.08

0.06

0.04

0.02

0.00

MEAN ±3 SIGMA

–0.02

–0.04

–0.06

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 21. Conversion Gain Change vs. Temperature, Supply 3 V,

Ground Reference Mode, Frequency 900 MHz

Figure 18. Output Reference Change vs. Temperature,

Supply 3 V, Ground Reference Mode

0.02

0.01

0.18

0.16

0.14

0.12

0.10

MEAN ±3 SIGMA

0.00

0.08

0.06

0.04

–0.01

–0.02

–0.03

0.02

0.00

MEAN ±3 SIGMA

–0.02

–0.04

–0.06

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 19. Output Reference Change vs. Temperature, Supply 3 V,

Internal Reference Mode (MSOP Only)

Figure 22. Conversion Gain Change vs. Temperature, Supply 3 V,

Internal Reference Mode, Frequency 900 MHz (MSOP Only)

0.03

0.02

0.01

0.18

0.16

0.14

0.12

0.10

0.00

MEAN ±3 SIGMA

0.08

–0.01

0.06

0.04

–0.02

0.02

0.00

MEAN ±3 SIGMA

–0.03

–0.02

–0.04

–0.05

–0.04

–0.06

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 20. Output Reference Change vs. Temperature, Supply 3 V,

Supply Reference Mode (MSOP Only)

Figure 23. Conversion Gain Change vs. Temperature, Supply 3 V,

Supply Reference Mode, Frequency 900 MHz (MSOP Only)

Rev. F | Page 8 of 22

Data Sheet

AD8361

GATE PULSE FOR

900MHz RF TONE

PWDN INPUT

500mV PER

VERTICAL

DIVISION

370mV

270mV

370mV

270mV

500mV PER

VERTICAL

DIVISION

RF INPUT

67mV

25mV

5µs PER HORIZONTAL DIVISION

2µs PER HORIZONTAL DIVISION

Figure 24. Output Response to Modulated Pulse Input for Various RF Input

Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor

Figure 27. Output Response Using Power-Down Mode for Various RF Input

Levels, Supply 3 V, Frequency 900 MHz, No Filter Capacitor

GATE PULSE FOR

900MHz RF TONE

PWDN INPUT

370mV

500mV PER

VERTICAL

DIVISION

370mV

270mV

500mV PER

VERTICAL

RF INPUT

DIVISION

67mV

25mV

50µs PER HORIZONTAL DIVISION

20µs PER HORIZONTAL DIVISION

Figure 25. Output Response to Modulated Pulse Input for Various RF Input

Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor

Figure 28. Output Response Using Power-Down Mode for Various RF Input

Levels, Supply 3 V, Frequency 900 MHz, 0.01 µF Filter Capacitor

HPE3631A

POWER SUPPLY

HPE3631A

POWER SUPPLY

TEK TDS784C

SCOPE

TEK TDS784C

SCOPE

C2

100pF

C4

0.01µF

C2

100pF

C4

0.01µF

AD8361

1

2

3

4

SREF

8

7

6

5

VPOS

1

2

3

4

SREF

8

7

6

5

VPOS

TEK P6204

FET PROBE

TEK P6204

FET PROBE

IREF

VRMS

FLTR

IREF

VRMS

FLTR

C1

0.1µF

C3

C1

0.1µF

C3

C5

100pF

RFIN

C5

100pF

RFIN

R1

75Ω

R1

75Ω

COMM

PWDN

COMM

PWDN

HP8648B

SIGNAL

GENERATOR

HP8648B

SIGNAL

GENERATOR

HP8110A

SIGNAL

GENERATOR

Figure 26. Hardware Configuration for

Output Response to Modulated Pulse Input

Figure 29. Hardware Configuration

for Output Response Using Power-Down Mode

Rev. F | Page 9 of 22

AD8361

Data Sheet

7.8

7.6

7.4

7.2

7.0

6.8

6.6

6.4

6.2

16

14

12

10

8

V

= 3V

S

6

4

6.0

5.8

2

0

6.9

5.6

100

7.0

7.2

7.4

7.6

7.8

1000

CARRIER FREQUENCY (MHz)

CONVERSION GAIN (V/V rms)

Figure 30. Conversion Gain Change vs. Frequency, Supply 3 V, Ground

Reference Mode, Frequency 100 MHz to 2500 MHz, Representative Device

Figure 33. Conversion Gain Distribution Frequency 100 MHz,

Supply 5 V, Sample Size 3000

RF

INPUT

SUPPLY

12

10

8

370mV

500mV PER

VERTICAL

DIVISION

270mV

6

67mV

25mV

4

2

20µs PER HORIZONTAL DIVISION

0

0.32

0.34

0.36

0.38

0.40

0.42

0.44

IREF MODE INTERCEPT (V)

Figure 31. Output Response to Gating on Power Supply, for Various RF Input

Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 µF Filter Capacitor

Figure 34. Output Reference, Internal Reference Mode, Supply 5 V,

Sample Size 3000 (MSOP Only)

12

HP8110A

PULSE

AD811

10

8

GENERATOR

50Ω

TEK TDS784C

SCOPE

732Ω

6

4

2

0

C2

100pF

C4

0.01µF

AD8361

1

2

3

4

SREF

8

7

6

5

VPOS

TEK P6204

FET PROBE

IREF

VRMS

FLTR

C1

0.1µF

C3

C5

100pF

RFIN

R1

75Ω

COMM

PWDN

0.64

0.66

0.68

0.70

0.72

0.74

0.76

HP8648B

SIGNAL

SREF MODE INTERCEPT (V)

GENERATOR

Figure 32. Hardware Configuration for Output Response to Power Supply

Gating Measurements

Figure 35. Output Reference, Supply Reference Mode, Supply 5 V,

Sample Size 3000 (MSOP Only)

Rev. F | Page 10 of 22

Data Sheet

AD8361

CIRCUIT DESCRIPTION

The AD8361 is an rms-responding (mean power) detector that

provides an approach to the exact measurement of RF power

that is basically independent of waveform. It achieves this

function through the use of a proprietary technique in which

the outputs of two identical squaring cells are balanced by the

action of a high-gain error amplifier.

The squaring cells have very wide bandwidth with an intrinsic

response from dc to microwave. However, the dynamic range of

such a system is fairly small, due in part to the much larger

dynamic range at the output of the squaring cells. There are

practical limitations to the accuracy of sensing very small error

signals at the bottom end of the dynamic range, arising from small

random offsets that limit the attainable accuracy at small inputs.

The signal to be measured is applied to the input of the first

squaring cell, which presents a nominal (LF) resistance of 225 Ω

between the RFIN and COMM pins (connected to the ground

plane). Because the input pin is at a bias voltage of about 0.8 V

above ground, a coupling capacitor is required. By making this

an external component, the measurement range may be

extended to arbitrarily low frequencies.

On the other hand, the squaring cells in the AD8361 have a

Class-AB aspect; the peak input is not limited by their quiescent

bias condition but is determined mainly by the eventual loss of

square-law conformance. Consequently, the top end of their

response range occurs at a fairly large input level (approximately

700 mV rms) while preserving a reasonably accurate square-law

response. The maximum usable range is, in practice, limited by

the output swing. The rail-to-rail output stage can swing from a

few millivolts above ground to less than 100 mV below the

supply. An example of the output induced limit: given a gain of

7.5 and assuming a maximum output of 2.9 V with a 3 V

supply, the maximum input is (2.9 V rms)/7.5 or 390 mV rms.

The AD8361 responds to the voltage, V_IN, at its input by

squaring this voltage to generate a current proportional to V_IN

squared. This is applied to an internal load resistor, across

which a capacitor is connected. These form a low-pass filter,

which extracts the mean of V_INsquared. Although essentially

voltage-responding, the associated input impedance calibrates

this port in terms of equivalent power. Therefore, 1 mW

corresponds to a voltage input of 447 mV rms. The Application

Information section shows how to match this input to 50 Ω.

Filtering

An important aspect of rms-dc conversion is the need for

averaging (the function is root-MEAN-square). For complex RF

waveforms, such as those that occur in CDMA, the filtering

provided by the on-chip, low-pass filter, although satisfactory

for CW signals above 100 MHz, is inadequate when the signal

has modulation components that extend down into the

kilohertz region. For this reason, the FLTR pin is provided: a

capacitor attached between this pin and VPOS can extend the

averaging time to very low frequencies.

The voltage across the low-pass filter, whose frequency may be

arbitrarily low, is applied to one input of an error-sensing amplifier.

A second identical voltage-squaring cell is used to close a negative

feedback loop around this error amplifier. This second cell is

driven by a fraction of the quasi-dc output voltage of the

AD8361. When the voltage at the input of the second squaring

cell is equal to the rms value of V_IN, the loop is in a stable state,

and the output then represents the rms value of the input. The

feedback ratio is nominally 0.133, making the rms-dc

conversion gain ×7.5, that is

Offset

An offset voltage can be added to the output (when using the

MSOP version) to allow the use of ADCs whose range does not

extend down to ground. However, accuracy at the low end

degrades because of the inherent error in this added voltage.

This requires that the IREF (internal reference) pin be tied to

VPOS and SREF (supply reference) to ground.

V_OUT 7.5V_INrms

By completing the feedback path through a second squaring

cell, identical to the one receiving the signal to be measured,

several benefits arise. First, scaling effects in these cells cancel;

thus, the overall calibration may be accurate, even though the

open-loop response of the squaring cells taken separately need

not be. Note that in implementing rms-dc conversion, no

reference voltage enters into the closed-loop scaling. Second,

the tracking in the responses of the dual cells remains very close

over temperature, leading to excellent stability of calibration.

In the IREF mode, the intercept is generated by an internal

reference cell and is a fixed 350 mV, independent of the supply

voltage. To enable this intercept, IREF should be open-circuited,

and SREF should be grounded.

In the SREF mode, the voltage is provided by the supply. To

implement this mode, tie IREF to VPOS and SREF to VPOS.

The offset is then proportional to the supply voltage and is

400 mV for a 3 V supply and 667 mV for a 5 V supply.

Rev. F | Page 11 of 22

AD8361

Data Sheet

APPLICATION INFORMATION

+V 2.7V – 5.5V

S

Basic Connections

Figure 36 through Figure 38 show the basic connections for the

AD8361’s MSOP version in its three operating modes. In all

modes, the device is powered by a single supply of between

2.7 V and 5.5 V. The VPOS pin is decoupled using 100 pF and

0.01 μF capacitors. The quiescent current of 1.1 mA in

operating mode can be reduced to 1 μA by pulling the PWDN

pin up to VPOS.

100pF

AD8361

0.01F

1

2

3

4

SREF

8

7

6

5

VPOS

C

IREF

VRMS

FLTR

C

V rms

100pF

RFIN

R1

75

CFLTR

COMM

PWDN

A 75 Ω external shunt resistance combines with the ac-coupled

input to give an overall broadband input impedance near 50 Ω.

Note that the coupling capacitor must be placed between the

input and the shunt impedance. Input impedance and input

coupling are discussed in more detail below.

Figure 38. Basic Connections for Supply Referenced Mode

The output voltage is nominally 7.5 times the input rms voltage

(a conversion gain of 7.5 V/V rms). Three modes of operation

are set by the SREF and IREF pins. In addition to the ground

reference mode shown in Figure 36, where the output voltage

swings from around near ground to 4.9 V on a 5.0 V supply, two

additional modes allow an offset voltage to be added to the

output. In the internal reference mode (Figure 37), the output

voltage swing is shifted upward by an internal reference voltage

of 350 mV. In supply referenced mode (Figure 38), an offset

voltage of V_S/7.5 is added to the output voltage. Table 4

The input coupling capacitor combines with the internal input

resistance (Figure 37) to provide a high-pass corner frequency

given by the equation

1

f_{3 dB}



2 π C_C R_IN

With the 100 pF capacitor shown in Figure 36 through Figure 38,

the high-pass corner frequency is about 8 MHz.

summarizes the connections, output transfer function, and

minimum output voltage (i.e., zero signal) for each mode.

+V 2.7V – 5.5V

S

Output Swing

100pF

Figure 39 shows the output swing of the AD8361 for a 5 V

supply voltage for each of the three modes. It is clear from

Figure 39 that operating the device in either internal reference

mode or supply referenced mode reduces the effective dynamic

range as the output headroom decreases. The response for lower

supply voltages is similar (in the supply referenced mode, the

offset is smaller), but the dynamic range reduces further as

headroom decreases. Figure 40 shows the response of the

AD8361 to a CW input for various supply voltages.

AD8361

0.01F

1

2

3

4

SREF

VRMS

FLTR

8

7

6

5

VPOS

C

IREF

C

V rms

100pF

RFIN

R1

75

CFLTR

COMM

PWDN

Figure 36. Basic Connections for Ground Reference Mode

+V 2.7V – 5.5V

S

5.0

SUPPLY REF

4.5

100pF

4.0

INTERNAL REF

3.5

AD8361

0.01F

1

2

3

4

SREF

8

7

6

5

VPOS

GROUND REF

3.0

C

IREF

VRMS

FLTR

C

V rms

2.5

2.0

100pF

RFIN

R1

75

CFLTR

COMM

PWDN

1.5

1.0

0.5

0.0

Figure 37. Basic Connections for Internal Reference Mode

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

INPUT (V rms)

Figure 39. Output Swing for Ground, Internal, and

Supply Referenced Mode, VPOS = 5 V (MSOP Only)

Rev. F | Page 12 of 22

Data Sheet

AD8361

5.5

should however be noted that offsets at the low end can be

5.5V

5.0

either positive or negative, so this plot could also trend upwards

at the low end. Figure 9, Figure 10, Figure 12, and Figure 13

show a 3 sigma distribution of the device error for a large

population of devices.

4.5

4.0

3.5

3.0

2.5

2.0

5.0V

3.0V

2.0

1.5

1.0

2.7V

1.5

1.0

2.5GHz

0.5

100MHz

0.5

0.0

1.9GHz

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

–0.5

INPUT (V rms)

100MHz

Figure 40. Output Swing for Supply Voltages of

2.7 V, 3.0 V, 5.0 V and 5.5 V (MSOP Only)

–1.0

–1.5

900MHz

Dynamic Range

–2.0

Because the AD8361 is a linear-responding device with a

nominal transfer function of 7.5 V/V rms, the dynamic range in

dB is not clear from plots such as Figure 39. As the input level is

increased in constant dB steps, the output step size (per dB) also

increases. Figure 41 shows the relationship between the output

step size (i.e., mV/dB) and input voltage for a nominal transfer

function of 7.5 V/V rms.

0.01

0.02

(–21dBm)

0.1

(–7dBm)

0.4

(+5dBm)

1.0

INPUT (V rms)

Figure 42. Representative Unit, Error in dB vs. Input Level, V_S= 2.7 V

It is also apparent in Figure 42 that the error plot tends to shift

to the right with increasing frequency. Because the input

impedance decreases with frequency, the voltage actually

applied to the input also tends to decrease (assuming a constant

source impedance over frequency). The dynamic range is

almost constant over frequency, but with a small decrease in

conversion gain at high frequency.

Table 4. Connections and Nominal Transfer Function for

Ground, Internal, and Supply Reference Modes

Output

Reference

Mode

Intercept

(No Signal) Output

Input Coupling and Matching

IREF

SREF

The input impedance of the AD8361 decreases with increasing

frequency in both its resistive and capacitive components

(Figure 17). The resistive component varies from 225 Ω at

100 MHz down to about 95 Ω at 2.5 GHz.

Ground

Internal

Supply

VPOS COMM Zero

OPEN COMM 0.350 V

7.5 V_IN

7.5 V_IN+ 0.350 V

7.5 V_IN+ V_S/7.5

VPOS VPOS

V_S/7.5

700

600

500

400

300

200

100

A number of options exist for input matching. For operation at

multiple frequencies, a 75 Ω shunt to ground, as shown in

Figure 43, provides the best overall match. For use at a single

frequency, a resistive or a reactive match can be used. By

plotting the input impedance on a Smith Chart, the best value

for a resistive match can be calculated. The VSWR can be held

below 1.5 at frequencies up to 1 GHz, even as the input

impedance varies from part to part. (Both input impedance and

input capacitance can vary by up to 20% around their nominal

values.) At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a

shunt resistor is not sufficient to reduce the VSWR below 1.5.

Where VSWR is critical, remove the shunt component and

insert an inductor in series with the coupling capacitor as

shown in Figure 44.

0

100

200

300

400

INPUT (mV)

500

600

700

800

Figure 41. Idealized Output Step Size as a Function of Input Voltage

Table 5 gives recommended shunt resistor values for various

frequencies and series inductor values for high frequencies. The

coupling capacitor, C_C, essentially acts as an ac-short and plays

no intentional part in the matching.

Plots of output voltage versus input voltage result in a straight

line. It may sometimes be more useful to plot the error on a

logarithmic scale, as shown in Figure 42. The deviation of the

plot for the ideal straight line characteristic is caused by output

clipping at the high end and by signal offsets at the low end. It

Rev. F | Page 13 of 22

AD8361

Data Sheet

Table 6. Recommended Values for a Reactive Input

Matching (Figure 45)

C

RFIN

Frequency (MHz)

C_M(pF)

16

2

L_M(nH)

180

15

R

SH

AD8361

100

800

Figure 43. Input Coupling/Matching Options, Broadband Resistor Match

900

2

12

1800

1900

2500

1.5

4.7

3.3

C

L

C

M

RFIN

AD8361

Figure 44. Input Coupling/Matching Options, Series Inductor Match

Input Coupling Using a Series Resistor

Figure 46 shows a technique for coupling the input signal into

the AD8361 that may be applicable where the input signal is

much larger than the input range of the AD8361. A series

resistor combines with the input impedance of the AD8361 to

attenuate the input signal. Because this series resistor forms a

divider with the frequency dependent input impedance, the

apparent gain changes greatly with frequency. However, this

method has the advantage of very little power being tapped off

in RF power transmission applications. If the resistor is large

compared to the transmission line’s impedance, then the VSWR

of the system is relatively unaffected.

C

M

RFIN

L

M

AD8361

Figure 45. Input Coupling/Matching Options, Narrowband Reactive Match

C

R

SERIES

RFIN

AD8361

1.7

1.4

1.1

0.8

250

200

150

100

Figure 46. Input Coupling/Matching Options, Attenuating the Input Signal

Table 5. Recommended Component Values for Resistive or

Inductive Input Matching (Figure 43 and Figure 44)

Frequency

Matching Component

100 MHz

63.4 Ω Shunt

800 MHz

75 Ω Shunt

900 MHz

75 Ω Shunt

1800 MHz

1900 MHz

2500 MHz

150 Ω Shunt or 4.7 nH Series

150 Ω Shunt or 2.7 nH Series

0.5

0.2

50

0

Alternatively, a reactive match can be implemented using a shunt

inductor to ground and a series capacitor, as shown in Figure 45. A

method for hand calculating the appropriate matching components

is shown on page 12 of the AD8306 data sheet.

0

500

1000

1500

2000

2500

3000

3500

FREQUENCY (MHz)

Figure 47. Input Impedance vs. Frequency, Supply 3 V, SOT-23

Selecting the Filter Capacitor

Matching in this manner results in very small values for C_M,

especially at high frequencies. As a result, a stray capacitance as

small as 1 pF can significantly degrade the quality of the match.

The main advantage of a reactive match is the increase in

sensitivity that results from the input voltage being gained up

(by the square root of the impedance ratio) by the matching

network. Table 6 shows the recommended values for reactive

matching.

The AD8361’s internal 27 pF filter capacitor is connected in

parallel with an internal resistance that varies with signal level

from 2 kΩ for small signals to 500 Ω for large signals. The

resulting low-pass corner frequency between 3 MHz and

12 MHz provides adequate filtering for all frequencies above

240 MHz (i.e., 10 times the frequency at the output of the

squarer, which is twice the input frequency). However, signals

with high peak-to-average ratios, such as CDMA or W-CDMA

signals, and low frequency components require additional

filtering. TDMA signals, such as GSM, PDC, or PHS, have a

peak-to average ratio that is close to that of a sinusoid, and the

internal filter is adequate.

Rev. F | Page 14 of 22

Data Sheet

AD8361

The filter capacitance of the AD8361 can be augmented by

connecting a capacitor between Pin 6 (FLTR) and VPOS. Table 7

shows the effect of several capacitor values for various

communications standards with high peak-to-average ratios

along with the residual ripple at the output, in peak-to-peak and

rms volts. Note that large filter capacitors increase the enable and

pulse response times, as discussed below.

The AD8361 can be disabled either by pulling the PWDN

(Pin 4) to VPOS or by simply turning off the power to the

device. While turning off the device obviously eliminates the

current consumption, disabling the device reduces the leakage

current to less than 1 μA. Figure 27 and Figure 28 show the

response of the output of the AD8361 to a pulse on the PWDN

pin, with no capacitance and with a filter capacitance of 0.01 μF,

respectively; the turn-on time is a function of the filter

capacitor. Figure 31 shows a plot of the output response to the

supply being turned on (i.e., PWDN is grounded and VPOS is

pulsed) with a filter capacitor of 0.01 μF. Again, the turn-on

time is strongly influenced by the size of the filter capacitor.

Table 7. Effect of Waveform and CFILT on Residual AC

Output

V dc

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

0.5

1.0

2.0

Residual AC

Waveform

C_FILT

mV p-p mV rms

IS95 Reverse Link

Open

550

1000

2000

40

100

180

360

6

If the input of the AD8361 is driven while the device is disabled

(PWDN = VPOS), the leakage current of less than 1 μA increases

as a function of input level. When the device is disabled, the

output impedance increases to approximately 16 kΩ.

0.01 μF

0.1 μF

160

430

20

60

3

Volts to dBm Conversion

40

6

In many of the plots, the horizontal axis is scaled in both rms

volts and dBm. In all cases, dBm are calculated relative to an

impedance of 50 Ω. To convert between dBm and volts in a

50 Ω system, the following equations can be used. Figure 48

shows this conversion in graphical form.

110

290

975

2600

50

18

40

150

430

7

IS95 8-Channel

Forward Link

0.01 μF

0.1 μF

2











V rms

50 ꢀ

0.001 W



190

670

225

940

2500

45

30

95

35

135

390

6

2

Power



dBm



10log



20



V rms



W-CDMA 15

Channel

0.01 μF

0.1 μF









dBm

10

log^1



dBm/10

20



_1







V rms  0.001W 50 ꢀ log





165

550

25

80



V rms

dBm

+20

Operation at Low Frequencies

1

+10

0

Although the AD8361 is specified for operation up to 2.5 GHz,

there is no lower limit on the operating frequency. It is only

necessary to increase the input coupling capacitor to reduce the

corner frequency of the input high-pass filter (use an input

resistance of 225 Ω for frequencies below 100 MHz). It is also

necessary to increase the filter capacitor so that the signal at

the output of the squaring circuit is free of ripple. The corner

frequency is set by the combination of the internal resistance

of 2 kΩ and the external filter capacitance.

0.1

–10

–20

–30

–40

0.01

0.001

Figure 48. Conversion from dBm to rms Volts

Power Consumption, Enable and Power-On

The quiescent current consumption of the AD8361 varies with

the size of the input signal from about 1 mA for no signal up to

7 mA at an input level of 0.66 V rms (9.4 dBm, re 50 Ω). If the

input is driven beyond this point, the supply current increases

steeply (see Figure 16). There is little variation in quiescent

current with power supply voltage.

Rev. F | Page 15 of 22

AD8361

Data Sheet

Output Drive Capability and Buffering

OUTPUT REFERENCE TEMPERATURE DRIFT

COMPENSATION

The AD8361 is capable of sourcing an output current of

approximately 3 mA. If additional current is required, a simple

buffering circuit can be used as shown in Figure 51. Similar

circuits can be used to increase or decrease the nominal conversion

gain of 7.5 V/V rms (Figure 49 and Figure 50). In Figure 50, the

AD8031 buffers a resistive divider to give a slope of 3.75 V/V

rms. In Figure 49, the op amp’s gain of two increases the slope

to 15 V/V rms. Using other resistor values, the slope can be

changed to an arbitrary value. The AD8031 rail-to-rail op amp,

used in these example, can swing from 50 mV to 4.95 V on a

single 5 V supply and operate at supply voltages down to 2.7 V.

If high output current is required (>10 mA), the AD8051, which

also has rail-to- rail capability, can be used down to a supply

voltage of 3 V. It can deliver up to 45 mA of output current.

5V

The error due to low temperature drift of the AD8361 can be

reduced if the temperature is known. Many systems incorporate

a temperature sensor; the output of the sensor is typically

digitized, facilitating a software correction. Using this information,

only a two-point calibration at ambient is required.

The output voltage of the AD8361 at ambient (25°C) can be

expressed by the equation

V_OUT

= GAIN ×V_IN+ ς_ΟΣ

( )

where GAIN is the conversion gain in V/V rms and V_OSis the

extrapolated output voltage for an input level of 0 V. GAIN and

V_OS(also referred to as intercept and output reference) can be

calculated at ambient using a simple two-point calibration by

measuring the output voltages for two specific input levels.

Calibration at roughly 35 mV rms (−16 dBm) and 250 mV rms

(+1 dBm) is recommended for maximum linear dynamic range.

However, alternative levels and ranges can be chosen to suit the

application. GAIN and V_OSare then calculated using the

equations

100pF

0.01µF

VPOS

VOUT

15V/V rms

AD8031

AD8361

COMM PWDN

(

V

_OUT2−V_OUT1

_IN2−V_IN1

)

5kΩ

GAIN =

5kΩ

V_OS=V_OUT1− GAIN ×V_IN1

( )

Figure 49. Output Buffering Options, Slope of 15 V/V rms

Both GAIN and V_OSdrift over temperature. However, the drift

of V_OShas a bigger influence on the error relative to the output.

This can be seen by inserting data from Figure 18 and Figure 21

5V

100pF

0.01µF

10kΩ

(intercept drift and conversion gain) into the equation for V_OUT

These plots are consistent with Figure 14 and Figure 15, which

show that the error due to temperature drift decreases with

.

VPOS

VOUT

0.01µF

5kΩ

AD8361

increasing input level. This results from the offset error having a

diminishing influence with increasing level on the overall

measurement error.

3.75V/V rms

AD8031

COMM PWDN

From Figure 18, the average intercept drift is 0.43 mV/°C from

−40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a

less rigorous compensation scheme, the average drift over the

complete temperature range can be calculated as

Figure 50. Output Buffering Options, Slope of 3.75 V/V rms

5V

100pF

0.01µF

0.010V −

( )

+ 85°C − − 40°C

(

−0.028V

)





0.01µF

VPOS

DRIFT_VOS

(

V/°C

)

= 



 = 0.000304 V/°C



VOUT





7.5V/V rms

AD8031

AD8361

With the drift of V_OSincluded, the equation for V_OUTbecomes

_OUT= (GAIN × V_IN) + V_OS+ DRIFT_VOS× (TEMP − 25°C)

V

COMM PWDN

Figure 51. Output Buffering Options, Slope of 7.5 V/V rms

Rev. F | Page 16 of 22

Data Sheet

AD8361

The equation can be rewritten to yield a temperature

Extended Frequency Characterization

compensated value for V_IN:

Although the AD8361 was originally intended as a power

measurement and control device for cellular wireless

applications, the AD8361 has useful performance at higher

frequencies. Typical applications may include MMDS, LMDS,

WLAN, and other noncellular activities.

(

V_OUT−V_OS− DRIFT_VOS

×

(

TEMP −25°C

)

V_IN

=

GAIN

Figure 52 shows the output voltage and error (in dB) as a

function of input level for a typical device (note that output

voltage is plotted on a logarithmic scale). Figure 53 shows the

error in the calculated input level after the temperature

compensation algorithm has been applied. For a supply voltage

of 5 V, the part exhibits a worst-case linearity error over

temperature of approximately 0.3 dB over a dynamic range of

35 dB.

In order to characterize the AD8361 at frequencies greater than

2.5 GHz, a small collection of devices were tested. Dynamic

range, conversion gain, and output intercept were measured at

several frequencies over a temperature range of −30°C to

+80°C. Both CW and 64 QAM modulated input wave forms

were used in the characterization process in order to access

varying peak-to-average waveform performance.

2.5

10

The dynamic range of the device is calculated as the input

power range over which the device remains within a

2.0

1.5

+85°C

permissible error margin to the ideal transfer function. Devices

were tested over frequency and temperature. After identifying

an acceptable error margin for a given application, the usable

dynamic measurement range can be identified using the plots in

Figure 54 through Figure 57. For instance, for a 1 dB error

margin and a modulated carrier at 3 GHz, the usable dynamic

range can be found by inspecting the 3 GHz plot of Figure 57.

Note that the −30°C curve crosses the −1 dB error limit at

−17 dBm. For a 5 V supply, the maximum input power should

not exceed 6 dBm in order to avoid compression. The resultant

usable dynamic range is therefore

1.0

0.5

+25°C

0

–0.5

–1.0

–1.5

1.0

–40°C

–2.0

–2.5

0.1

10

–25

–20

–15

–10

–5

0

5

PIN (dBm)

Figure 52. Typical Output Voltage and Error vs.

Input Level, 800 MHz, VPOS = 5 V

6 dBm − (−17 dBm)

or 23 dBm over a temperature range of −30°C to +80°C.

2.0

1.5

2.5

2.0

1.5

1.0

10

1.0

+25°C

+85°C

+80°C

0.5

+25°C

0

–30°C

0.5

0

–0.5

–1.0

–1.5

–40°C

1

–0.5

–1.0

–2.0

–2.5

–3.0

–1.5

–2.0

–2.5

–30

–25

–20

–15

–10

PIN (dBm)

–5

0

5

10

0.1

–25

–20

–15

–10

–5

0

5

10

Figure 53. Error after Temperature Compensation of

Output Reference,800 MHz, V_POS= 5 V

PIN (dBm)

Figure 54. Transfer Function and Error Plots Measured at

1.5 GHz for a 64 QAM Modulated Signal

Rev. F | Page 17 of 22

AD8361

Data Sheet

2.5

2.0

1.5

1.0

10

2.5

2.0

1.5

1.0

10

+80°C

+25°C

CW

–30°C

0.5

0

0.5

0

1

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–2.5

64 QAM

0.1

–2.5

–25

0.1

–20

–15

–10

–5

0

5

10

–25

–20

–15

–10

–5

0

5

10

PIN (dBm)

Figure 55. Transfer Function and Error Plots Measured at

2.5 GHz for a 64 QAM Modulated Signal

Figure 58. Error from CW Linear Reference vs. Input Drive Level for CW

and 64 QAM Modulated Signals at 3.0 GHz

2.5

2.0

1.5

1.0

10

8.0

7.5

7.0

6.5

+80°C

+25°C

–30°C

0.5

0

1

–0.5

–1.0

–1.5

–2.0

–2.5

6.0

5.5

0.1

5.0

–25

–20

–15

–10

–5

0

5

10

100 200 400 800 1200 1600 2200 2500 2700 3000

PIN (dBm)

FREQUENCY (MHz)

Figure 56. Transfer Function and Error Plots Measured at

2.7 GHz for a 64 QAM Modulated Signal

Figure 59. Conversion Gain vs. Frequency for a

Typical Device, Supply 3 V, Ground Reference Mode

2.5

2.0

1.5

1.0

10

The transfer functions and error for a CW input and a 64 QAM

input waveform is shown in Figure 58. The error curve is generated

from a linear reference based on the CW data. The increased

crest factor of the 64 QAM modulation results in a decrease in

output from the AD8361. This decrease in output is a result of

the limited bandwidth and compression of the internal gain stages.

This inaccuracy should be accounted for in systems where

varying crest factor signals need to be measured. The conversion

gain is defined as the slope of the output voltage vs. the input

rms voltage. An ideal best fit curve can be found for the measured

transfer function at a given supply voltage and temperature. The

slope of the ideal curve is identified as the conversion gain for a

particular device. The conversion gain relates the measurement

sensitivity of the AD8361 to the rms input voltage of the RF

waveform. The conversion gain was measured for a number of

devices over a temperature range of −30°C to +80°C. The

conversion gain for a typical device is shown in Figure 59.

Although the conversion gain tends to decrease with increasing

frequency, the AD8361 provides measurement capability at

frequencies greater than 2.5 GHz. However, it is necessary to

calibrate for a given application to accommodate for the change

in conversion gain at higher frequencies.

+80°C

+25°C

–30°C

0.5

0

1

–0.5

–1.0

–1.5

–2.0

–2.5

0.1

–25

–20

–15

–10

–5

0

5

10

PIN (dBm)

Figure 57. Transfer Function and Error Plots Measured at

3.0 GHz for a 64 QAM Modulated Signal

Rev. F | Page 18 of 22

Data Sheet

AD8361

EVALUATION BOARD

Figure 60 and Figure 63 show the schematic of the AD8361

evaluation board. Note that uninstalled components are drawn

in as dashed. The layout and silkscreen of the component side

are shown in Figure 61, Figure 62, Figure 64, and Figure 65. The

board is powered by a single supply in the 2.7 V to 5.5 V range.

The power supply is decoupled by 100 pF and 0.01 µF

capacitors. Additional decoupling, in the form of a series

resistor or inductor in R6, can also be added. Table 8 details the

various configuration options of the evaluation board.

Table 8. Evaluation Board Configuration Options

Component Function

Default Condition

Not Applicable

TP1, TP2

SW1

Ground and Supply Vector Pins.

Device Enable. When in Position A, the PWDN pin is connected to +V_Sand the AD8361 is in power- SW1 = B

down mode. In Position B, the PWDN pin is grounded, putting the device in operating mode.

SW2/SW3

C1, R2

Operating Mode. Selects either ground reference mode, internal reference mode or supply

reference mode. See Table 4 for more details.

Input Coupling. The 75 Ω resistor in Position R2 combines with the AD8361’s internal input

impedance to give a broadband input impedance of around 50 Ω. For more precise matching C1 = 100 pF (Size 0402)

at a particular frequency, R2 can be replaced by a different value (see Input Coupling and

Matching and Figure 43 through Figure 46).

SW2 = A, SW3 = B

(Ground Reference Mode)

R2 = 75 Ω (Size 0402)

Capacitor C1 ac couples the input signal and creates a high-pass input filter whose corner

frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower

frequencies. If resistive attenuation is desired at the input, series resistor R1, which is

nominally 0 Ω, can be replaced by an appropriate value.

C2, C3, R6

Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and 100 pF. A series

inductor or small resistor can be placed in R6 for additional decoupling.

C2 = 0.01 µF (Size 0402)

C3 = 100 pF (Size 0402)

R6 = 0 Ω (Size 0402)

C5

Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a

capacitance in C5.

C5 = 1 nF (Size 0603)

C4, R5

Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms.

C4 = R5 = Open (Size 0603)

Rev. F | Page 19 of 22

AD8361

Data Sheet

VPOS

C3

100pF

C2

0.01µF

TP2

R6

R4

0Ω

C2

0.01µF

AD8361

C3

100pF

V

S

J2

0Ω

VPOS

1

2

3

VRMS

6

5

4

VPOS

TP2

SW3

V

S

A

B

J1

C4

(OPEN)

R5

(OPEN)

AD8361

COMM RFIN

SW2

1

2

3

4

SREF

VRMS

FLTR

8

7

6

5

VPOS

A

B

R4

0Ω

C1

100pF

R2

75Ω

C1

100pF

IREF

V

PWDN

J3

rms

FLTR

C4

(OPEN)

R5

(OPEN)

C5

1nF

RFIN

VPOS

TP1

RFIN

3

2

1

R2

1nF

TP1

75Ω

COMM

PWDN

SW1

VPOS

R7

50Ω

A

B

SW1

Figure 63. Evaluation Board Schematic, SOT-23

Figure 60. Evaluation Board Schematic, MSOP

Figure 61. Layout of Component Side, MSOP

Figure 64. Layout of the Component Side, SOT-23

Figure 62. Silkscreen of Component Side, MSOP

Figure 65. Silkscreen of the Component Side, SOT-23

Rev. F | Page 20 of 22

Data Sheet

AD8361

Problems caused by impedance mismatch may arise using the

evaluation board to examine the AD8361 performance. One

way to reduce these problems is to put a coaxial 3 dB attenuator

on the RFIN SMA connector. Mismatches at the source, cable,

and cable interconnection, as well as those occurring on the

evaluation board, can cause these problems.

Analysis

The conversion gain and output reference are derived using the

coefficients of a linear regression performed on data collected

in its central operating range (35 mV rms to 250 mV rms). This

range was chosen to avoid areas of operation where offset

distorts the linear response. Error is stated in two forms error

from linear response to CW waveform and output delta from

2°C performance.

A simple (and common) example of such a problem is triple

travel due to mismatch at both the source and the evaluation

board. Here the signal from the source reaches the evaluation

board and mismatch causes a reflection. When that reflection

reaches the source mismatch, it causes a new reflection, which

travels back to the evaluation board, adding to the original

signal incident at the board. The resultant voltage varies with

both cable length and frequency dependence on the relative

phase of the initial and reflected signals. Placing the 3 dB pad at

the input of the board improves the match at the board and thus

reduces the sensitivity to mismatches at the source. When such

precautions are taken, measurements are less sensitive to cable

length and other fixture issues. In an actual application when

the distance between AD8361 and source is short and well

defined, this 3 dB attenuator is not needed.

The error from linear response to CW waveform is the

difference in output from the ideal output defined by the

conversion gain and output reference. This is a measure of both

the linearity of the device response to both CW and modulated

waveforms. The error in dB uses the conversion gain multiplied

by the input as its reference. Error from linear response to CW

waveform is not a measure of absolute accuracy, since it is

calculated using the gain and output reference of each device.

However, it does show the linearity and effect of modulation on

the device response. Error from 25°C performance uses the

performance of a given device and waveform type as the

reference; it is predominantly a measure of output variation

with temperature.

C4

C2

CHARACTERIZATION SETUPS

0.1F 100pF

Equipment

AD8361

1

2

3

4

SREF

8

7

6

5

SREF

VRMS

VPOS

IREF

RFIN

The primary characterization setup is shown in Figure 67. The

signal source used was a Rohde & Schwarz SMIQ03B, version

3.90HX. The modulated waveforms used for IS95 reverse link,

IS95 nine active channels forward (forward link 18 setting),

and W-CDMA 4-channel and 15-channel were generated using

the default settings coding and filtering. Signal levels were

calibrated into a 50 Ω impedance.

IREF

VRMS

FLTR

C3

RFIN

R1

C1

75

COMM

0.1F

PWDN

Figure 66. Characterization Board

AD8361

CHARACTERIZATION

BOARD

DC OUTPUT

RF SIGNAL

SMIQ038B

RFIN

VRMS

RF SOURCE

3dB

ATTENUATOR

PRUP +V

SREF IREF

S

DC SOURCES

IEEE BUS

DC MATRIX / DC SUPPLIES / DMM

PC CONTROLLER

Figure 67. Characterization Setup

Rev. F | Page 21 of 22

AD8361

Data Sheet

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

1

5

4

5.15

4.90

4.65

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.65 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.80

0.55

0.40

0.15

0.05

0.23

0.09

6°

0°

0.40

0.25

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 68. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00

2.90

2.80

6

1

5

2

4

3

3.00

2.80

2.60

1.70

1.60

1.50

PIN 1

INDICATOR

0.95 BSC

1.90

BSC

1.30

1.15

0.90

0.20 MAX

0.08 MIN

1.45 MAX

0.95 MIN

0.55

0.45

0.35

0.15 MAX

0.05 MIN

10°

4°

0°

SEATING

PLANE

0.60

BSC

0.50 MAX

0.30 MIN

COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 69. 6-Lead Small Outline Transistor Package [SOT-23]

(RJ-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

Branding

J3A

AD8361ARM

8-Lead MSOP, Tube

RM-8

RJ-6

AD8361ARM-REEL7

AD8361ARMZ

8-Lead MSOP, 7" Tape and Reel

8-Lead MSOP, Tube

J3A

AD8361ARMZ-REEL

AD8361ARMZ-REEL7

AD8361ARTZ-RL7

AD8361-EVALZ

8-Lead MSOP, 13" Tape and Reel

8-Lead MSOP, 7" Tape and Reel

6-Lead SOT-23, 7" Tape and Reel

Evaluation Board MSOP

J3A

AD8361ART-EVAL

Evaluation Board SOT-23-6L

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D01088–0–7/15(F)

Rev. F | Page 22 of 22


型号：	AD8361_15
厂家：	ADI
描述：	LF to 2.5 GHz TruPwr Detector
文件：	总22页 (文件大小：502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8361_15 [ADI]

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