AD8362ARUZ-REEL71 [ADI]
50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector; 50 Hz至2.7 GHz的60分贝TruPwr⑩探测器
| 型号： | AD8362ARUZ-REEL71 |
| 厂家： | 
ADI |
| 描述： | 50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector |
| 文件： | 总36页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 Hz to 2.7 GHz
60 dB TruPwr™ Detector
AD8362
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DECL
CHPF
Complete fully calibrated measurement/control system
Accurate rms-to-dc conversion from 50 Hz to 2.7 GHz
Input dynamic range of >60 dB: −52 dBm to +8 dBm in 50 Ω
Waveform and modulation independent:
(Such as GSM/CDMA/TDMA)
INHI
2
x
CLPF
VOUT
ACOM
INLO
Linear-in-decibels output, scaled 50 mV/dB
Law conformance error of 0.5 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V at 24 mA from −40°C to +85°C
Power-down capability to 1.3 mW
2
V
TGT
x
VSET
VPOS
AD8362
APPLICATIONS
Power amplifier linearization/control loops
BIAS
VREF
Transmitter power control
Transmitter signal strength indication (TSSI)
RF instrumentation
COMM
PWDN
Figure 1.
GENERAL DESCRIPTION
The AD8362 is a true rms-responding power detector that has a
60 dB measurement range. It is intended for use in a variety of
high frequency communication systems and in instrumentation
requiring an accurate response to signal power. It is easy to use,
requiring only a single supply of 5 V and a few capacitors. It can
operate from arbitrarily low frequencies to over 2.7 GHz and
can accept inputs that have rms values from 1 mV to at least
1 V rms, with peak crest factors of up to 6, exceeding the
requirements for accurate measurement of CDMA signals.
the input power. Optionally, the voltage at VSET may be a
replica of the RF signal’s amplitude modulation, in which case
the overall effect is to remove the modulation component prior
to detection and low-pass filtering. The corner frequency of the
averaging filter may be lowered without limit by adding an
external capacitor at the CLPF pin. The AD8362 can be used to
determine the true power of a high frequency signal having a
complex low frequency modulation envelope (or simply as a
low frequency rms voltmeter). The high-pass corner generated
by its offset-nulling loop can be lowered by a capacitor added
on the CHPF pin.
The input signal is applied to a resistive ladder attenuator
that comprises the input stage of a variable gain amplifier.
The 12 tap points are smoothly interpolated using a proprietary
technique to provide a continuously variable attenuator, which
is controlled by a voltage applied to the VSET pin. The resulting
signal is applied to a high performance broadband amplifier. Its
output is measured by an accurate square-law detector cell. The
fluctuating output is then filtered and compared with the output
of an identical squarer, whose input is a fixed dc voltage applied
to the VTGT pin, usually the accurate reference of 1.25 V
provided at the VREF pin.
Used as a power measurement device, VOUT is strapped to
VSET, and the output is then proportional to the logarithm of
the rms value of the input; that is, the reading is presented
directly in decibels and is conveniently scaled 1 V per decade,
that is, 50 mV/dB; other slopes are easily arranged. In controller
modes, the voltage applied to VSET determines the power level
required at the input to null the deviation from the setpoint.
The output buffer can provide high load currents.
The AD8362 is powered down by a logic high applied to the
PWDN pin, i.e., the consumption is reduced to about 1.3 mW. It
powers up within about 20 µs to its nominal operating current
of 20 mA at 25°C. The AD8362 is supplied in a 16-lead TSSOP
package for operation over the industrial temperature range of
−40°C to +85°C. An evaluation board is available.
The difference in the outputs of these squaring cells is
integrated in a high gain error amplifier, generating a voltage at
the VOUT pin with rail-to-rail capabilities. In a controller
mode, this low noise output can be used to vary the gain of a
host system’s RF amplifier, thus balancing the set point against
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8362
TABLE OF CONTENTS
Specifications ................................................................................... 3
Uncertainties in RIN and Power Calibration............................ 24
Choosing the Right Value for CHPF and CLPF..................... 24
Use of Nonstandard Target Voltages........................................ 24
Adjusting the Intercept.............................................................. 25
Altering the Slope....................................................................... 25
Envelope Elimination Mode ..................................................... 26
Operator in Controller Modes .................................................... 27
Use of an Input Balun ................................................................ 27
General Applications .................................................................... 29
RMS Voltmeter with >100 dB Dynamic Range...................... 29
RF Power Meter with 80 dB Range.......................................... 30
High Slope Detectors Centered on a Narrow Window......... 31
AD8362 Evaluation Board ........................................................ 32
Outline Dimensions...................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
Absolute Maximum Ratings .......................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description............................. 7
Equivalent Circuits.......................................................................... 8
Typical Performance Characteristics............................................ 9
Characterization Setup .................................................................14
Equipment ................................................................................... 14
Analysis........................................................................................ 14
Circuit Description........................................................................15
Square-Law Detection ............................................................... 15
Effect of Input Coupling on the Intercept Value.................... 16
Offset Elimination...................................................................... 16
Voltage vs. Power Calibration ................................................... 17
Effect of Signal Waveform......................................................... 17
Operation at Low Frequencies.................................................. 17
Time-Domain Response of the Closed Loop ......................... 17
Alteration of the Internal Target Voltage................................. 18
Effects at Each End of Dynamic Range................................... 18
Input Protection.......................................................................... 19
Power-Enable Response Time .................................................. 19
Using the AD8362.........................................................................20
Basic Connections...................................................................... 20
Main Modes of Operation............................................................21
Operation in Measurement Modes.............................................22
Law Conformance Error............................................................ 22
Alternative Input Coupling Means .......................................... 23
Using a Narrow-Band Input Match ......................................... 23
3/04—Data Sheet Changed from Rev. A to Rev. B.
Updated Format.................................................................Universal
Changes to Specifications............................................................... 3
Changes to the Offset Elimination Section................................ 16
Changes to the Operation at Low Frequencies Section............ 17
Changes to the Time-Domain Response of the Closed Loop
Section............................................................................................. 17
Changes to Equation 13................................................................ 24
Changes to Table 5......................................................................... 31
6/03—Data Sheet Changed from Rev. 0 to Rev. A.
Updated Ordering Guide................................................................ 5
Change to Analysis Section.......................................................... 12
Updated AD8362 Evaluation Board Section ............................. 26
2/03—Revision 0: Initial Version
Rev. B | Page 2 of 36
AD8362
SPECIFICATIONS
VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via Balun1, VTGT connected to VREF, VOUT tied to VSET, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Maximum Input Frequency
Input Power Range (Differential)
2.7
GHz
dB Referred to 50 Ω Impedance Level,
f ≤ 2.7 GHz, into 1:4 Balun1
Nominal Low End of Range
Nominal High End of Range
Input Voltage Range (Differential)
−52
+8
dBm
dBm
RMS Voltage at Input Terminals,
f ≤ 2.7 GHz, into Input of the Device
Nominal Low End of Range
Nominal High End of Range
Input Power Range (S-Sided)
1.12
1.12
mV rms
V rms
Single-Ended Drive, CW Input, f ≤ 2.7 GHz,
into Input Resistive Network2
Nominal Low End of Range
Nominal High End of Range
Input Voltage Range (S-Sided)
Nominal Low End of Range
Nominal High End of Range
Output Voltage Range
Nominal Low End of Range
Nominal High End of Range
Output Scaling (Log Slope)
Law Conformance Error
RF INPUT INTERFACE
−40
0
dBm
dBm
RMS Voltage at Input Terminals, f ≤ 2.7 GHz
2.23
223
mV rms
V rms
RL ≥ 200 Ω to Ground
In General, VS – 0.1 V
+100
+4.9
50
mV
V
mV/dB
dB
Over Central 60 dB Range, f ≤ 2.7 GHz
Pins INHI, INLO, AC-Coupled
Single-Ended Drive, wrt DECL
Differential Drive
0.5
Input Resistance
100
200
Ω
Ω
OUTPUT INTERFACE
Available Output Range
Absolute Voltage Range
Nominal Low End of Range
Nominal High End of Range
Source/Sink Current
Slew Rate Rising
Pin VOUT
RL ≥ 200 Ω to Ground
0.1
4.9
V
Measurement Mode, f = 900 MHz, PIN = −52 dBm
Measurement Mode, f = 900 MHz, PIN = +8 dBm
VOUT Held at VS/2, to 1% Change
CL = Open
CL = Open
0.2 V to 1.8 V, CLPF = 0
1.8 V to 0.2 V, CLPF = 0
CLPF = 1000 pF, fSPOT ≤ 100 kHz
Pin VSET
0.32
3.44
0.48
3.52
V
V
mA
V/µs
V/µs
ns
48
60
5
45
0.4
70
Slew Rate Falling
Rise Time, 10% to 90%
Fall Time, 90% to 10%
Wideband Noise
µs
nV/√Hz
VSET INTERFACE
Nominal Input Voltage Range
Input Resistance
To 1 dB Error
0.5
3.75
V
kΩ
68
Scaling (Log Slope)
Scaling (Log Intercept)
f = 900 MHz
f = 900 MHz, into 1:4 Balun
46
−64
−77
50
−60
−73
54
−56
−69
mV/dB
dBm
dBV
VOLTAGE REFERENCE
Output Voltage
Pin VREF
25°C
−40°C ≤ TA ≤ +85°C
1.225
1.25
0.08
8
1.275
V
Temperature Sensitivity3
mV/°C
Ω
Output Resistance
Rev. B | Page 3 of 36
AD8362
Parameter
Conditions
Min
Typ
Max
Unit
RMS TARGET INTERFACE
Nominal Input Voltage Range
Input Bias Current
Pin VTGT
Measurement Range = 60 dB, to 1 dB Error
VTGT = 1.25 V
VTGT = 0 V
0.625
2.5
V
−28
−52
52
µA
µA
kΩ
Incremental Input Resistance
POWER-DOWN INTERFACE
Logic Level to Enable
Logic Level to Disable
Input Current
Pin PWDN
Logic Low Enables
Logic High Disables
Logic High
Logic Low
From PWDN Low to VOUT within
10% of Final Value, CLPF = 1000 pF
1
V
V
µA
µA
ns
3
230
5
14.5
Enable Time
Disable Time
From PWDN High to VOUT within
10% of Final Value, CLPF = 1000 pF
2.5
µs
POWER SUPPLY INTERFACE
Supply Voltage
Quiescent Current
Supply Current
Pin VPOS
4.5
5
20
0.2
5.5
22
V
mA
mA
When Disabled
900 MHz
Dynamic Range
Error Referred to Best Fit Line (Linear Regression)
1 dB Linearity, CW Input
65
62
dB
dB
0.5 dB Linearity, CW Input
Deviation vs. Temperature
Deviation from Output at 25°C
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +85°C; PIN = −20 dBm
−40°C < TA < +85°C; PIN = +5 dBm
−1.7
−1.4
−1
dB
dB
dB
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
46
−64
50
−60
0.2
0.2
0.5
54
−56
mV/dB
dBm
dB
dB
dB
5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link)
12 dB Peak-to-RMS Ratio (WCDMA 4 Channels)
18 dB Peak-to-RMS Ratio (WCDMA 15 Channels)
1.9 GHz
Dynamic Range
Error Referred to Best Fit Line (Linear Regression)
1 dB Linearity, CW Input
65
62
dB
dB
0.5 dB Linearity, CW Input
Deviation vs. Temperature
Deviation from Output at 25°C
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +85°C; PIN = −20 dBm
−40°C < TA < +85°C; PIN= +5 dBm
−0.6
−0.5
−0.3
51
−59
0.2
dB
dB
dB
mV/dB
dBm
dB
dB
dB
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link)
12 dB Peak-to-RMS Ratio (WCDMA 4 Channels)
18 dB Peak-to-RMS Ratio (WCDMA 15 Channels)
0.2
0.5
Rev. B | Page 4 of 36
AD8362
Parameter
2.2 GHz
Conditions
Min
Typ
Max
Unit
Dynamic Range
Error Referred to Best Fit Line (Linear Regression)
±± dB Linearityꢀ ꢁC ꢂnꢃpt
65
65
dB
dB
±ꢄ.5 dB Linearityꢀ ꢁC ꢂnꢃpt
Deviation vs. Temꢃeratpre
Deviation from Optꢃpt at 25°ꢁ
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN = −45 dBm
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN = −2ꢄ dBm
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN= +5 dBm
−±.8
−±.6
−±.3
5ꢄ.5
−6±
ꢄ.2
dB
dB
dB
mV/dB
dBm
dB
dB
dB
Logarithmic Sloꢃe
Logarithmic ꢂnterceꢃt
Deviation from ꢁC Resꢃonse
5.5 dB Peak-to-RMS Ratio (ꢂS95 Reverse Link)
±2 dB Peak-to-RMS Ratio (CꢁDMA 4 ꢁhannels)
±8 dB Peak-to-RMS Ratio (CꢁDMA ±5 ꢁhannels)
ꢄ.2
ꢄ.5
2.7 GHz
Dynamic Range
Error Referred to Best Fit Line (Linear Regression)
±± dB Linearityꢀ ꢁC ꢂnꢃpt
63
62
dB
dB
±ꢄ.5 dB Linearityꢀ ꢁC ꢂnꢃpt
Deviation vs. Temꢃeratpre
Deviation from Optꢃpt at 25°ꢁ
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN = −4ꢄ dBm
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN = −±5 dBm
−4ꢄ°ꢁ < TA < +85°ꢁ; PꢂN = +±5 dBm
−5.3
−5.5
−4.8
5ꢄ.5
−58
ꢄ.2
dB
dB
dB
mV/dB
dBm
dB
dB
dB
Logarithmic Sloꢃe
Logarithmic ꢂnterceꢃt
Deviation from ꢁC Resꢃonse
5.5 dB Peak-to-RMS Ratio (ꢂS95 Reverse Link)
±2 dB Peak-to-RMS Ratio (CꢁDMA 4 ꢁhannels)
±8 dB Peak-to-RMS Ratio (CꢁDMA ±5 ꢁhannels)
ꢄ.2
ꢄ.4
± ±:4 balpn transformerꢀ M/A-ꢁOM ETꢁ ±.6-4-2-3.
2 Resistive network consists of 33 Ω shpnt and 25 Ω series.
3 See Figpre 36.
Rev. B | Page 5 of 36
AD8362
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters
Ratings
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage VPOS
Input Power (into Input of Device)
Equivalent Voltage
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
5.5 V
13 dBm
2 V rms
500 mW
125°C/W
125°C/W
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 36
AD8362
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM
CHPF
DECL
INHI
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
AD8362
TOP VIEW
INLO
(Not to Scale)
DECL
PWDN
COMM
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin
Equivalent
Circuit
No.
1, 8
2
Mnemonic Description
COMM
CHPF
DECL
Common Connection. Connect via low impedance to system common.
Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.
3, 6
4
5
7
9
INHI
High Signal Input Terminal. Part of a differential input port with INLO.
Low Signal Input Terminal. Part of a differential input port with INHI.
Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
Connection for loop filter integration (averaging) capacitor, the other pin of which is usually
grounded via a resistor to improve loop stability and response time.
Circuit A
Circuit A
INLO
PWDN
CLPF
10, 16 ACOM
Analog Common Connection for Output Amplifier.
11
VSET
The voltage applied to this pin sets the decibel value of the required RF input voltage that results in
zero current out of CLPF and thus the loop integrating capacitor.
Output of Error Amplifier. In measurement mode, normally connected directly to VSET.
Connect to 5 V Power Supply.
The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower
target voltage increases the crest factor capacity.
General-Purpose Reference Voltage Output of 1.25 V (usually connected only to VTGT).
Circuit B
Circuit C
12
13
14
VOUT
VPOS
VTGT
Circuit D
Circuit E
15
VREF
Rev. B | Page 7 of 36
AD8362
EQUIVALENT CIRCUITS
VPOS
VSET
VPOS
VPOS
DECL
RAIL-TO-RAIL
OUTPUT
~35kΩ
~35kΩ
0.7V
COMM
VOUT
ACOM
VSET
INTERFACE
2kΩ
INHI
CLPF
500Ω
100Ω
ACOM
COMM
COMM
VGA
100Ω
Figure 6. Circuit D
Figure 4. Circuit B
INLO
VPOS
SOURCE ONLY
REF BUF
VPOS
VPOS
COMM
DECL
~0.35V
50kΩ
50kΩ
VOUT
ACOM
VTGT
VTGT
INTERFACE
GAIN = 0.12
Figure 3. Circuit A
13kΩ
5kΩ
ACOM
COMM
COMM
Figure 7. Circuit E
Figure 5. Circuit C
Rev. B | Page 8 of 36
AD8362
TYPICAL PERFORMANCE CHARACTERISTICS
4.5
4.0
3.6
3.0
2.4
100MHz
4.0
3.2
2.8
1.8
1.2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2200MHz
–40°C
0.6
0
2.4
2.0
1.6
–0.6
–1.2
+85°C
2700MHz
+25°C
–40°C
1.2
0.8
0.4
+25°C
+85°C
–1.8
–2.4
–3.0
900MHz
1900MHz
0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm),
Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,
Sine Wave, Differential Drive
Figure 11. VOUT and Law Conformance vs. Input Amplitude, Frequency
1900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C
3.0
2.5
2.0
1.5
4.0
3.6
3.0
2.4
3.2
2.8
1.8
1.2
–40°C
1.0
0.5
100MHz
0.6
0
2.4
2.0
1.6
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
+25°C
+25°C
–0.6
–1.2
2200MHz
900MHz
1900MHz
1.2
0.8
0.4
+85°C
–40°C
–1.8
–2.4
–3.0
+85°C
2700MHz
0
–60
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
–10
–50 –45 –40 –35 –30 –25 –20 –15
–5
0
5
10 15
–55
INPUT AMPLITUDE (dBm)
Figure 9. Logarithmic Law Conformance vs. Input Amplitude
Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,
Sine Wave, Differential Drive
Figure 12. VOUT and Law Conformance vs. Input Amplitude, Frequency
2200 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C
4.0
3.0
2.4
4.0
3.5
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
1.8
1.2
CW
3.0
–40°C
2.5
0.6
IS95 REVERSE LINK
+25°C
WCDMA 8-CHANNEL
2.0
0
+85°C
–40°C
–0.6
WCDMA 15-CHANNEL
1.5
1.0
0.5
0
–1.2
–1.8
–2.4
+85°C
+25°C
–3.0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
–10
–5
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15
INPUT AMPLITUDE (dBm)
0
5
10 15
Figure 10. VOUT and Law Conformance vs. Input Amplitude, Frequency
900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C
Figure 13. VOUT vs. Input Amplitude with Different Waveforms, CW, IS95
Reverse Link, WCDMA 8-Channel, WCDM 15-Channel, Frequency 900 MHz
Rev. B | Page 9 of 36
AD8362
3.0
2.5
3.0
2.5
WCDMA
8-CHANNEL
2.0
2.0
1.5
1.5
WCDMA 8-CHANNEL
1.0
1.0
IS95 REVERSE LINK
0.5
0.5
CW
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
WCDMA 15-CHANNEL
WCDMA
15-CHANNEL
–3.0
–60
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
–55 –50 –45 –40 –35 –30 –25 –20 –15
–5
0
5
10 15
–10
INPUT AMPLITUDE (dBm)
Figure 14. Output Error from CW Linear Reference vs. Input Amplitude
with Different Waveforms, CW, IS95 Reverse Link, WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 900 MHz
Figure 17. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
15-Channel, Frequency 1900 MHz
3.0
2.5
3.0
2.5
2.0
1.5
2.0
WCDMA
8-CHANNEL
1.5
WCDMA
WCDMA
1.0
0.5
1.0
0.5
4-CHANNEL
8-CHANNEL
0
0
–0.5
–1.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
WCDMA 15-CHANNEL
–1.5
WCDMA
15-CHANNEL
–2.0
–2.5
–3.0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10
Figure 15. Output Error from CW Linear Reference vs. Input Amplitude
with Different WCDMA Channel Loading, 4-Channel, 8-Channel,
15-Channel, Frequency 2200 MHz
Figure 18. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 2200 MHz
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
WCDMA 8-CHANNEL
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
WCDMA 15-CHANNEL
–2.0
–2.5
–3.0
–60
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
Figure 16. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 1900 MHz
Figure 19. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,
Sine Wave, Frequency 900 MHz, Part-to-Part Variation
Rev. B | Page 10 of 36
AD8362
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
–40°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
+85°C
+25°C
10
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10
Figure 20. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,
Sine Wave, Frequency 1900 MHz, Part-to-Part Variation
Figure 23. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 2200 MHz,
Temperature −40°C, +25°C, and +85°C
3.0
52.0
–40°C
2.5
2.0
1.5
51.5
51.0
50.5
50.0
49.5
49.0
+85°C
+25°C
–40°C
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
+85°C
+25°C
–2.5
–3.0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10
FREQUENCY (MHz)
Figure 21. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz,
Temperature −40°C, +25°C, and +85°C
Figure 24. Logarithmic Slope vs. Frequency,
Temperature −40°C, +25°C, and +85°C
3.0
–53
–54
–55
–56
–57
–58
–59
–60
–61
–62
–63
–45°C
2.5
2.0
+85°C
1.5
1.0
0.5
0
+25°C
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–40°C
+25°C
+85°C
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10
FREQUENCY (MHz)
Figure 25. Logarithmic Intercept vs. Frequency,
Temperature −40°C, +25°C, and +85°C
Figure 22. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz,
Temperature −40°C, +25°C, and +85°C
Rev. B | Page 11 of 36
AD8362
3.0
2.5
80
70
60
50
40
30
20
900MHz
2.0
1.5
1900MHz
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
10
0
2200MHz
–61.0
–60.5
–60.0
–59.5
–59.0
–58.5
–58.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
INTERCEPT (dBm)
Figure 26. Change in Logarithmic Slope vs. Temperature, 3 Sigma to Either
Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz
Figure 29. Logarithmic Intercept Distribution, Frequency 900 MHz
2.0
1.5
1.0
5.0
6
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RF BURST
ENABLE
4
2V/DIV
2
0
900MHz
1900MHz
+2dBm
0.5
0
–2
–4
–6
–8
–10
–12
–14
VOUT
–10dBm
–20dBm
–0.5
–1.0
–1.5
–2.0
–30dBm
0.5V/DIV
2200MHz
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
2
4
6
8
10
TIME (
12
14
16
18
20
µ
s)
Figure 30. Output Response to RF Burst Input for Various
RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0.1 µF
Figure 27. Change in Logarithmic Intercept vs. Temperature, 3 Sigma to
Either Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
100
80
60
40
20
0
4
RF BURST
2V/DIV
ENABLE
2
0
+2dBm
–10dBm
–2
–4
VOUT
–20dBm
–6
–30dBm
–8
–10
0.5V/DIV
–12
–14
48
49
50
51
52
53
0
2
4
6
8
10
12
14
16
18
20
SLOPE (mV/dB)
TIME (ms)
Figure 31. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency 900 MHz, CLPF = 0.1 µF
Figure 28. Slope Distribution, Frequency 900 MHz
Rev. B | Page 12 of 36
AD8362
90
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
4
60
120
POWER-
DOWN
PIN
2V/DIV
2
0
150
30
+2dBm
VOUT
–2
–4
–6
–8
–10
–12
–14
–10dBm
–20dBm
180
0
0.5V/DIV
–30dBm
210
330
240
300
0
2
4
6
8
10
TIME (µs)
12
14
16
18
20
270
Figure 32. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
Figure 35. Input Impedance, ZO = 50 Ω, Differential Drive
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
5
0
4
2V/DIV
2
0
–5
+2dBm
–2
–4
–6
–8
–10
–12
–14
–10
–15
–20
–25
–30
–10dBm
–20dBm
–30dBm
0.5V/DIV
0
2
4
6
8
10
12
14
16
18
20
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TIME (ms)
TEMPERATURE (°C)
Figure 33. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0.1 µF
Figure 36. Change in VREF vs. Temperature, 3 Sigma to Either Side of Mean
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
6
300
250
200
150
100
50
4
2V/DIV
VPOS
2
0
–2
–4
–6
–8
–10
–12
–14
+2dBm
1V/DIV
–10dBm
–20dBm
–30dBm
0
1.230
1.235 1.240
1.245 1.250
VREF (V)
1.255 1.260
1.265 1.270
0
2
4
6
8
10
TIME (ms)
12
14
16
18
20
Figure 37. VREF Distribution
Figure 34. Output Response to Gating on Power Supply for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
Rev. B | Page 13 of 36
AD8362
CHARACTERIZATION SETUP
EQUIPMENT
TEK TDS5104
SCOPE
AD8362
The general hardware configuration used for most of the
AD8362 characterization is shown in Figure 38. The signal
source used was a Rohde & Schwarz SMIQ03B. A 1:4 balun
transformer was used to transform the single-ended RF signal
to differential form. For the response measurements in Figure
30 and Figure 31, the configuration shown in Figure 39 was
used; for Figure 32 and Figure 33, the configuration shown in
Figure 40 was used; and for Figure 34, the configuration shown
in Figure 41 was used.
TEK P5050
VOLTAGE PROBE
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
CHPF
DECL
INHI
C1
HPE3631A
POWER
SUPPLY
SMT03
SIGNAL
GENERATOR
BALUN
C2
3dB
INLO
DECL
PWDN
COMM
C3
RF 50Ω
C4
AD8362
CHARACTERIZATION
BOARD
SMIQ03B
RF SOURCE
MULTIMETER
HP34401A
3dB
RFIN
VOUT
Figure 39. Response Measurement Setup for Modulated Pulse
TEK TDS5104
AD8362
SCOPE
TEK P5050
VOLTAGE PROBE
COMM
CHPF
DECL
INHI
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
PC
CONTROLLER
C1
Figure 38. Primary Characterization Setup
HPE3631A
POWER
SUPPLY
SMT03
SIGNAL
BALUN
C2
3dB
ANALYSIS
GENERATOR
INLO
The slope and intercept are derived using the coefficients
of a linear regression performed on data collected in its
central operating range. Error is stated in two forms: error
from linear response to CW waveform and output delta
from 25°C performance.
DECL
PWDN
COMM
RF 50Ω
C3
HP8112A
PULSE
GENERATOR
C4
The error from linear response to CW waveform is the
decibel difference in output from the ideal output defined by
the conversion gain and output reference. This is a measure of
the linearity of the device response to both CW and modulated
waveforms. The error in dB is calculated by
Figure 40. Response Measurement Setup for Power-Down Step
HP8112A
PULSE
AD811
GENERATOR
50Ω
732Ω
VOUT − Slope ×
PIN − PZ
Error dB =
( )
Slope
AD8362
TEK TDS5104
SCOPE
where PZ is the x intercept, expressed in dBm.
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
Error from the linear response to CW waveform is not a
measure of absolute accuracy since it is calculated using the
slope and intercept of each device. However, it verifies the
linearity and the effect of modulation on the device response.
Error from 25°C performance uses the performance of a given
device and waveform type as the reference; it is predominantly a
measurement of output variation with temperature.
CHPF
DECL
INHI
TEK P5050
VOLTAGE
PROBE
C1
0.01µF
100pF
BALUN
C2
3dB
INLO
DECL
PWDN
COMM
C3
SMT03
SIGNAL
GENERATOR
C4
RF 50Ω
Figure 41. Response Measurement Setup for Gated Supply
Rev. B | Page 14 of 36
AD8362
CIRCUIT DESCRIPTION
The AD8362 is a fully calibrated, high accuracy, rms-to-dc
converter providing a measurement range of over 60 dB. It is
capable of operation from signals as low in frequency as a few
Hertz to at least 2.7 GHz. Unlike earlier rms-to-dc converters,
the response bandwidth is completely independent of the signal
magnitude. The −3 dB point occurs at about 3.5 GHz. The
capacity of this part to accurately measure waveforms having a
high peak-to-rms ratio (crest factor) is independent of either
the signal frequency or its absolute magnitude, over a wide
range of conditions.
shown how this basic range may be shifted either up or down,
and even extended to >80 dB. The VGA gain has the form
GSET = GO exp −VSET VGNS
(1)
where GO is a basic fixed gain and VGNS is a scaling voltage that
defines the gain slope (the dB change per volt). Note that the
gain decreases with VSET. The VGA output is
VSIG = GSETVIN = GOVIN exp VSET VGNS
(2)
where VIN is the ac voltage applied to the input terminals
of the AD8362.
This unique combination allows the AD8362 be to used with
equal ease as a calibrated RF wattmeter covering a power ratio
of >1,000,000:1, as a power controller in closed-loop systems, or
as a general-purpose rms-responding voltmeter, and in many
other low frequency applications.
As is later explained more fully, the input drive may be
either single-sided or differential but optimum performance at
input drive. The effect of HF imbalances when using a single-
sided drive is less apparent at low frequencies (from 50 Hz
to 500 MHz), but the peak input voltage capacity is always
halved relative to differential operation (see the Using the
AD8362 section).
AMPLITUDE TARGET
FOR V
–25dB TO +43dB
SIG
MATCH WIDE-
BAND SQUARERS
VTGT
INHI
2
2
X
VGA
× 0.06
V
X
TGT
V
V
ATG
SIG
I
ACOM
INLO
SQUARE-LAW DETECTION
I
SQU
TGT
The output of the variable-gain amplifier, VSIG, is
G
SET
CHPF
applied to a wideband square law detector, which provides a
true rms response to this alternating signal that is essentially
independent of waveform up to crest factors of 6. Its output
is a fluctuating current, ISQU, having a positive mean value. This
current is integrated by an on-chip capacitance, CF; this is
usually augmented by an external capacitance, CLPF, to extend
the averaging time. The resulting voltage is buffered by a gain-
of-5, dc-coupled amplifier whose rail-to-rail output, VOUT, may
be used either for measurement or control purposes.
OFFSET
NULLING
V
OUT
C
F
OUTPUT
FILTER
VOUT
V
SET
SETPOINT
VSET
VREF
INTERFACE
CLPF
INTERNAL RESISTORS
SET BUFFER GAIN TO 5
V
REF
BAND GAP
REFERENCE
1.25V
C
LPF
EXTERNAL
In most applications, the AGC loop is closed via the setpoint
interface pin, VSET, to which the VGA gain-control voltage
VSET is applied. In measurement modes, the closure is direct
and local by a simple connection from the output the VOUT
pin to the VSET pin. In controller modes, the feedback path is
around some larger system, but the operation is the same.
ACOM
Figure 42. Basic Structure of the AD8362
The part comprises the core elements of a high performance
AGC loop (Figure 42), laser-trimmed during manufacture to
close tolerances while fully operational at a test frequency of
100 MHz. Its linear, wideband, variable gain amplifier (VGA)
provides a general voltage gain, GSET; this may be controlled in a
precisely exponential (linear-in-dB) manner over the full 68 dB
range from −25 dB to +43 dB by a voltage VSET. However, to
provide adequate guard-banding, only the central 60 dB of this
range, from −21 dB to +39 dB, is normally used. Later, it is
The fluctuating current, ISQU, is balanced against a fixed setpoint
target current, ITGT, using current mode subtraction. With the
exact integration provided by the capacitor(s), the AGC loop
equilibrates when
MEAN
ISQU
= ITGT
(3)
The current ITGT is provided by a second-reference squaring
cell whose input is the amplitude-target voltage VATG. This is a
fraction of the voltage VTGT applied to a special interface that
accepts this input at the VTGT pin. Since the two squaring cells
are electrically identical and are carefully implemented in the
IC, process and temperature-dependent variations in the
detailed behavior of the two square-law functions cancel.
Rev. B | Page 15 of 36
AD8362
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Accordingly, VTGT (and its fractional part VATG) determines the
output that must be provided by the VGA for the AGC loop to
settle. Since the scaling parameters of the two squarers are
accurately matched, it follows that Equation 3 is satisfied only
when
2
2
MEAN
(
VSIG
)
= VATG
(4)
In a formal solution, one would then extract the square root of
both sides to provide an explicit value for the root-mean-square
(rms) value. However, it is apparent that by forcing this identity,
through varying the VGA gain and extracting the mean value
by the filter provided by the capacitor(s), the system inherently
establishes the relationship
0
100µV
1mV
10mV
100mV
1V
10V
RMS INPUT VOLTAGE (100µV TO 3.2V)
Figure 43. Ideal Response of the AD8362
rms
VSIG
=VATG
(5)
EFFECT OF INPUT COUPLING ON THE INTERCEPT
VALUE
Substituting the value of VSIG from Equation 2, we have
Reductions of VIN due to coupling losses directly affect VZ. In
high frequency applications, several factors contribute to the
coupling of the source into the IC, including the board and
package resonances and attenuation. Any uncertainties in the
input impedance result in the intercept expressed in power
terms, which is nominally −57 dBm for a 50 Ω system, being
less accurately determined than when stated in dBV (that is, in
pure voltage) terms. On the other hand, the slope VSLP is
unaffected by all such impedance or coupling uncertainties.
rms
GOVIN exp
−VSET VGNS
=VATG
(6)
As a measurement device, VIN is the unknown quantity and all
other parameters can be fixed by design. Solving Equation 6:
rms
GOVIN VATG
= exp
VSET VGNS
(7)
so
VSET =VGNS log
rms
(VIN
)
VZ
(8)
OFFSET ELIMINATION
The quantity VZ = VATG/GO is defined as the intercept voltage
because VSET must be 0 when rms (VIN) = VZ.
To address the small dc offsets that arise in the variable gain
amplifier, an offset-nulling loop is used. The high-pass corner
frequency of this loop is internally preset to 1 MHz, sufficiently
low for most HF applications. When using the AD8362 in LF
applications, the corner frequency can be reduced as needed by
the addition of a capacitor from the CHPF pin to ground having
a nominal value of 200 µF/Hz. For example, to lower the high-
pass corner frequency to 150 Hz, a capacitance of 1.33 µF is
required. The offset voltage varies depending on the actual gain
at which the VGA is operating, and thus, on the input signal
amplitude.
When connected as a measurement device, the output of the
buffer is tied directly to VSET, which closes the AGC loop.
Making the substitution VOUT = VSET and changing the log
base to 10, as needed in a decibel conversion, we have
VOUT =VSLP log10
rms
(VIN
)
VZ
(9)
where VSLP is the slope voltage, that is, the change in output
voltage for each decade of change in the input amplitude.
(Note that VSLP = VGNS log (10) = 2.303 VGNS). In the AD8362,
V
SLP is laser trimmed to 1 V using a 100 MHz test signal.
Baseline variations of this sort are a common aspect of all
VGAs, although more evident in the AD8362 because of the
method of its implementation, which causes the offsets to
ripple along the gain axis with a period of 6.33 dB. When an
excessively large value of CHPF is used, the offset correction
process may lag the more rapid changes in the VGA’s gain,
which may increase the time required for the loop to fully settle
for a given steady input amplitude.
Because a decade corresponds to 20 dB, this slope may also be
stated as 50 mV/dB. It is later shown how the effective value of
VSLP may be altered by the user.
Likewise, the intercept VZ is also laser trimmed to 316 µV
(−70 dBV). In an ideal system, VOUT would cross zero for an
rms input of that value. In a single-supply realization of the
function, VOUT cannot run fully down to ground; here, VZ is
the extrapolated value. In measurement modes, the output
ranges from 0.5 V for VIN = 1 mV (input values are stated as
rms, outputs values as dc), up to a voltage 60 dB × 50 mV/dB =
3 V above this for VIN = 1 V, that is, to 3.5 V. Figure 43 shows the
ideal form of Equation 9 scaled as in the AD8362.
Rev. B | Page 16 of 36
AD8362
In such cases, the input coupling capacitors should be large
VOLTAGE VS. POWER CALIBRATION
enough so that the lowest frequency components of the signal
that are to be included in the measurement are minimally
attenuated. For example, for a 3 dB reduction at 1.5 kHz,
capacitances of 1 µF are needed because the input resistance is
100 Ω at each input pin (200 Ω differentially) and we calculate
1/(2π × 1.5 kΩ × 100) = 1 µF. Also, to lower the high-pass
corner frequency of the VGA, a capacitor of value 200 µF-Hz
should be used between the CHPF pin and ground; to provide a
similar 1.5 kHz high-pass corner, a capacitor of 133 nF should
be used.
The AD8362 can be used as an accurate rms voltmeter
from arbitrarily low frequencies to microwave frequencies.
For low frequency operation, the input is usually specified
either in volts rms or in dBV (decibels relative to 1 V rms).
Driven differentially, the specified input range in dBV runs
from −60 dBV to 0 dBV (1 mV to 1 V rms). In these terms,
the intercept is at −70 dBV.
At high frequencies, signal levels are commonly specified
in power terms. In these circumstances, the source and
termination impedances are an essential part of the overall
scaling. To set the AD8362’s input impedance to 50 Ω, it is
necessary to add a resistor of 66.7 Ω across the internal 200 Ω
differential input impedance of the IC. (This is discussed
further in later sections.) For this condition, the intercept
occurs at a nominal power level of −57 dBm, and VOUT
can be stated in this way:
TIME-DOMAIN RESPONSE OF THE CLOSED LOOP
The external low-pass averaging capacitance, CLPF, added at
the output of the squaring cell, is chosen to provide adequate
filtering of the fluctuating detected signal. The optimum value
depends on the application; as a guideline, a value of roughly
900 µF-Hz should be used. For example, a capacitance of 5 µF
provides adequate filtering down to 180 Hz. Note that the
fluctuation in the quasi-dc output of a squaring cell operating
on a sine wave input is a raised cosine at twice the signal
frequency, easing this filtering function.
VOUT =
PIN + 57
× 50 mV dB
(10)
where PIN is expressed in dBm. For example, an input of
−30 dBm generates an output of 1.35 V.
In the standard connections for the measurement mode,
the VSET pin is tied to VOUT. For small changes in input
amplitude (a few decibels), the time-domain response of this
loop is essentially linear, with a 3 dB low-pass corner frequency
of nominally fLP = 1/(CLPF × 1.1 kΩ). Internal time delays
around this local loop set the minimum recommended value of
this capacitor to about 300 pF, giving fLP = 3 MHz.
EFFECT OF SIGNAL WAVEFORM
The measurement accuracy of an rms-responding device is
ideally unaffected by the waveform of the input signal. This is a
valuable asset in wideband CDMA systems and in many other
modulation modes where there is a significant amount of
random variation of the RF carrier amplitude at baseband
frequencies. The high accuracy of the AD8362 in such cases is
indicated by the Typical Performance Characteristics graphs
and in the Specifications table. Note that at low frequencies, it is
customary to provide a specification of measurement errors due
to waveform effects as a function of the crest factor (σ) rather
than in terms of a system-specific modulation mode.
When large and abrupt changes of input amplitude occur,
the loop response becomes nonlinear and exhibits slew rate
limitations. Further, due to the fundamentals of a system using
transconductance squaring cells as employed in the AD8362,
the slewing is asymmetric for increasing and decreasing inputs.
Figure 44 shows typical waveforms for VOUT for three values
of VIN using CLPF = 1 nF.
When measuring signals whose waveforms have high but
brief peak values (that is, having high crest factors), these
peaks may be clipped, causing a reduction in the apparent value
of the input being measured. This issue is discussed further in
connection with the detailed description of the input system.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
OPERATION AT LOW FREQUENCIES
In conventional rms-to-dc converters based on junction
techniques, the effective signal bandwidth is proportional to the
signal amplitude. For a 1 MHz rms-to-dc converter, this is the
full-scale bandwidth. However, at an input 60 dB below full-
scale, the bandwidth could be as low as 1 kHz. In sharp contrast,
the 3.5 GHz bandwidth of the VGA in the AD8362 is
independent of its gain. Since this amplifier is internally dc-
coupled, the system can also be used as a high accuracy rms
voltmeter at low frequencies, retaining its temperature-stable
decibel-scaled output, for example, in seismic, audio, and sonar
instrumentation.
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
8
16 24 32 40 48 56 64 72 80 88 96
0
TIME (µs)
Figure 44. Typical Large-Scale Response
Rev. B | Page 17 of 36
AD8362
3.7
3.2
2.7
2.2
1.7
1.2
0.7
0.2
10
The most satisfactory way to quantify slew-rate limitations is by
considering the peak currents that can be generated by the
squaring cells. During a fast increase in input level, the peak
current into the integrating (loop filter) capacitance, CLPF, is
approximately 2.5 mA. The actual value depends on several
factors, including the size of the step, and extremes in chip
temperature. The voltage across the 1 nF capacitor thus
increases at a rate of nominally 2.5 V/µs. Because the output
buffer has a gain of 5, the output slew rate is 12.5 V/µs. The peak
rate persists up to a point about 10 dB below the final value,
after which the response gradually converges on the linear
system response, as noted previously.
VTGT = 300mV
5
0
VTGT = 533mV
VTGT = 949mV
VTGT = 1.69V
VTGT = 3.0V
10m
–5
–10
100µ
1m
0.1
1
10
On the other hand, during a fast decrease in input level, the
peak current in CLPF in the opposite (discharging) direction is
much smaller; it is roughly 25 µA. Thus, the slew rate for VOUT
in the descending direction is only about 0.125 V/µs for CLPF =
1 nF. Discharging over the full 3 V range (a 60 dB reduction of
input) requires a time interval of ~24 µs. These figures are
verified in the results shown in Figure 44.
RMS INPUT VOLTAGE (V)
Figure 45. Response with VTGT Varied from 0.3 V to 3 V in 5 dB Steps,
Showing the Proportional Shift in Intercept
EFFECTS AT EACH END OF DYNAMIC RANGE
All AGC loops have a limited minimum and maximum input
beyond which the system cannot respond correctly. However,
the output of a well-behaved system is in error in such a way as
to avoid anomalous measurements. For an input below its
minimum capability, the output should not turn around to
falsely indicate a higher input value; for inputs above its
maximum capability, the output should not fold over and return
to some lower value.
ALTERATION OF THE INTERNAL TARGET VOLTAGE
The AD8362 incorporates several features that extend its
versatility. One of these is the ability to alter the target
voltage. As noted, the output of the VGA is forced to a
value set by the internal bias voltage (VATG = 0.06 × VTGT)
applied to the reference squaring cell. It is normally set to 75
mV dc by connecting VTGT to the 1.25 V reference voltage at
the VREF pin. However, it may optionally be varied from 0 V
up to 0.24 V ( 4 V at VTGT). Note that the sign of this input
is unimportant, because it is internally squared.
The actual behavior of the AD8362 under these conditions can
be seen in the set of plots in Figure 45, the lower panel of which
shows the deviation from the ideal response with a slope of
50 mV/dB. For inputs below a certain level corresponding to the
point at which the VGA is operating at its maximum gain, its
output can no longer meet the rms amplitude target set by
VTGT, so the output moves quickly to its minimum value in an
attempt to provide the needed extra gain. As VTGT is altered,
the corresponding end-limit voltage moves to the left or to the
right.
By lowering VATG, the output of the VGA needed to balance the
output currents of the two matched squaring cells is similarly
lowered. This reduces the intercept in precisely the same ratio.
Thus, if we halve the setpoint target voltage by halving the
voltage applied to the VTGT pin, the intercept moves to the left
(to a smaller input level) by 6.02 dB. This effectively doubles the
measurement system’s sensitivity.
On the other hand, when the input is above a certain upper
limit where the VGA gain has been driven to its minimum
gain, any further increase drives its output well above the target
voltage needed to balance the loop. The resulting integration of
this internal error signal causes VOUT to rise abruptly. In either
case, this output takes on a safe value and does not fold back
under any conditions.
Furthermore, because the signal amplitude needed to drive the
squaring cell is halved, the output stage of the VGA now has
twice the dynamic headroom (before clipping) and can handle
waveforms having crest factors that are twice as large. Figure 45
shows the overall response for an illustrative set of values of
VTGT = 0.3 V, 0.533 V, 0.949 V, 1.687 V, and 3.0 V. While this is
usually a fixed dc voltage, it can also be a time-varying, unipolar
or bipolar voltage, in which case the overall operation is rather
more complex. For example, when VTGT is derived from
VOUT, the dynamic range can be extended to over 80 dB.
Examples of such uses of this feature are presented later.
The dynamic range, the “dB distance” between these limits, is
not basically dependent on VTGT. The middle line in the plots
of Figure 45 (VTGT = 0.949 V) extends from 0.5 mV to 1.5 V
between the 1% error points; the dynamic range is thus
slightly over 68 dB. For other values of VTGT, this basic 68 dB
range just moves to the left or to the right.
Rev. B | Page 18 of 36
AD8362
VPOS
An unavoidable consequence of this method is that the diodes
will forward-conduct when the input amplitude is sufficient.
This is not an all-or-nothing effect, of course; they shunt the
input progressively as the signal increases. This conduction is
strongest at high temperatures when the forward drop voltage
of these diodes is lowest. The overall consequence is that high
amplitude peaks are clamped to a greater or lesser degree. This
affects the measurement accuracy at the top extreme of the
dynamic range whenever the signal waveform has a high crest
factor. These effects are, of course, included in the overall
performance specifications.
DECL
COMM
INHI
VGA
VIN
INLO
POWER-ENABLE RESPONSE TIME
COMM
The operating and standby currents for the AD8362 at 27°C
are 24 mA and 275 µA, respectively. The power-down mode
is activated by a logic high on the PWDN pin. When the
shutdown feature is used, the normal operating conditions
are restored relatively quickly when this pin is taken low.
DECL
VPOS
Figure 46. Input Protection at INHI and INLO Pins
INPUT PROTECTION
Figure 47 shows typical response times for a midscale signal
(VIN = 50 mV). The output rises to within 0.1 dB of its steady-
state value in about 20 µs; the reference voltage is available to
full accuracy in a much shorter time. This wake-up response
varies in detail depending on the input coupling means and the
capacitances CDEC, CHPF, and CLPF. These results are for a
measurement system operating in the 0.8 GHz to 2 GHz range,
balun coupled at the input port, with CDEC = 1 nF, CHPF = 0,
and CLPF = 1 nF.
Like all robust ICs, the AD8362 requires input protection
against high voltage transients at the input (ESD). However, the
techniques normally used for this purpose, based on breakdown
diodes from the input pins INHI and INLO to the supply pins
VPOS and COMM, cannot be used here because this raises the
risk of excessive signal coupling to internal nodes at the upper
end of the frequency range due to feedthrough in the
capacitances of these diodes. Package inductances cause all
internal nodes, including the supply and common lines, to have
a significant impedance back to the external ground plane; even
small disturbances on these nodes can cause anomalous
operation.
24.00mA
10.00mA
This risk is particularly evident because the main amplifier
in the AD8362’s VGA (an advanced X-AMP®) operates at full
gain under all conditions, while the signal input is variably
attenuated. Because this attenuation may be as high as 70 dB,
very small feedthrough effects in the 0.5 GHz to 3 GHz range
can have a pronounced impact on measurement accuracy.
1.00mA
0.27mA
0.10mA
2.20V
OUTPUT VOLTAGE
1dB
2.19V
2.18V
1.26V
REFERENCE VOLTAGE
Figure 46 shows the protection method used. The multiple
diodes arranged in back-to-back pairs limit the voltage swing
on the input pins by clamping to the two DECL pins, which
form a common ac low impedance node for the attenuators,
independently grounded via two external capacitors. The HF
currents in the capacitances of these diodes are thus shunted
directly to a signal null point.
1.25V
1.24V
0
10
20
30
40
TIME (µs)
Figure 47. Typical Wake-Up Response; t0 = 10 µs
Rev. B | Page 19 of 36
AD8362
USING THE AD8362
V
S
The AD8362 requires a single supply of nominally 5 V; its
performance is essentially unaffected by variations of up to
10%, the range over which the stated specifications apply.
Supplies as low as 2.7 V may be used with some loss of
performance at high inputs and at temperature extremes.
+5V nom, @ 24mA
AD8362
3.3Ω
1
2
3
4
COMM ACOM 16
CHPF
VREF 15
C
C
DEC
0.1µF
14
DECL
INHI
VTGT
DEC
1nF
V
VPOS 13
VOUT 12
SIGNAL INPUT
Z = 2 × 100Ω
The AD8362 is disabled by a logic high on the PWDN pin,
which may be directly grounded for continuous operation,
when the supply current at 27°C is nominally 24 mA and
essentially independent of supply voltage. When powered
down by a logic low on PWDN, the supply current is reduced
to about 275 µA.
C
CPL
5
6
INLO
DECL
1mV – 1V rms
OUT
11
VSET
C
DEC
LOGIC HIGH FOR
POWER-DOWN
7
8
PWDN ACOM 10
COMM CLPF
9
C
LPF
Figure 48. Basic Measurement Mode Connections
BASIC CONNECTIONS
The supply is connected to the VPOS pin using the decoupling
network shown in Figure 48, whose capacitors must provide a
low impedance over the full frequency range of the input, and
should be placed as close as possible to the VPOS pin. Two
different capacitors are used in parallel to reduce the overall
impedance since these have different resonant frequencies.
However, the measurement accuracy is not critically dependent
on supply decoupling because the high frequency signal path is
confined to the relevant input pins. It is more important that the
lead lengths to INHI and INLO, and in the decoupling
capacitors from both of the DECL pins to ground, and the
connections from COMM to the ground plane all use the
shortest possible connections.
Rev. B | Page 20 of 36
AD8362
MAIN MODES OF OPERATION
V
S
Both measurement and controller modes are supported by the
AD8362. Typical connections for the measurement mode,
which may also be viewed as the rms voltmeter mode, are also
illustrated in Figure 48. The output, VOUT, is proportional to
the logarithm of the rms magnitude of the input signal (that is,
a linear-on-dB response). When used in an accurately known
system impedance (but only then), the output is a scaled decibel
measurement of the power represented by the input voltage.
+5V nom, @ 24mA
AD8362
NO CONNECTION
FOR f >10MHz
3.3Ω
1
2
3
4
5
6
7
8
COMM ACOM 16
NC
CHPF
DECL
INHI
VREF 15
VTGT 14
VPOS 13
VOUT 12
VSET 11
0.1µF
1nF
1nF
V
SIGNAL INPUT
Z = 2 × 100Ω
1mV – 1V rms
C
CPL
RAIL-TO-RAIL
OUT
INLO
DECL
CONTROL OUTPUT
SETPOINT INPUT
0V–3.5V
1nF
PWDN ACOM 10
COMM CLPF
The choice of the capacitances CCPL, CDEC, CHPF, and CLPF
depends on the lowest frequency to be included in the
measurement spectrum. The default values shown support
operation down to 100 Hz. Using a large enough value of CLPF
(10 µF) to ensure sufficient filtering at this low input frequency,
the response time is approximately 20 ms over most of the
dynamic range. In high frequency applications, this capacitor is
much smaller and is usually chosen to minimize the response
time, consistent with well-behaved, large-signal behavior. In this
figure, CHPF is also shown as 10 µF, to lower the high-pass
corner to about 90 Hz. However, no capacitor will be needed
here in most HF applications since the internally set high-pass
corner is at about 2 MHz.
THIS CONNECTION
SETS CHIP-ENABLE
9
300pF
Figure 49. Basic Controller Mode Connections
Controller mode operation is more closely analogous to that of
a classical proportional/integral/derivative (PID) loop. The
error corresponding to the decibel deviation from the setpoint
is integrated by current into a capacitor (the sum of the internal
and external capacitance CLPF) until such deviation is nulled.
This action provides the fundamental proportional part of the
loop response (although VOUT has decibel scaling). The Q of
this system can be adjusted to minimize the loop response time
by including a resistor in series with CLPF, generating a
transmission zero, which provides the derivative term of a
standard PID loop.
Comparing the controller mode illustrated in Figure 49, the
AD8362 is used here to monitor the output of a variable gain
(or variable output power) signal processing element, frequently
a power amplifier, and adjust its output to a desired target value
(the setpoint) under the control of VSET. In this mode, its
function is somewhat like an RF comparator. With the path
from VOUT to VSET broken, any input larger than the
corresponding setpoint causes VOUT to rail to its maximum
value (which might loosely be viewed as a logic high). For
inputs smaller than the setpoint, the controller’s output falls to a
near-ground level (logic low). Using the AD8362 simply as a
threshold detector, this viewpoint may be useful, but in most
applications, it is an oversimplification. The AD8362 invariably
operates with the control loop closed, either locally with VOUT
connected to VSET (as in measurement mode), or globally via
some external nonlinear element (as in controller mode).
As a simple example, assume that the AD8362 operates at an
input power level of −20 dBm re: 50 Ω. Connected in the
measurement mode, it generates a VOUT of 2.00 V, because this
input is +40 dB above the intercept at −60 dBm and is scaled to
50 mV/dB. Rearranged to the controller mode with exactly this
voltage now externally applied to the VSET pin, the loop forces
VOUT to the control voltage required by the gain element to
provide a power sample of −20 dBm.
Of course, any control loop of this sort operates correctly
only if VSET corresponds to a power level (or a small sample of
such) that can actually be provided by the external gain element.
When this is a power amplifier, including the required amount
of RF attenuation ensures this condition. In certain instrument-
ation situations, it may be necessary to provide some low noise
gain ahead of the AD8362’s input.
These two primary modes of use are discussed in more detail,
with emphasis on practical considerations.
Rev. B | Page 21 of 36
AD8362
OPERATION IN MEASUREMENT MODES
Figure 50 shows the general connections for operating the
AD8362 as an RF power detector, more correctly viewed
as an accurate measurement system. The full performance
potential of this part, particularly at very high frequencies
(above 500 MHz), is realized only when the input is presented
to the AD8362 in differential (balanced) form. In this example, a
flux-coupled transformer is used at the input. Having a 1:4
impedance ratio (1:2 turns ratio), the 200 Ω differential input
resistance of the AD8362 becomes 50 Ω at the input to the
transformer, whose outputs can be connected directly to INHI
and INLO. If a center-tapped transformer is used, connect the
tap to the DECL pins, which are biased to the same potential as
the inputs (~3.6 V). Over the 0.9 GHz to 2.2 GHz range, a
transmission line transformer (balun) may be used, as explained
later. (The evaluation board is supplied with a M/A-COM
ETC1.6-4-2-3, 0.5 GHz to 2.5 GHz, 4:1 balun.)
LAW CONFORMANCE ERROR
In practice, the response deviates slightly from the ideal straight
line suggested by Equation 11. This deviation is called the law
conformance error. In defining the performance of high
accuracy measurement devices, it is customary to provide plots
of this error. In general terms, it is computed by extracting the
best straight line to the measured data using linear regression
over a substantial region of the dynamic range and under
clearly specified conditions.
3.0
3.8
3.5
2.5
2.0
1.5
1.0
0.5
–40°C
3.2
2.9
2.6
2.3
0
2.0
1.7
1.4
1.1
0.8
0.5
0.2
V
S
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
+25°C
+5V nom, @ 24mA
+85°C
AD8362
–40°C
1:4 Z-RATIO
(1:2 TURNS RATIO)
3.3Ω
1
2
3
4
5
6
7
8
COMM ACOM 16
+25°C
+85°C
NC
CHPF
DECL
INHI
VREF 15
VTGT 14
VPOS 13
0.1µF
SIGNAL INPUT
Z = 50Ω
1nF
1nF
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT AMPLITUDE (dBm)
0
5
10 15
200Ω
12
INLO
DECL
VOUT
V
RAIL-TO-RAIL
OUT
CONTROL OUTPUT
VSET 11
Figure 51. Output Voltage and Law Conformance Error,
at TA = −40°C, +25°C, and +85°C
1nF
PWDN ACOM 10
COMM CLPF
9
Figure 51 shows the output of the circuit of Figure 50 over the
full input range. The agreement with the ideal function (law
conformance) is also shown. This was determined by linear
regression on the data points over the central portion of the
transfer function (35 mV to 250 mV rms) for the 25°C data.
The error at +25°C, −40°C, and +85°C was then calculated by
subtracting the ideal output voltage at each input signal level
from the actual output and dividing this quantity by the mean
slope of the regression equation to provide a measurement of
the error in decibels (scaled on the right-hand axis of Figure 51).
300pF
Figure 50. Connections for RF Power Measurement
The output in this mode of use is a continuous, decibel-scaled
voltage ranging from about 0.5 V to 3.5 V.
VOUT =
PIN PZ
× 50 mV dB
(11)
The equivalent input power, PIN, is expressed in dBm (decibels
above 1 mW) in a particular system impedance, which in this
case is 50 Ω. The intercept, PZ, is that input power for which
the back-extrapolated output crosses zero. Expressed as a
voltage, it is 0.447 mV rms (−67 dBV, laser-calibrated at
100 MHz), corresponding to a PZ of −60 dBm in 200 Ω.
However, the 1:2 turns ratio of the transformer halves the
required input voltage, which moves the intercept down by
6 dB to 0.224 mV rms (−73 dBV) at the transformer’s input.
The error curves generated in this way reveal not only the
deviations from the ideal transfer function at a nominal
temperature but also all of the additional errors caused by
temperature changes. Notice there is a small temperature
dependence in the intercept (the vertical position of the error
plots); this variation is within 0.5 dB at high powers.
Figure 51 further reveals that there is a periodic ripple in the
conformance curves. This is due to the interpolation technique
used to select the signals from the attenuator, not only at
discrete tap points, but anywhere in between, thus providing
continuous attenuation values. The selected signal is then
applied to the 3.5 GHz, 40 dB fixed gain amplifier in the
remaining stages of the AD8362’s VGA.
Impedance mismatches and attenuation in the coupling
elements significantly affect the intercept position. This error
is stable over temperature and time, and thus can be removed
during calibration in a specific system. The logarithmic slope of
50 mV/dB varies only slightly with frequency; corrected values
for several common frequencies are provided in the
Specifications section.
Rev. B | Page 22 of 36
AD8362
An approximate schematic of the signal input section of the
AD8362 is shown in Figure 52. The ladder attenuator is
composed of 11 sections (12 taps), each of which progressively
attenuates the input signal by 6.33 dB. Each tap is connected to
a variable transconductance cell whose bias current determines
the signal weighting given to that tap. The interpolator
determines which stages are active by generating a discrete set
of bias currents, each having a Gaussian profile. These are
arranged to move from left to right, thereby determining the
attenuation applied to the input signal as the gain is
progressively lowered over the 69.3 dB range under control of
the VSET input. The detailed manner in which the
transconductance of adjacent stages varies as the virtual tap
point slides along the attenuator accounts for the ripple
observed in the conformance curves. Its magnitude is slightly
temperature dependent and also varies with frequency (see
Figure 10 to Figure 12). Notice that the system’s responses to
signal inputs at INHI and INLO are not completely
independent; these pins do not constitute a fully floating
differential input.
AD8362
THIS INPUT
IS DRIVEN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM ACOM
NC
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
1nF
RF INPUT
Z = 50Ω
R
SH
INLO
DECL
1nF
PWDN ACOM
COMM CLPF
DECL AND
INLO ARE
NOT DRIVEN
Figure 53. Input Coupling from a Single-Ended Source
Figure 53 illustrates one of many ways of coupling the signal
source to the AD8362. Because the input pins are biased to
about 3.6 V (for VS = 5 V) dc-blocking capacitors are required
when driving from a grounded source. For signal frequencies
>5 MHz, a value of 1 nF is adequate. While either INHI or
INLO may be used, INHI is chosen here, and INLO is
connected to the low side of the source. The resistor RSH is not
needed if a 100 Ω termination is acceptable. The corresponding
intercept is still −67 dBV, that is, 447 µV rms. However, specified
in power terms at 100 Ω, the PZ is now at 2 nW or −57 dBm.
ATTENUATION
GUASSIAN INTERPOLATOR
CONTROL
For a source termination of 50 Ω, the internal 100 Ω from INHI
to DECL must be shunted by a chip resistor of 100 Ω. At high
frequencies, a low attenuation pad at the input improves the
VSWR. For example, with a resistor of RSH = 33 Ω and an added
resistor of 25 Ω from the source to INHI, a termination of 50 Ω
is provided, with 6 dB of attenuation, raising the intercept to
−48 dBm.
TO FIXED
GAIN STAGE
gm
gm
gm
gm
INHI
DECL
USING A NARROW-BAND INPUT MATCH
INLO
While transformers offer the simplest method for providing
single-sided to balanced conversion, a good alternative is
using a specially designed narrow-band LC network, shown in
Figure 54, which also provides an input match. Using this basic
formulation, the match is to 50 Ω, with a voltage gain of 1.5
(3.56 dB) from the input connector to the AD8362. This
network is specially designed to provide a high degree of
amplitude balance at INHI and INLO as well as an exact phase
inversion. The narrow-band match provides a useful degree of
frequency selectivity, and the capacitors also serve to provide
the required dc blocking.
STAGE 1
6.33dB
STAGE 11
6.33dB
STAGE 2
6.33dB
Figure 52. Simplified Input Circuit
ALTERNATIVE INPUT COUPLING MEANS
The input stages of the AD8362 are optimally driven from a
fully balanced source, which should be provided wherever
possible. The ac low sides of both halves of the attenuator
internally connect to the DECL pin, which is therefore the RF
signal low terminal for both INHI and INLO. In many cases,
unbalanced sources can be applied directly to one or the other
of these two pins. The chief disadvantage of this driving method
is a reduction in dynamic range, particularly at very high
frequencies.
AD8362
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM
CHPF
DECL
INHI
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
NC
C1
RF INPUT
Z = 50Ω
100Ω
L
INLO
DECL
PWDN
COMM
C2
THESE INPUTS ARE
EQUAL IN AMPLITUDE
AND OF OPPOSITE SIGN
Figure 54. Narrow-Band Reactive Input Coupling
Rev. B | Page 23 of 36
AD8362
The network can readily be scaled to other frequencies by
varying the product LC, while keeping the ratio L/C constant to
preserve a 50 Ω input impedance. Table 4 provides some spot
values; these take into account the reactive ZIN of the AD8362.
CHOOSING THE RIGHT VALUE FOR CHPF AND
CLPF
The AD8362’s 3.5 GHz variable gain amplifier includes an offset
cancellation loop, which introduces a high-pass filter effect in
its transfer function. The corner frequency, fHP, of this filter
must be below that of the lowest input signal in the desired
measurement bandwidth frequency to properly measure the
amplitude of the input signal. The required value of the external
capacitor is given by
Table 4. Suggested Components for Narrow-Band 50 Ω
Match
Frequency (MHz)
L (nH)
21850
10925
4370
2185
1093
437
220
100
40
C1 (pF)
2230
1115
446
223
112
45
22
10
3.9
C2 (pF)
2765
1383
553
276
138
55
27
12
4.7
1
2
5
10
20
50
100
200
500
CHPF = 200μF fHP
fHP in Hz
(12)
Thus, for operation at frequencies down to 100 kHz, CHPF
should be 2 nF.
In the standard connections for the measurement mode, the
VSET pin is tied to VOUT. For small changes in input amplitude
(a few decibels), the time-domain response of this loop is
essentially linear with a 3 dB low-pass corner frequency of
nominally fLP = 1/(CLPF × 1.1 kΩ). Internal time delays around
this local loop set the minimum recommended value of this
capacitor to about 300 pF, making fLP = 3 MHz.
This coupling method can be used down to much lower
frequencies than shown in Table 4 simply by multiplying the
1 MHz component values proportionally. The effects of the
reactive components of the AD8362’s inputs above 500 MHz
may require some fine tuning of the suggested values. In the
gigahertz region, the input coupling is usually more effectively
implemented using a balun.
For operation at lower signal frequencies, or whenever the
averaging time needs to be longer, use
UNCERTAINTIES IN RIN AND POWER CALIBRATION
CLPF = 900μF fLP
fLP in Hz
(13)
In all the cases where a 50 Ω to 200 Ω transformation is
implemented, the voltage gain is only nominally ×2 (6 dB). This
ideal is impaired by the fact that the input resistances of the
AD8362 are not precise; variations of 20% can be expected
from lot to lot. Therefore, it is necessary to use a calibration step
whenever an accurate value for the power intercept, PZ, must be
established.
When the input signal exhibits large crest factors, such as a
WCDMA signal, CLPF must be much larger than might at
first seem necessary. This is due to the presence of significant
low frequency components in the complex, pseudo-random
modulation, which generates fluctuations in the output of
the AD8362.
When driven differentially, a significant improvement in
intercept accuracy can be achieved by shunting the 200 Ω
resistance from INHI to INLO with a 66.5 Ω resistor to set the
differential input resistance to 50 Ω. Assuming a tolerance of
20% for the basic RIN and 1% for the chip resistor, the net
input resistance could exhibit an error of 2.5%. The resulting
error in PZ (and thus in the absolute power measurement) may
vary from −0.26 dB to +0.21 dB.
USE OF NONSTANDARD TARGET VOLTAGES
An external connection between VREF and VTGT sets up
the internal target voltage, that is, the rms voltage that must
be provided by the VGA to balance the AGC feedback loop. In
the default scheme, the VREF of 1.25 V positions this target to
0.06 × 1.25 V = 75 mV. In principle, however, VTGT may be
driven by any voltage in the range −4 V to +4 V (the sign is
ignored) to alter this target, either in a fixed or dynamic way.
These precautions regarding input impedance do not apply
when the input is presented in voltage form, as is often the case
at low frequencies, or when the source impedance is low
compared to 200 Ω. For example, when using a feedback
amplifier as an impedance buffer ahead of the input, as in the
example in Figure 61, the loss at the interface at moderate
frequencies is negligible.
For example, if this pin is supplied from VREF via a simple
resistive attenuator of 1 kΩ:1 kΩ, the output required from the
VGA is halved (to 37.5 mV rms), which moves the nominal
intercept to −73 dBV. Under these conditions, the effective
headroom in the signal path that drives the squaring cell is
doubled. In principle, this doubles the peak crest factor that may
be handled by the system.
If VTGT is reduced too far, the accuracy and stability of the
intercept are compromised. The currents generated by the
transconductance mode squaring cells become smaller by the
square of the ratio. Thus, a factor of 5 reduction in VTGT
Rev. B | Page 24 of 36
AD8362
lowers the signal currents in the squaring cells by a factor of 25.
As well as making the system more sensitive to small static
errors (offsets) in the postdetection circuitry, such a reduction
also reduces the peak slew rate. A suitable adjustment to the
value of CLPF is needed to maintain a given AGC loop
bandwidth. On the other hand, increasing the target voltage can
improve the accuracy and stability of the intercept for low crest
factor signals. Thus, using VTGT = 2.5 V, the peak output
currents of the squaring cell are quadrupled and the peak slew
rate is increased by the same factor. CLPF should be increased
to maintain an adequate stability margin in the AGC loop.
Also, it is worth remembering that these shifts in intercept are
equivalent, in most respects, to a dc offset applied to the
AD8362’s output, with the main differences being that:
•
Varying VTGT affects the crest factor capacity to some
extent
•
This technique makes better use of the available output
range than a post-VOUT adjustment would
5V
AD8362
1
2
3
4
5
6
7
8
4.02kΩ
16
15
14
13
12
11
COMM ACOM
VREF
VTGT
VPOS
VOUT
VSET
CHPF
DECL
INHI
4.02kΩ
5.75kΩ
In many applications, it is useful to use a nonstandard value of
VTGT to shift the measurement range by a constant amount to
accommodate either a reduced or increased range of signal
inputs. The dynamic span remains >60 dB for such changes.
This technique is particularly useful when the sensitivity can be
lowered by raising VTGT, and there is little expectation of high
crest factor signals.
VR1
20kΩ
INLO
DECL
PWDN
COMM
ACOM 10
CLPF
9
Figure 55. Adjustments of the Intercept by 3 dB
ADJUSTING THE INTERCEPT
ALTERING THE SLOPE
Another way to take advantage of the effect of VTGT is to use it
to introduce an adjustment to the log intercept, represented by
the voltage VZ in Equation 14. Formally, this can be expressed in
terms of a modified value of VZ'.
None of the changes in operating conditions discussed so far
affect the logarithmic slope, VSLP, in Equation 9. However, this
can readily be altered by controlling the fraction of VOUT that
is fed back to the setpoint interface at the VSET pin. When the
full signal from VOUT is applied to VSET, the slope assumes its
nominal value of 50 mV/dB. It can be increased by including an
attenuator between these pins, as shown in Figure 56. Moder-
ately low resistance values should be used to minimize scaling
errors due to the 70 kΩ input resistance at the VSET pin. Keep
in mind that this resistor string also loads the output, and it
eventually reduces the load-driving capabilities if very low
values are used. To calculate the resistor values, use
VZ' =VZVTGT 1.25V
(14)
A lower VTGT effectively increases the sensitivity of the
measurement system, which is just another way of stating that the
intercept moves to a lower value. This raises VOUT for all input
amplitudes, as demonstrated by the plots in Figure 45. This
control of the measurement system’s intercept could therefore be
brought about by applying the output of a DAC to the VTGT pin,
if that suits the overall objectives of an application.
R1= R2'
SD 50 −1
)
(15)
For many purposes, a small manual adjustment range of 3 dB
is sufficient. This can be implemented as shown in Figure 55.
Here, the largest fraction of VTGT is still provided by the built-
in reference to minimize the sensitivity to supply voltage
variations. Now a variable component is provided by the trim
network. For a 5 V supply, this added component of VTGT is 0
when VR1 is centered. With the slider closest to ground, VTGT
is lowered by 366 mV, which corresponds to a 3 dB decrease in
intercept; in the opposite condition, it is raised by 518 mV,
which increases the intercept by 3 dB. That is, VTGT ranges
from 1.25 V/√2 to √2 × 1.25 V.
where SD is the desired slope, expressed in mV/dB, and
R2' is the value of R2 in parallel with 70 kΩ. For example, using
R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' = 1.649 kΩ), the nominal
slope is increased to 100 mV/dB. This choice of scaling is useful
when the output is applied to a digital voltmeter because the
displayed number reads as a decibel quantity directly, with only
a decimal point shift.
AD8362
COMM ACOM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
Other adjustment ranges can be readily calculated from this
example. The resistance at the VTGT pin is nominally 52 kΩ;
resistor values should be calculated with this in mind. In some
situations, this control interface might be driven from a
programmable source. In the simplest case, a logic level could
provide two intercept values, differing by say, 10 dB, thus
providing essentially two switched input ranges.
V
INLO
DECL
OUT
R1
R2
PWDN ACOM
COMM CLPF
Figure 56. External Network to Raise Slope
Rev. B | Page 25 of 36
AD8362
Operation at high slopes is useful when a particular subrange of
the input is measured in greater detail. However, a measurement
range of 60 dB would correspond to a 6 V change in VOUT at
this slope, exceeding the capacity of the AD8362’s output stage
when operating on a 5 V supply. This requires that the intercept
is repositioned to place the desired subrange within a window
corresponding to an output range of 0.2 V ≤ VOUT ≤ 4.8 V,
a 46 dB range.
That being the case, the gain-control voltage, VSET, likewise
does not need to change. It follows that the output is free of
fluctuations. In measurement mode, that voltage is also the
output, so it also remains at a constant value as the modulation
varies the input magnitude. The bandwidth of the dc-coupled
amplifier in the AD8362 that buffers VTGT has been kept high
(~300 MHz) so that even fast AM modulation envelopes can be
accurately tracked.
Using the arrangement shown in Figure 57, an output of 0.5 V
corresponds to the lower end of the desired subrange, and 4.5 V
corresponds to the upper limit with 3 dB of margin at each end
of the range, which is nominally 3 mV rms to 300 mV rms, with
the intercept at 1.9 mV rms. Note that R2 is connected to VREF
rather than ground. R3 is needed to ensure that the AD8362’s
reference buffer, which can sink only a small current, is
correctly loaded.
Figure 58 shows an example. As depicted in the top panel of
Figure 59, the input to the AD8362 is a pure, ideal, sinusoidal
100 MHz carrier that is amplitude modulated at 100 kHz by
another pure sine wave. A suitably scaled sample of the
modulation voltage is also applied to the VTGT pin. In this
example, its average value is 1.25 V (the normal bias level for
VTGT), and the amplitude is 0.75 V. Therefore VTGT ranges
from 0.5 V to 2 V, corresponding to a factor of 4 change (16 dB)
in the target voltage over each cycle of the modulation. The
resulting VOUT waveform is of essentially constant value at
about 2.5 V, as shown in Figure 59; this is compared with the
deeply fluctuating output for a fixed VTGT of 1.25 V.
It is apparent that a variable attenuation factor based on this
scheme could provide a manual adjustment of the slope, but
there are few situations in which this is of value. When the slope
is raised by some factor, the loop capacitor, CLPF, should be
raised by the same factor to ensure stability and to preserve a
chosen averaging time. The slope can be lowered by placing a
two-resistor attenuator after the output pin, following standard
practice.
BASEBAND REPLICA
OF MODULATED INPUT
SIGNAL ENVELOPE
V
S
+5V nom,
@ 24mA
AD8362
3.3Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM ACOM
NC
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
NC
AMPLITUDE
0.1µF
MODULATED
SIGNAL INPUT
AD8362
R3
2kΩ
1nF
1
2
16
15
14
13
12
11
10
9
COMM ACOM
1nF
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
INLO
DECL
V
OUT
3
4
5
6
7
8
R2
4.32kΩ
1nF
PWDN ACOM
COMM CLPF
V
INLO
DECL
OUT
R1
C
4.02kΩ
LPF
PWDN ACOM
COMM CLPF
Figure 58. Envelope Elimination Using the VTGT Interface
Figure 57. Scheme Providing 100 mV/dB Slope for Operation
over a 3 mV to 300 mV Input Range
0.2
0
ENVELOPE ELIMINATION MODE
–0.2
The VTGT input can be used to track the AM modulation
envelope on an RF signal to affect a form of envelope
FIXED TARGET VOLTAGE (1.25V)
elimination. The modulation waveform must be known and a
sample must be available as a baseband voltage. Using this
voltage as VTGT, the AD8362 tracks this envelope when
demodulation is realized by the squaring cell. So if the envelope
output of the main amplifier should, for example, double over
some interval while the target voltage that satisfies the AGC
loop criterion also doubles, the net effect is that the gain of the
amplifier does not need to change to keep the loop balanced.
2
1
VARYING TARGET VOLTAGE
0
3
2
1
WITH FIXED TARGET
VOLTAGE
WITH VARYING TARGET VOLTAGE
0
10
20
30
40
TIME (µs)
Figure 59. Waveforms for Envelope Elimination Scheme
Rev. B | Page 26 of 36
AD8362
OPERATOR IN CONTROLLER MODES
In order to fully understand this section, it is important to first
read the preceding discussion of measurement modes, because
there are only a few differences in operation and connections.
When used in controller applications, the basic objective is to
use the AD8362 as a level-sensing element in such a way that its
output, here VAPC, moves in a direction that increases the
controlled signal when the input sample is too low, and vice
versa. A general scheme is shown in Figure 60.
Every value of VSET maps uniquely to a specific rms value at its
input. Thus, the major loop shown in Figure 60 forces the
system being controlled to deliver exactly this level (which may
be either in voltage form or as a sample of the power output).
This mode of operation is therefore just an extension of the
measurement mode, having exactly the same scaling (slope and
intercept) at the VSET pin.
When the system in Figure 60 is an RF power amplifier (PA), a
practical consideration immediately comes to our attention.
Frequently, the gain (and thus output power) is arranged to
increase in response to an increasing positive voltage applied to
the gain control pin. However, the AD8362’s output tends
toward higher values as its input crosses over the level
corresponding to the setpoint, which would cause the PA’s
output to increase further. In other words, the feedback polarity
is reversed, forcing the control loop to latch up at one of its
power extremes.
CONTROLLED SYSTEM
(OUTPUT POWER
DECREASES AS V
APC
INCREASES)
SYSTEM
OUTPUT
SYSTEM
INPUT
OUTPUT
INPUT
V
APC
R
= 100Ω
SH
V
S
FOR 50Ω
TERMINATION
AD8362
COMM ACOM 16
3.3Ω
1
2
3
4
An increasing number of modular PAs feature a control polarity
that reduces the power output with increases in control voltage.
These can be controlled directly from the VOUT pin of the
AD8362. Elsewhere, it is necessary to provide the sign inversion
using a low noise buffer. This amplifier may also include
provisions to ensure that the PA is never driven beyond its safe
limits. The complete details of such a control system depends
on many factors, and this example shows only generic aspects of
the design.
NC
CHPF
DECL
INHI
VREF 15
VTGT 14
0.1µF
1nF
1nF
VPOS
13
R
1nF
SH
5
6
7
8
INLO
VOUT 12
VSET 11
1nF
1nF
SETPOINT
VOLTAGE INPUT
0.5V TO 3.5V
DECL
PWDN ACOM 10
COMM CLPF
9
C
LPF
Figure 60. Generalized Control Loop Using the AD8362
USE OF AN INPUT BALUN
Because the AD8362 integrates any input error relative to the
setpoint, and ideally would fully null this error over an
appropriate time interval, it follows that VAPC swings rail-
to-rail over a very narrow range of inputs. In practice, a few
millidecibels of amplitude deviation at the input fully swing the
output.
A balun (balance to unbalance) is used either to transform
differential RF signals to single-ended form or in reverse to
convert single-sided signals to differential form. A typical balun
consists of a short length of transmission line (miniature coaxial
or twisted pair) through which the signal passes without
significant degradation, wound on a core (often a ferrite) to
generate a series mode inductor having a high reactive
impedance, compared to the through-mode impedance of the
transmission line, which is often 50 Ω.
The signal input level at which this occurs (the setpoint) is
determined by the control voltage, VSET. This voltage defines
the narrow range of the ac input over which the AD8362’s
output is most sensitive to the absolute input magnitude. In base
stations, for example, VSET is often delivered by the ramp DAC,
and the setpoint is a rapidly varying sequence of levels during
the ramp-up and ramp-down intervals of each burst as well as
with output power demand variations from one channel to
another.
High frequency common-mode voltages applied to the input of
this line are sustained across this series reactance and do not
appear at the loaded side of the line. On the other hand, the
through-mode bandwidth is very high, and the losses incurred
in a short line of this sort are trivial.
Baluns of slightly more elaborate construction can provide an
impedance transformation (usually designated by their
impedance ratio, for example, 4:1, which becomes a 1:4 ratio
when used in reverse) in order to convert a single-sided signal
to the balanced form, as is desirable in driving the AD8362,
while also presenting a 50 Ω input interface.
Rev. B | Page 27 of 36
AD8362
The evaluation board for the AD8362 includes a 1:4 balun,
part number M/A-COM ETC1.6-4-2-3, providing low loss
coupling from 0.5 GHz to 2.5 GHz and an impedance
transformation from the board’s 50 Ω input (at the SMA
connector) to the 200 Ω differential input resistance of the
AD8362. At high frequencies, the actual impedance at the
connector is influenced by reactive aspects of the IC’s input
impedance. Because these can alter the magnitude of the input
voltage, the logarithmic intercept cannot be precisely specified.
However, the shift is temperature stable.
Note that the balun used here increases the signal voltage by the
square root of its impedance ratio of 4:1, in this case by a factor
of 2. The use of a transformer to match the 500 Ω source to the
200 Ω load presented by the AD8362 thus increases the effective
sensitivity of the measurement system by 6 dB, whether
specified in dBV or dBm at the input to the transformer.
Rev. B | Page 28 of 36
AD8362
GENERAL APPLICATIONS
The unusual versatility of the AD8362 opens up many new
possibilities whenever an element having an accurate rms
response is needed. Developed primarily to address the need for
true power measurement in communications systems operating
at frequencies as high as 2.7 GHz, the AD8362 is capable of
meeting the requirements of instrumentation at much lower
frequencies. As noted earlier, the AD8362 is unique in providing
rms-to-dc conversion with a completely constant bandwidth
regardless of signal amplitude and in providing a calibrated
linear-in-dB measurement.
The basic gain of the AD8330 varies from 0 dB to 50 dB. Here it
is raised 8 dB by driving VMAG from the 1.25 V available from
the AD8362, whose 200 Ω loading on the 150 Ω ROUT of the
AD8330 in turn lowers the overall gain by 5 dB. The peak gain
is thus ~53 dB. (Mismatches between the on-chip resistors in
each IC can cause a gain error of up to 1.3 dB.)
Using the AD8330’s inverse gain mode (MODE pin low), its
gain decreases on a slope of 30 mV/dB to a minimum value of
3 dB for a gain voltage (VDBS) of 1.5 V. VDBS is 40% of the
AD8362’s output. Over the 3 V range from 0.5 V to 3.5 V, the
gain of the AD8330 varies by (0.4 × 3 V)/(30 mV/dB), that is,
40 dB. Combined with the 60 dB gain span of the AD8362, this
results in a 100 dB variation for a 3 V change in VOUT. The
overall log slope is therefore 30 mV/dB.
Caution: The applications shown in Figure 61 are provided only
for illustrative purposes and should not be regarded as ready for
immediate incorporation into a user’s system. They have been
validated for the present purpose by simulation studies.
The full gain noise-spectral density at the AD8330’s input is
5 nV/√Hz which is raised (by 53 dB) to 2.2 mV/√Hz at its
output. To realize the full 100 dB potential, the noise at the
AD8362’s input must be much less than 1 mV rms. This
requires limiting the AD8330’s noise bandwidth to ~100 kHz
(when eN = 0.7 mV rms) provided by a single-pole, low-pass
section at the coupling interface, formed by CFLT = 18 nF and
the net differential resistance of 86 Ω (that is, 150 Ω || 200 Ω).
RMS VOLTMETER WITH >100 dB DYNAMIC RANGE
The 60 dB range of the AD8362 can be extended by adding a
standalone VGA as a preamplifier whose gain control input is
derived directly from VOUT. This extends the dynamic range
by the gain control range of this second amplifier. When this
VGA also provides a linear-in-dB (exponential) gain control
function, the overall measurement remains linearly scaled in
decibels. The VGA gain must decrease with an increase in its
gain bias, like the AD8362. It is convenient to select a VGA
needing only a single 5 V supply and capable of generating a
fully balanced differential output. All of these conditions are
met by the AD8330. Figure 61 shows the schematic. The signal
can be applied to the AD8330 in either single-ended or
differential form by using a variety of coupling arrangements
(see the AD8330 data sheet for more information).
5V
3.3Ω
3.3Ω
3.3Ω
AD8362
3.6V
ENBL OFST VPOS CNTR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM ACOM
10µF
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
C
18nF
FLT
VPS1
VPS0
INHI
OPHI
INPUT
(SEE AD8330
DATA SHEET)
3.6V
AD8330
INLO
OPLO
V
OUT
INLO
DECL
MODE
CMOP
PWDN ACOM
COMM CLPF
VDBS CMGN COMM VMAG
10µF
6.04kΩ
402kΩ
ALL UNMARKED CAPACITORS ARE 0.1µF
Figure 61. RMS Voltmeter with >100 dB Dynamic Range
Rev. B | Page 29 of 36
AD8362
If optimized for use at lower frequencies, CFLT should be
increased accordingly; for audio applications, use 0.1 µF. In RF
measurements where the carrier frequency is known, the
coupling and bandwidth limiting between the ICs might be
provided by a narrow-band SAW filter. Figure 62 shows the
output and law conformance error for this AD8330/AD8362
collaboration. The dynamic range extends from 5 µV to 0.5 V
rms between the 0.5 dB error points in this simulation.
For example, a 10:1 change of VTGT from 0.35 V to 3.5 V shifts
the intercept by 20 dB. This has the effect of stretching the
measurement range by the same amount, from >60 dB to more
than 80 dB. So the slope decreases to about 40 mV/dB because a
larger input range is now represented by the same 3.15 V. The
simulation results shown in Figure 64 compare the expanded
range response with that for a fixed VTGT. The upper end of
the measurement range is extended from 1.5 V to over 4 V
(limited by the input protection).
4
3
2
1
4
3
V
= V
OUT
TGT
V
= 1.25V
2
1
TGT
0
3
2
0
15
1
0
10
5
V
= V
OUT
TGT
–1
–2
–3
V
= 1.25V
TGT
0
500m
5µ
50µ
500µ
5m
50m
RMS INPUT VOLTAGE (V)
100µ
1m
10m
0.1
1
10
RMS INPUT VOLTAGE (V)
Figure 62. Output and Conformance for the AD8330/AD8362 Collaboration
Figure 64. Dynamic Range Expansion Using VTGT = VOUT
RF POWER METER WITH 80 DB RANGE
However, it is apparent that the transfer function is no
longer a simple logarithmic law; further consideration shows
that the modified function is nonanalytic. Nevertheless, this
function is dependable, and it remains as stable over supply
and temperature variations as in the normal mode. A good
approximation is provided by
According to simulations, the basic 60 dB measurement range
of the AD8362 can be extended by up to 20 dB by using a target
voltage, VTGT, that increases progressively with the input level.
In the simplest case, this can be achieved by connecting VTGT
to the output VOUT/VSET. Figure 63 shows the connections;
for present purposes, R1 is omitted and R2 is short-circuited.
3
VOUT = VSLP
log10
VIN VZ
−11.3m
log10
VIN
)
(16)
For small signal inputs, VOUT is also small, and the target is
well below the normal 75 mV (with 1.25 V applied to VTGT).
The lower target means that the AD8362’s VGA output does
not have to be as large as normal, which increases the input
sensitivity. As the signal and thus VOUT increases, so does the
target voltage, which progressively shifts the required VGA
input to a higher level.
′
where the modified slope voltage VSLP'' is 0.868 V, that is,
43.4 mV/dB. Using this expression, the dynamic range is 86 dB
to the 0.5 dB error points (0.2 mV ≤ VIN ≤ 4 V). The actual
range is reduced in practice by the effects of the AD8362’s
input-referred noise at low inputs. If the basic 60 dB+ range is
only slightly less than required in a particular application, then
a fraction of VOUT can be summed with a part of VREF to the
VTGT pin, which is why R1 and R2 were included. The output
now conforms in general terms to the formula
AD8362
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMM ACOM
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
R1
R2
3
VOUT =VSLP
log10
VIN VZ
− KC
log10
(
VIN
)
(17)
′
′
V
INLO
DECL
OUT
where the correction factor KC introduces the required
PWDN ACOM
COMM CLPF
nonlinear correction to minimize the law-conformance error.
Table 5 provides several representative spot values using
progressively greater amounts of dynamic range extension.
Figure 63. RF Power Meter with 80 dB Range
Rev. B | Page 30 of 36
AD8362
Table 5. Suggested Values for Use in Scheme of Figure 63
4
3
2
1
R1 (Ω)
R2 (Ω)
VSLP' (V/decade)
VZ' (mV)
0.334
0.336
0.333
0.340
0.355
0.380
KC (m)
11.3
10.4
6.5
O/C
S/C
0.868
1904
1346
872
480
200
96
654
1128
1520
1800
0.870
0.890
0.914
0.942
0
3.7
1.5
0.5
30
20
10
0.972
0
HIGH SLOPE DETECTORS CENTERED ON A
NARROW WINDOW
–10
–20
–30
The situation often arises in system monitoring in which an
input signal varies by much less than 60 dB, and the highest
possible sensitivity and accuracy of measurement is required
within a narrow window of input magnitudes. Adapting the
AD8362 to this task requires that the slope be increased and the
intercept repositioned. Using an attenuator from VOUT to
VSET, any slope >50 mV/dB can be realized. Then, using a
fraction of VREF (or external reference voltage), the particular
region of the dynamic range to be measured can be positioned
wherever desired. In these high slope applications, the full rail-
to-rail output swing of the AD8362 can be exploited.
100µ
1m
10m
0.1
1
10
RMS INPUT VOLTAGE (V)
Figure 66. Illustrative Results for Slope of 100 mV/dB
4
3
2
1
0
30
SLOPE
R1
R2
AD8362
(V/dec)
2
4
5
(kΩ)
4.02
8.66
8.66
9.1
(kΩ)
4.32
3.01
2.15
1.02
20
10
1
2
3
4
5
16
15
14
13
12
11
10
9
COMM ACOM
CHPF
DECL
INHI
VREF
VTGT
VPOS
VOUT
VSET
0
10
–10
–20
–30
V
INLO
DECL
OUT
R1
R2
100µ
1m
10m
0.1
1
10
6
7
8
RMS INPUT VOLTAGE (V)
PWDN ACOM
COMM CLPF
INTERCEPT OFFSET
VOLTAGE, V
Figure 67. Illustrative Results for Slope of 200 mV/dB
SHIFT
Figure 65. Slope and Intercept Adjustment
4
3
2
1
Figure 65 shows the basic connections for this mode of use; the
intercept repositioning voltage VSHIFT can be introduced by
adding a third resistor from VREF to VSET with recalculated
values of R1 and R2 or by using an external voltage source.
Figure 66 presents the simulation results for a log slope of
100 mV/dB (2 V/dec) covering two-decade spans over several
sub-ranges, while Figure 67 shows the results for a slope of
200 mV/dB (4 V/dec), providing just a one-decade span.
0
30
20
10
0
To accurately reposition the range (intercept) when very high
slopes are used, a low output impedance DAC can be used to
provide VSHIFT. Figure 68 shows simulated results for a slope of
500 mV/dB (10 V/dec) presuming this configuration. In all
cases, the fixed-pattern ripple in the log conformance remains
unchanged in dB terms. Residual fluctuations due to insufficient
averaging (in low frequency applications) are likewise
unaffected in their equivalent decibel value, though greater in
absolute voltage terms.
–10
–20
–30
100µ
1m
10m
0.1
1
10
RMS INPUT VOLTAGE (V)
Figure 68. Illustrative Results for Slope of 10 mV/dec
Rev. B | Page 31 of 36
AD8362
AD8362 EVALUATION BOARD
The AD8362 evaluation board provides for a number of
different operating modes and configurations, including many
of those described in this data sheet. The measurement mode is
set up by positioning SW2 as shown in Figure 69. The AD8362
can be operated in controller mode by flipping SW2 to its
alternate position, thereby connecting the VSET pin to the
VSET connector and applying the setpoint voltage to the VSET
connector.
In measurement mode, the slope of the response at VOUT may
be increased through the use of a voltage divider implemented
with the appropriately valued resistors, as explained in this data
sheet, in Positions R17 and R9, and with SW2 switched to its
alternate position.
The AD8362 is powered up with SW3 in the position shown in
Figure 69 and connector PWDN open. The part can be powered
down either by connecting a logic high voltage to connector
PWDN with SW3 in the position shown in Figure 69 or by
switching SW3 to its alternate position.
The internal voltage reference is used for the target voltage
when SW1 is in the position shown in Figure 69. This voltage
may optionally be reduced via a voltage divider implemented
with R4 and R5, with LK1 in place as shown in Figure 69 and
SW1 switched to its alternate position. Alternatively, an external
target voltage may be used with SW1 switched to its alternate
position, LK1 removed, and the external target voltage applied
to the VTGT connector.
Balun Transformer T1 may be removed and replaced by two
capacitors and an inductor, as shown in Figure 54, or by two 0 Ω
resistors (links, size 0402): one in series with Capacitors C6 and
C10, and the other in series with C5 and a 100 Ω resistor installed
in Position R16, to implement the circuit shown in Figure 53.
R1
0Ω
AGND
VPOS
C1
0.1µF
C2
100pF
R14
OPEN
R15
0Ω
AD8362
1
2
3
4
5
6
7
8
COMM
ACOM
16
15
R4
0Ω
C8
1000pF
C7
1000pF
VREF
CHPF
DECL
INHI
VREF
R5
10kΩ
C10
1000pF
C6
100pF
VTGT 14
VPOS
LK1
SW1
T1
R6
0Ω
RFIN
13
VTGT
VOUT
R16
OPEN
INLO
VOUT 12
VSET 11
R8
R17
R7
0Ω
C5
100pF
0Ω
OPEN
DECL
PWDN
COMM
SW2
R9
10kΩ
C4
1000pF
ACOM
CLPF
10
9
VSET
C3
0.1µF
SW3
PDWN
R10
R13
10kΩ
0Ω
C9
OPEN
Figure 69. Evaluation Board Schematic
Rev. B | Page 32 of 36
AD8362
Figure 70. Component Side Metal of Evaluation Board
Figure 71. Component Side Silkscreen of Evaluation Board
Table 6. Evaluation Board Configuration Options
Component
Function
Part Number
Default Value
T1
C1
C2
C3
C9
M/A-COM ETC1.6-4-2-3
Supply filtering/decoupling capacitor
Supply filtering/decoupling capacitor
Output low-pass filter capacitor
Output low-pass filter capacitor
(normally omitted, not installed)
0.1 µF
100 pF
0.1 µF
C4, C7, C10
C5, C6
C8
DUT
Input bias-point decoupling capacitors
Input signal coupling capacitors
Input high-pass filter capacitor
AD8362
1000 pF
100 pF
1000 pF
AD8362ARU
R1, R4, R6, R7, R8, R10, R15
Jumpers
0 Ω
R5, R9, R13
R16
R17
RA
RB
Optional pull-down resistors
Not installed, see text
Slope adjustment (not installed, see text)
Not installed, see text
10 kΩ
100 Ω
(See text)
25 Ωor 0 Ω
33 Ω
Not installed, see text
RC
Not installed, see text
0 Ω
SW1
SW2
SW3
Internal/external target voltage selector
Measurement mode/controller mode selector
Power-down/enable or external power-down selector
Rev. B | Page 33 of 36
AD8362
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 72. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8362ARU
AD8362ARU-REEL7
AD8362ARUZ1
AD8362ARUZ-REEL71
AD8362-EVAL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RU-16
RU-16
RU-16
RU-16
16-Lead TSSOP, Tube
16-Lead TSSOP, 7" Tape and Reel
16-Lead TSSOP, Tube
16-Lead TSSOP, 7" Tape and Reel
Evaluation Board
1 Z = Pb-free part.
Rev. B | Page 34 of 36
AD8362
NOTES
Rev. B | Page 35 of 36
AD8362
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02923–0–3/04(B)
Rev. B | Page 36 of 36
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