AD8366-EVALZ [ADI]
DC to 500 MHz, Dual Digital Gain Trim Amplifier; DC至500 MHz的双通道数字增益调整放大器
| 型号： | AD8366-EVALZ |
| 厂家： | 
ADI |
| 描述： | DC to 500 MHz, Dual Digital Gain Trim Amplifier |
| 文件： | 总13页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DC to 500 MHz,
Dual Digital Gain Trim Amplifier
AD8366
Preliminary Technical Data
FEATURES
Matched Pair of Differential Digitally-Controlled VGAs
Gain Range: 4.5 dB to 20.5 dB
Step 0.25 dB
FUNCTIONAL BLOCK DIAGRAM
Ch. A Data Enable
Ch. B Data Enable
Operating frequency
DC to 500MHz
800MHz 3-dB bandwidth
AD8366
NF 10.5 dB @ max. gain, 18dB @ min. gain at 10MHz
OIP3 36dBVrms at 10MHz
IAN
OAN
OAP
DC OFFSET
HD2, HD3 > 88dBc for 2Vpp output at 10MHz at max gain
Differential Input and Output
Adjustable output common-mode
Optional DC output offset correction
Serial/Parallel Port Programmable
Power-down Feature
CANCELLATION
IAP
VCMA
VCMB
IBP
OBP
OBN
Single 5V Supply Operation
DC OFFSET
CANCELLATION
IBN
APPLICATIONS
Baseband I/Q receivers
Diversity receivers
ADC drivers
CHANNEL
GAIN
CONTROL
W-CDMA/CDMA/CDMA2000/GSM
Point-to-(Multi)Point Radio
CATV
Wireless local loop
WiMax
B0 B1 B2 B3 B4 B5
Serial /
Parallel
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD8366 is a matched pair of fully differential low-noise
and low-distortion digitally programmable variable gain
amplifiers. The gain of each amplifier can be programmed
separately or simultaneously over a range of 5 dB to 21 dB in
steps of 0.25 dB. The amplifier offers flat frequency
performance and group delay from DC out to 150 MHz,
independent of gain code.
The output common-mode defaults to Vps/2 but can be
programmed via pins VCMA and VCMB over a range of
voltages. The built-in DC-offset compensation loop can be
disabled if DC-coupled operation is desired. The high-pass
corner is defined by external capacitors on pins OFSA and
OFSB. The input common mode also defaults to Vps/2 but can
be driven from 1.2V to 3.4V.
The AD8366 offers excellent spurious-free dynamic range,
suitable for driving 12-bit ADCs. The NF at max gain is 10.5 dB
at 10 MHz and increases 2dB for every 4dB decrease in gain.
Over the entire gain range, the HD3 and HD2 are >88dBc for
2 V p-p at the output at 10 MHz into 500 Ω. The 2-tone
intermodulation distortion of -90dBc into 200 Ω translates to
an OIP3 of 43 dBm. The differential input impedance is 200 ꢀ
to provide a well-defined termination. The differential output is
voltage-mode with a low impedance of 30 ꢀ.
The digital interface allows for parallel or serial gain
programming. The AD8366 operates off a 4.5V to 5.5V supply
and consumes a supply current of 175mA. When disabled, it
consumes ~ 4mA. The AD8366 is fabricated using Analog
Devices’ advanced Silicon-Germanium bipolar process and is
available in a 32-lead exposed paddle LFCSP package.
Performance is specified over a -40oC to +85oC temperature
range.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD8366
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
APPLICATIONS SCHEMATIC......................................................8
Parallel and SERIAL Interface timing.............................................9
Outline Dimensions....................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
10/07—Revision PrA: Initial Version
02/08—Revision PrB: Updated Performance Specifications
06/08—Revision PrC: Evaluation Board Section
Rev. PrC | Page 2 of 13
Preliminary Technical Data
AD8366
SPECIFICATIONS
VS. = 5 V, TA = 25°C, Zs = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
Bandwidth
3dB; all gain codes
1dB; all gain codes
Max. Gain
MHz
MHz
V/ns
V/ns
1000
250
TBD
TBD
Slew Rate
Min. Gain
INPUT STAGE
IPPA, IPMA, IPPB, IPMB
At minimum gain Av=4.5dB
Maximum Input Swing
Differential Input Impedance
Input Common Mode Range
3.2
200
Vp-p
Ώ
1Vp-p Input
TBD
4.5
TBD
V
Input pins left floating
Vps/2
GAIN
Voltage Gain Range
Gain Step Size
0.1dB Gain Flatness
Mismatch
20.5 dB
dB
All gain codes
Max. Gain
Channels A and B at same gain code
0.25
150
+/-
MHz
dB
0.05dB
Group Delay Flatness
Mismatch
Gain Step Response
All gain codes, 20% frac. bandwidth, fc<100MHz
Channels A and B at same gain code
Max. gain to Min. gain
<0.5
2
TBD
TBD
TBD
ns
ps
ns
ns
dB
Min. gain to Max gain
Common-mode Rejection Ratio
OUTPUT STAGE
Maximum Output Swing
Differential Output Impedance
Output DC offset
OPPA, OPMA, OPPB, OPMB, VCMA, VCMB
At maximum gain, Av=20.5dB
6
30
TBD
Vp-p
Ώ
mV
V
Inputs Shorted, offset loop disabled
1Vp-p output
-15
1.2
-4
3.4
Output Common Mode Range
VCMA and VCMB left floating
Vps/2
4
V
kΏ
Common-Mode Setpoint Input
Impedance
NOISE/DISTORTION
10 MHz
Noise Figure
Max Gain
Min Gain
10.5
18
88
88
92
85
36
35
7
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
2nd Harmonic
2 Vp-p output, Max Gain, ZL=500Ώ
2 Vp-p output, Min Gain, ZL=500Ώ
2 Vp-p output, Max Gain, ZL=500Ώ
2 Vp-p output, Min Gain, ZL=500Ώ
2 V p-p composite, Max. Gain, ZL=200Ώ
2 V p-p composite, Min. Gain, ZL= 200Ώ
Max. gain, ZL=500Ώ
3rd Harmonic
OIP3
Output 1 dB Compression Point
Min. Gain, ZL=500Ώ
6.9
50 MHz
Noise Figure
Max Gain
Min Gain
2 Vp-p output , Max Gain
Min Gain
2 V p-p output, Max Gain
Min Gain
11.2
18.5
TBD
TBD
TBD
TBD
dB
dB
dBc
dBc
dBc
dBc
2nd Harmonic
3rd Harmonic
Rev. PrC | Page 3 of 13
AD8366
Preliminary Technical Data
OIP3
2 V p-p composite, Max. Gain, ZL=500Ώ
2 V p-p composite, Min. Gain, ZL=500Ώ
Max. gain, ZL=500Ώ
34.2
30.7
6.7
dBVrms
dBVrms
dBVrms
dBVrms
Output 1 dB Compression Point
Min. Gain, ZL=500Ώ
7.2
100 MHz
Noise Figure
Max Gain
Min Gain
2 Vp-p output , Max Gain
Min Gain
2 Vp-p output, Max Gain
Min Gain
2Vp-p composite, Max. Gain @ 500 Load impedance
Min. Gain
11.84
18.8
TBD
TBD
TBD
TBD
29.5
21
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
2nd Harmonic
3rd Harmonic
OIP3
Output 1 dB Compression Point
Max. gain
Min. Gain
4
6
DIGITAL LOGIC
SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
VINH, Input High Voltage
VINL, Input Low Voltage
TBD
V
V
TBD
IINH/IINL, Input Current
CIN, Input Capacitance
TBD μA
TBD pF
SPI INTERFACE TIMING
SENB = HIGH
fSCLK
TBD MHz
t1
t2
t3
t4
t5
t6
CS rising edge to first SCLK rising edge
SCLK high pulse width
SCLK low pulse width
SDAT setup time
SDAT hold time
SCLK falling edge to CS low
SENB = LOW
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
PARALLEL PORT TIMING
t7
t8
t9
t10
DENA/B high pulse width
DENA/B low pulse width
BIT[0-5] setup time
TBD
TBD
TBD
TBD
ns
ns
ns
ns
BIT[0-5] hold time
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
VPSI, VPSO, ICOM, OCOM, ENBL
4.5
5.5
V
ENBL = 5V
ENBL = 0V
180
3.2
TBD
TBD
mA
mA
V
Delay following high-to-low transition until device
meets full specifications
ns
Disable Response Time
Delay following low-to-high transition until device
produces full attenuation
TBD
ns
Rev. PrC | Page 4 of 13
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
AD8366
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
5.5 V
Supply Voltages VPSI, VPSO
ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2,
BIT3, BIT4, BIT5
TBD V
IPPA, IPMA, IPPB, IPMB
TBD V
OPPA, OPMA, OPPB, OPMB
OFSA, OFSB
TBD V
TBD V
DECA, DECB, VCMA, VCMB, CCMA, CCMB
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
TBD V
ESD CAUTION
TBD mW
TBD°C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Rev. PrC | Page 5 of 13
AD8366
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BIT0/CS
VPSIA 1
24
23
22
21
20
19
18
2
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
3
4
5
6
7
AD8366
TOP VIEW
BIT5
VPSIB 8
17 DENA
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8, 13, 28
VPSIA, VPSIB,
Input and Output Stage Positive Supply Voltage. 4.5 V − 5.5 V.
VPSOA, VPSOB
2, 3, 6, 7
IPPA, IPMA,
IPPB, IPMB
Differential Inputs
4
ENBL
Chip Enable. Pull high to enable.
5, 20
ICOM, OCOM
Input and Output Stage Common. Connect via lowest possible impedance to external circuit
common
9, 32
10, 31
DECA, DECB
OFSA, OFSB
Vpos/2 Reference Output Decoupling. Connect decoupling capacitor to circuit common.
Output Offset Correction Loop Compensation. Connect capacitor to circuit common. Tie to
common to disable.
11, 30
12, 29
14, 15, 26, 27
CCMA, CCMB
VCMB, VCMA
OPPB, OPMB,
OPMA, OPPA
Output Common-mode Centering Loop Compensation. Connect capacitor to circuit common
Output Common-mode Setpoint. Defaults to Vpos/2 if left open
Differential Outputs
16, 17
DENB, DENA
Data enable . Pull high to address each or both channels for parallel load. Not used in serial mode.
18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3,
BIT2, BIT1, BIT0
Parallel data path for SENB pulled low. For SENB pulled high, BIT0 becomes a chip-select (CS), BIT1
becomes serial data input, SDAT, and BIT2 becomes serial clock, SCLK. BIT3-BIT5 are not used in
the serial mode
25
SENB
Serial interface enable. Pull high for serial; pull low for parallel.
Rev. PrC | Page 6 of 13
Preliminary Technical Data
AD8366
TYPICAL PERFORMANCE CHARACTERISTICS
1
0.75
0.5
50MHz
10MHz
0.25
0
-0.25
-0.5
-0.75
-1
100MHz
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Gaincodes
Figure 6. Gain Error vs. Ideal Gain Codes at 10MHz, 50MHz and 100MHz
Figure 3. Gain vs. Frequency for Multiple Gain Codes
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-0.1
-0.2
-0.3
-0.4
-0.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
16.5
17.5
18.5
19.5
20.5
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Ideal Gain (dB)
Ideal Gain (dB)
Figure 4. IQ Gain Mismatch at 10 MHz vs. Ideal Gain
Figure 7. IQ Phase Mismatch at 10 MHz vs. Ideal Gain
10.00
8.00
22.00
21.00
20.00
19.00
18.00
17.00
16.00
15.00
14.00
13.00
12.00
11.00
10.00
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
OIP2
6.00
NF
4.00
2.00
OIP3
0.00
-2.00
-4.00
-6.00
-8.00
-10.00
6
4
2
0
4
6
8
10
12
14
16
18
20
22
-21.00
-19.00
-17.00
-15.00
-13.00
-11.00
-9.00
)
-7.00
-5.00
-3.00
-1.00
Gain (dB)
Input (dBVRMS
Figure 5.O IP2,OIP3 and NF vs. Gain at 10 MHz
Figure 8. Gain & Output Swing vs. Input Power at Max Gain Setting at
10MHz
Rev. PrC | Page 7 of 13
AD8366
Preliminary Technical Data
APPLICATIONS SCHEMATIC
VPOS
0ꢀ
0.01µF
VPOS
0.01µF
10kꢀ
0.1µF
0ꢀ
VPOS
C
OFS
1000pF
Vin
0.01µF
DECA
VPSIA
CCMA
OFSA
VPSOA OPMA
VCMA
SENB
BIT0
OPPA
BIT1
BIT2
BIT3
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
VPOS
AD8366
OCOM
BIT4
BIT5
DENA
DENB
VCMB
CCMB
OPPB
OFSB
DECB
VPSOB
OPMB
Vin
OFS 1000pF
0ꢀ
VPOS
C
0.01µF
10kꢀ
0.01µF
0.01µF
0.1µF
0ꢀ
VPOS
Figure 9 Applications Schematic with Basic Connections
Rev. PrC | Page 8 of 13
Preliminary Technical Data
EVALUATION BOARD
AD8366
Figure 10. Evaluation Board Schematic
Rev. PrC | Page 9 of 13
AD8366
Preliminary Technical Data
Table 4. Evaluation Board Configuration Options
Components
Function
Default Conditions
C1, C13 to C16, R3 to R6
C1 = 0.1μF (size 0603)
Power Supply Decoupling. Nominal supply decoupling consists a
0.1μF capacitor to ground followed by 0.01 μF capacitors to ground
positioned as close to the device as possible.
C13 to C16 = 0.01 μF (size 0402)
R3 to R6 = 0 Ω (size 0603)
T1, T2, C5,C18,C20,C21,
R12 to R21, R44 to R48,
R50, R54, R58, R62, R63
Input Interface. The default configuration of the Eval board is for
single ended operation. T1 and T2 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 200 Ω-balanced
differential signal. R12 to R14 and R15, R16, and R19 are populated
for appropriate balun interface. R44 to R48 and R50, R54, R58, R62,
andR63 are provided for generic placement of matching
components. C5 to C20 are balun decoupling capacitors.
R17, R18, R20, R21 can be populated with 0 Ω and the balun
interfacing resistors can be removed to bypass T1 and T2 for
differential interfacing.
T1, T2 = ADT4-6T+ (Mini-Circuits)
C5,C20 = 0.1 μF (size 0402)
C18,C21 = Do not install
R12 to R16, R19, R44 to R47= 0 Ω (size
0402)
R17, R18, R20, R21,R48, R50, R54, R58,
R62, andR63 = open (size 0402)
T3, T4, C24 to C27,
R29 to R31,R33 to
R39,R65,R67 to R74, R80
Output Interface. The default configuration of the Eval board is for
single ended operation. T3 and T4 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended output into a 200 Ω-balanced
differential load. R29 to R31, R33, R38, R39 are populated for
appropriate balun interface. R65, R67 to R74, and R80 are provided
for generic placement of matching components. C24, C25 are balun
decoupling capacitors.
R34 to R37 can be populated with 0 Ω and the balun interfacing
resistors can be removed to bypass T3 and T4 for differential
interfacing.
T3, T4 = ADT4-6T+ (Mini-Circuits)
C24,C25 = 0.1 μF (size 0402)
C26,C27 = Do not install
R29 to R31, R33, R38, R39, R65, R67,
R68, R80 = 0 Ω (size 0402)
R34 to R37, R69 to R74= open (size
0402)
S1, S5, S7, R53, R57, R79,
C29, C30, C31
Enable Interface.
S1,S5,S7 = installed
R53, R57= 5.1kΩ (size 0603)
R79 = 10kΩ (size 0402)
C30=0.01uF (size 0402)
C29, C31=1500pF (size 0402)
-Device Enable. The AD8366 is enabled by applying a logic high
voltage to the ENBL pin. The device is enabled when the switch S1 is
set in the down position (HIGH), connecting the ENBL pin to VPOS.
-Data Enable. DENA and DENB are used to enable the data path for
Channel A and Channel B respectively. Channel A is enabled when
the switch S5 is set in the down position (HIGH), connecting the
DENA pin to VPOS. Likewise, Channel B is enabled when the switch
S7 is set in the down position (HIGH), connecting the DENB pin to
VPOS. Both channels are disabled by setting the switches to the up
position, connecting the DENA and DENB pins to GND.
S2,S3,S4,S6,S8,S9, S10
R26, R32, R40-R43,
R61,R64
C23, C33
U1
Serial/Parallel Interface Control. SENB is used to set the data
control either in parallel or serial mode. Parallel Interface is enabled
when the switch S4 is up position (LOW). Serial interface enabled
when S4 is in the down position (HIGH).
For SENB pulled LOW,
S2,S3,S4, S6, S8, S9, 10 = installed
R26=698 kΩ (size 0603)
R32, R40-R43, R61,R64 = 5.1kΩ (size
0603)
C23, C33 = 1500pF (size 0603)
U1= SN74LVC2G14, Clock Chip
BIT0 (switch S9) sets 0.25dB Gain
BIT1 (switch S2) sets 0.5dB Gain
BIT2 (switch S3) sets 1dB Gain
BIT3 (switch S6)sets 2dB Gain
BIT4 (switch S8)sets 4dB Gain
BIT5 (switch S10) sets 8dB Gain
For SENB pulled HIGH, BIT0 becomes a chip-select (CS), BIT1
becomes serial data input, SDAT, and BIT2 becomes serial clock,
SCLK. BIT3-BIT5 are not used in the serial mode.
S11, S12, C9, C10
S11, S12 = installed
C9, C10=8200pF (size 0402)
DC Offset Correction Loop Compensation. The DC offset
correction loop is enabled (HIGH) with switch S11 and S12 for
channel A and channel B respectively. When enabled, the capacitor
is connected to circuit common. When disabled (LOW), the
OFSA/OFSB pins are tied to common.
Rev. PrC | Page 10 of 13
Preliminary Technical Data
AD8366
R10, R22, R24, R28, C22,
C28
Output Common-mode Setpoint. The output common mode on
R10, R24= 10 kΩ Potentiometers
R22, R28= 0Ω
channels A and B can be set externally when applied to the VCMA
and VCMB. The resistive change thorough the potentiometer sets a
variable VCMA voltage. If left open, the output common mode
defaults to Vpos/2.
C2, C3, C11, C12
C4, C17
Vpos/2 Reference Output Decoupling Capacitor to circuit common.
C2, C3= 0.1μF (size 0402)
C11, C12= 0.01μF (size 0402)
C4, C17= 1 nF (size 0402)
Output Common-mode Centering Loop Compensation. Connect
capacitor to circuit common
Rev. PrC | Page 11 of 13
AD8366
Preliminary Technical Data
PARALLEL AND SERIAL INTERFACE TIMING
1
CS
t0
0
t2
t1
t3
1
t4
SCLK
0
1
0
B-LSB
A-LSB
A-MSB
B-MSB
SDATA
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE.
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL LATCHES
ON LE FALLING EDGE.
1
0
SENB
Figure 11. SPI Port Timing Diagram
1
0
GAIN A/B
X
X
X
BIT[0-6]
DENA
X
GAIN A
GAIN B
t0
t1
1
0
t2
t3
1
0
DENB
SENB
1
0
PROGRAM A ONLY
PROGRAM A AND B
PROGRAM B ONLY
Figure 12. Parallel Port Timing Diagram
Rev. PrC | Page 12 of 13
Preliminary Technical Data
OUTLINE DIMENSIONS
AD8366
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 x 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
5.00
0.60 MAX
BSC SQ
0.60 MAX
0.50
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
EXPOSED
PAD
(BOTTOM VIEW)
3.65
BSC
TOP
VIEW
4.75
BSC SQ
3.50 SQ
3.35
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 13. Outline Dimensions.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8366-EVALZ
Evaluation Board
Rev. PrC | Page 13 of 13
PR07584-0-6/08(PrC)
相关型号：
©2020 ICPDF网 联系我们和版权申明