AD8369_17 [ADI]
45 dB Digitally Controlled VGA;
| 型号： | AD8369_17 |
| 厂家： | 
ADI |
| 描述： | 45 dB Digitally Controlled VGA |
| 文件： | 总24页 (文件大小：856K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
45 dB Digitally Controlled VGA
LF to 600 MHz
AD8369
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Digitally Controlled Variable Gain in 3 dB Steps
–5 dB to +40 dB (RL = 1 k⍀)
BIT3 BIT2 BIT1 BIT0
–10 dB to +35 dB (RL = 200 ⍀)
Less than 0.2 dB Flatness over a +20 MHz Bandwidth
up to 380 MHz
VPOS
BIAS
PWUP
3dB STEP
DENB
SENB
GAIN CODE DECODE
4-Bit Parallel or 3-Wire Serial Interface
Differential 200 ⍀ Input and Output Impedance
Single 3.0 V–5.5 V Supply
FILT
OPHI
OPLO
Gm CELLS
Draws 37 mA at 5 V
Power-Down <1 mA Maximum
APPLICATIONS
INHI
Cellular/PCS Base Stations
IF Sampling Receivers
Fixed Wireless Access
Wireline Modems
CMDC
COMM
INLO
Instrumentation
COMM
PRODUCT DESCRIPTION
OPHI and OPLO. The overall gain depends upon the source
and load impedances due to the resistive nature of the input and
output ports.
The AD8369 is a high performance digitally controlled variable
gain amplifier (VGA) for use from low frequencies to a –3 dB
frequency of 600 MHz at all gain codes. The AD8369 delivers
excellent distortion performance: the two-tone, third-order
intermodulation distortion is –69 dBc at 70 MHz for a 1 V p-p
composite output into a 1 kW load. The AD8369 has a nominal
noise figure of 7 dB when at maximum gain, then increases with
decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a
1 kW load and remains fairly constant over the gain range.
Digital control of the AD8369 is achieved using either a serial or
a parallel interface. The mode of digital control is selected by
connecting a single pin (SENB) to ground or the positive sup-
ply. Digital control pins can be driven with standard CMOS
logic levels.
The AD8369 may be powered on or off by a logic level applied
to the PWUP pin. For a logic high, the chip powers up rapidly
to its nominal quiescent current of 37 mA at 25ºC. When low,
the total dissipation drops to less than a few milliwatts.
The signal input is applied to pins INHI and INLO. Variable gain
is achieved via two methods. The 6 dB gain steps are implemented
using a discrete X-AMP® structure, in which the input signal is
The AD8369 is fabricated on an Analog Devices proprietary, high
performance 25 GHz silicon bipolar IC process and is available
in a 16-lead TSSOP package for the industrial temperature range
of –40rC to +85rC. A populated evaluation board is available.
progressively attenuated by a 200 W R-2R ladder network that
also sets the input impedance; the 3 dB steps are implemented at
the output of the amplifier. This combination provides very
accurate 3 dB gain steps over a span of 45 dB. The output imped-
ance is set by on-chip resistors across the differential output pins,
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8369–SPECIFICATIONS (V = 5 V, T = 25؇C, R = 200 ⍀, R = 1000 ⍀, Frequency = 70 MHz, at maximum gain,
unless otherwise noted.)
S
S
L
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
3 dB Bandwidth
LF*
600
MHz
GAIN CONTROL INTERFACE
Voltage Gain Span
Maximum Gain
Minimum Gain
Gain Step Size
45
40
–5
3
dB
dB
dB
dB
dB
ns
All bits high (1 1 1 1)
All bits low (0 0 0 0)
Gain Step Accuracy
Gain Step Response Time
Over entire gain range, with respect to 3 dB step
Step = 3 dB, settling to 10% of final value
±0.05
30
INPUT STAGE
Input Resistance
From INHI to INLO
From INHI to COMM, from INLO to COMM
From INHI to INLO
200
100
0.1
1.1
2
W
W
Input Capacitance
pF
pF
From INHI to COMM, from INLO to COMM
Input Noise Spectral Density
Input Common-Mode DC Voltage Measured at pin CMDC
Maximum Linear Input
nV/÷Hz
1.7
2.2
V
V
|VINHI – VINLO| at Minimum Gain
OUTPUT STAGE
Output Resistance
From OPHI to OPLO
From OPHI to COMM, from OPLO to COMM
From OPHI to OPLO
From OPHI to COMM, from OPLO to COMM
No input signal
Output step = 1 V
200
100
0.25
1.5
VS/2
1200
W
W
Output Capacitance
pF
pF
V
V/ms
Common-Mode DC Voltage
Slew Rate
POWER INTERFACE
Supply Voltage
Quiescent Current
vs. Temperature
Disable Current
vs. Temperature
3.0
2.2
5.5
42
52
750
1
V
PWUP high
37
mA
mA
mA
mA
–40rC £ TA £ 85rC
PWUP low
400
–40rC £ TA £ 85rC
Pin PWUP
POWER UP INTERFACE
Enable Threshold
Disable Threshold
Response Time
1.0
V
V
ms
Time delay following low to high transition
on PWUP until output settles to within 10%
of final value
7
Input Bias Current
PWUP = 5 V
160
mA
DIGITAL INTERFACE
Pins SENB, BIT0, BIT1, BIT2, BIT3,
and DENB
Low Condition
High Condition
Input Bias Current
2.0
V
V
mA
3.0
Low input
150
Frequency = 10 MHz
Voltage Gain
Gain Flatness
Noise Figure
40.5
+0.05*
7.0
dB
dB
dB
Within ±10 MHz of 10 MHz
Output IP3
f1 = 9.945 MHz, f2 = 10.550 MHz
+22
+22
dBV rms
dBm
IMD3
f1 = 9.945 MHz, f2 = 10.550 MHz
V
OPHI – VOPLO = 1 V p-p composite
–74
–72
–71
+3
dBc
dBc
dBc
dBV rms
dBm
Harmonic Distortion
P1dB
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
+3
*The low frequency high-pass corner is determined by the capacitor on pin FILT, CFILT. See the Theory of Operation section for details.
REV. A
–2–
AD8369
SPECIFICATIONS (Continued)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency = 70 MHz
Voltage Gain
40.5
±0.1
7.0
dB
dB
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 70 MHz
Output IP3
f1 = 69.3 MHz, f2 = 70.7 MHz
+19.5
+19.5
dBV rms
dBm
IMD3
f1 = 69.3 MHz, f2 = 70.7 MHz
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–69
–68
–64
+3
dBc
dBc
dBc
dBV rms
dBm
Harmonic Distortion
P1dB
+3
Frequency = 140 MHz
Voltage Gain
40.0
±0.10
7.0
dB
dB
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 140 MHz
Output IP3
f1 = 139.55 MHz, f2 = 140.45 MHz
+17
+17
dBV rms
dBm
IMD3
f1 = 139.55 MHz, f2 = 140.45 MHz
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–64
–63
–55
+3
dBc
dBc
dBc
dBV rms
dBm
Harmonic Distortion
P1dB
+3
Frequency = 190 MHz
Voltage Gain
39.7
±0.1
7.2
dB
dB
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 190 MHz
Output IP3
f1 = 189.55 MHz, f2 = 190.45 MHz
+15.5
+15.5
dBV rms
dBm
IMD3
f1 = 189.55 MHz, f2 = 190.45 MHz
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–61
–57
–51
+2
dBc
dBc
dBc
dBV rms
dBm
Harmonic Distortion
P1dB
+2
Frequency = 240 MHz
Voltage Gain
39.3
±0.1
7.2
dB
dB
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 240 MHz
Output IP3
f1 = 239.55 MHz, f2 = 240.45 MHz
+14
+14
dBV rms
dBm
IMD3
f1 = 239.55 MHz, f2 = 240.45 MHz
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–58
dBc
Harmonic Distortion
P1dB
–50
dBc
–49
dBc
+1.5
+1.5
dBV rms
dBm
Frequency = 320 MHz
Voltage Gain
39.0
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 320 MHz
±0.15
dB
dB
7.4
Output IP3
f1 = 319.55 MHz, f2 = 320.45 MHz
+11.5
+11.5
dBV rms
dBm
IMD3
f1 = 319.55 MHz, f2 = 320.45 MHz
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–53
dBc
Harmonic Distortion
P1dB
–47
dBc
–49
dBc
+1.0
+1.0
dBV rms
dBm
REV. A
–3–
AD8369
SPECIFICATIONS (Continued)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency = 380 MHz
Voltage Gain
38.5
±0.15
7.8
dB
dB
dB
Gain Flatness
Noise Figure
Within ±20 MHz of 380 MHz
Output IP3
f1 = 379.55 MHz, f2 = 380.45 MHz
+8.5
+8.5
dBV rms
dBm
IMD3
f1 = 379.55 MHz, f2 = 380.45 MHz,
V
OPHI – VOPLO = 1 V p-p composite
–47
dBc
Harmonic Distortion
P1dB
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ±1 dB deviation from linear gain
–45
–49
+0.5
+0.5
dBc
dBc
dBV rms
dBm
Specifications subject to change without notice.
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25
rC)
Parameter
Typ
Unit
Minimum Clock Pulsewidth (TPW
Minimum Clock Period (TCK
Minimum Setup Time Data vs. Clock (TDS
Minimum Setup Time Data Enable vs. Clock (TES)
Minimum Hold Time Clock vs. Data Enable (TEH
Minimum Hold Time Data vs. Clock (TDH
)
10
20
2
2
2
ns
ns
ns
ns
ns
ns
)
)
)
)
4
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25
rC)
Parameter
Typ
Unit
Minimum Setup Time Data Enable vs. Data (TES)
Minimum Hold Time Data Enable vs. Data (TEH
2
2
4
ns
ns
ns
)
MSB
(BIT3)
Minimum Data Enable Width (TPW
)
MSB–1
(BIT2)
T
T
DH
DS
DATA
(BIT 0)
MSB
MSB–1
MSB–2
LSB
MSB–2
(BIT1)
T
PW
T
CK
LSB
(BIT0)
CLOCK
(BIT 1)
T
T
T
PW
ES
EH
T
T
EH
ES
DATA
ENABLE DISABLED
(DENB)
CLOCK
CLOCK
DISABLED
DENB
CLOCK
ENABLED
DATA IS LATCHED ON HIGH-TO-LOW
TRANSITION OF DENB
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
(NOT TO SCALE)
(NOT TO SCALE)
Serial Programming Timing
Parallel Programming Timing
REV. A
–4–
AD8369
ABSOLUTE MAXIMUM RATINGS*
Table I. Typical Voltage Gain vs. Gain Code (VS = 5 V, f = 70 MHz)
Supply Voltage VS, VPOS . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
PWUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS + 200 mV
BIT0, BIT1, BIT2, BIT3, DENB, SENB . . . . . . VS + 200 mV
Input Voltage, VINHI – VINLO . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Input Voltage, VINHI or VINLO with respect to COMM . . 4.5 V
Input Voltage, VINHI – VINLO with respect to COMM
Typical
Gain (dB) Gain (dB)
Code BIT3 BIT2 BIT1 BIT0 RL = 1 k⍀ RL = 200 ⍀
Typical
Gain
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–5
–2
1
–10
–7
–4
–1
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMM – 200 mV
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 265 mW
2
3
4
121.48°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
4
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125rC
Operating Temperature Range . . . . . . . . . . . . –40rC to +85rC
Storage Temperature Range . . . . . . . . . . . . . –65rC to +150rC
Lead Temperature Range (soldering 60 sec) . . . . . . . to 300rC
5
6
7
8
10
13
16
19
22
25
28
31
34
37
40
5
8
11
14
17
20
23
26
29
32
35
9
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
10
11
12
13
14
15
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8369 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. A
–5–
AD8369
PIN CONFIGURATION
INLO
COMM
BIT0
1
2
3
4
5
6
7
8
16 INHI
15 COMM
14 PWUP
13 VPOS
12 SENB
11 FILT
AD8369
TOPVIEW
(NotTo Scale)
BIT1
BIT2
BIT3
DENB
OPLO
10 CMDC
9
OPHI
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1
2
INLO
COMM
BIT0
Balanced Differential Input. Internally biased, should be ac-coupled.
Device Common. Connect to low impedance ground.
3
Gain Selection Least Significant Bit. Used as DATA input signal when in serial mode of operation.
Gain Selection Control Bit. Used as CLOCK input pin when in serial mode of operation.
Gain Selection Control Bit. Inactive when in serial mode of operation.
Gain Selection Most Significant Bit. Inactive when in serial mode of operation.
Data Enable Pin. Writes data to register. See Timing Specifications for details.
Balanced Differential Output. Biased to midsupply, should be ac-coupled.
Balanced Differential Output. Biased to midsupply, should be ac-coupled.
4
BIT1
5
BIT2
6
BIT3
7
DENB
OPLO
OPHI
CMDC
8
9
10
Common-Mode Decoupling Pin. Connect bypass capacitor to ground for additional common-mode supply
decoupling beyond the existing internal decoupling.
11
12
FILT
High-Pass Filter Connection. Used to set high-pass corner frequency.
SENB
Serial or Parallel Interface Select. Connect SENB to VPOS for serial operation. Connect SENB to COMM
for parallel operation.
13
14
15
16
VPOS
PWUP
COMM
INHI
Positive Supply Voltage, VS = +3 V to +5.5 V.
Power-Up Pin. Connect PWUP to VPOS to power up the device. Connect PWUP to COMM to power-down.
Device Common. Connect to a low impedance ground.
Balanced Differential Input. Internally biased, should be ac-coupled.
REV. A
–6–
Typical Performance Characteristics–AD8369
(VS = 5 V, T = 25؇C, RS = 200 ⍀, Maximum gain, unless otherwise noted.)
50
40
50
40
GAIN CODE 15
30
20
10
0
30
R
= 1k⍀
L
20
R
= 200⍀
L
10
0
؊10
؊20
؊10
؊20
GAIN CODE 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
10
100
FREQUENCY – MHz
1000
GAIN CODE
TPC 1. Gain vs. Gain Code at 70 MHz
TPC 4. Gain vs. Frequency by Gain Code, RL = 1 kW
43
41
50
V
= 5V, R = 1k⍀
L
40
S
GAIN CODE 15
39
37
V
= 3V, R = 1k⍀
L
S
30
20
10
0
V
= 5V, R = 200⍀
L
S
35
V
= 3V, R = 200⍀
S
L
33
31
29
27
25
؊10
GAIN CODE 0
؊20
10
100
1000
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Maximum Gain vs. Frequency by RL and
Supply Voltage
TPC 5. Gain vs. Frequency by Gain Code, RL = 200 W
28
26
21
35
30
28
23
19
25
20
15
18
13
8
24
22
20
18
17
15
13
11
10
5
3
–2
–7
16
14
9
7
0
10
100
1000
0
1
2
3
4
5
6
7
GAIN CODE
8
9
10 11 12 13 14 15
FREQUENCY – MHz
TPC 3. Output IP3 vs. Gain Code at 70 MHz, VS = 5 V,
RL = 200 W
TPC 6. Output IP3 vs. Frequency, VS = 5 V, RL = 200 W
Maximum Gain
REV. A
–7–
AD8369
–63
–20
–30
–40
–50
–64
–65
–66
–67
–68
–69
–60
–70
–80
–70
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
50 100 150 200 250 300 350 400 450 500 550 600
FREQUENCY – MHz
GAIN CODE
TPC 7. Two-Tone, IMD3 vs. Gain Code at 70 MHz,
OPHI – VOPLO = 1 V p-p, VS = 5 V, RL = 1 kW
TPC 10. Two-Tone IMD3 vs. Frequency VOPHI – VOPLO = 1 V p-p,
VS = 5 V, RL = 1 kW, Maximum Gain
V
؊40
؊45
؊50
؊35
؊40
؊45
HD
3
HD
3
؊55
؊60
؊65
؊70
؊75
؊50
HD
2
HD
2
؊55
؊60
؊65
؊70
0
50
100
150
200
250
FREQUENCY – MHz
300
350
400
0
50
100
150
200
250
FREQUENCY – MHz
300
350
400
TPC 8. Harmonic Distortion at VOPHI – VOPLO = 1 V p-p vs.
Frequency, VS = 5 V, RL = 1 kW, Maximum Gain
TPC 11. Harmonic Distortion at VOPHI – VOPLO = 1 V p-p vs.
Frequency, VS = 5 V, RL = 200 W, Maximum Gain
50
40
30
20
8.0
7.8
5V
7.6
3V
7.4
7.2
R
= 1k⍀
L
7.0
6.8
6.6
10
0
R
= 200⍀
L
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
50
100
150
200
250
300
350
400
FREQUENCY – MHz
GAIN CODE
TPC 12. Noise Figure vs. Frequency by RL and
Supply Voltage at Maximum Gain
TPC 9. Noise Figure vs. Gain Code at 70 MHz, VS = 5 V,
RL = 200 W
REV. A
–8–
AD8369
9.0
8.5
2.0
1.5
9
8
7
2
1
0
8.0
7.5
1.0
0.5
6
5
–1
–2
7.0
6.5
6.0
5.5
5.0
0
–0.5
–1.0
–1.5
–2.0
4
3
–3
–4
2
1
0
–5
–6
4.5
4.0
–2.5
–3.0
–7
1000
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
10
100
FREQUENCY – MHz
GAIN CODE
TPC 13. Output P1dB vs. Gain Code at 70 MHz,
VS = 5 V, RL = 200 W
TPC 16. Output P1dB vs. Frequency, VS = 5 V,
RL = 200 W, Maximum Gain
80
70
60
50
؊40
؊50
؊60
؊70
؊80
؊90
؊100
40
30
20
10
0
10
100
1000
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 14. Common-Mode Rejection Ratio vs. Frequency
at Maximum Gain, VS = 5 V, RL = 200 W (Refer to
Appendix for Definition)
TPC 17. Reverse Isolation vs. Frequency at
Maximum Gain, VS = 5 V, RL = 200 W (Refer to
Appendix for Definition)
250
200
150
100
0.75
0.50
0.25
0
250
200
150
100
0.75
R
R
C
0.50
0.25
0
INHI
OPHI
INLO
C
OPLO
10
100
FREQUENCY – MHz
1000
10
100
FREQUENCY – MHz
1000
TPC 15. Equivalent Input Resistance and
Capacitance vs. Frequency at Maximum Gain
TPC 18. Equivalent Output Resistance and
Capacitance vs. Frequency at Maximum Gain
REV. A
–9–
AD8369
90
90
60
60
120
120
150
150
30
30
GAIN
CODE
15
GAIN
CODE
15
750MHz
10MHz
10MHz
750MHz
0
0
180
180
380MHz
380MHz
GAIN CODES
0, 1, AND 9
GAIN CODES
0, 1, AND 9
500MHz
500MHz
330
330
210
210
240
240
300
300
270
270
TPC 19. Differential Input Reflection Coefficient,
S11, ZO = 50 W Differential, Selected Gain Codes
TPC 22. Differential Output Reflection Coefficient,
S22, ZO = 50 W Differential, Selected Gain Codes
AVERAGE OF 128 SAMPLES
INPUT = 250mV p-p, 10MHz
OVERDRIVE
OUTPUT
1V/VERTICAL
DIVISION
DIFFERENTIAL OUTPUT
250mV/VERTICAL DIVISION
ZERO
RECOVERY
ZERO
BIT 3
2V/VERTICAL DIVISION
BIT 0
2V/VERTICAL DIVISION
GND
GND
TIME – 1s/DIV
TIME – 20ns/DIV
TPC 20. Gain Step Time Domain Response, 3 dB Step,
VS = 5 V, RL = 1 kW, Parallel Transparent Mode
TPC 23. Overdrive Recovery, Maximum Gain,
VS = 5 V, RL = 1 kW, Parallel Transparent Mode
DIFFERENTIAL
OUTPUT
200mV/DIV
ZERO
DIFFERENTIAL OUTPUT
70MHz, 750mV/DIV
ZERO
INPUT
2mV/DIV
PWUP 2V/VERTICAL DIVISION
GND
GND
TIME – 2s/DIV
TIME – 20s/DIV
TPC 21. PWUP Time Domain Response,
Maximum Gain, VS = 5 V, RL = 1 kW
TPC 24. Pulse Response, Maximum Gain, VS = 5 V,
RL = 1 kW
REV. A
–10–
AD8369
2.0
1.5
2.0
1.5
1.0
0.5
1.0
0.5
؊40؇C
؊40؇C
؉85؇C
0
0
؊0.5
؊0.5
؉85؇C
؊1.0
؊1.5
؊2.0
؊1.0
؊1.5
؊2.0
GAIN ERROR AT ؊40؇C AND ؉85؇C
WITH RESPECTTO ؉25؇C. DATA BASED
ON 45 PARTS FROM TWO BATCH LOTS.
GAIN ERROR AT ؊40؇C AND ؉85؇C
WITH RESPECTTO ؉25؇C. DATA BASED
ON 45 PARTS FROM TWO BATCH LOTS.
10
100
FREQUENCY – MHz
1000
10
100
FREQUENCY – MHz
1000
TPC 25. Gain Error Due to Temperature Change vs.
Frequency, 3 Sigma to Either Side of Mean, VS = 5 V,
RL = 1 kW, Maximum Gain
TPC 28. Gain Error Due to Temperature Change
vs. Frequency, 3 Sigma to Either Side of Mean,
VS = 5 V, RL = 200 W, Maximum Gain
2.0
1.5
2.0
1.5
؊40؇C
1.0
1.0
0.5
؊40؇C
0.5
0
0
؊0.5
؊0.5
؊1.0
؊1.0
؉85؇C
GAIN ERROR AT ؊40؇C AND ؉85؇C
WITH RESPECTTO ؉25؇C. DATA BASED
ON 45 PARTS FROM TWO BATCH LOTS.
GAIN ERROR AT ؊40؇C AND ؉85؇C
؊1.5
؊1.5
WITH RESPECTTO ؉25؇C. DATA BASED
ON 45 PARTS FROM TWO BATCH LOTS.
؉85؇C
؊2.0
؊2.0
10
100
FREQUENCY – MHz
1000
10
100
FREQUENCY – MHz
1000
TPC 26. Gain Error Due to Temperature Change vs.
Frequency, 3 Sigma to Either Side of Mean, VS = 3 V,
RL = 1 kW, Maximum Gain
TPC 29. Gain Error Due to Temperature Change
vs. Frequency, 3 Sigma to Either Side of Mean,
VS = 3 V, RL = 200 W, Maximum Gain
10
8
3
1
35
30
25
28
23
18
؉85؇C
+25؇C
؉25؇C
6
4
2
–1
–3
–5
20
15
10
13
8
؊40؇C
–40؇C
+85؇C
3
0
–7
–9
5
0
–2
–7
–2
10
100
FREQUENCY – MHz
1000
10
100
FREQUENCY – MHz
1000
TPC 27. IP3 vs. Frequency by Temperature, VS = 5 V,
RL = 200 W, Maximum Gain
TPC 30. Output P1dB vs. Frequency by Temperature,
VS = 5 V, RL = 200 W, Maximum Gain
REV. A
–11–
AD8369
60
40
35
30
SAMPLE FROM
ONE BATCH LOT
SAMPLE FROM
ONE BATCH LOT
50
40
30
25
20
15
20
10
10
5
0
0
3.06
3.08
3.10
GAIN STEP SIZE – dB/CODE
3.12
3.14
3.16
3.18 3.20
GAIN STEP SIZE – dB/CODE
3.22
TPC 31. Distribution of Gain Step Size, 70 MHz,
VS = 5 V
TPC 34. Distribution of Gain Step Size, 320 MHz,
VS = 5 V
18
26
SAMPLE FROM
TWO BATCH LOTS
16
SAMPLE FROM
TWO BATCH LOTS
24
22
20
18
16
14
12
14
12
10
8
10
6
8
6
4
4
2
2
0
0
–74 –73 –72 –71 –70 –69 –68 –67 –66 –65 –64 –63 –62
IMD – dBc
–58 –57 –56 –55 –54 –53 –52 –51 –50 –49 –48
IMD – dBc
TPC 32. Distribution of IMD3, 70 MHz, RL = 1 kW,
VOPHI – VOPLO = 1 V p-p Composite, VS = 5 V,
Maximum Gain
TPC 35. Distribution of IMD3, 320 MHz, RL = 1 kW,
VOPHI – VOPLO = 1 V p-p Composite, VS = 5 V,
Maximum Gain
3000
2500
1600
1400
1200
1000
3V, R = 1k⍀
L
2000
5V, R = 1k⍀
L
1500
ALL GAIN CODES
REPRESENTED
3V, R = 200⍀
L
800
1000
5V, R = 200⍀
L
500
0
600
400
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
FREQUENCY – MHz
FREQUENCY – MHz
TPC 33. Group Delay vs. Frequency by RL and
Supply Voltage at Maximum Gain
TPC 36. Group Delay vs. Frequency by Gain Code,
VS = 5 V, RL = 1 kW, Maximum Gain
REV. A
–12–
AD8369
100
90
80
70
60
50
40
30
20
10
0
10
100
1000
10000
FREQUENCY – kHz
TPC 37. Power Supply Rejection Ratio, VS = 5 V,
RL = 1 kW, Maximum Gain
V
S
DIGITAL
GAIN STEP SELECTION
OPHI
100⍀
100⍀
V /2
S
V
S
3dB SWITCHED
ATTENUATOR
FIXED
GAIN
Gm CELLS
OPLO
INHI
CMDC
INLO
V
S
~
– 0.7
V /2
S
2
BIAS
22pF
20pF
Figure 1. General Block Diagram, Control and Signal Paths Are Differential
THEORY OF OPERATION
complementary pair of current sources, loaded with internal
100 W resistors to ac ground which provides a 200 W differential
output impedance. The low frequency gain of the AD8369
can be approximated by the equation:
The AD8369 is a digitally controlled fully differential VGA
based on a variation of Analog Devices’ patented X-AMP archi-
tecture (Figure 1). It provides accurate gain control over a 45 dB
span with a constant –3 dB bandwidth of 600 MHz.
Ê
ˆ
Ê
ˆ
VOUT
VIN
200RL
1
= 0.6
Á
Á
Ë
˜
˜
¯
Á
Ë
˜
¯
The 3 dB gain steps can be controlled by a user-selectable
parallel- or serial-mode digital interface. A single pin (SENB)
selects the mode. The AD8369 is designed for optimal
operation when used in a fully differential system, although
single-ended operation is also possible. Its nominal input and
output impedances are 200 W.
200 + R
15-n
)
2(
L
where RL is the external load resistor in ohms and n is the gain
code; 0 is the minimum gain code and 15 is the maximum gain
code. The external load, which is in parallel combination with
the internal 200 W output resistor, affects the overall gain and
peak output swing. Note that the external load has no effect on the
gain step size.
Input Attenuator and Output 3 dB Step
The AD8369 is comprised of a seven-stage R-2R ladder net-
work (eight taps) and a selected Gm stage followed by a
fixed-gain differential amplifier. The ladder provides a total
attenuation of 42 dB in 6 dB steps. The full signal is applied to
the amplifier using the first tap; at the second tap, the signal
is 6 dB lower and so on. A further 3 dB interpolating gain step is
introduced at the output of the fixed gain amplifier, providing
the full 45 dB of gain span.
Input and Output Interfaces
The dc working points of the differential input and output inter-
faces of the AD8369 are internally biased. The inputs INHI and
INLO are biased to a diode drop below VS/2 (~1.7 V for a 5 V
positive supply) to meet isolation and headroom constraints,
while the outputs OPHI and OPLO are centered on the supply
midpoint, VS/2, to provide the maximum output swing.
Fixed Gain Amplifier
The internal VS/2 reference and the CMDC reference are buff-
ered and decoupled to ground via internal capacitors. The
input bias voltage, derived from this VS/2 reference, is brought
The fixed gain amplifier is driven by the tap point of the R-2R
ladder network via the selected Gm cell. The output stage is a
REV. A
–13–
AD8369
out to pin CMDC for decoupling to ground. An external
capacitor from CMDC to COMM of 0.01 mF or more is
recommended to lower the input common-mode impedance of
the AD8369 and improve single-ended operation.
shift registers are composed of four flip-flops that accept the
serial data stream.
TO GAIN CONTROL SECTION
BIT0
BIT1
BIT2
BIT3
Signals must be ac-coupled at the input, either via a pair of
capacitors or a transformer. These may not be needed when the
source has no dc path to ground, such as a SAW filter. The
output may need dc blocking capacitors when driving dc-
grounded loads, but it can be directly coupled to an ADC,
provided that the common-mode levels are compatible.
GAIN CONTROL REGISTER
(LATCH)
T/H
DENB
SENB
MUX
MUX
MUX
MUX
A/B
B
A
B
A
B
A
B
A
The input and output resistances form a high-pass filter in com-
bination with any external ac-coupling capacitors that should
be chosen to minimize signal roll-off at low frequencies. For
example, using input-coupling capacitors of 0.1 mF, each driving
a 100 W input node (200 W differential), the –3 dB high-pass
corner frequency is at:
SHIFT
REGISTER
SHIFT
REGISTER
SHIFT
REGISTER
SHIFT
REGISTER
1
= 16kHz
2p(10–7 )(100)
It is important to note that the input and output resistances are
subject to process variations of up to ±20%. This will affect the
high-pass corner frequencies and the overall gain when driven
from, or loaded by, a finite impedance (see the Reducing Gain
Sensitivity to Input and Output Impedance Variation section).
BIT0
(DATA)
BIT1
(CLOCK)
BIT2
BIT3
Figure 2. Digital Interface Block Diagram
In parallel operation, the 4-bit parallel data is placed on pins
BIT3 through BIT0 and passed along to the gain control register
via the mux. Data is latched into the gain control register on the
falling edge of the input to DENB, subject to meeting the speci-
fied setup and hold times. If this pin is held high (> VS/2), any
changes in the parallel data will result in a change in the gain,
after propagation delays. This is referred to as the transparent
mode of operation. If DENB is held low, the last 4-bit word in
the gain control register will remain latched regardless of the signals
at the data inputs.
Noise and Distortion
It is a common aspect of this style of VGAs, however imple-
mented, that the effective noise figure worsens as the gain is
reduced. The AD8369 uses a fixed gain amplifier, having a certain
invariant noise spectral density, preceded by an attenuator.
Thus, the noise figure increases simply by 6 dB per tap point,
from a starting point of 7 dB at full gain.
However, unlike voltage-controlled amplifiers that must neces-
sarily invoke nonlinear elements in the signal path, the distortion
in a step-gain amplifier can be very low and is essentially indepen-
dent of the gain setting. Note that the postamplifier 3 dB step
does not affect the noise performance, but it has some bearing
on the output third-order intercept (OIP3). See TPCs 3 and 9.
In serial operation, the BIT0 pin is used for data input while the
BIT1 pin is the clock input. Data is loaded into the serial shift
registers on the rising edge of the clock when DENB is low.
Given the required setup and hold times are observed, four rising
edge transitions of the clock will fully load the shift register. On
the rising edge of DENB, the 4-bit word in the shift register is
passed into the gain control register. While this pin is held high,
the clock input to the shift registers is turned off. Once DENB is
taken low, the shift register clock is again enabled and the last 4-bit
word prior to enabling the clock will be latched into the gain
control registers. This enables the loading of a new 4-bit gain
control word without interruption of the signal path. Only when
DENB goes high is data transferred from the shift registers to the
gain control registers. If no connections are made to the digital
control pins, internal 40 kW resistors pull these pins to levels
that set the AD8369 to its minimum gain condition.
Offset Control Loop
The AD8369 uses a control loop to null offsets at the input. If
left uncorrected, these offsets, in conjunction with the gain of
the AD8369, would reduce the available voltage swing at the
output. The control loop samples the differential output volt-
age error and feeds nulling currents back into the input stage.
The nominal high-pass corner frequency of this loop is inter-
nally set to 520 kHz, but it is subject to process variations of
up to ±20%. This corner frequency can be reduced by adding
an external capacitor from the FILT pin to ground, in parallel
to an internal 30 pF capacitor. For example, an external capaci-
tor of 0.1 mF would lower the high-pass corner by a factor of
30/100,030, to approximately 156 Hz. This frequency should
be chosen to be at least one decade below the lowest compo-
nent of interest in the input spectrum.
At power-up or chip enable, if the AD8369 is in parallel mode
and DENB is held low, the gain control register will come up in
an indeterminate state. To avoid this, DENB should be held
high with valid data present during power-up when operating in
the parallel mode. In serial mode, the data in the gain control
interface powers up with a random gain code independent of
the DENB pin. Serial mode operation requires at least four
clock cycles and the transition of DENB from low to high for
valid data to be present at the gain control register.
Digital Control
The gain of the AD8369 is controlled via a serial or parallel
interface, as shown in Figure 2. Serial or parallel operation is
selected via the SENB pin. Setting SENB to a logic low (< VS/2)
selects parallel operation, while a logic high on SENB (> VS/2)
selects serial operation. The AD8369 has two control registers, the
gain control register and the shift register. The gain control register
is a latch that holds the data that sets the amplifier gain. The
REV. A
–14–
AD8369
0.1F
V
S
3VTO 5.5V
0.1F
0.1F
0.1F
0.1F
16
INHI
15
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
IN؉
50⍀TX LINE
R
AD8369
L
TC4-1W
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
0.1F
0.1F
CONTROL INTERFACE
Figure 3. Basic Connections
BASIC CONNECTIONS
In general, there is a loss factor, 1/(1+ ␣), at each interface so
the overall gain reduction due to source and output loading is
40 log10 (1 + ␣). In this case, the input and output loss factors
are 0.8 (1.94 dB) at each interface so the overall gain is
reduced by 3.88 dB.
Figure 3 shows the minimum connections required for basic
operation of the AD8369. Supply voltages of between +3 V and
+5.5 V are permissible. The supply to the VPOS pin should be
decoupled with at least one low inductance surface-mount ceramic
capacitor of 0.1 mF placed as close as possible to the device. More
effective decoupling is provided by placing a 100 pF capacitor in
parallel and including a 4.7 W resistor in series with the supply.
Attention should be paid to voltage drops. A ferrite bead is a
better choice than the resistor where a smaller drop is required.
Operation from a Single-Sided Source
While there are distinct benefits of driving the AD8369 with a
well-balanced input, in terms of distortion and gain conform-
ance at high frequencies, satisfactory operation will often be
possible when a single-sided source is ac-coupled directly to pin
INHI, and pin INLO is ac-grounded via a second capacitor. This
mode of operation takes advantage of the good HF common-mode
rejection of the input system. The capacitor values are, as always,
selected to ensure adequate transmission at low frequencies.
Input-Output Interface
A broadband 50 W input termination can be achieved by
using a 1:2 turns-ratio transformer, as shown in Figure 3.
This also can be used to convert a single-ended input signal
to a balanced differential form at the inputs of the AD8369.
0.1F
V
S
As in all high frequency applications, the trace impedance
should be maintained right up to the input pins by careful
design of the PC board traces, as described in the PCB
Layout Considerations section.
0.1F
0.1F
0.1F
50⍀
SOURCE
0.1F
16
15
14
13
12
11
10
9
Reducing Gain Sensitivity to Input and Output Impedance
Variation
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
The lot-to-lot variations in gain mentioned previously can, in
principle, be eliminated by adjustments to the source and load.
R
L
AD8369
Define a term ␣ as a function of the input and output resistances
of the AD8369 and the source and load resistances presented to it:
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
0.1F
RSOURCE = a R
(
)
INPUT
0.1F
ROUTPUT = a R
(
)
LOAD
CONTROL INTERFACE
For a 50 W source, ␣ = 0.25. Then the load resistance for zero
sensitivity to variations must be 800 W. Put more simply:
Figure 4. Single-Ended-to-Differential Application Example
R
R
= R
(
R
OUTPUT
= 2002
(
) (
)
) (
)
SOURCE
LOAD
INPUT
REV. A
–15–
AD8369
For example, suppose the input signal in Figure 4 is a 140 MHz
sinusoid from a ground-referenced 50 W source. The 0.1 mF
coupling capacitors present a very low reactance at this frequency
(11 mW) so that essentially all of the ac voltage is delivered to the
differential inputs of the AD8369. It will be apparent that, in
addition to the use of adequate coupling capacitance, the external
capacitor used to extend the low frequency range of the offset
control loop, CFILT, must also be large enough to prevent the
offset control loop from attempting to track the ac signal fluctuations.
Interfacing to an ADC
The AD8369 can be used to effectively increase the dynamic
range of an ADC in a direct IF sampling receiver application.
Figure 5 provides an example of an interface to an ADC designed
for an IF of 70 MHz. It comprises a low-pass filter that attenuates
harmonics while providing an impedance transformation from
200 W to 1 kW. This impedance transformation allows the AD8369
to operate much below its peak output swing in the pass band,
which significantly reduces distortion.
0.1F
V
S
0.1F
0.1F
270nH
0.1F
16
15
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
6.8pF
15pF
1k⍀
ADC
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
0.1F
270nH
CONTROL INTERFACE
Figure 5. AD8369 to ADC Interface
0
–10
–20
–30
–40
–50
–60
–70
A high performance 14-bit ADC, the AD6645, is used for illus-
trative purposes and is sampling at 64 MSPs with a full-scale
input of 2.2 V p-p. Typically, an SNR of 51 dB and an SFDR of
almost –90 dBFS are realized by this configuration. Figure 6 shows
an FFT of the AD8369 delivering a single tone at –1 dBFS (that
is, 2 V p-p) at the input of the ADC with an HD2 of –83 dBc and
HD3 of –80 dBc. Figure 7 shows that the two-tone, third-order
intermodulation distortion level is –65.5 dBc.
70MHz – 1dBFS
HD2 = –83dBc
HD3 = –80dBc
SNR = 51dB
PCB Layout Considerations
Each input and output pin of the AD8369 presents 100 W
relative to their respective ac grounds. To ensure that signal
integrity is not seriously impaired by the printed circuit board, the
relevant connection traces should provide a characteristic
impedance of 100 W to the ground plane. This can be achieved
through proper layout. Figure 8 shows the cross section of a PC
board and Table II shows the dimensions that will provide a
100 W line impedance.
–80
–90
–100
0
5
10
15
20
ADC OUTPUT FREQUENCY – MHz
25
30
Figure 6. Single-Tone 70 MHz, –1 dBFS
0
–7dBFS
Table II. Dimensions Required for 100 W Characteristic
–10
Impedance Microstrip Line in FR-4
–20
–30
–40
–50
–60
–70
⑀
r (FR-4)
4.6
W
H
T
22 mils
53 mils
2.1 mils
–72.5dBFS
–80
–90
–100
0
5
10
15
20
ADC OUTPUT FREQUENCY – MHz
25
30
Figure 7. Two-Tone, 70 MHz, 70.3 MHz, –7 dBFS
REV. A
–16–
AD8369
3W
W
3W
Key considerations when laying out an RF trace with a controlled
impedance include:
T
•
Space the ground plane to either side of the signal trace at least
3 line-widths away to ensure that a microstrip (vertical dielec-
tric) line is formed, rather than a coplanar (lateral dielectric)
waveguide.
H
⑀
r
•
Ensure that the width of the microstrip line is constant and
that there are as few discontinuations (component pads, etc.)
as possible along the length of the line. Width variations
cause impedance discontinuities in the line and may result
in unwanted reflections.
Figure 8. Cross-Sectional View of a PC Board
The AD8369 contains both digital and analog sections. Care
should be taken to ensure that the digital and analog sections
are adequately isolated on the PC board. The use of separate
ground planes for each section connected at only one point via a
ferrite bead inductor will ensure that the digital pulses do not
adversely affect the analog section of the AD8369.
•
•
Do not use silkscreen over the signal line; this will alter the
line impedance.
Keep the length of the input and output connection lines as
short as possible.
SW 2
PWUP
3
1
PWDN
R5
OPEN
2
V
S
C5
0.1F
C8
1nF
C7 C8
0.1F 1nF
C4
C2
1nF
1nF
16
15
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
OUT؉
J6
IN؉
J1
T2
T1
R11
0⍀
R2
0⍀
TC4-1W
TC4-1W
AD8369
OUT؊
J7
IN؊
J2
R12
0⍀
R1
0⍀
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
1nF
C3
1nF
C1
R6
0⍀
R7
0⍀
R8
0⍀
R9
0⍀
R10
0⍀
LATCH
CLOCK
DATA
C9
OPEN
V
S
2
1
5
4
8
7
11 SW3
R3
1k⍀
R13
1k⍀
R4
1k⍀
4
SW4
V
3
S
3
6
9
10
12
1
2
4
8
A
2
SW1
B
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D-SUB 25 PIN MALE
Figure 9. Evaluation Board Schematic
REV. A
–17–
AD8369
Evaluation Board
Evaluation Board Software
The evaluation board allows for quick testing of the AD8369
using standard 50 W test equipment. The schematic is shown in
Figure 9. Transformers T1 and T2 are used to transform 50 W
source and load impedances to the desired 200 W reference level.
This allows for broadband operation of the device without the need
to pay close attention to impedance matching (see Table III).
The evaluation board comes with the AD8369 control software
that allows for serial gain control from most computers. The
evaluation board is connected via a cable to the parallel port of
the computer. By simply adjusting the slider bar in the control
software, the gain code is automatically updated to the AD8369.
On some older PCs, it may be necessary to use 5 kW pull-up
resistors to VPOS on DATA, CLOCK, and LATCH depending
upon the capabilities of the port transceiver.
It is necessary to set SW3 on the evaluation board to “SER” for
the control software to function normally.
A screen shot of the evaluation software interface is shown in
Figure 11.
Figure 10. Evaluation Board Layout
Figure 11. Evaluation Software Interface
REV. A
–18–
AD8369
Table III. AD8369 Evaluation Board Configuration Options
Component
Function
Default Condition
VPOS, GND
SW1
Supply and Ground Vector Pins
Not Applicable
Not Applicable
Data Enable: Set to Position A when in serial mode of operation, set to Position B
when in parallel mode of operation.
SW2
Device Enable: When in the PWDN position, the PWUP pin will be connected to
ground and the AD8369 will be disabled. The device is enabled when the switch is
in the PWUP position, connecting the PWUP pin to VPOS.
Not Applicable
SW3, R5
Serial/Parallel Selection. The device will respond to serial control inputs from
connector P1 when the switch is in the SER position. Parallel operation is achieved
when in the PAR position. Device can be hardwired for parallel mode of operation by
placing the 0 W resistor in position R5.
Not Applicable
R5 = Open (Size 0603)
SW4
Parallel Interface Control. Used to hardwire BIT0 through BIT3 to the desired gain
code when in parallel mode of operation. The switch functions as a hexadecimal
to binary encoder (Gain Code 0 = 0000, Gain Code 15 = 1111).
Not Applicable
Not Applicable
J1, J2, J6, J7
C1, C2, C3, C4
T1, T2
Input and Output Signal Connectors. These SMA connectors provide a convenient
way to interface the evaluation board with 50 W test equipment.
AC-Coupling Capacitors. Provides ac-coupling of the input and output signals.
C1, C2, C3, C4
= 1 nF (Size 0603)
Impedance Transformers. Used to transform the 200 W input and output
impedance to 50 W.
T1, T2 = TC4-1W
(MiniCircuits)
R1, R2, R11, R12
Single-Ended or Differential. R2 and R11 are used to ground the center tap of
the secondary windings on transformers T1 and T2. R1 and R12 should be used
to ground J2 and J7 when used in single-ended applications. R1 and R12 should be
removed for differential operation.
R1, R2, R11, R12
= 0 W (Size 0603)
R6, R7, R8, R9, R10 Control Interface Resistors. Simple series resistors for each control interface signal.
R6, R7, R8, R9,
R10 = 0 W (Size 0603)
C5, C6, C8
Power Supply Decoupling. Nominal supply decoupling consists of a 0.1 mF capacitor
to ground followed by a 1 nF capacitor to ground positioned as close to the device
as possible. C8 provides additional decoupling of the input common-mode voltage.
C5 = 0.1 mF (Size 0603)
C6 = C8 = 1 nF
(Size 0603)
C7
C9
High-Pass Filter Capacitor. Used to set high-pass corner frequency of output.
C7 = 0.1 mF (Size 0603)
Clock Filter Capacitor. May be required with some printer ports to minimize overshoot. C9 = Open (Size 0603)
The clock waveform may be smoothed using a simple filter network established by
R7 and C9. Some experimentation may be necessary to determine optimum values.
REV. A
–19–
AD8369
APPENDIX
Composite Waveform Assumption
Characterization Equipment
The nonlinear two-tone measurements made for this data sheet,
i.e., IMD3 and IP3, are based on the assumption of a fixed value
composite waveform at the output, generally 1 V p-p. The fre-
quencies of interest dictate the use of RF test equipment and
because this equipment is generally not designed to work in
units of volts, but rather watts and dBm, an assumption was
made to simplify equipment setup and operation.
Two sets of automated characterization equipment were used to
obtain the majority of the information contained in this data sheet.
An Agilent N4441A Balanced Measurement System was used to
obtain the gain, phase, group delay, reverse isolation, CMRR,
and s-parameter information. Except for the s-parameter informa-
tion, T-attenuator pads were used to match the 50 W impedance of
the ports of this instrument to the AD8369.
Two sinusoidal tones can be represented as:
An Anritsu MS4623B “Scorpion” Vector Network Analyzer was
used to obtain nonlinear measurements IMD3, IP3, and P1dB
through matching baluns and attenuator networks.
V = sin 2p f t
(
)
)
1
1
V = sin 2p f t
(
2
2
The average voltage of one tone is:
Definitions of Selected Parameters
Common-mode rejection ratio (TPC 14) has been defined for
this characterization effort as:
1 T
1
V
2dt =
(
)
Ú
1
T
0
2
Differential - Mode, forwardgain
Common - Mode, forwardgain
where T is the period of the waveform. The average voltage of the
two-tone composite signal is:
where the numerator is the gain into a differential load at the
output due to a differential source at the input and the denomina-
tor is the gain into a common-mode load at the output due to a
common-mode source at the input. In terms of mixed-mode
s-parameters, this equates to:
1 T
V +V 2dt = 1
(
)
Ú
1
2
T
0
So each tone contributes 1/÷2 to the average composite ampli-
tude in terms of voltage. It can be shown that the average
power of this composite waveform is two times greater, or 3dB,
than that of the single tone. This principle can be used to set
correct input amplitudes from generators scaled in dBm and
is correct if the two tones are of equal amplitude and are not
farther than 1 percent apart in frequency.
SDD21
SCC21
Reverse isolation (TPC 17) is defined as SDD12.
More information on mixed-mode s-parameters can be obtained
in the a reference by Bockelman, D.E. and Eisenstadt, W.R.,
Combined Differential and Common-Mode Scattering Parameters:
Theory and Simulation. IEEE Transactions on Microwave Theory
and Techniques, v 43, n 7, 1530 (July 1995).
V
S
R = 200⍀ DIFFERENTIAL: R1 = 69.8⍀, R2 = 69.8⍀
L
0.1F
10nF
0.1F
1nF
R = 1000⍀ DIFFERENTIAL: R1 = 475⍀, R2 = 52.3⍀
L
69.8⍀ 10nF
R1
10nF
69.8⍀
R2
16
INHI
15
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
69.8⍀ 10nF
R1
10nF
R2
69.8⍀
CONTROL INTERFACE
PORT1
PORT3
PORT2
PORT4
AGILENT N4441A
(ALL PORTS 50⍀)
Figure 12. Balanced Measurement System Setup
REV. A
–20–
AD8369
V
S
0.1F
10nF
15
0.1F
1nF
10nF
10nF
16
INHI
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
MINI-CIRCUITS
TC4-1W
MINI-CIRCUITS
TC4-1W
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
10nF
10nF
CONTROL INTERFACE
ANRITSU MS4623BVNA
RECEIVER
INPUT
SOURCE
OUTPUT
Figure 13. Vector Network Analyzer Setup (200 W)
V
S
0.1F
10nF
15
0.1F
1nF
604⍀
10nF
10nF
16
14
13
12
11
10
9
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
MINI-CIRCUITS
TC4-1W
MINI-CIRCUITS
TC4-1W
4120⍀
237⍀
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
604⍀
10nF
10nF
CONTROL INTERFACE
ANRITSU MS4623BVNA
RECEIVER
INPUT
SOURCE
OUTPUT
Figure 14. Vector Network Analyzer Setup (1 kW)
REV. A
–21–
AD8369
V
S
5.0V
0.1F
1nF
15
0.1F
12 11
1nF
10
100nF
100nF
16
INHI
14
13
9
100nF
COMM PWUP VPOS SENB FILT CMDC OPHI
–19dB
162⍀
100nF
100nF
191⍀
113⍀
TEK P6248
DIFF
PROBE
AD8351
R
L
AD8369
MACOM
ETC1-1-13
113⍀
191⍀
LPF
162⍀
100nF
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
–12dB
100nF
100nF
TEK 1103
PROBE
POWER
SUPPLY
V
S
RF OUT
R & S SMT-03
SIGNAL GENERATOR
R & S
FSEA30
SPECTRUM
ANALYZER
Figure 15. Harmonic Distortion Setup
V
R & S SMT-03
SIGNAL GENERATOR
S
5.0V
0.1F
1nF
15
0.1F
1nF
RF OUT
–34dBm AT 70MHz
604⍀
10nF
10nF
16
14
13
12
11
10
9
AGILENT INFINIUM
DSO
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
MINI-CIRCUITS
TC4-1W
4120⍀
237⍀
MINI-CIRCUITS
TC4-1W
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
604⍀
10nF
10nF
50⍀
V
S
PICOSECOND
PULSE LABS
PULSE GENERATOR
Figure 16. Gain Step Response Setup
REV. A
–22–
AD8369
AGILENT 8112A
PULSE
GENERATOR
SPLITTER
TEK TDS 5104 DSO
V
S
5.0V
2F
10F
R & S SMT-03
SIGNAL GENERATOR
RF OUT
PULSE IN
0.1F
12 11
1nF
10
100nF
10nF
16
15
14
13
9
COMM PWUP VPOS SENB FILT CMDC OPHI
INHI
TEK 1103
PROBE
POWER
SUPPLY
TEK P6248
DIFF
PROBE
MINI-CIRCUITS
TC4-1W
1000⍀
AD8369
0⍀
0⍀
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
10nF
C2
100nF
V
S
Figure 17. Pulse Response Setup
V
R & S SMT-03
SIGNAL GENERATOR
S
5.0V
0.1F
1nF
15
0.1F
1nF
RF OUT
–20dBm AT 10MHz
604⍀
10nF
10nF
16
INHI
14
13
12
11
10
9
AGILENT INFINIUM
DSO
COMM PWUP VPOS SENB FILT CMDC OPHI
MINI-CIRCUITS
TC4-1W
4120⍀
237⍀
MINI-CIRCUITS
TC4-1W
AD8369
INLO COMM BIT0 BIT1 BIT2 BIT3 DENB OPLO
1
2
3
4
5
6
7
8
604⍀
10nF
10nF
50⍀
V
S
PICOSECOND
PULSE LABS
PULSE GENERATOR
Figure 18. Overdrive Response Setup
REV. A
–23–
AD8369
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 19. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
–40°C to +85°C
Package Description
Tube, 16-Lead TSSOP
16-Lead TSSOP 7" Tape and Reel
Evaluation Board
Package Option
AD8369ARUZ
AD8369ARUZ-REEL7
AD8369-EVALZ
RU-16
–40°C to +85°C
1 Z = RoHS Compliant Part.
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changed θJA from 150°C/W to 121.48°C/W..................................5
Changes to Ordering Guide...........................................................24
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03029-0-9/15(A)
Rev. A | Page 24
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