AD8372_17 [ADI]
Programmable Dual VGA;
| 型号： | AD8372_17 |
| 厂家： | 
ADI |
| 描述： | Programmable Dual VGA |
| 文件： | 总16页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
41 dB Range, 1 dB Step Size,
Programmable Dual VGA
Data Sheet
AD8372
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Dual independent digitally controlled VGA
Differential input and output
ENB1
REF1
AD8372
IPC1
INC1
OPC1
ONC1
150 Ω differential input
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 130 MHz
CHANNEL 1
POSTAMP
RXT1
CLK2
SDO2
SDI2
CLK1
SDO1
SDI1
REGISTERS
AND
GAIN DECODER
LCH1
41 dB gain range
LCH2
1 dB step size 0.2 dB
RXT2
IPC2
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
OPC2
ONC2
REF2
INC2
Pin-programmable output stage
Power-down feature
CHANNEL 2
POSTAMP
ENB2
Figure 1.
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier (VGA) that provides precise gain control, high IP3,
and low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial inter-
face consists of a clock, latch, data input, and data output lines
for each channel.
Fabricated on an Analog Devices, Inc., high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 kΩ shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
Rev. C
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Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8372
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 10
Single-Ended and Differential Signals..................................... 10
Passive Filter Techniques........................................................... 10
Digital Gain Control .................................................................. 10
Driving Analog-to-Digital Converters.................................... 10
Evaluation Board Schematic ......................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Serial Control Interface Timing ................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
9/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
6/2011—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 6
Changes to Figure 4 and Table 5..................................................... 7
Added Exposed Pad Notation to Outline Dimensions ............. 13
Changes to Ordering Guide .......................................................... 13
5/2008—Rev. 0 to Rev. A
Changes to Features and Figure 1................................................... 1
Changes to Figure 2 and Figure 3................................................... 5
Changes to Figure 9.......................................................................... 8
Changes to Figure 16...................................................................... 12
11/2007—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
AD8372
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 150 Ω, ZL = 250 Ω at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
INPUT STAGE
VOUT < 1 V p-p, CLOAD < 3pF
130
MHz
Pin IPC1, Pin INC1, Pin IPC2, and Pin INC2
Maximum Input Swing at Each Input Pin
Input Resistance
5
V p-p
Ω
Differential
150
2.4
55
Common-Mode Input Voltage
CMRR
V
Gain code = 1x101010 (max gain)
dB
GAIN
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain code = 1x101010
32
dB
Gain code = 1x000001
−9
1.0
0.3
0.7
7.5
20
dB
From gain code 1x000001 to 1x101010
From gain code 1x000001 to 1x101010
Gain code = 1x101010, from 5 MHz to 65MHz
Gain code = 1x101010
dB
Gain Step Accuracy
Gain Flatness
dB
dB
Gain Temperature Sensitivity
Step Response
mdB/°C
ns
For 6 dB gain step, 10% settling
Pin OPC1, Pin ONC1, Pin OPC2, and Pin ONC2
At P1dB, gain code = 1x101010
Differential
OUTPUT STAGE
Output Voltage Swing
Output Resistance
Channel Isolation
9
V p-p
kΩ
3.5
55
Measured at differential output for differential input
applied to alternate channel
dB
NOISE/HARMONIC PERFORMANCE
5 MHz
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010 (max gain)
Gain code = 1x101010
Noise Figure
7.8
79
dB
Second Harmonic
Third Harmonic
Output IP3
dBc
dBc
dBm
dBm
91
32
Output 1 dB Compression Point
35 MHz
18.2
Noise Figure
7.8
79
dB
Second Harmonic
Third Harmonic
Output IP3
dBc
dBc
dBm
dBm
87
35
Output 1 dB Compression Point
65 MHz
18.1
Noise Figure
7.9
78
dB
Second Harmonic
Third Harmonic
Output IP3
dBc
dBc
dBm
dBm
85
35
Output 1 dB Compression Point
85 MHz
17.9
Noise Figure
8.1
77
dB
Second Harmonic
Third Harmonic
Output IP3
dBc
dBc
dBm
dBm
85
35
Output 1 dB Compression Point
17.7
Rev. C | Page 3 of 16
AD8372
Data Sheet
Parameter
Conditions
Min
Typ
Max
Unit
POWER INTERFACE
Supply Voltage
4.5
5.5
V
Quiescent Current per Channel
Thermal connection made to exposed paddle under
device
106
1.2
mA
vs. Temperature
−40°C ≤ TA ≤ +85°C
135
1.3
0.8
mA
mA
mA
Power-Down Current, Both Channels
vs. Temperature
ENB1 and ENB2 low
−40°C ≤ TA ≤ +85°C
ENABLE INTERFACE
Pin ENB1 and Pin ENB2
Minimum voltage to enable the device
ENB1, ENB2 = 0 V
Enable Threshold
V
ENB1, ENB2 Input Bias Current
GAIN CONTROL INTERFACE
400
nA
Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
VIH
Minimum voltage for a logic high
2.4
V
Input Bias Current
400
−60
nA
dB
Serial Port Output Feedthrough
Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code1
RW DC 000000
RW DC 000001
RW DC 000010
RW DC 000011
RW DC 000100
RW DC 000101
RW DC 000110
RW DC 000111
RW DC 001000
RW DC 001001
RW DC 001010
RW DC 001011
RW DC 001100
RW DC 001101
RW DC 001110
RW DC 001111
RW DC 010000
RW DC 010001
RW DC 010010
RW DC 010011
RW DC 010100
RW DC 010101
Voltage Gain (dB)
8-Bit Binary Gain Code1
RW DC 010110
RW DC 010111
RW DC 011000
RW DC 011001
RW DC 011010
RW DC 011011
RW DC 011100
RW DC 011101
RW DC 011110
RW DC 011111
RW DC 100000
RW DC 100001
RW DC 100010
RW DC 100011
RW DC 100100
RW DC 100101
RW DC 100110
RW DC 100111
RW DC 101000
RW DC 101001
RW DC 101010
RW DC 101011
Voltage Gain (dB)
< −60
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
< −60
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
1 RW is the read/write bit. RW = 0 for read mode; RW = 1 for write mode. DC is
the don’t care bit.
Rev. C | Page 4 of 16
Data Sheet
AD8372
SERIAL CONTROL INTERFACE TIMING
tCLK
tPW
CLK1 OR CLK2
LCH1 OR LCH2
tLH
tLS
tDS
tDH
SDI1 OR SDI2
NOTES
WRITE BIT
DON'T CARE
LSB
LSB + 1
LSB + 2
MSB – 2
MSB – 1
MSB
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON CONSECUTIVE
RISING EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
tLH
tPW
tCLK
tD
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
tLS
tDS
tDH
READ BIT
DC
LSB
DC
DC
LSB + 2
DC
DC
DC
MSB
DC
SDO1 OR SDO2
NOTES
LSB + 1
MSB – 2
MSB – 1
1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE GAIN WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE
FALLING EDGES OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter
Min
10
Unit
ns
Clock Pulse Width (tPW
)
Clock Period (tCK
Write Mode
)
20
ns
Setup Time Data vs. Clock (tDS
Hold Time Data vs. Clock (tDH
Setup Time Latch vs. Clock (tLS)
)
0.0
ns
ns
ns
ns
)
1.6
−1.8
2.0
Hold Time Latch vs. Clock (tLH
Read Mode
)
Clock to Data Out (tD)
4.5
ns
Rev. C | Page 5 of 16
AD8372
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
5.5 V
Supply Voltage, VS
ENB1, ENB2, SDI1, SDI2, SDO1, SDO2, CLK1, DGDx − 0.5 V to
VS + 500 mV
CLK2, LCH1, LCH2
Input Voltage, VIPC1, VINC1, VIPC2, VINC2
AGDx − 0.5 V to
VS + 500 mV
Internal Power Dissipation
1.4 W
34.6°C/W1, 2
3.6°C/W2
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
ESD CAUTION
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
150°C
−40°C to +85°C
−65°C to +150°C
1 Still air.
2 All values are modeled using a standard 4-layer JEDEC test board with the
pad soldered to the board and thermal vias in the board.
Rev. C | Page 6 of 16
Data Sheet
AD8372
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
DVS1
LCH1
SDI1
CLK1
CLK2
SDI2
1
2
3
4
5
6
7
8
24 OPC1
23
22 AGD1
21 SDO1
ONC1
AD8372
TOP VIEW
20
19
SDO2
AGD2
(Not to Scale)
LCH2
DVS2
18 ONC2
17 OPC2
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO AGD1 AND AGD2.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
DVS1
LCH1
SDI1
Description
Digital Supply Pin for Channel 1
Latch Input for Channel 1
2
3
Serial Data Input for Channel 1
Clock Input for Channel 1
4
CLK1
CLK2
SDI2
5
Clock Input for Channel 2
6
Serial Data Input for Channel 2
Serial Data Input for Channel 2 Latch Input for Channel 2
Digital Supply Pin for Channel 2
Digital Ground for Channel 2
7
LCH2
DVS2
DGD2
INC2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Negative Input for Channel 2
IPC2
Positive Input for Channel 2
REF2
Reference Voltage for Channel 2
External Bias Setting Resistor Connection for Channel 2
Analog Ground for Channel 2
RXT2
AGD2
ENB2
AVS2
OPC2
ONC2
AGD2
SDO2
SDO1
AGD1
ONC1
OPC1
AVS1
ENB1
AGD1
RXT1
REF1
Chip Enable Pin for Channel 2
Analog Supply Pin for Channel 2
Positive Output for Channel 2
Negative Output for Channel 2
Analog Ground for Channel 2
Serial Data Output for Channel 2
Serial Data Output for Channel 1
Analog Ground for Channel 1
Negative Output for Channel 1
Positive Output for Channel 1
Analog Supply Pin for Channel 1
Chip Enable Pin for Channel 1
Analog Ground for Channel 1
External Bias Setting Resistor Connection for Channel 1
Reference Voltage for Channel 1
Positive Input for Channel 1
IPC1
INC1
Negative Input for Channel 1
DGD1
EPAD
Digital Ground for Channel 1
Exposed Pad. The exposed pad should be connected to AGD1 and AGD2.
Rev. C | Page 7 of 16
AD8372
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 150 Ω, ZL = 250 ꢀ, 1 V p-p differential output, both channels enabled, unless otherwise noted.
20
19
18
17
16
15
40
30
20
+25°C
10
+85°C
–40°C
0
–10
–20
–30
0
10
20
30
40
50
60
70
80
90
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 8. P1dB, Maximum Gain
Figure 5. Gain vs. Frequency by Gain Code (All Codes),
Differential In, Differential Out
180
9
8
7
6
5
4
3
2
1
0
–60
–65
–70
–75
–80
–85
–90
–95
–100
160
140
120
100
80
HD2
HD3
60
40
20
0
0
50
100
150
200
250
300
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. 2nd and 3rd Harmonic Distortion
Figure 9. Input Equivalent Parallel Impedance
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
OIP2 – A = 32
V
OIP2 – A = 10
V
OIP2 – A = –9
V
OIP3 – A = 10
OIP3 – A = 32
V
V
OIP3 – A = –9
V
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. CMRR vs. Frequency
Figure 7. OIP2 and OIP3
Rev. C | Page 8 of 16
Data Sheet
AD8372
50
45
40
35
30
25
20
15
10
5
A
= 0dB
V
A
= 10dB
= 20dB
V
A
V
V
A
= 32dB
0
20ns/DIV
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
Figure 11. Noise Figure vs. Frequency
Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register
Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 12. Isolation, Input to Opposite Output at Maximum Gain
(To calculate output to output gain, subtract 29 dB from this plot)
Rev. C | Page 9 of 16
AD8372
Data Sheet
THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each
amplifier consists of a 150 Ω digitally controlled 6 dB attenuator
followed by a 1 dB vernier and a fixed gain transconductance
amplifier.
primarily to the use of differential signaling techniques to
cancel various distortion components in the device. In addition,
all ac characterization is done using differential signal paths.
Using this device with either the input or the output in a single-
ended circuit significantly degrades the overall performance of
the AD8372.
The differential output on each amplifier consists of a pair of
open-collector transistors. It is recommended that each open-
collector output be biased to +5 V with a high value inductor.
A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an
excellent choice for this component. A 250 Ω resistor should be
placed across the differential outputs to provide a current-to-
voltage conversion and as a source impedance for passive
filtering, post AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 Ω differential input impedance. For
optimal performance, the differential output load should be
250 Ω. When designing passive filters around the AD8372,
these impedances must be taken into account.
DIGITAL GAIN CONTROL
The gain for each side is based on a 250 Ω differential load and
varies as the RLOAD changes per the following equations:
The digital gain control interface consists of the following pins:
SDI, SDO, CLK, and LATCH. The interface is active when the
LATCH pin is shifted low. Gain words are written into the
AD8372 via the SDI pin, and read back from the SDO pin. The
first bit clocked into the data input pin determines whether the
interface is in write or read mode. The second bit is a don’t care
bit, while the remaining six bits program the gain. In read
mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB.
The gain can be programmed between −9 dB and 32 dB in 1 dB
steps. Timing details are given in Figure 2 and Figure 3. The
gain code is given in Table 2.
Gain = 20log(RLOAD/250), for voltage gain
Gain = 10log(RLOAD/250), for power gain
The dependency of the gain on the load is due to the open-
collector output stage that is biased using external chokes. The
inductance of the chokes and the resistance of the load deter-
mine the low frequency pole of the amplifier. The high frequency
pole is set by the parasitic capacitance of the chokes and outputs
in parallel with the output resistance.
The total supply current of 106 mA per side consists of 70 mA
for the combined outputs and about 36 mA through the power
supply pins. Each side has an external resistor (REXT) to ground
to set the transconductance of the output stage. For optimum
distortion, 106 mA total current per side is recommended,
making the REXT value about 2.0 kΩ. Each side has a 2.4 V
reference pin and that same common-mode voltage appears on
the inputs. This reference should be decoupled using a 0.1 μF
capacitor. The part can be powered down to less than 2.6 mA by
setting the ENB pin low for the appropriate side.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 is designed with the intention of driving high
speed, high dynamic range ADCs. The circuit in Figure 14
represents a simplified front end of one-half of the AD8372 dual
VGA driving an AD9445 14-bit, 125 MHz analog-to-digital
converter (ADC). The input of the AD8372 is driven
differentially using a 1:3 impedance ratio transformer, which
also matches the 150 Ω input resistance to a 50 Ω source. The
open-collector outputs are biased through the 33 μH inductors
and are ac-coupled from the 142 Ω load resistors that, in
parallel with the 2 kΩ input resistance of the ADC, provide a
250 Ω load for gain accuracy.
The noise figure of the AD8372 is 7.8 dB at maximum gain and
increases as the gain is reduced. The increase in noise figure is
equal to the reduction in gain.
The ADC is ac-coupled from the 142 Ω resistors to negate a dc
effect on the input common-mode voltage of the AD9445.
Including the series 33 Ω resistors improves the isolation of the
AD8372 from the switching currents caused by the ADC input
sample and hold. The AD9445 represents a 2 kΩ differential
load and requires a 2 V p-p signal when VREF = 1 V for a full-
scale output. This circuit provides variable gain, isolation, and
source matching for the AD9445. Using this circuit with the
AD8372 in a gain of 32 dB (maximum gain), an SFDR
The linearity of the part measured at the output is first-order
independent of the gain setting.
Layout considerations should include minimizing capacitance
on the outputs by avoiding ground planes under the chokes, and
equalizing the output line lengths for phase balance.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 is designed to be used by applying differential
signals to the inputs and using the differential output drive of
the device to drive the next device in the signal chain. The
excellent distortion performance of the AD8372 is due
performance of 74.5 dBc is achieved at 85 MHz (see Figure 15).
Rev. C | Page 10 of 16
Data Sheet
AD8372
5V
5V
33µH
142Ω
0.1µF
0.1µF 0.1µF
33Ω
33Ω
1:3
VIN+
VIN–
½
14
AD9445
14-BIT ADC
AD8372
VGA
50Ω
0.1µF
0.1µF 0.1µF
AC
33µH
142Ω
5V
Figure 14. AD8372 Driving an AD9445 ADC
0
–10
1
FUND: –1.053dBFS
SNR: 58.12dBc
2ND: –74.55dBc
3RD: –86.45dBc
4TH: –91.35dBc
5TH: –89.57dBc
6TH: –91.15dBc
SNRFS: 59.18dBc
THD: –73.99dBc
–20
SINAD: 58.01dBc
SFDR: 74.73dBc
WO SPUR: –85.5dBc
NOISE FLOOR: –101.3dB
–30
–40
–50
–60
2
–70
–80
3
5
6
4
–90
–100
–110
–120
–130
–140
–150
ENCODE: 105MHz
SAMPLES: 32768
FUND LEAK: 100
HARM LEAK: 3
DC LEAK: 6
ANALOG: 19.8766MHz
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 15. 74.5 dBc SFDR Performance of the AD8372 Driving the AD9445 ADC
Rev. C | Page 11 of 16
AD8372 CHAR BD
AGND
AGND
R11
R12
R15
H1-1
TBD
R0603
0
H1-7
R0603
0
R0603
C21
50 OHMS
C8
H1-15
0.1UF
R47
1NF
C0603
AGND
AGND
AGND
C0603
50 OHMS
T2
0.1UF
C17
AGND
TBD
C0603
R44
R31
TBD
R32
TBD
R0603
DGND
DGND
24.9_1%
R2
2K
R0603
R0603
R0603
R9
0
1:3
75 OHMS
W2
H1-3
R0603
R0603
100 OHMS
100 OHMS
R29
0
R0603
R35
R0603
0
C6
75 OHMS
R39
R0603
AGND
R16
AGND
113
C0603
TBD
R40
T4
C0603
0.1UF
C27
C0603
1NF
3
2
1
4
6
0
TBD
10K
R18
0.1UF
C11
OPC1
C0603
DGND
R0603
R21
R0603
R0603
DGND
R10
0
AGND
AGND
TBD
H1-15
H1-4
50 OHMS
SEC
PRI
C0603
R0603
C0603
C16
R0603
C0603
AGND
0.1UF
C26
H1-15
0.1UF
C25
0.1UF
C32
100 OHMS
C7
R36
113
R30
0
ONC1
TBD
75 OHMS
R0603
R0603
C0603
L1
33UH
AGND
100 OHMS
R43
C15
50 OHMS
1812
DGND
C0603
L2
33UH
DGND
75 OHMS
0.1UF
C18
R8
0
C0603
1812
0.1UF
DGND
AGND
H1-5
24.9_1%
R0603
32 31 30 29 28 27 26 25
R22
R0603
C5
0
R23
AGND
TBD
R0603
C0603
0
100 OHMS
R0603
1
24
23
22
21
20
19
18
17
DGND
DVS1
LCH1
SDI1
OPC1
DGND
R7
2
3
4
5
6
7
8
ONC1
AGD1
SDO1
SDO2
AGD2
ONC2
OCP2
H1-11
AGND
SDO1
SDO2
AGND
100 OHMS
R0603
0
C4
Z1
CLK1
CLK2
SDI2
AD8372
TBD
C0603
100 OHMS
DGND
LCH2
DVS2
DGND
R6
AGND
R0603
100 OHMS
SDO1
R46
H1-10
H1-9
H1-1
C0603
R0603
R14
0
0
0
24.9_1%
0.1UF
C28
R37
R0603
C3
R25
R28
0
R0603
H1-6
R0603
0
R0603
9
10 11 12 13 14 15 16
TBD
C10
100 OHMS
C0603
R24
TBD
DGND
R0603
AGND
C0603
DGND
DGND
75 OHMS
C24
L4
33UH
113
AGND
50 OHMS
75 OHMS
R5
0
AGND
T3
1812
C0603
L3
33UH
3
2
1
4
6
ONC2
R0603
R26
TBD
0.1UF
C29
R13
0
1812
C22
0.1UF
C2
SEC
PRI
R0603
0.1UF
H1-12
SDO2
TBD
C0603
R0603
C19
0.1UF
AGND
C0603
C0603
H1-15
R38
113
C9
R27
0
C0603
C23
0.1UF
DGND
OPC2
TBD
DGND
R0603
R0603
R41
R42
C0603
H1-15
R4
C0603
AGND
0
0
AGND
AGND
100 OHMS
50 OHMS
R0603
R0603
75 OHMS
R0603
0.1UF
C14
0
C0603
R45
C20
0.1UF
75 OHMS
C1
24.9_1%
R34
TBD
1NF
C0603
R33
TBD
T1
1:3
R0603
C0603
C12
R17
R0603
R49
0
R1
2K
R0603
AGND
AGND
DGND
DGND
R0603
C0603
H1-7
H1-13
AGND
10K
R0603
AGND
1NF
R0603
W1
50 OHMS
R20
AGND
R3
50 OHMS
0
0.1UF
C13
AGND
R0603
C0603
R19
VDD
VSS
T
R48
TE S TLOOP
E S TLOOP
0
0
TBD
AGND
DGND
R0603
ORANGE
C34
RED
R0603
R0603
AGND
C33
AGND
P1
P1
P1
P1
P1
P1
P1
P1
P1
1
2
3
4
5
6
7
8
9
H1-13
AGND
L6
TBD
3528
L5
H1-3
H1-4
H1-5
H1-6
H1-12
H1-11
H1-10
H1-9
H1-15
3528
TBD
C1206
P2 B11
P2 B12
P2 B13
P2 B14
P2 B15
P2 B16
P2 B17
P2 B18
P2 B19
P2 B20
H1-13
10UF
C1206
P2 A1
P2 A11
P2 A12
P2 A13
P2 A14
P2 A15
P2 A16
P2 A17
P2 A18
P2 A19
P2 A20
H1-13
H1-14
H1-6
P2 B1
P2 B2
P2 B3
P2 B4
P2 B5
P2 B6
P2 B7
P2 B8
P2 B9
P2 B10
AGND
10UF
DGND
AGND
H1-14
H1-6
H1-15
AGND
P2 A2
P2 A3
P2 A4
P2 A5
P2 A6
P2 A7
P2 A8
P2 A9
P2 A10
H1-1
H1-1
P1 14
P1 15
P1 16
P1 17
P1 18
P1 19
DGND
H1-1
H1-12
H1-6
H1-5
H1-5
H1-4
H1-9
H1-4
H1-9
P1 20
H1-3
H1-10
H1-11
H1-12
H1-7
H1-3
H1-10
H1-11
H1-12
H1-7
P1 21
P1 22
P1 23
P1 24
P1 25
H1-15
H1-16
H1-15
H1-16
P1 10
P1 11
P1 12
P1 13
AGND
H1-8
H1-8
H1-6
AGND
H1-12
Data Sheet
AD8372
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
25
32
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
8
9
16
0.50
0.40
0.30
0.25 MIN
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model1
Package Description
AD8372ACPZ-WP
AD8372ACPZ-R7
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP], Waffle Pack
CP-32-7
CP-32-7
36
32-Lead Lead Frame Chip Scale Package [LFCSP], 7”Tape
and Reel
1,500
AD8372-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. C | Page 13 of 16
AD8372
NOTES
Data Sheet
Rev. C | Page 14 of 16
Data Sheet
NOTES
AD8372
Rev. C | Page 15 of 16
AD8372
NOTES
Data Sheet
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07051-0-9/17(C)
Rev. C | Page 16 of 16
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