AD8390A [ADI]
Low Power, High Output Current Differential Amplifier; 低功耗，高输出电流差动放大器
| 型号： | AD8390A |
| 厂家： | 
ADI |
| 描述： | Low Power, High Output Current Differential Amplifier |
| 文件： | 总12页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, High Output Current
Differential Amplifier
AD8390A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
Voltage feedback amplifier
Ideal for ADSL and ADSL2+ central office (CO) and
customer premises equipment (CPE) applications
Enables high current differential applications
Low power operation
Single- or dual-supply operation from 10 V ( 5 V)
up to 24 V ( 12 V)
5.5 mA total quiescent supply current for full power ADSL
and ADSL2+ CO applications
Adjustable supply current to minimize power
consumption
AD8390A
INP
OUTN
VCC
56kΩ
56kΩ
56kΩ
56kΩ
VCOM
OUTP
VEE
INN
VEE
High output voltage and current drive
400 mA peak output drive current
44 V p-p differential output voltage
Low distortion
Figure 1.
−70 dBc MTPR, 26 kHz to 1.1 MHz
−65 dBc MTPR, 1.1 MHz to 2.2 MHz
High speed: 260 V/μs differential slew rate
APPLICATIONS
ADSL/ADSL2+ CO and CPE line drivers
xDSL line drivers
High current differential amplifiers
GENERAL DESCRIPTION
The AD8390A is a high output current, low power consumption
differential amplifier. It is particularly well suited for the central
office (CO) driver interface in digital subscriber line systems
such as ADSL and ADSL2+. In full bias operation, the driver
delivers 20.4 dBm output power into low resistance loads while
compensating for hybrid and transformer insertion losses and
back termination resistors.
PD1, providing three levels of driver bias and one power-down
state. In addition, the IADJ pin is available for fine quiescent
current trimming to tailor the performance of the AD8390A.
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the
AD8390A to be used as the central office line driver in ADSL,
ADSL2+, and proprietary xDSL systems, as well as in other high
current applications requiring a differential amplifier.
The AD8390A is available in a thermally enhanced LFCSP
package (16-lead LFCSP). Significant control and flexibility
in bias current have been designed into the AD8390A.
Four power modes are selectable via two digital inputs, PD0 and
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2013 Analog Devices, Inc. All rights reserved.
AD8390A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits........................................................................................8
Theory of Operation .........................................................................9
Applications Information .............................................................. 10
Supplies, Grounding, and Layout............................................. 10
VCOM Pin .................................................................................. 10
Power Management.................................................................... 10
ADSL and ADSL2+ Applications............................................. 11
Lightning and AC Power Fault................................................. 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
2/13—Revision B: Initial Version
Rev. B | Page 2 of 12
Data Sheet
AD8390A
SPECIFICATIONS
VS = 12 V or VS = 24 V, RL = 100 Ω, G = 10, PD(1:0) = (1,1), IADJ = NC, VCOM = NC (bypassed with 0.1 μF capacitor), TA = 25°C, unless
otherwise noted. Refer to the basic test circuit in Figure 14.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Large Signal Bandwidth
Peaking
VOUT = 0.2 V p-p, RF = 10 kΩ
VOUT = 4 V p-p
VOUT = 0.2 V p-p
38
35
45
38
0.1
260
MHz
MHz
dB
Slew Rate
VOUT = 4 V p-p
V/µs
NOISE/DISTORTION PERFORMANCE
Multitone Power Ratio (26 kHz to 1.1 MHz)
ZLINE = 100 Ω, PLINE = 20.4 dBm,
crest factor (CF) = 5.4
–70
–65
5
dBc
Multitone Power Ratio (1.1 MHz to 2.2 MHz) ZLINE = 100 Ω, PLINE = 20.4 dBm,
crest factor (CF) = 5.4
Voltage Noise (RTI)
dBc
f = 10 kHz
nV/√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage (VOS,DM(RTI)
)
VINP − VINN, VCOM = midsupply
VINP – VINN, VCOM = NC
–3.0
–3.0
1.0
1.0
–4.0
0.05
400
2
+3.0
+3.0
–7.0
mV
mV
µA
µA
kΩ
pF
Input Bias Current
Input Offset Current
Input Resistance
–0.35
+0.35
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Output Balance Error
Linear Output Current
Output Impedance
(∆VOS,DM(RTI))/(∆VIN,CM
)
58
69
dB
∆VOUT
(∆VOS,CM)/∆VOUT
RL = 10 Ω, fC = 100 kHz
fC = 2 MHz
(VOUTP + VOUTN)/2, VCOM = midsupply
(VOUTP + VOUTN)/2, VCOM = NC
42.8
44
60
400
0.1
35
44.6
V
dB
mA
Ω
mV
mV
Output Common-Mode Offset
–75
–75
+75
+75
35
POWER SUPPLY
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current, IADJ = VEE
5
10
12
24
V
V
PD(1:0) = (1,1)
PD(1:0) = (1,0)
PD(1:0) = (0,1)
PD(1:0) = (0,0)
PD(1:0) = (1,1)
PD(1:0) = (1,0)
PD(1:0) = (0,1)
PD(1:0) = (0,0)
5.5
4.0
2.6
0.56
10.0
6.7
3.8
0.67
94
6.5
5.0
3.5
1.0
11.0
8.0
5.0
1.0
mA
mA
mA
mA
mA
mA
mA
mA
dB
V
Total Quiescent Current, IADJ = NC
Power Supply Rejection Ratio (PSRR)
PD(1:0) = 0 (Low Logic State)
PD(1:0) = 1 (High Logic State)
VCOM
∆VOS,DM/∆VS, ∆VS = 1 V, VCOM = midsupply
72
0.8
1.6
V
Input Voltage Range
Input Resistance
VCOM Accuracy
−11.0
0.995
+10.0
1.005
V
kΩ
V/V
28
1.0
∆VOUT,CM/∆VCOM
Rev. B | Page 3 of 12
AD8390A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 150°C
J
Parameter
Rating
Supply Voltage (VCC − VEE)
VCOM
26 V
VEE < VCOM < VCC
See Figure 2
150°C
–40°C to +85°C
–65°C to +150°C
300°C
Package Power Dissipation
Maximum Junction Temperature (TJ MAX
Operating Temperature Range (TA)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
–25 –15 –5
5
15
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load RL is referenced
to midsupply, the total drive power is VS/2 × IOUT, part of which
is dissipated in the package and part in the load (VOUT × IOUT).
THERMAL RESISTANCE
θJA is specified in still air with exposed pad soldered to 4-layer
JEDEC test board. θJC is specified at the exposed pad.
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
RMS output voltages should be considered. If RL is referenced to
16-Lead LFCSP (CP-16-4)
30.4
16
°C/W
VEE as in single-supply operation, the total power is VS × IOUT
.
In single-supply operation with RL referenced to VEE, the worst
case is VOUT = VS/2.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8390A is
limited by its junction temperature on the die.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more copper in direct contact with the package leads
from PCB traces, through holes, ground, and power planes
reduces θJA.
The maximum safe junction temperature of plastic encapsu-
lated devices, as determined by the glass transition temperature
of the plastic, is 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding this
limit for an extended period can result in device failure.
ESD CAUTION
Figure 2 shows the maximum safe power dissipation in
the package vs. the ambient temperature. θJA values are
approximations.
Rev. B | Page 4 of 12
Data Sheet
AD8390A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 OUTN
11 VEE
10 VCC
INP
PD1
PD0
INN
1
2
3
4
AD8390A
TOP VIEW
(Not to Scale)
9
OUTP
NOTES
1. NC = NO CONNECT.
2. NO ELECTRICAL CONNECTION. CONNECT THE
EXPOSED PAD TO A SOLID EXTERNAL PLANE
WITH LOW THERMAL RESISTANCE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
INP
Amplifier Noninverting Input.
2
3
4
5
PD1
PD0
INN
Power Mode Control.
Power Mode Control.
Amplifier Inverting Input.
No Connection.
NC
6
7
8
DGND
IADJ
NC
Ground.
Bias Current Adjustment.
No Connection.
9
OUTP
VCC
VEE
OUTN
NC
NC
VCOM
NC
Amplifier Noninverting Output.
Positive Power Supply.
Negative Power Supply.
Amplifier Inverting Output.
No Connection.
No Connection.
Common-Mode Voltage.
No Connection.
10
11
12
13
14
15
16
EPAD
Exposed pad. No electrical connection. Connect the exposed pad to a solid external plane with low thermal
resistance.
Rev. B | Page 5 of 12
AD8390A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±±1 V, RL = ±00 Ω, G = ±0, PD(±:0) = (±,±), IADJ = NC, VCOM = NC (bypassed with 0.± μF capacitor), TA = 15°C, unless otherwise
noted. Refer to the basic test circuit in Figure ±4.
44
42
40
38
36
34
25
20
15
10
5
PD(1:0) = (1,1)
= NC
I
ADJ
PD(1:0) = (1,0)
= NC
I
ADJ
PD(1:0) = (0,1)
= NC
I
ADJ
PD(1:0) = (1,1)
= V
I
ADJ
EE
PD(1:0) = (1,0)
= V
I
ADJ
EE
PD(1:0) = (0,1)
= V
0
I
ADJ
EE
–5
0.1
20
30
40
50
60
70
80
90
100
110
1
10
100
FREQUENCY (MHz)
LOAD (Ω)
Figure 4. Differential Small Signal Frequency Response;
VS = 12 V, Gain = 10, VOUT = 200 mV p-p
Figure 7. Differential DC Output Swing vs. RL;
VS = 12 V, PDꢀ1:0) = ꢀ1,1), RIADJ = NC
10
25
20
15
10
5
8
6
4
2
0
PD(1:0) = (1,1)
I
= NC
ADJ
PD(1:0) = (1,0)
= NC
PD(1:0) = (1,1)
I
ADJ
PD(1:0) = (0,1)
= NC
I
ADJ
PD(1:0) = (1,0)
PD(1:0) = (0,1)
PD(1:0) = (1,1)
= V
I
ADJ
EE
PD(1:0) = (1,0)
= V
I
ADJ
EE
0
PD(1:0) = (0,1)
I
= V
10
ADJ
EE
–5
0.1
0.01
0.1
1
10
100
1000
1
100
R
(kΩ)
FREQUENCY (MHz)
ADJ
Figure 8. Quiescent Current vs. IADJ Resistor; VS = 12 V
Figure 5. Differential Large Signal Frequency Response;
VS = 12 V, Gain = 10, VOUT = 4 V p-p
6
4
1.5
1.0
0.5
0
1000
800
600
400
200
PD PULSE
PD(1:0) = (1,1)
PD(1:0) = (1,0)
2
PD(1:0) = (0,1)
0
–0.5
–1.0
–1.5
–2
–4
–6
OUTPUT
0
12
14
16
18
20
22
0
1
2
3
4
5
6
7
8
9
10
OUTPUT POWER (dBm)
TIME (µs)
Figure 9. Power-Down to Power-Up Time;
PDꢀ1:0) = ꢀ1,1) to PDꢀ1:0) = ꢀ0,0) to PDꢀ1:0) = ꢀ1,1)
Figure 6. Internal Power Dissipation vs. Output Power;
Transformer Turns Ratio = 1:1.4
Rev. B | Page 6 of 12
Data Sheet
AD8390A
–30
0
–10
–20
–30
–40
–50
–60
–70
V
= ±12V
S
G = 10
R
PD(1:0) = (0,0)
–35
–40
–45
–50
–55
–60
–65
= 100Ω
L
0.01
0.1
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. CMRR vs. Frequency; VIN = 200 mV p-p, Gain = 10, IADJ = NC
Figure 10. Signal Feedthrough
7
6
0
–20
5
4
–40
3
PSR+
2
–60
1
–80
0
PSR–
–1
–2
–3
–100
–120
0.01
0.1
1
10
100
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Gain with VCOM Driven vs. Frequency; VCOM = 200 mV p-p
Figure 11. PSRR vs. Frequency; PD(1:0) = (1,1)
Rev. B | Page 7 of 12
AD8390A
Data Sheet
TEST CIRCUITS
R
= 10kΩ
F
52.3Ω
R
= 1kΩ
G
V
= 100Ω
V
OUT, DM
IN
AD8390A
R
L, DM
R
= 1kΩ
G
52.3Ω
R
= 10kΩ
F
Figure 14. Basic Test Circuit
Rev. B | Page 8 of 12
Data Sheet
AD8390A
THEORY OF OPERATION
R
F
VCC
R
G
INP
INN
OUTN
OUTP
AD8390A
+
IN, DM
–
–
INP
OUTN
A
V
VCOM
R
V
L, DM
OUT, DM
+
VCC
56kΩ
56kΩ
R
G
C
R
F
VCOM
OUTP
Figure 16. Basic Application Circuit
56kΩ
VEE
56kΩ
The high open-loop gain of the AD8390A and the negative
feedback minimize the differential and common-mode error
voltages.
B
INN
VEE
With the differential and common-mode error voltages assumed
to be 0, the differential-mode gain and input impedance of the
basic application circuit shown in Figure 16 are as follows:
Figure 15. Functional Block Diagram
The AD8390A is a true differential amplifier with common-
mode feedback. The AD8390A is functionally equivalent to three
amplifiers, as shown in Figure 15. Amplifier A and Amplifier B
form a standard dual amplifier in an inverting configuration.
Amplifier C maintains the common-mode voltage VCOM at
the output.
VOUT ,DM
RF
RG
VIN,DM
RIN,DM 2 RG
With VCOM left unconnected, the outputs are internally biased
to midsupply. VCOM can be driven externally to set the dc
output common-mode voltage.
Rev. B | Page 9 of 12
AD8390A
Data Sheet
APPLICATIONS INFORMATION
POWER MANAGEMENT
SUPPLIES, GROUNDING, AND LAYOUT
The AD8390A offers significant versatility for maximizing
efficiency while maintaining optimal levels of performance.
The AD8390A can be powered from either single or dual
supplies, with the total supply voltage ranging from 10 V to
24 V. For optimum performance, use well-regulated low ripple
supplies.
Optimizing driver efficiency while delivering the required signal
level is accomplished with two on-chip power management
features: two PD pins to select one of four bias modes and an
As with all high speed amplifiers, pay close attention to supply
decoupling, grounding, and overall board layout. Provide low
frequency supply decoupling with 10 µF tantalum capacitors
from each supply to ground. In addition, decouple all supply
pins with 0.1 µF quality ceramic chip capacitors placed as close
as possible to the driver. Use an internal low impedance ground
plane to provide a common ground point for all driver and
decoupling capacitor ground requirements. Whenever possible,
use separate ground planes for analog and digital circuitry.
I
ADJ pin for fine bias adjustments.
PD(1:0) Pins
Two CMOS-compatible logic pins, PD1 and PD0, select one of
three active power levels and a power-down mode.
The digital ground pin (DGND) is the logic ground reference
for the PD(1:0) pins. PD(1:0) = (0,0) is the power-down mode.
The PD pins are internally connected to DGND via termination
resistors. When the PD pins are left unconnected, the AD8390A
is in power-down mode.
Follow high speed layout techniques to minimize parasitic
capacitance around the inverting inputs. Some practical
examples of these techniques are keeping feedback traces as
short as possible and clearing away ground plane in the area of
the inverting inputs.
The AD8390A exhibits a low output impedance in the three
active modes. The output impedance in the power-down mode
is high but undefined and may not be suitable for systems that
rely on a high impedance OFF state, such as multiplexing.
Keep input and output traces as short as possible and as far
apart from each other as practical to minimize crosstalk. Keep
all differential signal traces as symmetrical as possible.
IADJ Pin
The IADJ pin provides bias current fine-tuning.
VCOM PIN
With the IADJ pin unconnected, the bias currents are internally
set to 10 mA, 6.7 mA, and 3.8 mA for the three active modes.
By design, the VCOM pin is internally biased at midsupply,
eliminating the need for external resistors. However, the
designer may set VCOM to other voltage levels with an external
low impedance source.
With the IADJ pin connected to the negative supply (VEE), the
bias currents are reduced by approximately 50%.
A resistor, RADJ, connected between the IADJ pin and the negative
supply, provides fine bias adjustment as shown in Figure 8.
When the VCOM pin is left unconnected, decouple it with a
0.1 µF capacitor to ground, placed in close proximity to the
AD8390A.
Table 5. PD and IADJ Selection Guide
PD1
1
PD0
1
RADJ (Ω)
IQ (mA)
10.0
6.7
With dual equal supplies, connect the VCOM pin directly to
ground to bias the outputs at midsupply, eliminating the need
for the external decoupling capacitor.
∞
∞
∞
∞
0
1
0
0
1
3.8
0
0
0.67
5.5
1
1
1
0
0
4.0
0
1
0
2.6
0
0
0
0.56
Rev. B | Page 10 of 12
Data Sheet
AD8390A
Assuming low values for back termination resistor RM, R3 is
approximated as
ADSL AND ADSL2+ APPLICATIONS
In a typical ADSL/ADSL2+ application, a differential line driver
drives the signal from the analog front end (AFE) onto the
twisted pair telephone line. Referring to the typical circuit
representation in Figure 17, the differential input appears at
R3 ≅ R1×2×k ×AV
where AV is the voltage gain.
R2 is given by
V
IN+ and VIN− from the AFE. The differential output is
transformer-coupled to the telephone line at tip and ring. The
common-mode operating point, generally midway between the
supplies, is set through VCOM.
R3
1− k
R2 =
With RM, R3, and R2 calculated, the closest 1% resistors are
chosen and the gain rechecked with the following equation:
In ADSL/ADSL2+ applications, it is common practice to
conserve power by using positive feedback (R3 in Figure 17) to
synthesize the output resistance, lowering the required value of
the line matching resistors, RM.
R2× R3
AV =
R1
[
RM + R2
(
k +1
)
− R3
]
Table 6 compares the results of the exact values, the simplified
approximation, and the closest 1% resistor value calculations. In
this example, R1 = 1.0 kΩ, AV = 10, and k = 0.1.
R2
R3
VCC
0.1µF
R1
10µF
Note that decreasing the value of the back termination resistors
attenuates the receive signal by approximately 1/k. Advances in
low noise receive amplifiers permit the use of k values as small
as 0.1.
0.1µF
+IN
R
R
M
1:N
–OUT
+
VCOM
R
V
L
OUT, DM
–
The line impedance, turns ratio, and k factor specify the output
voltage and current required from the AD8390A. To accom-
modate higher crest factors or lower supply rails, the turns ratio,
N, may need to be increased. Because higher turns ratios and
smaller k factors both attenuate the receive signal, a large
increase in N may require an increase in k to maintain the
desired noise performance. Any particular design process
requires that these trade-offs be addressed.
+OUT
R3
0.1µF
10µF
M
R1
–IN
R
ADJ
R2
VEE
0.1µF
Figure 17. ADSL/ADSL2+ Application Circuit
The differential input impedance to the circuit is 2 × R1.
R1 is chosen by the designer to match system requirements.
Table 6. Resistor Selection
The synthesized value of the back termination resistor is given
by the following equation.
Exact
Value
Approximate Standard 1%
Component
R1 (Ω)
R2 (Ω)
R3 (Ω)
RM (Ω)
Calculation
Resistor Value
1000
2246.95
2022.25
5
1000
1000
RL
RM = k×
2×N2
2222.22
2000
2210
2000
where RL is the line impedance, and N is the turns ratio of the
transformer.
5
4.99
Actual AV
Actual k
10.000
0.1
9.889
0.1
10.138
0.095
The factor k defines the relationship between the negative and
positive feedback resistors and is given by
LIGHTNING AND AC POWER FAULT
R3
R2
k =1 −
When the AD8390A is an ADSL/ADSL2+ line driver, it is
transformer-coupled to the twisted pair telephone line. In this
environment, the AD8390A is subject to large line transients
resulting from events such as lightning strikes or downed power
lines. Additional circuitry is required to protect the AD8390A
from damage due to these events.
Commonly used values for k are between 0.1 and 0.25. Values
less than 0.1 can lead to instability and are not recommended.
Rev. B | Page 11 of 12
AD8390A
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.60 MAX
1.95 REF
0.60 MAX
PIN 1
INDICATOR
13
12
16
1
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
3.75 BSC
SQ
0.65
BSC
EXPOSED
PAD
9
4
8
5
0.75
0.60
0.50
0.25 MIN
BOTTOM VIEW
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.35
0.30
0.25
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
AD8390AACPZ-R2
AD8390AACPZ-RL
AD8390AACPZ-R7
16-Lead LFCSP_VQ, 250 Piece Reel
16-Lead LFCSP_VQ, 13”Tape and Reel
16-Lead LFCSP_VQ, 7”Tape and Reel
CP-16-4
CP-16-4
CP-16-4
1 Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07094-0-2/13(B)
Rev. B | Page 12 of 12
相关型号：
AD8390ACPZ-R2
IC OP-AMP, 3000 uV OFFSET-MAX, PQCC16, 4 X 4 MM, MO-220-VGGC, LFCSP-16, Operational Amplifier
ADI
AD8390ACPZ-REEL
IC OP-AMP, 3000 uV OFFSET-MAX, PQCC16, 4 X 4 MM, MO-220-VGGC, LFCSP-16, Operational Amplifier
ADI
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