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AD8421BRMZ-R7 [ADI]

3 nV/√Hz, Low Power; 3内华达州/ √Hz的低功耗
AD8421BRMZ-R7
型号： AD8421BRMZ-R7
厂家： ADI    ADI
描述：

3 nV/√Hz, Low Power
3内华达州/ √Hz的低功耗
文件： 总28页 (文件大小：656K)
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3 nV/√Hz, Low Power  
Instrumentation Amplifier  
AD8421  
Data Sheet  
FEATURES  
PIN CONNECTION DIAGRAM  
Low power  
2.3 mA maximum supply current  
Low noise  
3.2 nV/√Hz maximum input voltage noise at 1 kHz  
200 fA/√Hz current noise at 1 kHz  
Excellent ac specifications  
AD8421  
1
2
3
4
8
7
6
5
–IN  
+V  
S
R
R
V
OUT  
G
G
REF  
–V  
+IN  
S
TOP VIEW  
(Not to Scale)  
10 MHz bandwidth (G = 1)  
2 MHz bandwidth (G = 100)  
Figure 1.  
0.6 μs settling time to 0.001% (G = 10)  
80 dB CMRR at 20 kHz (G = 1)  
35 V/μs slew rate  
High precision dc performance (AD8421BRZ)  
94 dB CMRR minimum (G = 1)  
10µ  
1µ  
G = 100  
0.2 μV/°C maximum input offset voltage drift  
1 ppm/°C maximum gain drift (G = 1)  
500 pA maximum input bias current  
Inputs protected to 40 V from opposite supply  
2.5 V to 18 V dual supply (5 V to 36 V single supply)  
Gain set with a single resistor (G = 1 to 10,000)  
BEST AVAILABLE  
7mA LOW NOISE IN-AMP  
100n  
10n  
APPLICATIONS  
BEST AVAILABLE  
1mA LOW POWER IN-AMP  
Medical instrumentation  
Precision data acquisition  
Microphone preamplification  
Vibration analysis  
AD8421  
R
NOISE ONLY  
S
1n  
100  
1k  
10k  
100k  
1M  
Multiplexed input applications  
ADC driver  
SOURCE RESISTANCE, R (Ω)  
S
Figure 2. Noise Density vs. Source Resistance  
GENERAL DESCRIPTION  
The AD8421 is a low cost, low power, extremely low noise, ultralow  
bias current, high speed instrumentation amplifier that is ideally  
suited for a broad spectrum of signal conditioning and data  
acquisition applications. This product features extremely high  
CMRR, allowing it to extract low level signals in the presence of  
high frequency common-mode noise over a wide temperature  
range.  
The AD8421 delivers 3 nV/√Hz input voltage noise and  
200 fA/√Hz current noise with only 2 mA quiescent current,  
making it an ideal choice for measuring low level signals. For  
applications with high source impedance, the AD8421 employs  
innovative process technology and design techniques to provide  
noise performance that is limited only by the sensor.  
The AD8421 uses unique protection methods to ensure robust  
inputs while still maintaining very low noise. This protection  
allows input voltages up to 40 V from the opposite supply rail  
without damage to the part.  
The 10 MHz bandwidth, 35 V/μs slew rate, and 0.6 μs settling  
time to 0.001% (G = 10) allow the AD8421 to amplify high speed  
signals and excel in applications that require high channel count,  
multiplexed systems. Even at higher gains, the current feedback  
architecture maintains high performance; for example, at G = 100,  
the bandwidth is 2 MHz and the settling time is 0.8 μs. The  
AD8421 has excellent distortion performance, making it suitable  
for use in demanding applications such as vibration analysis.  
A single resistor sets the gain from 1 to 10,000. The reference  
pin can be used to apply a precise offset to the output voltage.  
The AD8421 is specified from −40°C to +85°C and has typical  
performance curves to 125°C. It is available in 8-lead MSOP  
and SOIC packages.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2012 Analog Devices, Inc. All rights reserved.  
 
AD8421  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Gain Selection............................................................................. 20  
Reference Terminal .................................................................... 21  
Input Voltage Range................................................................... 21  
Layout .......................................................................................... 21  
Input Bias Current Return Path ............................................... 22  
Input Voltages Beyond the Supply Rails.................................. 22  
Radio Frequency Interference (RFI)........................................ 23  
Calculating the Noise of the Input Stage................................. 23  
Applications Information.............................................................. 25  
Differential Output Configuration .......................................... 25  
Driving an ADC ......................................................................... 26  
Outline Dimensions....................................................................... 27  
Ordering Guide .......................................................................... 27  
Applications....................................................................................... 1  
Pin Connection Diagram ................................................................ 1  
General Description......................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
AR and BR Grades........................................................................ 3  
ARM and BRM Grades................................................................ 5  
Absolute Maximum Ratings............................................................ 8  
Thermal Resistance ...................................................................... 8  
ESD Caution.................................................................................. 8  
Pin Configuration and Function Descriptions............................. 9  
Typical Performance Characteristics ........................................... 10  
Theory of Operation ...................................................................... 20  
Architecture................................................................................. 20  
REVISION HISTORY  
5/12—Revision 0: Initial Version  
Rev. 0 | Page 2 of 28  
 
Data Sheet  
AD8421  
SPECIFICATIONS  
VS = 15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.  
AR AND BR GRADES  
Table 1.  
AR Grade  
BR Grade  
Typ  
Test Conditions/  
Comments  
Parameter  
Unit  
Min  
Typ  
Max  
Min  
Max  
COMMON-MODE REJECTION  
RATIO (CMRR)  
CMRR DC to 60 Hz with 1 kΩ  
Source Imbalance  
VCM = −10 V to +10 V  
G = 1  
G = 10  
G = 100  
G = 1000  
Over Temperature, G = 1  
CMRR at 20 kHz  
G = 1  
G = 10  
G = 100  
86  
94  
dB  
dB  
dB  
dB  
dB  
106  
126  
136  
80  
114  
134  
140  
93  
T = −40°C to +85°C  
VCM = −10 V to +10 V  
80  
90  
100  
110  
80  
dB  
dB  
dB  
dB  
100  
110  
120  
G = 1000  
NOISE  
Voltage Noise, 1 kHz1  
Input Voltage Noise, eni  
Output Voltage Noise, eno  
Peak to Peak, RTI  
G = 1  
VIN+, VIN− = 0 V  
3
3.2  
60  
3
3.2  
60  
nV/√Hz  
nV/√Hz  
f = 0.1 Hz to 10 Hz  
2
0.5  
0.07  
2
0.5  
0.07  
2.2  
μV p-p  
μV p-p  
μV p-p  
G = 10  
G = 100 to 1000  
Current Noise  
Spectral Density  
Peak to Peak, RTI  
VOLTAGE OFFSET2  
Input Offset Voltage, VOSI  
Over Temperature  
Average TC  
Output Offset Voltage, VOSO  
Over Temperature  
Average TC  
Offset RTI vs. Supply (PSR)  
G = 1  
0.09  
f = 1 kHz  
f = 0.1 Hz to 10 Hz  
200  
18  
200  
18  
fA/√Hz  
pA p-p  
VS = 5 V to 15 V  
TA = −40°C to +85°C  
60  
86  
0.4  
350  
0.66  
6
25  
45  
0.2  
250  
0.45  
5
μV  
μV  
μV/°C  
μV  
mV  
TA = −40°C to +85°C  
VS = 2.5 V to 18 V  
μV/°C  
90  
120  
120  
130  
140  
100  
120  
140  
140  
120  
140  
150  
150  
dB  
dB  
dB  
dB  
G = 10  
G = 100  
G = 1000  
110  
124  
130  
INPUT CURRENT  
Input Bias Current  
Over Temperature  
Average TC  
Input Offset Current  
Over Temperature  
Average TC  
1
2
8
0.1  
0.5  
6
nA  
nA  
pA/°C  
nA  
nA  
TA = −40°C to +85°C  
TA = −40°C to +85°C  
50  
0.5  
50  
0.1  
2
2.2  
0.5  
0.8  
1
1
pA/°C  
Rev. 0 | Page 3 of 28  
 
AD8421  
Data Sheet  
AR Grade  
Typ  
BR Grade  
Typ  
Test Conditions/  
Comments  
Parameter  
DYNAMIC RESPONSE  
Small Signal Bandwidth  
G = 1  
Unit  
Min  
Max  
Min  
Max  
−3 dB  
10  
10  
2
10  
10  
2
MHz  
MHz  
MHz  
MHz  
G = 10  
G = 100  
G = 1000  
0.2  
0.2  
Settling Time to 0.01%  
G = 1  
G = 10  
G = 100  
G = 1000  
Settling Time to 0.001%  
G = 1  
G = 10  
G = 100  
G = 1000  
10 V step  
10 V step  
0.7  
0.4  
0.6  
5
0.7  
0.4  
0.6  
5
μs  
μs  
μs  
μs  
1
1
μs  
μs  
μs  
μs  
0.6  
0.8  
6
0.6  
0.8  
6
Slew Rate  
G = 1 to 100  
GAIN3  
Gain Range  
Gain Error  
G = 1  
G = 10 to 1000  
Gain Nonlinearity  
G = 1  
35  
35  
V/μs  
V/V  
G = 1 + (9.9 kΩ/RG)  
1
10,000  
1
10,000  
VOUT  
= 10 V  
0.02  
0.2  
0.01  
0.1  
%
%
VOUT = −10 V to +10 V  
RL ≥ 2 kΩ  
RL = 600 Ω  
RL ≥ 600 Ω  
VOUT = −5V to +5V  
1
3
50  
10  
1
3
50  
10  
ppm  
ppm  
ppm  
ppm  
1
30  
5
1
30  
5
G = 10 to 1000  
Gain vs. Temperature3  
G = 1  
G > 1  
5
−50  
0.1  
1
−50  
ppm/°C  
ppm/°C  
INPUT  
Input Impedance  
Differential  
Common Mode  
30||3  
30||3  
30||3  
30||3  
GΩ||pF  
GΩ||pF  
V
V
V
Input Operating Voltage Range4 VS = 2.5 V to 18 V  
−VS + 2.3  
−VS + 2.5  
−VS + 2.1  
+VS − 1.8  
+VS − 2.0  
+VS − 1.8  
−VS + 2.3  
−VS + 2.5  
−VS + 2.1  
+VS − 1.8  
+VS − 2.0  
+VS − 1.8  
Over Temperature  
TA = −40°C  
TA = +85°C  
OUTPUT  
RL = 2 kΩ  
Output Swing  
Over Temperature  
Short-Circuit Current  
REFERENCE INPUT  
RIN  
VS = 2.5 V to 18 V  
TA = −40°C to +85°C  
−VS + 1.2  
−VS + 1.2  
+Vs − 1.6  
+Vs − 1.6  
−VS + 1.2  
−VS + 1.2  
+VS − 1.6  
+VS − 1.6  
V
V
mA  
65  
65  
20  
20  
20  
20  
kΩ  
μA  
V
IIN  
VIN+, VIN− = 0 V  
24  
+VS  
24  
+VS  
Voltage Range  
Reference Gain to Output  
−VS  
−VS  
1
1
V/V  
0.0001  
0.0001  
Rev. 0 | Page 4 of 28  
 
Data Sheet  
AD8421  
AR Grade  
Typ  
BR Grade  
Typ  
Test Conditions/  
Comments  
Parameter  
Unit  
Min  
Max  
Min  
Max  
POWER SUPPLY  
Operating Range  
Dual supply  
Single supply  
2.5  
5
18  
36  
2.5  
5
18  
36  
V
V
Quiescent Current  
Over Temperature  
2
2.3  
2.6  
2
2.3  
2.6  
mA  
mA  
TA = −40°C to +85°C  
TEMPERATURE RANGE  
For Specified Performance  
Operational5  
−40  
−40  
+85  
+125  
−40  
−40  
+85  
+125  
°C  
°C  
1 Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information.  
2 Total RTI VOS = (VOSI) + (VOSO/G).  
3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table.  
4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage.  
See the Input Voltage Range section for more details.  
5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C.  
ARM AND BRM GRADES  
Table 2.  
ARM Grade  
Typ  
BRM Grade  
Typ  
Test Conditions/  
Comments  
Parameter  
Unit  
Min  
Max  
Min  
Max  
COMMON-MODE REJECTION  
RATIO (CMRR)  
CMRR DC to 60 Hz with 1 kΩ  
Source Imbalance  
VCM = −10 V to +10 V  
G = 1  
G = 10  
G = 100  
G = 1000  
Over Temperature, G = 1  
CMRR at 20 kHz  
G = 1  
G = 10  
G = 100  
84  
92  
dB  
dB  
dB  
dB  
dB  
104  
124  
134  
80  
112  
132  
140  
90  
TA = −40°C to +85°C  
VCM = −10 V to +10 V  
80  
90  
100  
100  
80  
90  
100  
100  
dB  
dB  
dB  
dB  
G = 1000  
NOISE  
Voltage Noise, 1 kHz1  
Input Voltage Noise, eni  
Output Voltage Noise, eno  
Peak to Peak, RTI  
G = 1  
VIN+, VIN− = 0 V  
3
3.2  
60  
3
3.2  
60  
nV/√Hz  
nV/√Hz  
f = 0.1 Hz to 10 Hz  
2
0.5  
0.07  
2
0.5  
0.07  
2.2  
μV p-p  
μV p-p  
μV p-p  
G = 10  
G = 100 to 1000  
Current Noise  
Spectral Density  
Peak to Peak, RTI  
VOLTAGE OFFSET2  
Input Offset Voltage, VOSI  
Over Temperature  
Average TC  
0.09  
f = 1 kHz  
f = 0.1 Hz to 10 Hz  
200  
18  
200  
18  
fA/√Hz  
pA p-p  
VS = 5 V to 15 V  
TA = −40°C to +85°C  
70  
135  
0.9  
600  
1
50  
135  
0.9  
400  
1
μV  
μV  
μV/°C  
μV  
mV  
Output Offset Voltage, VOSO  
Over Temperature  
Average TC  
TA = −40°C to +85°C  
9
9
μV/°C  
Rev. 0 | Page 5 of 28  
 
 
AD8421  
Data Sheet  
ARM Grade  
Typ  
BRM Grade  
Typ  
Test Conditions/  
Comments  
Parameter  
Offset RTI vs. Supply (PSR)  
G = 1  
Unit  
Min  
Max  
Min  
Max  
VS = 2.5 V to 18 V  
90  
120  
120  
130  
140  
100  
120  
140  
140  
120  
140  
150  
150  
dB  
dB  
dB  
dB  
G = 10  
G = 100  
G = 1000  
110  
124  
130  
INPUT CURRENT  
Input Bias Current  
Over Temperature  
Average TC  
Input Offset Current  
Over Temperature  
Average TC  
DYNAMIC RESPONSE  
Small Signal Bandwidth  
G = 1  
1
2
8
0.1  
1
6
nA  
nA  
pA/°C  
nA  
nA  
TA = −40°C to +85°C  
TA = −40°C to +85°C  
−3 dB  
50  
0.5  
50  
0.1  
2
3
1
1.5  
1
1
pA/°C  
10  
10  
2
10  
10  
2
MHz  
MHz  
MHz  
MHz  
G = 10  
G = 100  
G = 1000  
0.2  
0.2  
Settling Time 0.01%  
G = 1  
G = 10  
G = 100  
G = 1000  
Settling Time 0.001%  
G = 1  
G = 10  
G = 100  
G = 1000  
10 V step  
10 V step  
0.7  
0.4  
0.6  
5
0.7  
0.4  
0.6  
5
μs  
μs  
μs  
μs  
1
1
μs  
μs  
μs  
μs  
0.6  
0.8  
6
0.6  
0.8  
6
Slew Rate  
G = 1 to 100  
GAIN3  
Gain Range  
Gain Error  
35  
35  
V/μs  
V/V  
G = 1 + (9.9 kΩ/RG)  
1
10,000  
1
10,000  
VOUT  
= 10 V  
G = 1  
0.05  
0.3  
0.02  
0.2  
%
%
G = 10 to 1000  
Gain Nonlinearity  
G = 1  
VOUT = −10 V to +10 V  
RL ≥ 2 kΩ  
RL = 600 Ω  
RL ≥ 600 Ω  
VOUT = −5V to +5V  
1
3
50  
10  
1
3
50  
10  
ppm  
ppm  
ppm  
ppm  
1
30  
5
1
30  
5
G = 10 to 1000  
Gain vs. Temperature3  
G = 1  
G > 1  
5
−50  
0.1  
1
−50  
ppm/°C  
ppm/°C  
INPUT  
Input Impedance  
Differential  
Common Mode  
Input Operating Voltage  
Range4  
30||3  
30||3  
30||3  
30||3  
GΩ||pF  
GΩ||pF  
V
VS = 2.5 V to 18 V  
−VS + 2.3  
+VS − 1.8  
−VS + 2.3  
+VS − 1.8  
Over Temperature  
TA = −40°C  
TA = +85°C  
−VS + 2.5  
−VS + 2.1  
+VS − 2.0  
+VS − 1.8  
−VS + 2.5  
−VS + 2.1  
+VS − 2.0  
+VS − 1.8  
V
V
Rev. 0 | Page 6 of 28  
 
Data Sheet  
AD8421  
ARM Grade  
Typ  
BRM Grade  
Typ Max  
Test Conditions/  
Comments  
Parameter  
OUTPUT  
Unit  
Min  
Max  
Min  
RL = 2 kΩ  
Output Swing  
Over Temperature  
VS = 2.5 V to 18 V  
TA = −40°C to +85°C  
−VS + 1.2  
−VS + 1.2  
+VS − 1.6  
+VS − 1.6  
−VS + 1.2  
−VS + 1.2  
+Vs − 1.6  
+Vs − 1.6  
V
V
Short-Circuit Current  
REFERENCE INPUT  
RIN  
65  
65  
mA  
20  
20  
20  
20  
kΩ  
μA  
V
IIN  
VIN+, VIN− = 0 V  
24  
+VS  
24  
+VS  
Voltage Range  
Reference Gain to Output  
−VS  
−VS  
1
1
V/V  
0.0001  
0.0001  
POWER SUPPLY  
Operating Range  
Dual supply  
Single supply  
2.5  
5
18  
36  
2.5  
5
18  
36  
V
V
Quiescent Current  
Over Temperature  
2
2.3  
2.6  
2
2.3  
2.6  
mA  
mA  
TA = −40°C to +85°C  
TEMPERATURE RANGE  
For Specified Performance  
Operational5  
−40  
−40  
+85  
+125  
−40  
−40  
+85  
+125  
°C  
°C  
1 Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information.  
2 Total RTI VOS = (VOSI) + (VOSO/G).  
3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table.  
4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage.  
See the Input Voltage Range section for more information.  
5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C.  
Rev. 0 | Page 7 of 28  
 
AD8421  
Data Sheet  
ABSOLUTE MAXIMUM RATINGS  
Table 3.  
THERMAL RESISTANCE  
θJA is specified for a device in free air using a 4-layer JEDEC  
printed circuit board (PCB).  
Parameter  
Rating  
Supply Voltage  
18 V  
Output Short-Circuit Current Duration  
Maximum Voltage at −IN or +IN1  
Minimum Voltage at −IN or +IN  
Maximum Voltage at REF2  
Minimum Voltage at REF  
Storage Temperature Range  
Operating Temperature Range  
Maximum Junction Temperature  
ESD  
Indefinite  
Table 4.  
Package  
8-Lead SOIC  
8-Lead MSOP  
−VS + 40 V  
+VS − 40 V  
+VS + 0.3 V  
−VS − 0.3 V  
−65°C to +150°C  
−40°C to +125°C  
150°C  
θJA  
Unit  
°C/W  
°C/W  
107.8  
138.6  
ESD CAUTION  
Human Body Model  
2 kV  
Charged Device Model  
Machine Model  
1.25 kV  
0.2 kV  
1 For voltages beyond these limits, use input protection resistors. See the  
Theory of Operation section for more information.  
2 There are ESD protection diodes from the reference input to each supply, so  
REF cannot be driven beyond the supplies in the same way that +IN and −IN  
can. See the Reference Terminal section for more information.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rev. 0 | Page 8 of 28  
 
 
 
Data Sheet  
AD8421  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
AD8421  
1
2
3
4
8
7
6
5
–IN  
+V  
S
R
R
V
OUT  
G
G
REF  
–V  
+IN  
S
TOP VIEW  
(Not to Scale)  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
2, 3  
4
5
6
−IN  
RG  
Negative Input Terminal.  
Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (9.9 kΩ/RG).  
Positive Input Terminal.  
Negative Power Supply Terminal.  
Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output.  
+IN  
−VS  
REF  
VOUT  
+VS  
7
8
Output Terminal.  
Positive Power Supply Terminal.  
Rev. 0 | Page 9 of 28  
 
AD8421  
Data Sheet  
TYPICAL PERFORMANCE CHARACTERISTICS  
TA = 25°C, VS = 15 V, VREF = 0 V, RL = 2 kꢀ, unless otherwise noted.  
600  
600  
500  
400  
300  
200  
100  
0
500  
400  
300  
200  
100  
0
–60  
–40  
–20  
0
20  
40  
60  
–400  
–300  
–200  
–100  
0
100  
200  
300  
400  
INPUT OFFSET VOLTAGE (µV)  
OUTPUT OFFSET VOLTAGE (µV)  
Figure 4. Typical Distribution of Input Offset Voltage  
Figure 7. Typical Distribution of Output Offset Voltage  
1800  
1500  
1200  
900  
600  
300  
0
1200  
1000  
800  
600  
400  
200  
0
–2.0  
–1.5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
–2.0  
–1.5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
INPUT BIAS CURRENT (nA)  
INPUT OFFSET CURRENT (nA)  
Figure 5. Typical Distribution of Input Bias Current  
Figure 8. Typical Distribution of Input Offset Current  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
1400  
1200  
1000  
800  
600  
400  
200  
0
–20  
–15  
–10  
–5  
0
5
10  
15  
20  
–120  
–90  
–60  
–30  
0
30  
60  
90  
120  
PSRR (µV/V)  
CMRR (µV/V)  
Figure 6. Typical Distribution of PSRR (G = 1)  
Figure 9. Typical Distribution of CMRR (G = 1)  
Rev. 0 | Page 10 of 28  
 
 
Data Sheet  
AD8421  
15  
4
3
2
1
0
G = 1  
V
= ±15V  
G = 100  
S
10  
5
V
= ±5V  
S
V
= ±12V  
S
V
= ±2.5V  
S
0
–5  
–1  
–2  
–10  
–15  
–3  
–4  
–3  
–2  
–1  
0
1
2
3
4
–15  
–10  
–5  
0
5
10  
15  
OUTPUT VOLTAGE (V)  
OUTPUT VOLTAGE (V)  
Figure 10. Input Common-Mode Voltage vs. Output Voltage;  
VS = 12 V and 15 V (G = 1)  
Figure 13. Input Common-Mode Voltage vs. Output Voltage;  
VS = 2.5 V and 5 V (G = 100)  
4
40  
V
G = 1  
= 5V  
G = 1  
S
V
= ±5V  
S
30  
20  
3
2
1
0
10  
V
= ±2.5V  
S
0
–10  
–20  
–30  
–40  
–1  
–2  
–3  
–4  
–3  
–2  
–1  
0
1
2
3
4
–35 –30 –25 –20 –15 –10 –5  
0
5
10 15 20 25 30 35 40  
OUTPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
Figure 11. Input Common-Mode Voltage vs. Output Voltage;  
VS = 2.5 V and 5 V (G = 1)  
Figure 14. Input Overvoltage Performance; G = 1, +VS = 5 V, −VS = 0 V  
15  
30  
V
= ±15V  
V = ±15V  
S
G = 1  
G = 100  
S
10  
5
20  
10  
V
= ±12V  
S
0
0
–5  
–10  
–20  
–30  
–10  
–15  
–15  
–10  
–5  
0
5
10  
15  
–25 –20 –15 –10  
–5  
0
5
10  
15  
20  
25  
OUTPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
Figure 15. Input Overvoltage Performance; G = 1, VS = 15 V  
Figure 12. Input Common-Mode Voltage vs. Output Voltage;  
VS = 12 V and 15 V (G = 100)  
Rev. 0 | Page 11 of 28  
 
 
 
 
AD8421  
Data Sheet  
160  
140  
120  
100  
40  
V
= 5V  
GAIN = 1000  
S
G = 100  
30  
20  
GAIN = 100  
GAIN = 10  
10  
GAIN = 1  
0
80  
60  
40  
20  
0
–10  
–20  
–30  
–40  
–35 –30 –25 –20 –15 –10 –5  
0
5
10 15 20 25 30 35 40  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
INPUT VOLTAGE (V)  
Figure 16. Input Overvoltage Performance; +VS = 5 V, −VS = 0 V, G = 100  
Figure 19. Positive PSRR vs. Frequency  
160  
30  
V
= ±15V  
GAIN = 1000  
S
G = 100  
140 GAIN = 100  
20  
10  
GAIN = 10  
120  
GAIN = 1  
100  
0
80  
60  
40  
20  
0
–10  
–20  
–30  
–25 –20 –15 –10  
–5  
0
5
10  
15  
20  
25  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
INPUT VOLTAGE (V)  
Figure 17. Input Overvoltage Performance; VS = 15 V, G = 100  
Figure 20. Negative PSRR vs. Frequency  
2.5  
2.0  
70  
60  
50  
40  
30  
20  
10  
0
GAIN = 1000  
1.5  
1.0  
GAIN = 100  
GAIN = 10  
GAIN = 1  
0.5  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–10  
–20  
–30  
100  
–12 –10 –8 –6 –4 –2  
0
2
4
6
8
10 12 14  
1k  
10k  
100k  
1M  
10M  
COMMON-MODE VOLTAGE (V)  
FREQUENCY (Hz)  
Figure 18. Input Bias Current vs. Common-Mode Voltage  
Figure 21. Gain vs. Frequency  
Rev. 0 | Page 12 of 28  
 
 
Data Sheet  
AD8421  
6
4
160  
GAIN = 1000  
REPRESENTATIVE SAMPLES  
GAIN = 100  
GAIN = 10  
GAIN = 1  
140  
120  
100  
80  
2
0
–2  
–4  
–6  
–8  
60  
40  
0.1  
1
10  
100  
1k  
10k  
100k  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
Figure 25. Input Bias Current vs. Temperature  
Figure 22. CMRR vs. Frequency  
100  
80  
160  
140  
120  
100  
80  
GAIN = 1000  
REPRESENTATIVE SAMPLES  
GAIN = 1  
60  
GAIN = 100  
GAIN = 10  
40  
20  
GAIN = 1  
0
–20  
–40  
–60  
–80  
60  
40  
0.1  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
1
10  
100  
1k  
10k  
100k  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
Figure 23. CMRR vs. Frequency, 1 kΩ Source Imbalance  
Figure 26. Gain vs. Temperature (G = 1)  
2.0  
1.5  
1.0  
0.5  
0
15  
10  
5
REPRESENTATIVE SAMPLES  
GAIN = 1  
0
–5  
–10  
–15  
–0.5  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
WARM-UP TIME (Seconds)  
TEMPERATURE (°C)  
Figure 24. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time  
Figure 27. CMRR vs. Temperature (G = 1)  
Rev. 0 | Page 13 of 28  
AD8421  
Data Sheet  
3.0  
40  
35  
–SR  
2.5  
V
= ±15V  
S
30  
25  
20  
15  
10  
5
2.0  
1.5  
1.0  
0.5  
0
+SR  
V
= ±5V  
S
0
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 28. Supply Current vs. Temperature (G = 1)  
Figure 31. Slew Rate vs. Temperature, VS = 5 V (G = 1)  
+V  
80  
60  
S
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
I
SHORT+  
40  
20  
0
–20  
–40  
–60  
–80  
–100  
–120  
+2.5  
+2.0  
+1.5  
+1.0  
+0.5  
–40°C  
+25°C  
+85°C  
+105°C  
+125°C  
I
SHORT–  
–V  
S
2
4
6
8
10  
12  
14  
16  
18  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
SUPPLY VOLTAGE (±V )  
TEMPERATURE (°C)  
S
Figure 32. Input Voltage Limit vs. Supply Voltage  
Figure 29. Short-Circuit Current vs. Temperature (G = 1)  
+V  
S
40  
35  
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–SR  
+SR  
30  
25  
20  
15  
10  
5
–40°C  
+25°C  
+85°C  
+105°C  
+125°C  
+2.5  
+2.0  
+1.5  
+1.0  
+0.5  
–V  
S
0
0
2
4
6
8
10  
12  
14  
16  
18  
20  
–40 –25 –10  
5
20  
35  
50  
65  
80  
95 110 125  
SUPPLY VOLTAGE (±V )  
TEMPERATURE (°C)  
S
Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ  
Figure 30. Slew Rate vs. Temperature, VS = 15 V (G = 1)  
Rev. 0 | Page 14 of 28  
Data Sheet  
AD8421  
+V  
5
4
S
GAIN = 1  
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
3
2
–40°C  
+25°C  
+85°C  
+105°C  
+125°C  
1
0
+2.5  
+2.0  
+1.5  
+1.0  
+0.5  
–1  
–2  
–3  
–4  
–5  
R
R
= 2kΩ  
= 10kΩ  
L
L
–V  
S
–10  
–8  
–6  
–4  
–2  
0
2
4
6
8
10  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (±V )  
S
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 600 Ω  
Figure 37. Gain Nonlinearity (G = 1), RL = 10 kΩ, 2 kΩ  
5
4
15  
10  
GAIN = 1  
3
2
5
1
–40°C  
+25°C  
R
= 600Ω  
L
0
+85°C  
+105°C  
+125°C  
0
–5  
–1  
–2  
–3  
–4  
–5  
–10  
–15  
–10  
–8  
–6  
–4  
–2  
0
2
4
6
8
10  
100  
1k  
10k  
100k  
OUTPUT VOLTAGE (V)  
LOAD (Ω)  
Figure 35. Output Voltage Swing vs. Load Resistance  
Figure 38. Gain Nonlinearity (G = 1), RL = 600 Ω  
+V  
100  
80  
S
GAIN = 1000  
–2  
–4  
–6  
–8  
60  
40  
–40°C  
20  
R
= 600Ω  
+25°C  
+85°C  
+105°C  
+125°C  
L
0
+8  
+6  
+4  
+2  
–20  
–40  
–60  
–80  
–100  
–V  
S
–10  
–8  
–6  
–4  
–2  
0
2
4
6
8
10  
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10  
OUTPUT CURRENT (A)  
OUTPUT VOLTAGE (V)  
Figure 36. Output Voltage Swing vs. Output Current  
Figure 39. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT  
=
10 V  
Rev. 0 | Page 15 of 28  
AD8421  
Data Sheet  
100  
80  
10k  
1k  
GAIN = 1000  
60  
40  
20  
R
= 600Ω  
L
0
–20  
–40  
–60  
–80  
100  
10  
–100  
–5  
–4  
–3  
–2  
–1  
0
1
2
3
4
5
0.1  
1
10  
100  
1k  
10k  
100k  
OUTPUT VOLTAGE (V)  
FREQUENCY (Hz)  
Figure 40. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT  
=
5 V  
Figure 43. Current Noise Spectral Density vs. Frequency  
1k  
100  
GAIN = 1  
GAIN = 10  
10  
GAIN = 100  
GAIN = 1000  
5pA/DIV  
1s/DIV  
1
1
10  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
Figure 41. RTI Voltage Noise Spectral Density vs. Frequency  
Figure 44. 0.1 Hz to 10 Hz Current Noise  
30  
G = 1000, 40nV/DIV  
25  
20  
15  
10  
5
G = 1, 1µV/DIV  
1s/DIV  
0
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 42. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000)  
Figure 45. Large Signal Frequency Response  
Rev. 0 | Page 16 of 28  
Data Sheet  
AD8421  
5V/DIV  
5V/DIV  
720ns TO 0.01%  
1.12µs TO 0.001%  
3.8µs TO 0.01%  
5.76µs TO 0.001%  
0.002%/DIV  
0.002%/DIV  
1µs/DIV  
4µs/DIV  
Figure 46. Large Signal Pulse Response and Settling Time (G = 1),  
10 V Step, VS = 15 V, RL = 2 kΩ, CL = 100 pF  
Figure 49. Large Signal Pulse Response and Settling Time (G = 1000),  
10 V Step, VS = 15 V, RL = 2 kΩ, CL = 100 pF  
2500  
2000  
1500  
5V/DIV  
420ns TO 0.01%  
604ns TO 0.001%  
SETTLED TO 0.001%  
1000  
500  
0
0.002%/DIV  
SETTLED TO 0.01%  
1µs/DIV  
GAIN = 1  
18 20  
2
4
6
8
10  
12  
14  
16  
STEP SIZE (V)  
Figure 50. Settling Time vs. Step Size (G = 1), RL = 2 kΩ, CL = 100 pF  
Figure 47. Large Signal Pulse Response and Settling Time (G = 10),  
10 V Step, VS = 15 V, RL = 2 kΩ, CL = 100 pF  
GAIN = 1  
5V/DIV  
704ns TO 0.01%  
764ns TO 0.001%  
0.002%/DIV  
50mV/DIV  
1µs/DIV  
1µs/DIV  
Figure 51. Small Signal Pulse Response (G = 1), RL = 600 Ω, CL = 100 pF  
Figure 48. Large Signal Pulse Response and Settling Time (G = 100),  
10 V Step, VS = 15 V, RL = 2 kΩ, CL = 100 pF  
Rev. 0 | Page 17 of 28  
AD8421  
Data Sheet  
100pF  
G = 1  
GAIN = 10  
50pF  
20pF  
NO LOAD  
50mV/DIV  
1µs/DIV  
50mV/DIV  
1µs/DIV  
Figure 52. Small Signal Pulse Response (G = 10), RL = 600 Ω, CL = 100 pF  
Figure 55. Small Signal Response with Various Capacitive Loads (G = 1),  
RL = Infinity  
–40  
R
≥ 600Ω  
V
= 10V p-p  
GAIN = 100  
L
OUT  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
20mV/DIV  
1µs/DIV  
10  
100  
1k  
10k  
FREQUENCY (Hz)  
Figure 53. Small Signal Pulse Response (G = 100), RL = 600 Ω, CL = 100 pF  
Figure 56. Second Harmonic Distortion vs. Frequency (G = 1)  
–40  
NO LOAD  
V
= 10V p-p  
GAIN = 1000  
OUT  
–50  
–60  
R
R
= 2kΩ  
= 600Ω  
L
L
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
20mV/DIV  
2µs/DIV  
10  
100  
1k  
10k  
FREQUENCY (Hz)  
Figure 57. Third Harmonic Distortion vs. Frequency (G = 1)  
Figure 54. Small Signal Pulse Response (G = 1000), RL = 600 Ω, CL = 100 pF  
Rev. 0 | Page 18 of 28  
Data Sheet  
AD8421  
–40  
–20  
–30  
NO LOAD  
V
= 10V p-p  
G = 1  
V
= 10V p-p  
OUT  
OUT  
R = 2kΩ  
L
R
R
= 2kΩ  
= 600Ω  
G = 10  
G = 100  
G = 1000  
L
L
–50  
–60  
–40  
–50  
–60  
–70  
–70  
–80  
–80  
–90  
–90  
–100  
–110  
–120  
–130  
–140  
–100  
–110  
–120  
10  
100  
1k  
10k  
10  
100  
1k  
10k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 58. Second Harmonic Distortion vs. Frequency (G = 1000)  
Figure 60. THD vs. Frequency  
–40  
V
= 10V p-p  
R
≥ 600Ω  
OUT  
L
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
10  
100  
1k  
10k  
FREQUENCY (Hz)  
Figure 59. Third Harmonic Distortion vs. Frequency (G = 1000)  
Rev. 0 | Page 19 of 28  
AD8421  
Data Sheet  
THEORY OF OPERATION  
+V  
S
I
V
I
B
I
I
B
B
COMPENSATION  
COMPENSATION  
A1  
A2  
10kΩ  
+V  
–V  
C1  
C2  
S
10kΩ  
10kΩ  
NODE 1  
OUTPUT  
A3  
NODE 2  
+V  
S
R1  
4.95kΩ  
R2  
4.95kΩ  
S
Q1  
superβ  
Q2  
10kΩ  
ESD AND  
OVERVOLTAGE  
PROTECTION  
ESD AND  
OVERVOLTAGE  
PROTECTION  
+V  
+V  
S
S
REF  
superβ  
–IN  
+IN  
R
G
NODE 3  
NODE 4  
–V  
S
I
I
–V  
S
DIFFERENCE  
AMPLIFIER STAGE  
GAIN STAGE  
Figure 61. Simplified Schematic  
Users can easily and accurately set the gain using a single  
standard resistor.  
ARCHITECTURE  
The AD8421 is based on the classic 3-op-amp topology. This  
topology has two stages: a preamplifier to provide differential  
amplification, followed by a difference amplifier that removes the  
common-mode voltage. Figure 61 shows a simplified schematic  
of the AD8421.  
GAIN SELECTION  
Placing a resistor across the RG terminals sets the gain of the  
AD8421. The gain can be calculated by referring to Table 6 or  
by using the following gain equation:  
Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as  
precision current feedback amplifiers. Input Transistors Q1 and  
Q2 are biased at a fixed current so that any input signal forces  
the output voltages of A1 and A2 to change accordingly. The  
differential signal applied to the inputs is replicated across the  
RG pins. Any current through RG also flows through R1 and R2,  
creating a gained differential voltage between Node 1 and Node 2.  
9.9kΩ  
RG =  
G −1  
The AD8421 defaults to G = 1 when no gain resistor is used. To  
determine the total gain accuracy of the system, add the tolerance  
and gain drift of the RG resistor to the specifications of the AD8421.  
When the gain resistor is not used, gain error and gain drift are  
minimal.  
The amplified differential and common-mode signals are applied  
to a difference amplifier that rejects the common-mode voltage  
but preserves the amplified differential voltage. The difference  
amplifier employs innovations that result in very low output errors  
such as offset voltage and drift, distortion at various loads, as well  
as output noise. Laser-trimmed resistors allow for a highly accurate  
in-amp with gain error less than 0.01% and CMRR that exceeds  
94 dB (G = 1). The high performance pinout and special attention  
given to design and layout allow for high CMRR performance  
across a wide frequency and temperature range.  
Table 6. Gains Achieved Using 1% Resistors  
1% Standard Table Value of RG  
Calculated Gain  
10 kΩ  
2.49 kΩ  
1.1 kΩ  
523 Ω  
200 Ω  
100 Ω  
49.9 Ω  
20 Ω  
1.99  
4.98  
10.00  
19.93  
50.50  
100.0  
199.4  
496.0  
Using superbeta input transistors and bias current compensation,  
the AD8421 offers extremely high input impedance, low bias cur-  
rent, low offset current, low current noise, and extremely low  
voltage noise of 3 nV/√Hz. The current-limiting and overvoltage  
protection scheme allow the input to go 40 V from the opposite  
rail at all gains without compromising the noise performance.  
10 Ω  
991.0  
4.99 Ω  
1985  
RG Power Dissipation  
The AD8421 duplicates the differential voltage across its inputs  
onto the RG resistor. Choose an RG resistor size that is sufficient  
to handle the expected power dissipation at ambient temperature.  
The transfer function of the AD8421 is  
V
OUT = G × (V+IN − V−IN) + VREF  
9.9kΩ  
where G = 1 +  
RG  
Rev. 0 | Page 20 of 28  
 
 
 
 
 
Data Sheet  
AD8421  
Common-Mode Rejection Ratio over Frequency  
REFERENCE TERMINAL  
Poor layout can cause some of the common-mode signals to  
be converted to differential signals before reaching the in-amp.  
Such conversions occur when one input path has a frequency  
response that is different from the other. To maintain high CMRR  
over frequency, closely match the input source impedance and  
capacitance of each path. Place additional source resistance in  
the input path (for example, input protection resistors) close to  
the in-amp inputs, to minimize the interaction of the resistance  
with parasitic capacitance from the PCB traces.  
The output voltage of the AD8421 is developed with respect to  
the potential on the reference terminal. This can be used to sense  
the ground at the load, thereby taking advantage of the CMRR to  
reject ground noise or to introduce a precise offset to the signal  
at the output. For example, a voltage source can be tied to the REF  
pin to level shift the output, allowing the AD8421 to drive a single-  
supply ADC. The REF pin is protected with ESD diodes and  
should not exceed either +VS or −VS by more than 0.3 V.  
For best performance, maintain a source impedance to the  
REF terminal that is below 1 ꢀ. As shown in Figure 61, the  
reference terminal, REF, is at one end of a 10 kΩ resistor.  
Additional impedance at the REF terminal adds to this 10 kΩ  
resistor and results in amplification of the signal connected to  
the positive input. The amplification from the additional RREF  
can be calculated as follows:  
Parasitic capacitance at the gain setting pins (RG) can also affect  
CMRR over frequency. If the board design has a component at  
the gain setting pins (for example, a switch or jumper), choose  
a component such that the parasitic capacitance is as small as  
possible.  
Power Supplies and Grounding  
2(10 kΩ + RREF)/(20 kΩ + RREF  
)
Use a stable dc voltage to power the instrumentation amplifier.  
Noise on the supply pins can adversely affect performance.  
Only the positive signal path is amplified; the negative path is  
unaffected. This uneven amplification degrades CMRR.  
Place a 0.1 μF capacitor as close as possible to each supply pin.  
Because the length of the bypass capacitor leads is critical at  
high frequency, surface-mount capacitors are recommended.  
Any parasitic inductance in the bypass ground trace works against  
the low impedance that is created by the bypass capacitor. As  
shown in Figure 64, a 10 μF capacitor can be used farther away  
from the device. For these larger value capacitors, which are  
intended to be effective at lower frequencies, the current return  
path distance is less critical. In most cases, the 10 μF capacitor  
can be shared by other local precision integrated circuits.  
INCORRECT  
CORRECT  
AD8421  
AD8421  
REF  
REF  
V
V
+
OP1177  
–
+V  
S
Figure 62. Driving the Reference Pin  
0.1µF  
10µF  
INPUT VOLTAGE RANGE  
+IN  
–IN  
The 3-op-amp architecture of the AD8421 applies gain in the  
first stage before removing the common-mode voltage in the  
difference amplifier stage. Internal nodes between the first and  
second stages (Node 1 and Node 2 in Figure 61) experience  
a combination of a gained signal, a common-mode signal, and  
a diode drop. The voltage supplies can limit the combined signal,  
even when the individual input and output signals are not limited.  
Figure 10 through Figure 13 show this limitation in detail.  
V
OUT  
R
G
AD8421  
LOAD  
REF  
0.1µF  
10µF  
–V  
S
Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground  
LAYOUT  
A ground plane layer helps to reduce parasitic inductances, which  
minimizes voltage drops with changes in current. The area of  
the current path is directly proportional to the magnitude of  
parasitic inductances and, therefore, the impedance of the path  
at high frequency. Large changes in currents in an inductive  
decoupling path or ground return create unwanted effects due  
to the coupling of such changes into the amplifier inputs.  
To ensure optimum performance of the AD8421 at the PCB level,  
care must be taken in the design of the board layout. The pins of  
the AD8421 are arranged in a logical manner to aid in this task.  
1
2
3
4
8
7
6
5
+V  
V
–IN  
S
R
R
G
G
OUT  
REF  
–V  
+IN  
Because load currents flow from the supplies, the load should be  
connected at the same physical location as the bypass capacitor  
grounds.  
S
AD8421  
TOP VIEW  
(Not to Scale)  
Figure 63. Pin Configuration Diagram  
Rev. 0 | Page 21 of 28  
 
 
 
 
AD8421  
Data Sheet  
Reference Pin  
protection required at all gains. For example, if +VS = +5 V and  
−VS = −8 V, the part can safely withstand voltages from −35 V to  
+32 V.  
The output voltage of the AD8421 is developed with respect to  
the potential on the reference terminal. Ensure that REF is tied  
to the appropriate local ground.  
The remaining AD8421 terminals should be kept within the  
supplies. All terminals of the AD8421 are protected against ESD.  
INPUT BIAS CURRENT RETURN PATH  
Input Voltages Beyond the Maximum Ratings  
The input bias current of the AD8421 must have a return path  
to ground. When using a floating source without a current return  
path (such as a thermocouple), create a current return path as  
shown in Figure 65.  
For applications where the AD8421 encounters voltages beyond the  
limits in the Absolute Maximum Ratings table, external protection  
is required. This external protection depends on the duration of  
the overvoltage event and the noise performance that is required.  
INCORRECT  
CORRECT  
+V  
+V  
S
S
For short-lived events, transient protectors (such as metal oxide  
varistors (MOVs)), may be all that is required.  
+V  
+V  
S
S
R
PROTECT  
AD8421  
AD8421  
+
IN+  
–
+
IN+  
–
I
I
V
V
REF  
REF  
REF  
REF  
AD8421  
AD8421  
R
PROTECT  
–V  
S
–V  
S
+
IN–  
–
+
IN–  
–
V
–V  
S
–V  
S
V
TRANSFORMER  
TRANSFORMER  
+V  
+V  
S
S
TRANSIENT PROTECTION  
SIMPLE CONTINUOUS PROTECTION  
+V  
S
+V  
+V  
S
S
R
R
PROTECT  
I
PROTECT  
I
+
+
IN+  
–
AD8421  
AD8421  
V
V
V
IN+  
–
–V  
+V  
S
REF  
AD8421  
AD8421  
S
10MΩ  
R
R
PROTECT  
PROTECT  
+
IN–  
–
+
IN–  
–
–V  
–V  
S
S
–V  
–V  
S
V
S
–V  
S
THERMOCOUPLE  
THERMOCOUPLE  
LOW NOISE CONTINUOUS  
OPTION 1  
LOW NOISE CONTINUOUS  
OPTION 2  
+V  
+V  
S
S
C
C
C
Figure 67. Input Protection Options for Input Voltages Beyond Absolute  
Maximum Ratings  
R
R
1
fHIGH-PASS  
=
AD8421  
2πRC  
AD8421  
For longer events, use resistors in series with the inputs, combined  
with diodes. To avoid degrading bias current performance, low  
leakage diodes such as the BAV199 or FJH1100 are recommended.  
The diodes prevent the voltage at the input of the amplifier from  
exceeding the maximum ratings, and the resistors limit the current  
into the diodes. Because most external diodes can easily handle  
100 mA or more, resistor values do not need to be large and,  
therefore, have a minimal impact on noise performance.  
C
REF  
–V  
–V  
S
S
CAPACITIVELY COUPLED  
CAPACITIVELY COUPLED  
Figure 65. Creating an Input Bias Current Return Path  
INPUT VOLTAGES BEYOND THE SUPPLY RAILS  
The AD8421 has very robust inputs. It typically does not need  
additional input protection, as shown in Figure 66.  
At the expense of some noise performance, another solution is  
to use series resistors. In the case of overvoltage, current into  
the AD8421 inputs is internally limited. Although the AD8421  
inputs must be kept within the limits defined in the Absolute  
Maximum Ratings section, the I × R drop across the protection  
resistor increases the maximum voltage that the system can  
withstand, as follows:  
+V  
S
+
IN+  
–
I
V
AD8421  
+
IN+  
–
–V  
S
V
For positive input signals  
MOST APPLICATIONS  
V
MAX_NEW = (40 V + Negative Supply) + IIN × RPROTECT  
For negative input signals  
MIN_NEW = (Positive Supply − 40 V) − IOUT × RPROTECT  
Figure 66. Typical Application; No Input Protection Required  
The AD8421 inputs are current limited; therefore, input voltages  
can be up to 40 V from the opposite supply rail, with no input  
V
Rev. 0 | Page 22 of 28  
 
 
 
Data Sheet  
AD8421  
Overvoltage performance is shown in Figure 14, Figure 15,  
Figure 16, and Figure 17. The AD8421 inputs can withstand  
a current of 40 mA at room temperature for at least a day. This  
time is cumulative over the life of the device. If long periods of  
overvoltage are expected, the use of an external protection method  
is recommended. Under extreme input conditions, the output  
of the amplifier may invert.  
To achieve low noise and sufficient RFI filtering, the use of chip  
ferrite beads is recommended. Ferrite beads increase their impe-  
dance with frequency, thus leaving the signal of interest unaffected  
while preventing RF interference to reach the amplifier. They also  
help to eliminate the need for large resistor values in the filter,  
thus minimizing the system’s input-referred noise. The selection  
of the appropriate ferrite bead and capacitor values is a function  
of the interference frequency, input lead length, and RF power.  
RADIO FREQUENCY INTERFERENCE (RFI)  
For best results, place the RFI filter network as close as possible  
to the amplifier. Layout is critical to ensure that RF signals are  
not picked up on the traces after the filter. If RF interference is  
too strong to be filtered sufficiently, shielding is recommended.  
RF rectification is often a problem when amplifiers are used in  
applications that have strong RF signals. The problem is intensified  
if long leads or PCB traces are required to connect the amplifier  
to the signal source. The disturbance can appear as a dc offset  
voltage or a train of pulses.  
The resistors used for the RFI filter can be the same as those used  
for input protection.  
High frequency signals can be filtered with a low-pass filter  
network at the input of the instrumentation amplifier, as shown  
in Figure 68.  
CALCULATING THE NOISE OF THE INPUT STAGE  
The total noise of the amplifier front end depends on much more  
than the 3.2 nV/√Hz specification of this data sheet. The three  
main contributors to noise are: the source resistance, the voltage  
noise of the instrumentation amplifier, and the current noise of  
the instrumentation amplifier.  
+V  
S
0.1µF  
+IN  
10µF  
C
1nF  
C
L*  
L*  
R
In the following calculations, noise is referred to the input (RTI).  
In other words, all sources of noise are calculated as if the source  
appeared at the amplifier input. To calculate the noise referred  
to the amplifier output (RTO), multiply the RTI noise by the  
gain of the instru-mentation amplifier.  
33Ω  
V
C
OUT  
D
AD8421  
10nF  
R
REF  
–IN  
33Ω  
C
C
1nF  
Source Resistance Noise  
0.1µF  
10µF  
Any sensor connected to the AD8421 has some output resistance.  
There may also be resistance placed in series with inputs for pro-  
tection from either overvoltage or radio frequency interference.  
This combined resistance is labeled R1 and R2 in Figure 69. Any  
resistor, no matter how well made, has an intrinsic level of noise.  
This noise is proportional to the square root of the resistor value.  
At room temperature, the value is approximately equal to  
4 nV/√Hz × √(resistor value in kΩ).  
–V  
S
*CHIP FERRITE BEAD.  
Figure 68. RFI Suppression  
The choice of resistor and capacitor values depends on the  
desired trade-off between noise, input impedance at high  
frequencies, CMRR, signal bandwidth, and RFI immunity. An  
RC network limits both the differential and common-mode  
bandwidth, as shown in the following equations:  
SENSOR  
1
FilterFrequencyDIFF  
FilterFrequencyCM  
=
2πR(2CD +CC )  
R
R1  
R2  
G
AD8421  
1
=
2πRCC  
where CD ≥ 10 CC.  
Figure 69. Source Resistance from Sensor and Protection Resistors  
CD affects the differential signal, and CC affects the common-  
mode signal. A mismatch between R × CC at the positive input  
and R × CC at the negative input degrades the CMRR of the  
AD8421. By using a value of CD that is one order of magnitude  
larger than CC, the effect of the mismatch is reduced and CMRR  
performance is improved near the cutoff frequencies.  
For example, assume that the combined sensor and protection  
resistance is 4 kΩ on the positive input and 1 kΩ on the negative  
input. Then the total noise from the input resistance is  
2
2
(
4× 4  
)
+
(
4× 1  
)
= 64 +16 = 8.9 nV/√Hz  
Rev. 0 | Page 23 of 28  
 
 
 
 
AD8421  
Data Sheet  
Voltage Noise of the Instrumentation Amplifier  
For example, if the R1 source resistance in Figure 69 is 4 kΩ,  
and the R2 source resistance is 1 kΩ, the total effect from the  
current noise is calculated as follows:  
The voltage noise of the instrumentation amplifier is calculated  
using three parameters: the device output noise, the input noise,  
and the RG resistor noise. It is calculated as follows:  
2
2
)
(
4 × 0.2  
)
+
(1× 0.2  
= 0.8 nV/√Hz  
Total Voltage Noise =  
Total Noise Density Calculation  
2
2
2
(
OutputNoise/G  
)
+
(
InputNoise  
)
+
(
Noise of RG Resistor  
)
To determine the total noise of the in-amp, referred to input,  
combine the source resistance noise, voltage noise, and current  
noise contribution by the sum of squares method.  
For example, for a gain of 100, the gain resistor is 100 Ω. Therefore,  
the voltage noise of the in-amp is  
For example, if the R1 source resistance in Figure 69 is 4 kΩ, the  
R2 source resistance is 1 kΩ, and the gain of the in-amp is 100,  
the total noise, referred to input, is  
2
2
(
60 /100  
)
+ 3.22 +  
(
4 × 0.1  
)
= 3.5 nV/√Hz  
Current Noise of the Instrumentation Amplifier  
8.92 + 3.52 + 0.82 = 9.6 nV/√Hz  
Current noise is converted to a voltage by the source resistance.  
The effect of current noise can be calculated by multiplying the  
specified current noise of the in-amp by the value of the source  
resistance.  
Rev. 0 | Page 24 of 28  
Data Sheet  
AD8421  
APPLICATIONS INFORMATION  
Although the dc performance and resistor matching of the op amp  
affect the dc common-mode output accuracy, such errors are  
likely to be rejected by the next device in the signal chain and,  
therefore, typically have little effect on overall system accuracy.  
DIFFERENTIAL OUTPUT CONFIGURATION  
Figure 70 shows an example of how to configure the AD8421 for  
differential output.  
+IN  
Because this circuit is susceptible to instability, a capacitor is  
included to limit the effective op amp bandwidth. This capacitor  
can be omitted if the amplifier pairing is stable.  
+OUT  
AD8421  
–IN  
10kΩ  
REF  
V
BIAS  
The open-loop gain and phase of any amplifier may vary with  
process variation and temperature. Additional phase lag can be  
introduced by resistive or capacitive loading. To guarantee  
stability, the value of the capacitor in Figure 70 should be  
determined with a sample of circuits by evaluating the small signal  
pulse response of the circuit with load at the extremes of the  
output dynamic range.  
–
+
10kΩ  
OP AMP  
12pF  
–OUT  
Figure 70. Differential Output Configuration with Op Amp  
The ambient temperature should also be varied over the expected  
range to evaluate its effect on stability. The voltage at +OUT may  
still have some overshoot after the circuit is tuned because the  
AD8421 output amplifier responds faster than the op amp. A 12 pF  
capacitor is a good starting point.  
The differential output voltage is set by the following equation:  
V
DIFF_OUT = V+OUT − V−OUT = Gain × (V+IN − V−IN  
The common-mode output is set by the following equation:  
CM_OUT = (V+OUT + V−OUT)/2 = VBIAS  
)
V
For best large signal ac performance, use an op amp with a high  
slew rate to match the AD8421 performance of 35 V/μs. High  
bandwidth is not essential because the system bandwidth is limited  
by the RC feedback. Some good choices for op amps are the  
AD8610, ADA4627-1, AD8510, and the ADA4898-1.  
The advantage of this circuit is that the dc differential accuracy  
depends on the AD8421, not on the op amp or the resistors. In  
addition, this circuit takes advantage of the precise control that the  
AD8421 has of its output voltage relative to the reference voltage.  
Rev. 0 | Page 25 of 28  
 
 
AD8421  
Data Sheet  
frequency, and set the filter cutoff to settle to ½ LSB in one  
sampling period for a full-scale step. For additional considerations,  
DRIVING AN ADC  
The Class AB output stage, low noise and distortion, and high  
bandwidth and slew rate make the AD8421 a good choice for  
driving an ADC in a data acquisition system that requires front-  
end gain, high CMRR, and dc precision. Figure 71 shows the  
AD8421, in a gain-of-10 configuration, driving the AD7685,  
a 16-bit, 250 kSPS pseudodifferential SAR ADC. The RC low-pass  
filter that is shown between the AD8421 and the AD7685 has  
several purposes. It isolates the amplifier output from excessive  
loading from the dynamic ADC inputs, reduces the noise  
bandwidth of the amplifier, and provides overload protection for  
the AD7685 analog inputs. The filter cutoff can be determined  
empirically. To achieve the best ac performance, keep the impe-  
dance magnitude greater than 1 kꢀ at the maximum input signal  
refer to the data sheet of the ADC in use.  
In a gain-of-10 configuration, the AD8421 has approximately  
8 nV/√Hz voltage noise RTI (See the Calculating the Noise of  
the Input Stage section.) The front-end gain makes the system  
ten times more sensitive to input signals, with only a 7.5 dB  
reduction of SNR. The high current output and load regulation  
of the ADR435 allow the AD7685 to be powered directly from the  
reference without the need to provide another analog supply rail.  
The reference pin buffer may be any low power, unity-gain stable,  
dc precision op amp with less than approximately 25 nV/√Hz of  
wideband noise, such as the OP1177. Not all proper decoupling is  
shown in Figure 71. Take care to follow decoupling guidelines for  
both amplifiers and the ADR435.  
+5V  
10Ω  
+12V  
ADR435  
10kΩ  
10kΩ  
1µF  
0.1µF  
2.5V  
±250mV  
+12V  
+IN  
–IN  
G = 10  
REF  
VDD  
VIO  
SDI  
100Ω  
3nF  
1.1kΩ  
IN+  
AD8421  
SCK  
SDO  
CNV  
REF  
3- OR 4-WIRE INTERFACE  
AD7685  
–12V  
IN–  
GND  
2.5V  
10µF  
5kΩ  
Figure 71. AD8421 Driving an ADC  
0
SNR 81.12dB  
THD –100.91dB  
SFDR 90.71dB  
–20  
–40  
–60  
–80  
–100  
–120  
–140  
–160  
0
25  
50  
75  
100  
125  
FREQUENCY (kHz)  
Figure 72. Typical Spectrum of the AD8421 (G = 10) Driving the AD7685  
Rev. 0 | Page 26 of 28  
 
 
Data Sheet  
AD8421  
OUTLINE DIMENSIONS  
5.00 (0.1968)  
4.80 (0.1890)  
8
1
5
4
6.20 (0.2441)  
5.80 (0.2284)  
4.00 (0.1574)  
3.80 (0.1497)  
0.50 (0.0196)  
0.25 (0.0099)  
1.27 (0.0500)  
BSC  
45°  
1.75 (0.0688)  
1.35 (0.0532)  
0.25 (0.0098)  
0.10 (0.0040)  
8°  
0°  
0.51 (0.0201)  
0.31 (0.0122)  
COPLANARITY  
0.10  
1.27 (0.0500)  
0.40 (0.0157)  
0.25 (0.0098)  
0.17 (0.0067)  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MS-012-AA  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 73. 8-Lead Standard Small Outline Package [SOIC_N]  
Narrow Body  
(R-8)  
Dimensions shown in millimeters and (inches)  
3.20  
3.00  
2.80  
8
1
5
4
5.15  
4.90  
4.65  
3.20  
3.00  
2.80  
PIN 1  
IDENTIFIER  
0.65 BSC  
0.95  
0.85  
0.75  
15° MAX  
1.10 MAX  
0.80  
0.55  
0.40  
0.15  
0.05  
0.23  
0.09  
6°  
0°  
0.40  
0.25  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-187-AA  
Figure 74. 8-Lead Mini Small Outline Package [MSOP]  
(RM-8)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
Package Description  
Package Option  
Branding  
AD8421ARZ  
AD8421ARZ-R7  
AD8421ARZ-RL  
AD8421BRZ  
AD8421BRZ-R7  
AD8421BRZ-RL  
AD8421ARMZ  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
8-Lead SOIC_N, standard grade  
R-8  
R-8  
R-8  
R-8  
R-8  
8-Lead SOIC_N, standard grade, 7”Tape and Reel,  
8-Lead SOIC_N, standard grade, 13”Tape and Reel  
8-Lead SOIC_N, high performance grade  
8-Lead SOIC_N, high performance grade, 7”Tape and Reel  
8-Lead SOIC_N, high performance grade, 13”Tape and Reel R-8  
8-Lead MSOP, standard grade  
RM-8  
Y49  
Y49  
Y49  
Y4A  
Y4A  
Y4A  
AD8421ARMZ-R7 −40°C to +85°C  
AD8421ARMZ-RL −40°C to +85°C  
8-Lead MSOP, standard grade, 7”Tape and Reel  
8-Lead MSOP, standard grade, 13”Tape and Reel  
8-Lead MSOP, high performance grade  
8-Lead MSOP, high performance grade, 7”Tape and Reel  
8-Lead MSOP, high performance grade, 13”Tape and Reel  
RM-8  
RM-8  
RM-8  
RM-8  
RM-8  
AD8421BRMZ  
AD8421BRMZ-R7 −40°C to +85°C  
AD8421BRMZ-RL −40°C to +85°C  
−40°C to +85°C  
1 Z = RoHS Compliant Part.  
Rev. 0 | Page 27 of 28  
 
 
AD8421  
NOTES  
Data Sheet  
©2012 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D10123-0-5/12(0)  
Rev. 0 | Page 28 of 28  
 
 
 

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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