AD8432ACPZ-RL [ADI]
Dual-Channel Ultralow Noise Amplifier with Selectable Gain and Input Impedance; 双通道超低噪声放大器，具有可选择的增益和输入阻抗
| 型号： | AD8432ACPZ-RL |
| 厂家： | 
ADI |
| 描述： | Dual-Channel Ultralow Noise Amplifier with Selectable Gain and Input Impedance |
| 文件： | 总28页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel Ultralow Noise Amplifier with
Selectable Gain and Input Impedance
AD8432
FUNCTIONAL BLOCK DIAGRAM
FEATURES
ENB
VPS1
VPS2
COMM
Low noise
Input voltage noise: 0.85 nV/√Hz
Current noise: 2.0 pA/√Hz
Excellent ac specifications
200 MHz bandwidth (G = 12.04 dB)
295 V/μs slew rate
Selectable gain
G = 12.04 dB (×4)
G = 18.06 dB (×8)
BIAS
AD8432
INH1
IND1
OPH1
OPL1
LNA1
GMH1
GOH1
GOL1
GML1
INL1
INH2
IND2
G = 21.58 dB (×12)
G = 24.08 dB (×16)
OPH2
OPL2
LNA2
Active input impedance matching
Integrated input clamp diodes
Single-ended input, differential output
Supply range: 4.5 V to 5.5 V
Low power: 60 mW/channel
GMH2
GOH2
GOL2
GML2
INL2
Figure 1.
APPLICATIONS
CW Doppler ultrasound front ends
Low noise preamplification
Predriver for I/Q demodulators and phase shifters
Wideband analog-to-digital drivers
GENERAL DESCRIPTION
The AD8432 is a dual-channel, low power, ultralow noise
amplifier with selectable gain and active impedance matching.
Each amplifier has a single-ended input, differential output, and
integrated input clamps. By pin strapping the gain setting pins, four
accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB
(×4, ×8, ×12, and ×16) are possible. A bandwidth of 200 MHz at
G = 12.04 dB makes this amplifier well suited for many high speed
applications.
The AD8432 achieves 0.85 nV/√Hz input referred voltage noise for
a gain of 12.04 dB. The AD8432’s ultralow noise, low distortion,
excellent gain accuracy, and channel-to-channel matching are ideal
for high performance ultrasound systems and for processing I/Q
demodulator signals.
The AD8432 operates on a single supply of 5 V at 24 mA. It is
available in a 4 mm × 4 mm, 24-lead LFSCP. The LFCSP features
an exposed paddle that provides a low thermal resistance path to
the PCB, which enables more efficient heat transfer and increases
reliability. The operating temperature range is −40°C to +85°C.
The exceptional noise performance of the AD8432 is made
possible by the active impedance matching. Using a feedback
network, the input impedance of the amplifiers can be adjusted
to match the signal source impedance without compromising
the noise performance. Impedance matching and low noise of
the AD8432 allow designers to create wider dynamic range
systems that are able to detect even very low level signals.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD8432
TABLE OF CONTENTS
Features .............................................................................................. 1
Low Noise Amplifier (LNA) ..................................................... 18
Gain Setting Technique ............................................................. 18
Active Input Resistance Matching............................................ 19
Applications Information.............................................................. 21
Typical Setup............................................................................... 21
I/Q Demodulation Front End................................................... 23
Differential-to-Single-Ended Conversion............................... 24
Evaluation Board ............................................................................ 25
Gain Setting................................................................................. 25
Power Supply............................................................................... 27
Input Termination...................................................................... 27
Output.......................................................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 16
Theory of Operation ...................................................................... 18
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8432
SPECIFICATIONS
VS = 5 V, TA = 25°C, RS = RIN = 50 Ω, RFB =150 ꢀ, CSH = 47 pF, RSH = 15 ꢀ, RL = 500 Ω (per SE output), CL = 5 pF (per SE output),
G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Gain Range
Input to differential output (selectable gain)
Input to single output (selectable gain)
12.04
6.02
24.08
18.06
1
dB
dB
dB
Gain Error
0.1
−3 dB Small Signal Bandwidth
RIN unterminated, RFB = ∞, CSH = 0 pF, RSH = 0 Ω
G = 12.04 dB
200
90
50
32
42
295
170
10
MHz
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
G = 18.06 dB
G = 21.58 dB
G = 24.08 dB
VOUT = 2 V p-p
VOUT = 2 V p-p, f = 10 MHz
VOUT = 2 V p-p, f = 10 MHz
−3 dB Large Signal Bandwidth
Slew Rate (Rising Edge)
Slew Rate (Falling Edge)
Overdrive Recovery Time
DISTORTION/NOISE PERFORMANCE
Input Voltage Noise
RFB = ∞
RFB = ∞
0.85
2.0
nV/√Hz
pA/√Hz
Input Current Noise
Noise Figure
Unterminated
Active Termination
RS = 50 Ω, RFB = ∞
2.8
4.8
4.2
3.2
2.1
2.3
3.4
6.8
10.2
13.6
dB
dB
dB
dB
dB
dB
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
RS = RIN = 50 Ω, RFB = 150 Ω
RS = 50 Ω, RFB = 226 Ω, RIN = 75 Ω
RS = 50 Ω, RFB = 301 Ω, RIN = 100 Ω
RS = 50 Ω, RFB = 619 Ω, RIN = 200 Ω
RS = 50 Ω, RFB = 3.57 kΩ, RIN = 1 kΩ
G = 12.04 dB, RFB = ∞
G = 18.06 dB, RFB = ∞
G = 21.58 dB, RFB = ∞
G = 24.08 dB, RFB = ∞
Output Referred Noise
Harmonic Distortion
1 MHz (VOUT = 1 V p-p)
HD2
−67
−74
−103
−106
−65
−72
−103
−92
−66
−62
−78
−73
−60
−56
−72
−65
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
HD2, RS = 50 Ω, RIN unterminated
HD3
HD3, RS = 50 Ω, RIN unterminated
HD2
HD2, RS = 50 Ω, RIN unterminated
HD3
HD3, RS = 50 Ω, RIN unterminated
HD2
HD2, RS = 50 Ω, RIN unterminated
HD3
HD3, RS = 50 Ω, RIN unterminated
HD2
HD2, RS = 50 Ω, RIN unterminated
HD3
1 MHz (VOUT = 2 V p-p)
10 MHz (VOUT = 1 V p-p)
10 MHz (VOUT = 2 V p-p)
HD3, RS = 50 Ω, RIN unterminated
Rev. 0 | Page 3 of 28
AD8432
Parameter
Conditions
Min
Typ
Max
Unit
Two-Tone IMD3 Distortion
10 MHz
RS = 50 Ω, RIN unterminated
VOUT = 1 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz
VOUT = 2 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz
VOUT = 1 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz
VOUT = 2 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz
f = 1 MHz
−89.1
−66.0
−88.9
−73.7
7.5
dBc
dBc
dBc
dBc
dBm
dBm
1 MHz
Input 1dB Compression Point
f = 10 MHz
7.7
Output Third-Order Intercept
1 MHz
VOUT = 1 V p-p of composite tones
VOUT = 2 V p-p of composite tones
VOUT = 1 V p-p of composite tones
VOUT = 2 V p-p of composite tones
VOUT = 1 V p-p of composite tones, reference to 50 Ω
VOUT = 2 V p-p of composite tones, reference to 50 Ω
VOUT = 1 V p-p of composite tones, reference to 50 Ω
VOUT = 2 V p-p of composite tones, reference to 50 Ω
VOUT = 1 V p-p, f = 1 MHz
29.7
28.2
23.2
24.2
42.7
41.2
36.2
37.2
102
dBV rms
dBV rms
dBV rms
dBV rms
dBm
dBm
dBm
dBm
dB
10 MHz
1 MHz
10 MHz
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
−6.25
+1
300
+6.25
mV
μV/°C
AC-coupled
RFB = 150 Ω
1.2
50
V p-p
Ω
RFB = 226 Ω
75
Ω
RFB = 301 Ω
RFB = 619 Ω
RFB = 3.57 kΩ
RFB = ∞, f = 100 kHz
100
200
1
6.2
6
Ω
Ω
kΩ
kΩ
pF
V
Input Capacitance
Input Common Mode Voltage
OUTPUT CHARACTERISTCS
Output Common-Mode Voltage
Output Offset Voltage
Output Voltage Swing
Output Resistance
Output Resistance in Shutdown Mode
Output Short-Circuit Current
Enable Response Time
3.25
2.5
+4
4.8
<0.1
2.5
77
V
−25
+25
mV
V p-p
Ω
kΩ
mA
μs
Single-ended, either output
Single-ended, either output
RL = 10 Ω differential
ENBON (enable high to output on)
ENBOFF (enable low to output off)
200
200
μs
POWER SUPPLY
Supply Voltage
4.5
5
5.5
V
Quiescent Current
Over Temperature
All channels enabled
TA = −40°C
TA = +85°C
24
21
27
50
120
−82
mA
mA
mA
μA
mW
dB
Supply Current in Shutdown Mode
Power Dissipation
PSRR
ENB = GND
100
G = 24.08 dB, f = 100 kHz, no bypass capacitors
Rev. 0 | Page 4 of 28
AD8432
ABSOLUTE MAXIMUM RATINGS
Table 2.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8432 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 150°C for an
extended period can cause changes in silicon devices, potentially
resulting in a loss of functionality.
Parameter
Rating
Voltage
Supply Voltage
Input Voltage
Power Dissipation
5.5 V
0 V to VPS
120 mW
Temperature
Operating Temperature
Storage Temperature
Package Glass Transition Temperature (TG)
Lead Temperature (Soldering, 60 sec)
–40°C to +85°C
–65°C to +150°C
150°C
300°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. The θJA
values in Table 3 assume a 4-layer JEDEC standard board with
zero airflow.
Table 3. Thermal Resistance1
Parameter
θJA
θJC
θJB
ΨJT
Unit
40-Lead LFCSP
57.9
11.2
35.9
1.1
°C/W
1 4-Layer JEDEC board (2S2P).
Rev. 0 | Page 5 of 28
AD8432
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
18 GOL1
OPL1
INH1
INL1 2
17
AD8432
TOP VIEW
(Not to Scale)
16 COM1
15 COM2
3
IND1
COMM 4
5
6
INL2
INH2
14
13
L2
OP
GOL2
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
INH1
INL1
LNA1 Noninverting Input.
LNA1 Inverting Input (AC-Coupled to Ground).
3, 7
4
5
6
8
IND1, IND2 Integrated Input Clamping Back-to-Back Diodes.
COMM
INL2
Input Ground.
LNA2 Inverting Input (AC-Coupled to Ground).
LNA2 Noninverting Input.
5 V Supply for LNA2.
INH2
VPS2
9
OPH2
GOH2
GMH2
GML2
GOL2
OPL2
COM2
COM1
OPL1
GOL1
GML1
GMH1
GOH1
OPH1
VPS1
Noninverting Output of LNA2.
Gain Setting Pin for LNA2.
Gain Setting Pin for LNA2.
Gain Setting Pin for LNA2.
Gain Setting Pin for LNA2.
Inverting Output of LNA2.
LNA2 Output Ground.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LNA1 Output Ground.
Inverting Output of LNA1.
Gain Setting Pin for LNA1.
Gain Setting Pin for LNA1.
Gain Setting Pin for LNA1.
Gain Setting Pin for LNA1.
Noninverting Output of LNA1.
5 V Supply of LNA1 .
ENB
Enable.
EPAD
Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 28
AD8432
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RIN = 50 Ω, RFB =150 ꢀ, CSH = 47 pF, RSH = 15 ꢀ, RL =500 Ω (per SE output), CL = 5 pF (per SE output),
G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified.
30
24
18
15
12
9
24
18
12
6
0
–6
–12
–18
–24
–30
6
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
R
R
R
R
UNTERMINATED
= 200Ω
IN
IN
IN
IN
3
= 100Ω
= 50Ω
0
1
10
100
1k
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3. Small Signal Differential Gain vs. Frequency, RIN Unterminated
Figure 6. Small Signal Frequency Response vs. RIN, G = 21.58 dB
24
21
18
15
12
9
27
24
21
18
15
12
9
6
3
0
–3
6
R
R
R
R
UNTERMINATED
= 200Ω
R
R
R
R
UNTERMINATED
= 200Ω
IN
IN
IN
IN
–6
–9
IN
IN
IN
IN
3
0
= 100Ω
= 100Ω
= 50Ω
= 50Ω
–12
1
10
100
500
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Small Signal Frequency Response vs. RIN, G = 12.04 dB
Figure 7. Small Signal Frequency Response vs. RIN, G = 24.08 dB
24
21
18
15
12
9
27
G = 24.08dB
24
G = 21.58dB
21
G = 18.06dB
18
15
G = 12.04dB
12
9
6
3
6
0
R
R
R
R
UNTERMINATED
= 200Ω
IN
IN
IN
IN
–3
–6
–9
3
0
= 100Ω
= 50Ω
1
10
100
500
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Differential Gain vs. Frequency, VOUT = 1 V p-p, RIN = 50 Ω
Figure 5. Small Signal Frequency Response vs. RIN, G = 18.06 dB
Rev. 0 | Page 7 of 28
AD8432
30
24
18
12
6
240
230
220
210
200
190
180
170
160
0
–6
–12
–18
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
–24
1
10
100
1k
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Differential Gain vs. Frequency, VOUT = 2 V p-p , RIN = 50Ω
Figure 12. Input Impedance RIN vs. Frequency, 200 Ω Active Termination
55
54
53
52
51
50
49
48
10
1
47
G = 24.08dB
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 21.58dB
46
G = 18.06dB
G = 12.04dB
G = 12.04dB
45
0.1
0.1
0.1
1
10
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Input Impedance RIN vs. Frequency, 50 Ω Active Termination
Figure 13. Input Impedance RIN vs. Frequency, Unterminated
115
110
105
100
95
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
90
85
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 11. Input Impedance RIN vs. Frequency, 100 Ω Active Termination
Figure 14. Output Impedance vs. Frequency
Rev. 0 | Page 8 of 28
AD8432
100
10
1
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.1
0.1
1
10
FREQUENCY (MHz)
100
–50
–30
–10
10
30
50
70
90
TEMPERATURE (°C)
Figure 15. Output Impedance vs. Frequency in Disable Mode
Figure 18. Input Voltage Noise vs. Temperature
10
16
14
12
10
8
f = 1MHz
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
1
R
THERMAL
S
NOISE ALONE
6
4
2
–50
0.1
1
10
100
1000
–30
–10
10
30
50
70
90
SOURCE RESISTANCE (ꢀ)
TEMPERATURE (°C)
Figure 16. Input-Referred Voltage Noise vs. Source Resistance (RS)
Figure 19. Output Voltage Noise vs. Temperature
100
1.6
f = 1MHz
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
G = 24.08dB
G = 21.58dB
10
G = 18.06dB
G = 12.04dB
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
1
0.01
0.1
1
10
100
1
10
100
1000
FREQUENCY (MHz)
SOURCE RESISTANCE (ꢀ)
Figure 17. Output-Referred Voltage Noise vs. Source Resistance (RS)
Figure 20. Input Voltage Noise vs. Frequency
Rev. 0 | Page 9 of 28
AD8432
20
18
16
14
12
10
8
–40
–50
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
HD2, 10MHz
HD2, 1MHz
HD3, 10MHz
HD3, 1MHz
MEASUREMENT
LIMIT
–60
–70
–80
6
–90
4
–100
–110
2
0
0.01
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.1
1
10
100
100
100
V
(V p-p)
FREQUENCY (MHz)
OUT
Figure 21. Output Voltage Noise vs. Frequency
Figure 24. Harmonic Distortion vs. Differential Output Voltage, G = 12.04 dB
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
LOW TONE
HIGH TONE
HD2, 10MHz
HD2, 1MHz
–80
–90
HD3, 10MHz
HD3, 1MHz
MEASUREMENT
LIMIT
–100
–110
–100
1
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
FREQUENCY (MHz)
V
(V p-p)
OUT
Figure 22. IMD3 vs. Frequency
Figure 25. Harmonic Distortion vs. Differential Output Voltage, G = 24.08 dB
50
45
40
35
30
25
20
15
10
5
–50
–60
–70
–80
G = 24.08dB
G = 12.04dB
HD2, 10MHz, 2V p-p
HD2, 10MHz, 1V p-p
HD3, 10MHz, 2V p-p
HD3, 10MHz, 1V p-p
HD2, 1MHz, 1V p-p
HD2, 1MHz, 2V p-p
HD3, 1MHz, 2V p-p
HD3, 1MHz, 1V p-p
–90
–100
–110
0
1
10
0
5
10
15
20
25
FREQUENCY (MHz)
C
(pF)
L
Figure 23. Output Third-Output Intercept vs. Frequency
Figure 26. Harmonic Distortion vs. Capacitive Load (CL), G = 12.04 dB
Rev. 0 | Page 10 of 28
AD8432
–40
–50
–50
–60
HD2, 10MHz, 2V p-p
HD2, 1MHz, 2V p-p
HD2, 10MHz, 1V p-p
–60
HD3, 10MHz, 2V p-p
–70
–70
HD2, 1MHz, 1V p-p
HD3, 10MHz, 1V p-p
–80
–80
–90
HD3, 1MHz, 2V p-p
–90
–100
–110
–120
HD2, 10MHz, 2V p-p
HD2, 10MHz, 1V p-p
HD3, 10MHz, 2V p-p
HD3, 10MHz, 1V p-p
HD2, 1MHz, 1V p-p
HD2, 1MHz, 2V p-p
HD3, 1MHz, 2V p-p
HD3, 1MHz, 1V p-p
–100
–110
HD3, 1MHz, 1V p-p
0
5
10
15
20
(pF)
25
30
35
2
4
6
8
10
12
14
16
18
C
GAIN (V/V)
L
Figure 30. Harmonic Distortion vs. Gain
Figure 27. Harmonic Distortion vs. Capacitive Load (CL), G = 24.08 dB
–70
–75
–50
–55
–60
–65
–70
–75
–80
–80
–85
–90
–95
–100
–105
–110
–115
–120
HD2, 10MHz, 2V p-p
HD2, 10MHz, 1V p-p
HD3, 10MHz, 2V p-p
HD3, 10MHz, 1V p-p
HD2, 1MHz, 1V p-p
HD2, 1MHz, 2V p-p
HD3, 1MHz, 2V p-p
HD3, 1MHz, 1V p-p
–85
–90
–95
0.1
1
10
FREQUENCY (MHz)
100
0
200 400 600 800 1000 1200 1400 1600 1800 2000
(ꢀ)
R
L
Figure 31. Channel Crosstalk vs. Frequency
Figure 28. Harmonic Distortion vs. Resistive Load (RL), G = 12.04 dB
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
HD2, 10MHz, 2V p-p
HD2, 10MHz, 1V p-p
HD3, 10MHz, 2V p-p
HD3, 10MHz, 1V p-p
HD2, 1MHz, 1V p-p
HD2, 1MHz, 2V p-p
HD3, 1MHz, 2V p-p
HD3, 1MHz, 1V p-p
100ns/DIV
0
200 400 600 800 1000 1200 1400 1600 1800 2000
(ꢀ)
R
L
Figure 29. Harmonic Distortion vs. Resistive Load (RL), G = 24.08 dB
Figure 32. Overdrive Recovery, G = 12.04 dB
Rev. 0 | Page 11 of 28
AD8432
C
C
C
= 15pF
= 10pF
= 5pF
L
L
L
100ns/DIV
10ns/DIV
Figure 36. Small Signal Transient Response vs. Capacitive Load (CL), G = 12.04 dB
Figure 33. Overdrive Recovery, G = 24.08 dB
C
C
C
C
C
= 5pF
L
L
L
L
L
G = 24.08dB
= 10pF
= 15pF
= 20pF
= 30pF
G = 21.58dB
G = 18.06dB
G = 12.04dB
10ns/DIV
10ns/DIV
Figure 37. Small Signal Transient Response vs. Capacitive Load (CL), G = 24.08 dB
Figure 34. Small Signal Transient Response vs. Gain, VIN = 100 mV p-p
R
R
R
R
R
= 499ꢀ
= 249ꢀ
= 24.9ꢀ
= 15ꢀ
L
L
L
L
L
= 10ꢀ
10ns/DIV
10ns/DIV
Figure 38. Small Signal Transient Response vs. Resistive Load (RL), G = 12.04 dB
Figure 35. Small Signal Transient Response, G = 12.04 dB
Rev. 0 | Page 12 of 28
AD8432
R
R
R
R
R
= 499ꢀ
= 249ꢀ
= 24.9ꢀ
= 15ꢀ
C
C
C
C
= 20pF
L
L
L
L
L
L
L
L
L
= 15pF
= 10pF
= 5pF
= 10ꢀ
10ns/DIV
10ns/DIV
Figure 39. Small Signal Transient Response vs. Resistive Load (RL), G = 24.08 dB
Figure 42. Large Signal Transient Response vs. Capacitive Load (CL), G = 12.04 dB
C
C
C
C
C
= 30pF
= 20pF
= 15pF
= 10pF
= 5pF
L
L
L
L
L
G = 18.06dB
G = 12.04dB
G = 21.58dB
G = 24.08dB
10ns/DIV
10ns/DIV
Figure 40. Small Signal Transient Response vs. Gain, VOUT = 200 mV p-p
Figure 43. Large Signal Transient Response vs. Capacitive Load (CL), G = 24.08 dB
R
R
R
R
= 499ꢀ
= 249ꢀ
= 24.9ꢀ
= 15ꢀ
L
L
L
L
G = 24.08dB
G = 21.58dB
G = 18.06dB
G = 12.04dB
10ns/DIV
10ns/DIV
Figure 41. Large Signal Transient Response vs. Gain, VIN = 125 mV p-p
Figure 44. Large Signal Transient Response vs. Resistive Load (RL), G = 12.04 dB
Rev. 0 | Page 13 of 28
AD8432
30
28
26
24
22
20
R
R
R
R
R
= 499ꢀ
= 249ꢀ
= 24.9ꢀ
= 15ꢀ
L
L
L
L
L
= 10ꢀ
10ns/DIV
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 48. Supply Current vs. Temperature
Figure 45. Large Signal Transient Response vs. Resistive Load (RL), G = 24.08 dB
140
120
100
80
G = 12.04dB
G = 21.58dB
G = 18.06dB
G = 24.08dB
60
40
20
0
–60
–40
–20
0
20
40
60
80
100
10ns/DIV
TEMPERATURE (°C)
Figure 46. Large Signal Transient Response vs. Gain, VOUT = 2 V p-p
Figure 49. Supply Current vs. Temperature in Disable Mode
–20
–30
–40
–50
–60
–70
–80
G = 24.08dB
NO BYPASS CAPS
–90
–100
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 47. PSRR vs. Frequency
Rev. 0 | Page 14 of 28
AD8432
ENB
5V/DIV
ENB
5V/DIV
1
1
OUTPUT
50mV/DIV
OUTPUT
500mV/DIV
2
2
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 50. Small Signal Enable Response
Figure 51. Large Signal Enable Response
Rev. 0 | Page 15 of 28
AD8432
TEST CIRCUITS
0.1µF
R
FB
1MHz
SPECTRUM
ANALZYER
(10MHz LPF)
DUAL FILTER
HP
0.1µF
0.1µF
INH
INH
INL
OPL
475ꢀ
56.2ꢀ
R
L
R
SH
50ꢀ
LP
INL
0.1µF
AD8432
0.1µF
1MHz
(10MHz)
LNA1
C
AD8130
SH
1.7MHz
(10.7MHz)
50ꢀ
G = 1
R
L
Figure 52. Harmonic Distortion vs. Resistive Load (RL) Measurements
0.1µF
DUAL FILTER
R
FB
50ꢀ
SPECTRUM
ANALYZER
LP
1MHz
(10MHz LPF)
0.1µF
0.1µF
0.1µF
50ꢀ
OPL
HP
487ꢀ
IN
INH
INL
1:1
C
26.1ꢀ
L
487ꢀ
0.1µF
OPH
R
1.7MHz
(10.7MHz)
SH
1MHz
(10MHz)
C
AD8432
SH
LNA1
26.1ꢀ
L
C
L
R
Figure 53. Harmonic Distortion vs. Capacitive Load (CL) Measurements
NETWORK
ANALYZER
50ꢀ
OUT
50ꢀ
IN
5pF
499ꢀ
0.1µF
OPL
R
FB
DIFF
PROBE
0.1µF
0.1µF
INH
INL
OPH
R
SH
AD8432
0.1µF
499ꢀ
LNA1
C
SH
0.1µF
5pF
Figure 54. Frequency Response Measurements
SPECTRUM
ANALYZER
0.1µF
0.1µF
OPL
INH
INL
50ꢀ
1kꢀ
OPH
AD8129
G = 10
AD8432
1kꢀ
0.1µF
0.1µF
LNA1
Figure 55. Voltage Noise Measurements
Rev. 0 | Page 16 of 28
AD8432
5pF
0.1µF
R
FB
10MHz
499ꢀ
499ꢀ
DIFF
PROBE
X
MULTIPLIER
0.1µF
OSCILLOSCOPE
CH1
0.1µF
INH
R
Y
SH
INL
C
SH
AD8432
0.1µF
5pF
LNA1
1MHz
0.1µF
Figure 56. Overdrive Recovery Measurements
499ꢀ
5pF
0.1µF
R
FB
NETWORK
ANALYZER
0.1µF
0.1µF
50ꢀ
OPL
OPH
OUT
INH
INL
0.1µF
R
SH
C
SH
499ꢀ
5pF
AD8432
0.1µF
LNA1
Figure 57. Input Impedance vs. Frequency Measurements
0.1µF
R
FB
NETWORK
ANALYZER
0.1µF
0.1µF
50ꢀ
OPL
OPH
INH
INL
0.1µF
R
SH
C
SH
499ꢀ
AD8130
LNA1
0.1µF
Figure 58. Output Impedance vs. Frequency Measurements
0.1µF
R
FB
SPECTRUM
ANALYZER
0.1µF
0.1µF
0.1µF
+IN
–IN
OPL1
INH1
50ꢀ
1kꢀ
1kꢀ
R
OUT
S
OPH1
AD8129
G = 10
INL1
AD8432
0.1µF
LNA1
Figure 59. Noise Figure Measurements
Rev. 0 | Page 17 of 28
AD8432
THEORY OF OPERATION
Clamping the inputs ensures quick recovery from large input
voltages. The input back-to-back diodes, which are integrated
inside the die (IND1 and IND2), should be used for the lowest gain
configuration (12.04 dB) to protect the input from overdriving.
They should be connected after the source resistance or before
the INH coupling capacitor.
LOW NOISE AMPLIFIER (LNA)
The AD8432 is a dual-channel, ultralow noise amplifier with
integrated pin-strappable, gain-setting resistors. The resistors
can be externally connected to achieve differential gains of
12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and
×16). A simplified schematic of a LNA is shown in Figure 60.
The use of a fully differential topology and negative feedback
minimizes distortion. A differential signal enables smaller swings at
each output, which results in reduction of third-order distortion.
The LNA is driven with a single-ended input and measured
differentially at the output. The inverting input INL must be
ac-coupled to ground through a capacitor for proper operation.
The LNA cannot be driven differentially due to the asymmetry
of the internal gain setting resistors. The gain from the inverting
input INL to the single-ended output (OPH or OPL) does not
match the gain from the noninverting input INH to the single-
ended output.
The AD8432 is a voltage feedback amplifier. Due to gain band-
width product (GBW), a decrease in bandwidth should be
expected as the gain increases. Table 5 displays the values of −3 dB
bandwidth for each gain with unterminated input impedance.
GAIN SETTING TECHNIQUE
The AD8432 inputs have a dc bias voltage of 3.25 V, which is
generated internally. The inputs must be ac-coupled through a
series capacitor to maintain the dc bias level of the inputs. Likewise,
the AD8432 outputs have a dc bias voltage of 2.5V. An ac coupling
capacitor in series with each connection is recommended to
prevent improper loading of the outputs.
Pin strapping is used to set the gain of the amplifier. Gain setting
resistors are integrated in the LNA and are accessible externally
through the GOH, GMH, GML, and GOL pins. By externally
shorting these pins, and thereby shorting or connecting the
internal resistors, the AD8432 can be configured for four different
gains. Table 5 shows which pins must be connected to achieve
the desired gain.
The AD8432 supports a differential output voltage of 4.8 V p-p
for the common-mode output voltage of 2.5 V. Therefore, for a
differential gain G = 12.04 dB, the maximum input voltage allowed
is 1.2 V p-p.
C
FB
R
FB
VPS
I
I
OPL
INL
OPH
INH
Q1
Q2
CINH
RG4
48ꢀ
RG3
24ꢀ
RG2
12ꢀ
RG1
12ꢀ
RG5
24ꢀ
RG6
24ꢀ
RG7
48ꢀ
RSH
CSH
CINL
GND
I
I
RS
GOH
GMH
GML
GOL
GND
VS
GND
Figure 60. Simplified Schematic of LNA
Table 5. Gain Setting Using Pin-Strapping Technique and −3 dB Bandwidth for Each Gain Configuration
Differential
Gain (dB)
Single −3 dB
Gain (dB) BW (MHz)
RG1 (Ω) RG2 (Ω) RG3 (Ω)
RG4 (Ω)
RG5 (Ω) RG6 (Ω)
RG7 (Ω)
12.04
18.06
21.58
24.08
6.02
200
90
12
12
12
12
12
12
12
12
Connect
GMH to GOH
Connect
GOH to OPH
24
24
24
24
Connect
GML to GOL
Connect
GOL to OPL
12.04
15.56
18.06
24
Connect
GOH to OPH
24
Connect
GOL to OPL
50
Connect
GMH to GOH
48
48
Connect
GML to GOL
48
48
32
24
24
Rev. 0 | Page 18 of 28
AD8432
The single-ended gain from INH to OPH (see Figure 60) is
defined as
To achieve this active impedance match, connect a feedback
resistor RFB between the INH and OPL (see Figure 61). RIN is
given in Equation 1, where G/2 is the single-ended gain.
R
G1 + RG2 + RG3 + RG4
GOPH−INH
=
RFB
RG1
RIN
=
(1)
G
1+
The single-ended gain from INH to OPL is defined as
2
RG5 + RG6 + RG7
In addition, to further reduce the input resistance, there is an
internal resistance of 6.2 kꢀ in parallel with the source resistance,
GOPL−INH = −
RG1
such that
The values of the seven gain resistors were chosen so that both
single-ended gains are equal. For example, to set a gain of
12.04 dB (G = ×4) differentially, the gain from INH to each
output (OPH, OPL) should be 6.02 dB (G = ×2).
RFB
RIN
=
RINTERNAL
(2)
G
1+
2
INH to OPH: For RG1 = RG2 = RG, then
Equation 3 should be used to calculate RFB accurately for a desired
input resistance and single-ended gain. Refer to Table 6 for
calculated results for RFB for several input resistance and gain
combinations.
2 × RG
R
G1 + RG2
GOPH−INH
=
=
= 2
RG1
RG
INH to OPL: For RG1 = RG and RG5 = 2 × RG, then
G
⎛
⎝
⎞
⎟
⎠
RIN 1+
⎜
2 ×RG
RG5
RG1
2
RIN
GOPL−INH = −
= −
= −2
⇒ RFB
=
, RINTERNAL = 6.2 kꢀ
(3)
RG
1−
RINTERNAL
ACTIVE INPUT RESISTANCE MATCHING
8
7
6
5
4
3
2
1
The AD8432 reduces noise and optimizes signal power transfer
by using active input termination to perform signal source
resistance matching.
The primary purpose of input impedance matching is to optimize
the input signal power transfer. With resistive termination, the
input noise increases due to the thermal noise of the terminating
resistor and the increased contribution of the input voltage noise
generator of the LNA. With active impedance matching, however,
the contributions of both are smaller than they would be for
resistive termination by a factor of 1/(1 + ½LNA Gain). The
noise figure (NF) for the three terminating schemes are shown
in Figure 62.
RESISTIVE TERMINATION
(R = R
)
IN
S
ACTIVE IMPEDANCE
MATCH
UNTERMINATED
(SIMULATED RESULTS)
100
0
50
1000
R
R
(ꢀ)
IN
S
R
INH
S
V
Figure 62. Noise Figure vs. RS for Resistive, Active Match, and
Unterminated Inputs
LNA
OUT
V
IN
UNTERMINATED
18
16
14
12
10
8
R
R
R
R
R
R
= 1kꢀ
IN
IN
IN
IN
IN
IN
= 200ꢀ
= 100ꢀ
= 75ꢀ
= 50ꢀ
R
IN
R
INH
S
V
LNA
OUT
= UNTERMINATED
R
S
V
IN
RESISTIVE
TERMINATION
R
FB
R
IN
6
R
INH
S
V
LNA
OUT
4
V
IN
ACTIVE
IMPEDANCE MATCH
2
(SIMULATED RESULTS)
100
0
50
Figure 61. Input Resistance Matching
1k
R
(ꢀ)
S
Figure 63. Noise Figure vs. RS for Various Values of RIN, Actively Matched
Rev. 0 | Page 19 of 28
AD8432
The user must determine the level of matching accuracy desired
and adjust RFB accordingly. The RFB and CFB network presents a
load to OPL that OPH does not see. The user may add an identical
load on OPH, to improve slightly the distortion caused by this
imbalance.
The unterminated bandwidth (RFB = ∞) is 200 MHz. The AD8432
has a low input referred voltage noise of 0.85 nV/√Hz at the
lowest gain, 12.04 dB (unterminated configuration). To achieve
such low noise, the dual amplifier consumes 24 mA, resulting in
a power consumption of 120 mW.
There is a feedback capacitor (CFB) in series with RFB (see Figure 60)
because the dc levels of the positive output and the positive input
are different. At higher frequencies, the value of the feedback
capacitor needs to be considered.
Table 6. Feedback Resistance for Several RIN and Gain Combinations
Single-Ended Gain,
G/2 (V/V)
Exact RFB (Ω),
Equation 2
Actual RIN (Ω),
Equation 2
Desired RIN (Ω)
Differential Gain (V/V)
RFB (Ω), 1% Standard Value
50
75
4
4
4
4
4
8
8
12
12
16
16
2
2
2
2
2
4
4
6
6
8
8
151.2
227.8
304.9
620
3.58 k
252
508.2
352.9
711.5
453.7
914.8
150
226
301
619
3.57 k
250
511
357
715
453
909
49.6
74.4
98.7
100
200
1 k
50
100
50
100
50
100
199.7
998.4
49.6
100.5
50.6
100.5
49.9
99.4
Rev. 0 | Page 20 of 28
AD8432
APPLICATIONS INFORMATION
The AD8432 LNA provides precision gain and ultralow noise
performance with minimal external components. Because it is
a high performance part, care must be taken to ensure that it is
configured optimally to attain the best performance and dynamic
range for the system.
The unterminated input impedance of the AD8432 is 6.2 kꢀ.
Any input resistance between 50 ꢀ and 6.2 kꢀ can be synthesized
using active impedance matching.
At the lowest gain (12.04 dB), the gain response exhibits some
peaking at higher frequencies. An RC shunt network at the input
(see RSHx and CSHx in Figure 64) is recommended to reduce gain
peaking and enhance stability at higher frequencies.
TYPICAL SETUP
The internal bias circuitry of the AD8432 sets the input bias
voltage at 3.25 V and the output bias voltage at 2.5 V. It is important
to ac-couple the inputs through a capacitor to maintain the internal
dc bias levels. When active input termination is used (RFB), a
decoupling capacitor (CFB) is required to isolate the input and
output bias voltages of the LNA. A typical value for CFB is 0.1 μF, but
a smaller value capacitor is more appropriate at higher frequencies.
Table 7 shows the recommended values of RFB, CSH, and RSH for
all four gains and several input impedance combinations. The
values for the CSH and RSH network are determined empirically
and can be customized as needed to optimize performance. As
RIN increases, the value of CSH diminishes, and for higher input
impedance values, no capacitor may be required.
C
FB1
0.1µF
R
FB1
FB
120nH
G = 12dB
0.1µF
0.1µF
ENB
VPS1
COMM
VPS2
BIAS
FB
120nH
0.1µF
0.1µF
INH1
IND1
OPH1
IN1
OUT1+
OUT1–
R
SH1
15ꢀ
R
L
C
LNA1
L
OPL1
C
SH1
47pF
0.1µF
GMH1
GOH1
GOL1
GML1
INL1
0.1µF
0.1µF
FB
120nH
0.1µF
INH2
IND2
OPH2
OPL2
IN2
OUT2+
OUT2–
R
SH2
15ꢀ
R
L
C
LNA2
L
C
SH2
0.1µF
47pF
0.1µF
C
GMH2
GOH2
GOL2
GML2
INL2
AD8432
FB2
0.1µF
R
FB2
Figure 64. Typical AD8432 Setup, G = 12.04 dB
Rev. 0 | Page 21 of 28
AD8432
Table 7. External Components Selections for Common Input Impedance
RIN (Ω)
Gain (dB)
RFB (Ω)
150
249
357
453
226
383
536
681
301
511
715
909
619
1.02 k
1.43 k
1.87 k
3.57 k
5.9 k
8.25 k
10.7 k
∞
CSH (pF)
RSH (Ω)
15
15
None
None
15
None
None
None
15
None
None
None
15
None
None
None
10
None
None
None
None
None
None
None
None
None
None
None
−3 dB BW (MHz)
50
12
18
21
24
47
30
176
116
117
87
None
None
36
None
None
None
30
None
None
None
18
None
None
None
10
None
None
None
None
None
None
None
None
None
None
None
75
12
18
21
24
167
144
100
72
100
12
18
21
24
164
134
90
63
200
12
18
21
24
164
116
74
51
1 k
12
18
21
24
160
99
61
43
Unterminated, RS = 50 Ω
Unterminated, RS = 0 Ω
12
18
21
24
178
95
59
∞
∞
∞
40
12
18
21
24
∞
∞
∞
∞
210
96
55
38
Rev. 0 | Page 22 of 28
AD8432
resistors. The 4LOP and 4LON pins of the AD8339 are driven by
a differential clock signal, which has a frequency 4× that of the
RF inputs. The AD8339 downconverts the RF signals, generates
quadrature, and phase-shifts the resultant I and Q signals.
I/Q DEMODULATION FRONT END
The AD8432 low noise amplifiers can be used to drive the
differential RF inputs of the dual AD8333 or the quad AD8339
I/Q demodulators. The primary application for the AD8339 is
phased array beamforming in medical ultrasound, specifically
in CW Doppler processing. Other applications include phased
array radar and smart antennas for mobile communications.
The I and Q outputs of the AD8339 are current outputs. A
transimpedance amplifier, such as the AD8021, processes the
outputs and performs several functions, including the following:
AD8021
•
•
•
Current-to-voltage conversion
Summation amplifier for multiple channels
Active low-pass filter
Q1
0.1µF
20ꢀ
787ꢀ
RF1P
Q1OP
I1OP
2.2nF
2.2nF
787ꢀ
AD8339
AD8432
In beamforming applications, the I and Q outputs of a number
of receiver channels are summed, which increases the system
dynamic range by 10 log10 (N), N being the number of channels
being summed. The external RC feedback network of the
AD8021 is a 100 kHz low-pass filter as shown in Figure 65.
Refer to the AD8333 and AD8339 datasheets for more details
on implementing I/Q demodulators.
RF1N
20ꢀ
0.1µF
4LOP
0.1µF
I1
AD8021
Figure 65. Block Diagram of AD8432 + AD8339 Application for
Ultrasound Beamforming
Evaluation boards are available for the AD8432 and the AD8339
to facilitate system level design and test. A detailed reference
schematic of the setup is shown in Figure 66. The AD8432 is
shown in this configuration with a gain of 12.04 dB, with
unterminated inputs. If active termination is preferred, use an
RFB and CFB network as discussed in the Theory of Operation.
Clamping diodes IND1/IND2 can be connected to IN1/IN2 to
protect the LNA input from being overdriven.
Because of its low output noise and low distortion, the AD8432
ensures minimal degradation in dynamic range while amplifying
the RF input signal. At the lowest gain of 12.04 dB, the AD8432
contributes only 3.4 nV/√Hz output voltage noise.
Figure 65 shows a simplified block diagram of one channel of
the AD8432 driving the AD8339. The AD8432 outputs can be
connected directly to the AD8339 RF inputs through 20 ꢀ
4LO
0.1µF
+5V
−5V
+5V
787ꢀ
0.1µF
0.1µF
0.1µF
0.1µF
2.2nF
ENB VPS1
VPS2 COMM
BIAS
VPOS
VNEG 4LOP
2
7
–
0ꢀ
6
0.1µF
IN1
Q1 + Q2
INH1
IND1
AD8021
20ꢀ
20ꢀ
RF1P
RF1N
Q1OP
I1OP
OPH1
+
4
R
15ꢀ
3
LNA1
SH1
OPL1
C
47pF
0.1µF
GMH1
GOH1
GOL1
SH1
−5V
INL1
+5V
0.1µF
GML1
IN2
787ꢀ
INH2
IND2
20ꢀ
20ꢀ
Q2OP
I2OP
OPH2
OPL2
RF2P
RF2N
0.1µF
2
0.1µF
0.1µF
2.2nF
LNA2
R
SH2
15ꢀ
7
–
GMH2
GOH2
GOL2
C
SH2
47pF
0ꢀ
6
I1 + I2
AD8339
INL2
AD8021
+
4
GML2
G = –1.3dB
3
AD8432
LPF
fC = 100kHz
0.1µF
G = 12dB
−5V
Figure 66. Schematic of AD8432 (G = 12.04 dB) + AD8339 Application for Ultrasound Beamforming
Rev. 0 | Page 23 of 28
AD8432
A transformer or balun can also be used to convert the differential
output of the AD8432 to a single-ended output. Transformers
have lower distortion; however, care must be taken to properly
match the impedance of the transformer. The test circuit for
distortion measurements in Figure 53 uses an ADTT1-1
transformer to perform differential-to-single-ended conversion.
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
Some applications require the low noise and high dynamic
range of the AD8432; however, they may also require a single-
ended output, rather than a differential output. The AD8129
and AD8130 differential receiver amplifier can be used for the
differential-to-single-ended conversion of the AD8432 output,
as shown in Figure 67.
The AD8129 is a low noise, high gain (10 or greater) amplifier
intended for applications over very long cables, where signal
attenuation is significant. The AD8130 is stable at a gain of 1
and can be used for applications where lower gains are required.
The AD8129 and AD8130 have user-adjustable gain, set by the
ratio of two resistors, to help compensate for losses in the
transmission line.
0.1µF
0.1µF
ENB VPS1
VPS2 COMM
BIAS
+V
SERIES R IF DRIVING
HIGH CAP LOAD
AC-COUPLING CAPS
(AD8432 HAS 2.5V
OUTPUT BIAS)
S
0.1µF
IN1
INH1
IND1
20ꢀ
20ꢀ
0.1µF
0.1µF
1
8
OPH1
OPL1
7
2
+
–
R
LNA1
SH1
V
OUT1
6
15ꢀ
4
5
C
GMH1
GOH1
GOL1
GML1
SH1
499ꢀ
499ꢀ
+
–
47pF
INL1
AD8130
0.1µF
R’S PROVIDE BIAS CURRENT
PATH AND TERMINATION
IF NECESSARY
G = 12 dB
–V
S
Figure 67. AD8432 Differential-to-Single-Ended Conversion Using the AD8129/AD8130 with Unity Gain
Rev. 0 | Page 24 of 28
AD8432
EVALUATION BOARD
Figure 68 shows the AD8432 evaluation board, and the schematic
diagram is shown in Figure 69. Using the board is a convenient
and fast way to verify system design and assess the performance of
the AD8432 under the user-specific operating conditions. The
board provides access to all LNA inputs, outputs, and gain setting
pins. The board is shipped in a typical G = 12.04 dB configuration
but is designed to allow customization of the setup as required.
Table 8 outlines which resistors or headers need to be installed or
shorted for each gain configuration.
Table 8. Gain Setting Using Resistors or Headers
Gain (V/V)
LNA1
W5
LNA2
W9
4
8
12
16
R1
R2
R3
R4
R9
X1
X1
X1
X1
X1
W6
W7
W8
R10
R11
R12
W10
W11
W12
X1
X1
The AD8432-EVALZ requires a single 5 V power supply. An
on-board switch (S1) allows VPS to drive the enable (ENB) input.
X1
GAIN SETTING
1 X = shorting the indicated header or resistor.
Headers (W5 to W12) are provided across the gain setting pins
and can be shorted using jumpers to allow gain setting quickly
and easily. Alternately, it is recommended to short the gain setting
pins using surface-mount (0402), 0 ꢀ resistors (R1 to R4, R9 to
R12) that eliminate the small parasitic capacitances from longer
trace lengths to the headers. As shipped, the evaluation board is
configured for G = 12.04 dB with these 0 Ω resistors.
Figure 68. Evaluation Board
Rev. 0 | Page 25 of 28
AD8432
SCHEMATIC
2
0 4 1 - 3 4 0 8
12
11
10
9
GML1 19
GMH1 20
GOH1 21
OPH1 22
VPS1 23
ENB 24
GML2
GMH2
GOH2
OPH2
VPS2
IND2
8
7
Figure 69. Schematic
Rev. 0 | Page 26 of 28
AD8432
OUTPUT
POWER SUPPLY
The AD8432 evaluation board provides the space to configure
the output loading conditions required by the user, by populating
the given footprints (for example, RL1, RL2, C7, and C8). SMA
connectors are available at the outputs, and space for a transformer
is also available for differential-to-single-ended conversion.
The AD8432 should be powered by a single 5 V supply connected
to the VPOS terminal. Separate supplies can be used for VPS1,
VPS2, and ENB, or they can all be tied to VPOS by shorting
the W3 and W4 headers and the S1 switch. Ferrite beads and
decoupling capacitors are installed for isolation, protection, and
power supply noise reduction.
The 4-pin headers, PRB3 and PRB4, are placed close to the AD8432,
and they provide a way for monitoring the differential output or
the single-ended output using a high impedance differential probe.
The two inner pins of the headers are connected to OPL/OPH,
and the two outer pins of the headers are connected to ground.
INPUT TERMINATION
Active input impedance matching can be realized by installing
a feedback resistor (RFB), the value of which is determined by
the gain and source impedance, as described in the Theory of
Operation section. CFB provides the necessary ac coupling
between the input and output when using active termination;
a 0.1 μF capacitor value is recommended. The RFB and CFB network
presents a load to OPL, and an equivalent load at OPH can be
used to balance the differential output.
There are several footprints provided to install ac coupling
capacitors at the outputs (C7 to C14). The AD8432 outputs are
biased internally at 2.5 V. To maintain the dc bias level, use coupling
capacitors between the outputs and the load.
Input clamping diodes (IND1 and IND2) can be connected to the
inputs, by shorting the connection on the W1 and W2 headers.
The diodes provide overvoltage protection to the input and
enable faster overdrive recovery times, especially at the lowest
gain (12.04 dB).
Rev. 0 | Page 27 of 28
AD8432
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
19
18
24
0.50
BSC
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
13
12
BOTTOM VIEW
6
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 70. 24-Lead Lead Frame Chip Scale Package [LFSCP_WQ]
4 mm × 4 mm, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8432ACPZ-R71
AD8432ACPZ-RL1
AD8432ACPZ-WP1
AD8432-EVALZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-24-7
CP-24-7
24-Lead LFCSP_WQ, 7”Tape and Reel
24-Lead LFCSP_WQ, 13”Tape and Reel
24-Lead LFCSP_WQ, Waffle Pack
Evaluation Board
CP-24-7
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08341-0-10/09(0)
Rev. 0 | Page 28 of 28
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