AD8436ACPZ-RL_技术文档

Low Cost, Low Power,

True RMS-to-DC Converter

AD8436

FEATURES

FUNCTIONAL BLOCK DIAGRAM

CAVG CCF

Computes true rms value instantly

Accuracy: 10 μV 0.5% of reading

Wide dynamic input range

100 μV rms to 3 V rms (8.5 V p-p) full-scale input range

Larger inputs with external scaling

Wide bandwidth:

VCC

100kΩ

SUM

IGND

100kΩ

8kΩ

RMS CORE

RMS

VEE

OGND

OUT

1 MHz for −3 dB (300 mV)

65 kHz for additional 1% error

16kΩ

10pF

Zero converter dc output offset

No residual switching products

Specified at 300 mV rms input

Accurate conversion with crest factors up to 10

Low power: 300 µA typical at 2.4 V

Fast settling at all input levels

10kΩ

IBUFGN

IBUFIN–

IBUFIN+

–

+

FET OP AMP

IBUFOUT

High-Z FET separately powered input buffer

OBUFIN+

OBUFIN–

+

–

DC BUFFER

OBUFOUT

R

_IN≥ 10¹²Ω, C_IN≤ 2 pF

16kΩ

Precision dc output buffer

Wide supply range

AD8436

Figure 1.

Dual: 2.4 V to 18 V

Single: 4.8 V to 36 V

Small size: 4 mm × 4 mm package

ESD protected

GENERAL DESCRIPTION

The AD8436 is a new generation, translinear precision, low power,

true rms-to-dc converter that is loaded with options. It computes

a precise dc equivalent of the rms value of ac waveforms, including

complex patterns such as those generated by switchmode power

supplies and triacs. Its accuracy spans a wide range of input levels

(see Figure 2) and temperatures. The ensured accuracy of ≤±±.ꢀ5

and ≤1± μV output offset result from the latest Analog Devices,

Inc., technology. The crest factor error is <±.ꢀ5 for CF values

between 1 and 1±.

meters and other battery-powered applications. The precision

dc output buffer offers extremely low offset voltages, thanks to

bias current cancellation.

Unlike digital solutions, the AD8436 has no switching circuitry

limiting performance at high or low amplitudes (see Figure 2).

A usable response of <1±± μV and >3 V extends the dynamic

range with no external scaling, accommodating the most

demanding low signal conditions.

GREATER INPUT DYNAMIC RANGE

The AD8436 delivers instant true rms results at less cost than

misleading peak, averaging, or digital solutions. There is no

programming expense or processor overhead to consider, and the

4 mm × 4 mm package easily fits into those tight applications.

AD8436

∆Σ SOLUTION

On-board buffer amplifiers enable the widest range of options

for any rms-to-dc converter available, regardless of cost. For

minimal applications, only a single external averaging capacitor

is required. The built-in high impedance FET buffer provides an

interface for external attenuators, frequency compensation, or

driving low impedance loads. A matched pair of internal resistors

enables an easily configurable gain-of-two or more, extending

the usable input range even lower. The low power, precision input

buffer makes the AD8436 attractive for use in portable multi-

100µV

1mV

10mV

100mV

1V

3V

Figure 2. Usable Dynamic Range of the AD8436 vs. ΔΣ

The AD8436 operates from single or dual supplies of ±2.4 V

(4.8 V) to ±18 V (36 V). A and J grades are available in a compact

4 mm × 4 mm, 2±-lead chip-scale package. The operating

temperature ranges are −4±°C to 12ꢀ°C and ±°C to 7±°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8436

TABLE OF CONTENTS

Features .............................................................................................. 1

Test Circuits........................................................................................9

Theory of Operation ...................................................................... 1±

Overview ..................................................................................... 1±

Applications Information.............................................................. 12

Using the AD8436....................................................................... 12

AD8436 Evaluation Board......................................................... 16

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. ꢀ

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD8436

SPECIFICATIONS

e_IN= 3±± mV ac (rms), frequency = 1 kHz sinusoidal, ac-coupled, ±V_S= ±ꢀ V, T_A= 2ꢀ°C, C_AVG= 1± μF, unless otherwise specified.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RMS CORE

Conversion Error

Vs. Temperature

Vs. Rail Voltage

Input Offset Voltage

Output Offset Voltage

Vs. Temperature

DC Reversal Error

Nonlinearity

Default conditions

ꢀ40°C < T < ±2ꢁ C

±2.4 V to ±±1 V

DC-coupled

Default conditions, ac-coupled input

ꢀ40 C < T < ±2ꢁ°C

DC-coupled, V_IN= ±300 mV

e_IN= ±0 mV to 300 mV ac (rms)

Additional error

±±0 ꢀ 0.ꢁ

±0 ± 0

0.006

±0.0±3

0

0.3

±±0 ꢂ 0.ꢁ

μV/% rdg

%/°C

±%/V

μV

ꢀꢁ00

ꢂꢁ00

±2

V

μV/°C

%

±0.ꢁ

0.0ꢁ

Crest Factor Error

± < CF < ±0

CCF = 0.± μF

ꢀ0.ꢁ

ꢀV_Sꢀ 0.7

7.92

ꢂ0.ꢁ

ꢂV_Sꢂ 0.7

1.01

%

V

kΩ

Peak Input Voltage

Input Resistance

Frequency Response

±% Additional Error

3 dB Bandwidth

Settling Time

0.±%

1

V_IN= 300 mV rms

6ꢁ

±

kHz

MHz

Rising/falling

±41/34±

±ꢁ1/3ꢁ0

±6

ms

kΩ

μA

0.0±%

Output Resistance

Supply Current

INPUT BUFFER

Signal Voltage Swing

Input

±ꢁ.61

±6.32

400

No input

32ꢁ

G = ±

AC- or dc-coupled

AC-coupled to Pin RMS

ꢀV_S

ꢀV_Sꢂ 0.2

ꢀ±

ꢂV_S

ꢂV_Sꢀ 0.2

ꢂ±

V

Output

mV

pA

Ω

Offset Voltage

Input Bias Current

Input Resistance

Frequency Response

0.± dB

3 dB Bandwidth

Supply Current

Optional Gain Resistor

Gain Error

0

ꢁ0

±0^±2

9ꢁ0

2.±

±60

ꢂ±0

kHz

MHz

μA

kΩ

%

±00

ꢀ9.9

200

ꢂ±0.±

0.0ꢁ

G = ×±

OUTPUT BUFFER

Offset Voltage

Input Current

Output Voltage Swing

Gain Error

Supply Current

SUPPLY VOLTAGE

Dual

Connected to Pin OUT

ꢀ200

0

ꢂ200

3

ꢂV_Sꢀ ±

0.0±

70

μV

nA

V

%

μA

ꢀV_Sꢂ 0.000ꢁ

0.003

40

±2.4

4.1

±±1

36

V

Single

Rev. 0 | Page 3 of 20

AD8436

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Supply Voltage

Internal Power Dissipation

Input Voltage

Output Short-Circuit Duration

Differential Input Voltage

Temperature

Operating Range

Storage Range

THERMAL RESISTANCE

Rating

±±1 V

±1 mW

±V_S

Indefinite

ꢂV_Sand ꢀV_S

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type

θ_JA

16

41

Unit

°C/W

CP-20-±0 LFCSP Without Thermal Pad

CP-20-±0 LFCSP With Thermal Pad

ꢀ40°C to ꢂ±2ꢁ°C

ꢀ6ꢁ°C to ꢂ±2ꢁ°C

300°C

Lead Soldering (60 sec)

ESD Rating

ESD CAUTION

2 kV

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 4 of 20

AD8436

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SUM

20

CAVG

CCF

VCC

IBUFV+

16

1

15

DNC

RMS

OBUFV+

OBUFOUT

OBUFIN–

OBUFIN+

IGND

PIN 1

INDICATOR

AD8436

TOP VIEW

IBUFOUT

IBUFIN–

IBUFIN+

(Not to Scale)

5

11

6

10

IBUFGN DNC

OGND

OUT

VEE

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD SHOULD NOT BE CONNECTED.

Figure 3. Pin Configuration, Top View

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

±

2

3

4

ꢁ

6

7

1

DNC

RMS

Do Not Connect. Used for factory test.

AC Input to the RMS Core.

IBUFOUT

IBUFIN–

IBUFINꢂ

IBUFGN

DNC

Output Connection for the FET Input Buffer Amplifier.

Inverting Input to the FET Input Buffer Amplifier.

Noninverting Input to the FET Input Buffer Amplifier.

Optional ±0 kΩ Precision Gain Resistor.

Do Not Connect. Used for factory test.

OGND

Internal ±6 kΩ Current-to-Voltage Resistor. Connect to ground for voltage output at Pin 9; leave unconnected

for current output at Pin 9.

9

OUT

Voltage or Current Output of the RMS Core.

±0

±±

±2

±3

±4

±ꢁ

±6

±7

±1

±9

20

EP

VEE

IGND

Negative Supply Rail.

Half Supply Node. Leave open for single-supply operation.

Noninverting Input of the Optional Precision Output Buffer. OBUFINꢂ is typically connected to OUT.

Inverting Input of the Optional Precision Output Buffer. OBUFINꢀ is typically connected to OBUFOUT.

Low Impedance Output for ADC or Other Loads.

Power Pin for the Output Buffer.

Power Pin for the Input Buffer.

Positive Supply Rail for the RMS Core.

Connection for Crest Factor Capacitor.

Connection for Averaging Capacitor.

Summing Amplifier Input Node. An external resistor can be connected for custom scaling.

Exposed Pad. The exposed pad should not be connected.

OBUFINꢂ

OBUFINꢀ

OBUFOUT

OBUFVꢂ

IBUFVꢂ

VCC

CCF

CAVG

SUM

DNC

Rev. 0 | Page ꢁ of 20

AD8436

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 2ꢀ°C, ±V_S= ±ꢀ V, C_AVG= 1± μF, 1 kHz sine wave, unless otherwise indicated.

5V

1V

100mV

10mV

1mV

1V

100mV

10mV

1mV

−3dB BW

V

= 4.8V

1M

100µV

50µV

S

100µV

50µV

50 100

1k

10k

100k

5M

50 100

1k

10k

100k

1M

5M

FREQUENCY (Hz)

Figure 4. RMS Core Frequency Response (See Figure 20)

Figure 7. RMS Core Frequency Response with V_S= +4.8 V (See Figure 21)

5V

1V

15

e_IN= 3.5mV rms

12

9

6

100mV

10mV

1mV

3

0

–3

–6

–9

–12

–15

−3dB BW

V

= ±2.4V

1M

100µV

50µV

S

100

1k

10k

100k

1M

5M

50 100

1k

10k

100k

5M

FREQUENCY (Hz)

Figure 5. RMS Core Frequency Response with V_S= 2.4 V (See Figure 20)

Figure 8. Input Buffer, Small Signal Bandwidth at 0 dB and 6 dB Gain

15

5V

1V

e_IN= 300mV rms

12

9

6

100mV

3

0

10mV

–3

–6

–9

–12

–15

−3dB BW

1mV

V

= ±15V

1M

100µV

50µV

S

100

1k

10k

100k

1M

5M

50 100

1k

10k

100k

5M

FREQUENCY (Hz)

Figure 6. RMS Core Frequency Response with V_S= 15 V (See Figure 20)

Figure 9. Input Buffer, Large Signal Bandwidth at 0 dB and 6 dB Gain

Rev. 0 | Page 6 of 20

AD8436

10

5

15

12

9

e_IN= 3.5mV rms

P

= 100µs

W

6

CAVG = 10µF

CCF = 0.1µF

3

0

–3

–6

–9

–12

–15

CAVG = 10µF

−5

−10

100

1k

10k

100k

1M

5M

0

2

4

6

8

10

FREQUENCY (Hz)

CREST FACTOR RATIO

Figure 10. Output Buffer, Small Signal Bandwidth

Figure 13. Crest Factor Error vs. Crest Factor for CAVG and CAVG and CCF

Capacitor Combinations

1.00

0.75

0.50

0.25

0

0.5

0.4

CAVG = 10µF

8 SAMPLES

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

−0.25

−0.50

−0.75

−1.00

–50

–25

0

25

50

75

100

125

0

2

4

6

8

10

12

14

16

18

20

TEMPERATURE (°C)

SUPPLY VOLTAGE (±V)

Figure 14. Additional Conversion Error vs. Temperature

Figure 11. Additional Error vs. Supply Voltage

2.5

2.0

1.5

1.0

0.5

0

2.0

1.6

1.2

0.8

0.4

0

V

= ±15V

S

V

= ±5V

S

V

= ±2.4V

S

0

0.5

1.0

INPUT VOLTAGE (V rms)

1.5

2.0

0

16

2

4

6

8

10

12

14

18

SUPPLY VOLTAGE (±V)

Figure 15. RMS Core Supply Current vs. Input for V_S= 2.4 V, 5 V, and 15 V

Figure 12. Core Input Voltage for 1% Error vs. Supply Voltage

Rev. 0 | Page 7 of 20

AD8436

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

−50

−100

−150

−200

−250

−10

−50

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 16. FET Input Buffer Bias Current vs. Temperature

Figure 18. Output Buffer V_OSvs. Temperature

1000

750

CAVG = 10µF

1kHz 300mV rms BURST INPUT

0V

500

250

0

300mV DC OUT

−250

−500

−750

−1000

0V

1kHz 1mV rms BURST INPUT

1mV DC OUT

−50

−25

0

25

50

75

100

125

0V

TEMPERATURE (°C)

TIME (50ms/DIV)

Figure 17. Input Offset Voltage of FET Buffer vs. Temperature

Figure 19. Transition Times with 1 kHz Burst at Two Input Levels

(See Theory of Operation Section)

Rev. 0 | Page 1 of 20

AD8436

TEST CIRCUITS

SIGNAL SOURCE

10µF +5V

VCC

CAV

4.7µF

RMS

100kΩ

RMS CORE

IGND

AC-IN MONITOR

PRECISION DMM

100kΩ

16kΩ

OUT

OGND

VEE

–5V

PRECISION DMM

Figure 20. Core Response Test Circuit Using Dual Supplies

SIGNAL SOURCE

10µF 4.80V

CAV

VCC

4.7µF

RMS

100kΩ

RMS CORE

IGND

AC-IN MONITOR

PRECISION DMM

4.7µF

16kΩ

OUT

OGND

VEE

PRECISION DMM

Figure 21. Core Response Test Circuit Using a Single Supply

10µF +5V

FUNCTION GENERATOR

CAV

VCC

4.7µF

RMS

100kΩ

RMS CORE

IGND

AC-IN MONITOR

PRECISION DMM

16kΩ

OGND

VEE

OUT

–5V

PRECISION DMM

Figure 22. Crest Factor Test Circuit

Rev. 0 | Page 9 of 20

AD8436

THEORY OF OPERATION

OVERVIEW

For additional information, select Section I of the 2^ndedition of

The AD8436 is an implicit function rms-to-dc converter that

renders a dc voltage dependent on the rms (heating value) of an

ac voltage. In addition to the basic converter, this highly integrated

functional circuit block includes two fully independent, optional

amplifiers, a standalone FET input buffer amplifier and a precision

dc output buffer amplifier (see Figure 1). The rms core includes

a precision current responding full-wave rectifier and a log-antilog

transistor array for current squaring and square rooting to imple-

ment the classic expression for rms (see Equation 1). For basic

applications, the converter requires only an external capacitor, for

averaging (see Figure 3±). The optional on-board amplifiers

offer utility and flexibility in a variety of applications without

incurring additional circuit board footprint. For lowest power,

the amplifier supply pins are left unconnected.

the Analog Devices RMS-to-DC Applications Guide.

RMS Core

The core consists of a voltage-to-current converter (precision

resistor), absolute value, and translinear sections. The translinear

section exploits the properties of the bipolar transistor junctions

for squaring and root extraction (see Figure 23). The external

capacitor (CAVG) provides for averaging the product. Figure 19

shows that there is no effect of signal input on the transition times,

as seen in the dc output. Although the rms core responds to input

voltages, the conversion process is current sensitive. If the rms

input is ac-coupled, as recommended, there is no output offset

voltage, as reflected in Table 1. If the rms input is dc-coupled, the

input offset voltage is reflected in the output and can be calibrated

as with any fixed error.

Why RMS?

V+

The rms value of an ac voltage waveform is equal to the dc voltage

providing the same heating power to a load. A common measure-

ment technique for ac waveforms is to rectify the signal in a

straightforward way using a diode array of some sort, resulting in

the average value. The average value of various waveforms (sine,

square, and triangular, for example) varies widely; true rms is

the only metric that achieves equivalency for all ac waveforms.

See Table ꢀ for non-rms-responding circuit errors.

+

OUT

5kꢀ CAVG

AC IN

V-TO-I

ABSOLUTE

VALUE

CIRCUIT

V+

16kꢀ

The acronym “rms” means root-mean-square and reads as follows:

“the square root of the average of the sum of the squares” of the

peak values of any waveform. RMS is shown in the following

equation:

V–

Figure 23. RMS Core Block Diagram

(1)

Table 5. General AC Parameters

Reading of an Average Value Circuit

Calibrated to an RMS Sine Wave

Waveform Type (1 V p-p)

Crest Factor

RMS Value

0.707

±.00

0.ꢁ77

0.333

0.ꢁ

Error (%)

Sine

±.4±4

±.00

±.73

3

2

±0

0.707

±.±±

0.ꢁꢁꢁ

0.29ꢁ

0.271

0.0±±

0

±±.0

ꢀ3.1

Square

Triangle

Noise

Rectangular

Pulse

SCR

DC = ꢁ0%

DC = 2ꢁ%

ꢀ±±.4

ꢀ44

ꢀ19

ꢀ21

ꢀ30

0.±

2

4.7

0.49ꢁ

0.2±2

0.3ꢁ4

0.±ꢁ0

Rev. 0 | Page ±0 of 20

AD8436

The 16 kΩ resistor in the output converts the output current to

a dc voltage that can be connected to the output buffer or to the

circuit that follows. The output appears as a voltage source in

series with 16 kΩ. If a current output is desired, the resistor

connection to ground is left open and the output current is

applied to a subsequent circuit, such as the summing node of

a current summing amplifier. Thus, the core has both current

and voltage outputs, depending on the configuration. For a

voltage output with ± Ω source impedance, use the output

buffer. The offset voltage of the buffer is 2ꢀ ꢁV or ꢀ± ꢁV,

depending on the grade.

The output buffer can be configured as a single or two-pole low-

pass filter using circuits shown in the Applications Information

section. Residual output ripple is reduced, without affecting the

converted dc output. As the response approaches the low

frequency end of the bandwidth, the ripple rises, dependent on

the value of the averaging capacitor. Figure 26 shows the effects of

four combinations of averaging and filter capacitors. Although

the filter capacitor reduces the ripple for any given frequency, the

dc error is unaffected. Of course, a larger value averaging

capacitor can be selected, at a larger cost. The advantage of using

a low-pass filter is that a small value of filter capacitor, in

conjunction with the 16 kꢂ output resistor, reduces ripple and

permits a smaller averaging capacitor, effecting a cost savings.

The recommended capacitor values for operation to 4± Hz are

1± μF for averaging and 3.3 μF for filter.

FET Input Buffer

Referring to Figure 1, the input resistance of the AD8436 is 8 kꢂ,

and a voltage source input is preferred. The optional input buffer

is a wideband JFET input amplifier that minimally loads non-± ꢂ

sources, such as a tapped resistor attenuator or voltage sensor.

Although the input buffer consumes only 1ꢀ± ꢁA, the supply is

pinned out and left unconnected to reduce power where needed.

Dynamic Range

The AD8436 is a translinear rms-to-dc converter with exceptional

dynamic range. Although accuracy varies slightly more at the

extreme input values, the device still converts with no spurious

noise or dropout. Figure 24 is a plot of the rms/dc transfer function

near zero voltage. Unlike processor or other solutions, residual

errors at very low input levels can be disregarded for most

applications.

Optional matched 1± kꢂ input and feedback resistors are provided

on chip. Consult the Applications Information section to learn

how these resistors can be used. The 3 dB bandwidth of the input

buffer is 2.7 MHz at 1± mV rms input and approximately 1.ꢀ MHz

at 1 V rms. The amplifier gain and bandwidth are sufficient for

applications requiring modest gain or response enhancement to

a few hundred kilohertz (kHz), if desired. Configurations of the

input buffer are discussed in the Applications Information

section.

30

∆Σ OR OTHER DIGITAL

SOLUTIONS CANNOT

20

WORK AT ZERO

VOLTS

Precision Output Buffer

10

The precision output buffer is a bipolar input amplifier, laser

trimmed to cancel input offset voltage errors. As with the input

buffer, the supply current is very low (<ꢀ± ꢁA, typically), and the

power can be disconnected for power savings if the buffer is not

needed. Be sure that the noninverting input is also disconnected

from the core output (OUT) if the buffer supply pin is discon-

nected. Although the input current of the buffer is very low,

a laser-trimmed 16 kΩ resistor, connected in series with the

inverting input, offsets any self-bias offset voltage.

AD8436

SOLUTION

0

–30

–20

–10

0

10

20

30

INPUT VOLTAGE (mV DC)

Figure 24. DC Transfer Function near Zero

Rev. 0 | Page ±± of 20

AD8436

APPLICATIONS INFORMATION

Ripple is reduced by increasing the value of the averaging capacitor,

or by postconversion filtering. Ripple reduction following

conversion is far more efficient because the ripple average value

has been converted to its rms value. Capacitor values for post-

conversion filtering are significantly less than the equivalent

averaging capacitor value for the same level of ripple reduction.

This approach requires only a single capacitor connected to the

OUT pin (see Figure 2ꢀ). The capacitor value correlates to the

simple frequency relation of ½ π R-C, where R is fixed at 16 kꢂ.

USING THE AD8436

This section describes the power supply and feature options,

as well as the function and selection of averaging and filter

capacitor values. Averaging and filtering options are shown

graphically and apply to all circuit configurations.

Averaging Capacitor Considerations—RMS Accuracy

Typical AD8436 applications require only a single external

capacitor (CAVG) connected to the CAVG pin (see Figure 3±).

The function of the averaging capacitor is to compute the mean

(that is, average value) of the sum of the squares. Averaging

(that is, integration) follows the absolute value circuit, where

the polarity of negative input current components is reversed

(rectified) prior to squaring. The mean value is the average

value of the squared input voltage over several input waveform

periods. The rms error is directly affected by the number of

periods averaged, as is the resultant peak-to-peak ripple.

OUT

CORE

DC OUTPUT

CLPF

9

16kꢀ

OGND

8

Figure 25. Simple One-Pole Post Conversion Filter

As seen in Figure 26, CAVG alone determines the rms error,

and CLPF serves purely to reduce ripple. Figure 26 shows a

constant rms error for CLPF values of ±.33 μF and 3.3 μF; only

the ripple is affected.

The result of the conversion process is a dc component and a

ripple component whose frequency is twice that of the input. The

rms conversion accuracy depends on the value of CAVG, so the

value selected need only be large enough to average enough periods

at the lowest frequency of interest to yield the required rms

accuracy. Figure 27 is a plot of rms error vs. frequency for various

averaging capacitor values. For Figure 27, the additional error

was ±.±±15 at 4± Hz using a 1± μF metalized polyester capacitor.

Larger values yield diminished returns because the settling time

increases with negligible improvement in rms accuracy.

1

CAVG = 10µF

CLPF = 0.33µF OR 3.3µF

0

–1

–2

–3

–4

–5

To use Figure 27, determine the minimum operating frequency

and accuracy of the application and then find the suggested

capacitor value on the chart. For example, for –±.ꢀ5 rms at 1±± Hz,

the capacitor value is 1 μF.

–6

CAVG = 1µF

CLPF = 0.33µF OR 3.3µF

–7

–8

–9

Post Conversion Ripple Reduction Filter

Input rectification included in the AD8436 introduces a

residual ripple component that is dependent on the value

of CAVG and twice the input signal frequency. For sampling

applications such as a high resolution ADC, the ripple component

may cause one or more LSBs to cycle, and low value display

numerals to flash.

–10

10

100

1k

FREQUENCY (Hz)

Figure 26. RMS Error vs. Frequency for Two Values of CAVG and CLPF

(Compare the effects of CAVG and CLPF, and

note that CLPF does not affect rms error result.)

0

22µF

47µF

10µF

–0.5

–1.0

4.7µF

0.47µF

CAVG = 0.22µF

2.2µF

1µF

–1.5

–2.0

10

100

FREQUENCY (Hz)

1k

Figure 27. Conversion Error vs. Frequency for Various Values of CAVG

Rev. 0 | Page ±2 of 20

AD8436

For simplicity, Figure 28 shows ripple vs. frequency for four

combinations of CAVG and CLPF

The signal source sees the input 8 kΩ voltage-to-current conversion

resistor at Pin 2 (RMS); thus, the ideal source impedance is a

voltage source (± Ω source impedance). If a non-zero signal source

impedance cannot be avoided, be sure to account for any series

connected voltage drop.

An input coupling capacitor must be used to realize the near-zero

output offset voltage feature of the AD8436. Select a coupling

capacitor value that is appropriate for the lowest expected

operating frequency of interest. As a rule of thumb, the input

coupling capacitor can be the same as or half the value of the

averaging capacitor because the time constants are similar. For

a 1± ꢁF averaging capacitor, a 4.7 ꢁF or 1± ꢁF tantalum capacitor

is a good choice (see Figure 3±).

1

AC INPUT = 300mV rms

CAVG = 1µF, CLPF = 0.33µF

CAVG = 1µF, CLPF = 3.3µF

CAVG = 10µF, CLPF = 0.33µF

CAVG = 10µF, CLPF = 3.3µF

0.1

0.01

0.001

0.0001

CAVG

+5V

10

100

INPUT FREQUENCY (Hz)

1k

10µF

Figure 28. Residual Ripple Voltage for Various Filter Configurations

4.7µF

OR

10µF

19

17

CAVG

VCC

Figure 29 shows the effects of averaging and post-rms filter

capacitors on transition and settling times using a 1±-cycle,

ꢀ± Hz, 1 second period burst signal input to demonstrate time-

domain behavior. In this instance, the averaging capacitor value

was 1± μF, yielding a ripple value of 6 mV rms. A postconversion

capacitor (CLPF) of .±68 ꢁF reduced the ripple to 1 mV rms. An

averaging capacitor value of 82 ꢁF reduced the ripple to 1 mV

but extended the transition time (and cost) significantly.

AD8436

2

9

RMS

OUT

IGND VEE OGND

11

10

8

–5V

Figure 30. Basic Applications Circuit

Using a Capacitor for High Crest Factor Applications

The AD8436 contains a unique crest factor feature. Crest factor

is often overlooked when considering the requirements of rms-

to-dc converters, but it is very important when working with

signals with spikes or high peaks. The crest factor is defined as

the ratio of peak voltage to rms. See Table ꢀ for crest factors for

some common waveforms.

INPUT

50Hz 10 CYCLE BURST

400mV/DIV

CAVG = 10µF FOR BOTH

PLOTS, BUT RED PLOT HAS

NO LOW-PASS FILTER, GREEN

PLOT HAS CLPF = 68nF 100mV/DIV

CAVG

+5V

10µF

CCF

CAVG = 82µF

0.1µF

4.7µF

OR

10µF

19

18

17

CAVG CCF

VCC

AD8436

2

9

RMS

OUT

TIME (100ms/DIV)

Figure 29. Effects of Various Filter Options on Transition Times

IGND VEE OGND

11

10

8

Capacitor Construction

–5V

Although tolerant of most capacitor styles, rms conversion

accuracy can be affected by the type of capacitor that is selected.

Capacitors with low dc leakage yield best all around performance,

and many sources are available. Metalized polyester or similar

film styles are best, as long as the temperature range is appropriate.

Figure 31. Connection for Additional Crest Factor Performance

Crest factor performance is mostly applicable for unexpected

waveforms such as switching transients in switchmode power

supplies. In such applications, most of the energy is in these

peaks and can be destructive to the circuitry involved, although

the average ac value can be quite low.

For practical applications such as the rms-to-dc function in

DMMs or power monitoring circuits, surface mount tantalums

are the best over-all choice.

Figure 13 shows the effects of an additional crest factor

capacitor of ±.1 ꢁF and an averaging capacitor of 1± ꢁF. The

larger capacitor serves to average the energy over long spaces

between pulses, while the CCF capacitor charges and holds the

energy within the relatively narrow pulse.

Basic Core Connections

Many applications require only a single external capacitor for

averaging. A 1± μF capacitor is more than adequate for acceptable

rms errors at line frequencies and below.

Rev. 0 | Page ±3 of 20

AD8436

Using the FET Input Buffer

The bandwidth diminishes at the typical rate of a decade per 2± dB

of gain, and the output voltage range is constrained. The small

signal response, as shown in Figure 8, serves as a guide. As an

example, suppose one wanted to detect small input signals at power

line frequencies? An external 1± ꢂ resistor connected from Pin 4 to

ground sets the gain to 1±1 and the 3 dB bandwidth to ~3± kHz,

which is more than adequate for amplifying power line frequencies.

The on-chip FET input buffer is an uncommitted FET input

op amp used for driving the 8 kꢂ I-to-V input resistor of the

rms core. Pin 3, Pin 4, and Pin ꢀ are the I/O, Pin 6 is an optional

connection for gain in the input buffer, and and Pin 16 connects

power to the buffer (see Figure 3 and Table 4 for location and

description). Connecting Pin 16 to the positive rail is the only

power connection required because the negative rail is internally

connected. Because the input stage is a FET and the input

impedance must be very high to prevent loading of the source,

a large value (1± Mꢂ) resistor must be connected from midsupply

at Pin 11 (IGND) to Pin ꢀ (IBUFIN+) to prevent the input gate

from floating high.

Using the Output Buffer

The AD8436 output is a precision op amp that is optimized

for dc operation. Figure 33 shows a block diagram of the basic

amplifier and I/O pins. The amplifier is intended for noninverting

operation only; note that the 16 kΩ resistor, in series with the

inverting input of the amplifier, is used to balance the bias

current of the noninverting amplifier.

For unity gain, connect Pin 3 (IBUFOUT) to Pin 4 (IBUFIN−).

For a gain of 2×, connect Pin 6 (IBUFGN) to ground. See Figure 8

and Figure 9 for large and small signal responses at the two

built-in gain options.

As with the input FET buffer, the amplifier positive supply is

pinned out separately for power sensitive applications. In normal

circumstances, the buffers are connected to the same supply as

the core. Figure 34 shows the signal connections to the output

buffer. Note that the input offset voltage contribution by the

bias currents are balanced by equal value series resistors,

resulting in near zero offset voltage.

The offset voltage of the input buffer is ≤ꢀ±± ꢁV, depending on

grade. A capacitor connected between the Buffer Output Pin 3

(IBUFOUT) and Pin 2 (RMS) is recommended so that the input

buffer offset voltage does not contribute to the overall error.

Select the capacitor value for least minimum error at the lowest

operating frequency. Figure 32 is a schematic showing internal

components and pin connections.

OUTPUT BUFFER

OBUFIN+

OBUFIN–

+

–

OBUFOUT

16kꢀ

16

Figure 33. Output Buffer Block Diagram

RMS

IBUFV+

2

10µF

IBUFOUT

IBUFIN–

IBUFIN+

3

4

5

–

IBIAS

0.47µF

OUT

OBUFIN+

CORE

OBUFOUT

9

12

13

+

–

10kꢀ

14

16kꢀ

10Mꢀ

10pF

OBUFIN–

11 IGND

OGND

8

10kꢀ

6

Figure 34. Basic Output Buffer Connections

IBUFGN

For applications requiring ripple suppression in addition to the

single-pole output filter described previously, the output buffer

is configurable as a two-pole Sallen-Key filter using two external

resistors and two capacitors. At just over 1±± kHz, the amplifier

has enough bandwidth to function as an active filter for low

frequencies such as power line ripple. For a modest savings in

cost and complexity, the external 16 kΩ feedback resistor can be

omitted, resulting in slightly higher V_OS(8± ꢁV).

Figure 32. Connecting the FET Input Buffer

Capacitor coupling at the input and output of the FET buffer is

recommended to avoid transferring the buffer offset voltage to

the output. Although the FET input impedance is extremely high,

the 1± MΩ centering resistor connected to IGND must be taken

into account when selecting an input capacitor value. This is simply

an impedance calculation using the lowest desired frequency,

and finding a capacitor value based on the least attenuation desired.

2C

Because the 1± kΩ resistors are closely matched and trimmed to

a high tolerance, the input buffer gain can be increased to several

hundred with an external resistor connected to Pin 4 (IBUFIN−).

OBUFIN+

OUT

16kꢀ

9

12

13

CORE

+

–

14

C

16kꢀ

OBUFOUT

OBUFIN–

OGND

8

16kꢀ

Figure 35. Output Buffer Amplifier Configured as a Two-Pole, Sallen-Key

Low-Pass Filter

Rev. 0 | Page ±4 of 20

AD8436

10µF

Configure the output buffer as shown in Figure 36 to invert the

dc output.

19

17

CAV

VCC

OUT

16kꢀ

CORE

9

13

12

–

+

2

3

4

5

RMS

AD8436

OBUFIN–

OUT

9

14

4.7µF

16kꢀ

OBUFOUT

IBUFOUT

IBUFIN–

IBUFIN+

OBUFIN+

OGND

32.4kꢀ

8

0.47µF

IGND 11

4.7µF

Figure 36. Inverting Output Configuration

OGND

VEE

10

10Mꢀ

8

Current Output Option

If a current output is required, connect the current output, OUT

(Pin 9), to the destination load. To maximize precision, provide

a means for external calibration to replace the internal trimmed

resistor, which is bypassed. This configuration is useful for conve-

nient summing of the AD8436 result with another voltage, or

for polarity inversion.

Figure 38. Connections for Single Supply Operation

Recommended Application

Figure 39 shows a circuit for a typical application for frequencies

as low as power line, and above. The recommended averaging,

crest factor and LPF capacitor values are 1± ꢁF, ±.1 ꢁF and

3.3 ꢁF. Refer to the Using the Output Buffer section if additional

low-pass filtering is required.

CAVG CCF

19

18

DIRECTION OF

DC OUTPUT

CURRENT

VCC

2kꢀ

(OPTIONAL)

OUT

15kꢀ

8kꢀ

10µF

2

9

CORE

RMS

0.1µF

+

20 19

18

17

16

–

SUM CAVG CCF VCC IBUFV+

INVERTED DC

VOLTAGE

OUTPUT

+

15

14

13

12

11

16kꢀ

1

2

DNC

OBUFV+

16kꢀ

AD8436

8

DC

OUT

RMS

OBUFOUT

OBUFIN–

OBUFIN+

OGND

DO NOT CONNECT FOR

CURRENT OUTPUT

10µF

3

4

5

IBUFOUT

IBUFIN–

IBUFIN+

Figure 37. Connections for Current Output Showing Voltage Inversion

Single Supply

0.47µF

Connections for single supply operation are shown in Figure 38

and are similar to those for dual power supply when the device is

ac-coupled. The analog inputs are all biased to half the supply

voltage, but the output remains referred to ground because the

output of the AD8436 is a current source. An additional bypass

connection is required at Pin 11 (IGND) to suppress ambient noise.

IGND

VEE

AC IN

10Mꢀ

IBUFGN DNC OGND OUT

6

7

8

9

10

VEE

3.3µF

Figure 39. Typical Application Circuit

Rev. 0 | Page ±ꢁ of 20

AD8436

AD8436 EVALUATION BOARD

The AD8436-EVALZ provides a platform to evaluate AD8436

performance. The board is fully assembled, tested and ready to

use after the power and signal sources are connected. Figure 45

is a photograph of the board. Signal connections are located

on the primary and secondary sides, with power and ground

on the inner layers. Figure 40, Figure 41, Figure 42, Figure 43,

and Figure 44 illustrate the various design details of the board,

including a basic layout and copper patterns. These figures are

useful for reference for application designs.

Figure 41. AD8436-EVALZ Primary Side Copper

A Word About Using the AD8436 Evaluation Board

The AD8436-EVALZ offers many options, without sacrificing

simplicity. The board is tested and shipped with a 10 μF averaging

capacitor (CAVG), 3.3 μF low-pass filter capacitor (C8) and a

0.1 μF (COPT) capacitor to optimize crest factor performance.

To evaluate minimum cost applications, remove C8 and COPT.

The functions of the five switches are listed in Table 6.

Table 6.

Switch

Function

Figure 42. AD8436-EVALZ Secondary Side Copper

CORE_BUFFER

INCOUP

Selects core or input for the input signal

Selects ac or dc coupling to the core

SDCOUT

Selects the output buffer or the core

output at the DCOUT BNC.

IBUF_VCC

OBUF_VCC

Enable or disables the input buffer

Enable or disables the output buffer

All the I/Os are provided with test points for easy monitoring

with test equipment. The input buffer gain default is unity; for

2× gain, install a 0603 0 Ω resistor at Position R5. For higher

IBUF gains, remove the 0 Ω resistor at Position RFBH (there is

an internal 10 kΩ resistor from the OBUF_OUT to IBUFIN−)

and install a smaller value resistor in Position RFBL. A 100 Ω

resistor establishes a gain of 100×.

Figure 43. AD8436-EVALZ Power Plane

Single supply operation requires removal of Resistor R6 and

installing a 0.1 μF capacitor in the same position for noise

decoupling.

Figure 44. AD8436-EVALZ Ground Plane

Figure 40. Assembly of the AD8436-EVALZ

Rev. 0 | Page 16 of 20

AD8436

Figure 45. Photograph of the AD8436-EVALZ

+V

(RED)

–V

(GRN)

CAVE

10µF

GND1 GND2 GND3 GND4 GND5 GND6

C2

+ 10µF

50V

–40°C TO +125°C

VEE

C1

10µF

50V

C4

0.1µF

TIBUFV+

EN

+

COPT

0.1µF

+

DIS

TCAVE

TOPT

18

TSUM

–40°C TO +125°C

IBUF_VCC

20

SUM

19

17

VCC

16

IBUF

INCOUP

DC

CAVG

DNC

VCC

TOBUFV+

15

EN

V+

DIS

AC

OBUF

DNC

1

V+

CORE_BUF

CORE

OBUF_VCC

CIN

10µF

TOBFOUT

14

AC IN

TRMSIN

2

OBUF

OUT

RMS

R8

0ꢀ

BUF

C6

0.47µF

TOBUFIN–

13

TIBUFOUT

3

OBUF

IN–

AD8436

IBUFOUT

IBUFIN–

IBUFIN+

TACIN

TDCOUT

BUF

RFBH

DC

0ꢀ

TOBUFIN+

TIBFIN–

OUT

4

12

11

C5

0.47µF

OBUF

IN+

CORE

RFBL

DNI

C7

0.22µF

SDCOUT

TIBFIN+

5

TIGND

IGND

VEE

R1

1Mꢀ

R3

4.99kꢀ

IBUFGN

6

DNC

7

OGND

8

OUT

9

R7

0ꢀ

10

TBUFGN

TOGND

R6

0ꢀ

C3

R4

4.99kꢀ

TIOUT

0.1µF

R5

0ꢀ

R2

0ꢀ

VEE

C38

3.3µF

*COMPONENTS IN GRAY ARE NOT FACTORY INSTALLED.

Figure 46. Evaluation Board Schematic

Rev. 0 | Page ±7 of 20

AD8436

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

PIN 1

INDICATOR

16

15

20

0.50

BSC

1

EXPOSED

PAD

2.65

2.50 SQ

2.35

5

11

6

10

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 47. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

(CP-20-10)

Dimensions shown in inches

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-20-±0

AD1436ACPZ-R7

AD1436ACPZ-RL

AD1436ACPZ-WP

AD1436JCPZ-R7

AD1436JCPZ-RL

AD1436JCPZ-WP

AD1436-EVALZ

ꢀ40°C to ꢂ±2ꢁ°C

0°C to ꢂ70°C

20-Lead Lead Frame Chip Scale [LFCSP_WQ]

Evaluation Board

CP-20-±0

^±Z = RoHS Compliant Part.

Rev. 0 | Page ±1 of 20

AD8436

NOTES

Rev. 0 | Page ±9 of 20

AD8436

NOTES

registered trademarks are the property of their respective owners.

D10033-0-7/11(0)

Rev. 0 | Page 20 of 20


型号：	AD8436ACPZ-RL
厂家：	ADI
描述：	Low Cost, Low Power 低成本，低功耗
文件：	总20页 (文件大小：742K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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