AD844JR-16-REEL [ADI]
60 MHz, 2000 V/us Monolithic Op Amp; 60兆赫， 2000 V / us的单片运算放大器
| 型号： | AD844JR-16-REEL |
| 厂家： | 
ADI |
| 描述： | 60 MHz, 2000 V/us Monolithic Op Amp |
| 文件： | 总16页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60 MHz, 2000 V/ꢀs
Monolithic Op Amp
a
AD844
FEATURES
CONNECTION DIAGRAMS
Wide Bandwidth: 60 MHz at Gain of –1
Wide Bandwidth: 33 MHz at Gain of –10
Very High Output Slew Rate: Up to 2000 V/ꢀs
20 MHz Full Power Bandwidth, 20 V p-p, RL = 500 ꢁ
Fast Settling: 100 ns to 0.1% (10 V Step)
Differential Gain Error: 0.03% at 4.4 MHz
Differential Phase Error: 0.158 at 4.4 MHz
High Output Drive: 650 mA into 50 ꢁ Load
Low Offset Voltage: 150 mV Max (B Grade)
Low Quiescent Current: 6.5 mA
8-Lead Plastic (N),
and Cerdip (Q) Packages
16-Lead SOIC
(R) Package
1
2
3
4
5
6
7
8
16
NC
NC
AD844
1
2
3
4
8
7
6
5
NULL
–IN
NULL
AD844
OFFSETNULL
15 OFFSETNULL
+V
S
14
13
12
11
10
9
–IN
NC
+IN
NC
V–
V+
+IN
OUTPUT
TZ
NC
TOP VIEW
(Not to Scale)
–V
S
OUTPUT
TZ
Available in Tape and Reel in Accordance with
EIA-481A Standard
NC
TOP VIEW
(Not to Scale)
NC
NC
APPLICATIONS
NC = NO CONNECT
Flash ADC Input Amplifiers
High-Speed Current DAC Interfaces
Video Buffers and Cable Drivers
Pulse Amplifiers
package. The AD844A is also available in an 8-lead plastic
mini-DIP (N). The AD844S is specified over the military tempera-
ture range of –55°C to +125°C. It is available in the 8-lead
cerdip (Q) package. “A” and “S” grade chips and devices processed
to MIL-STD-883B, REV. C are also available.
PRODUCT DESCRIPTION
The AD844 is a high-speed monolithic operational amplifier
fabricated using Analog Devices’ junction isolated complemen-
tary bipolar (CB) process. It combines high bandwidth and very
fast large signal response with excellent dc performance. Although
optimized for use in current to voltage applications and as an
inverting mode amplifier, it is also suitable for use in many
noninverting applications.
PRODUCT HIGHLIGHTS
1. The AD844 is a versatile, low cost component providing an
excellent combination of ac and dc performance.
The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac perfor-
mance, high linearity and an exceptionally clean pulse response.
2. It is essentially free from slew rate limitations. Rise and fall
times are essentially independent of output level.
This type of op amp provides a closed-loop bandwidth which is
determined primarily by the feedback resistor and is almost inde-
pendent of the closed-loop gain. The AD844 is free from the slew
rate limitations inherent in traditional op amps and other
current-feedback op amps. Peak output rate of change can be over
2000 V/µs for a full 20 V output step. Settling time is typically
100 ns to 0.1%, and essentially independent of gain. The AD844
can drive 50 Ω loads to 2.5 V with low distortion and is short
circuit protected to 80 mA.
3. The AD844 can be operated from 4.5 V to 18 V power
supplies and is capable of driving loads down to 50 Ω, as well
as driving very large capacitive loads using an external network.
4. The offset voltage and input bias currents of the AD844 are
laser trimmed to minimize dc errors; VOS drift is typically
1 µV/°C and bias current drift is typically 9 nA/°C.
5. The AD844 exhibits excellent differential gain and differen-
tial phase characteristics, making it suitable for a variety of
video applications with bandwidths up to 60 MHz.
The AD844 is available in four performance grades and three
package options. In the 16-lead SOIC (R) package, the AD844J is
specified for the commercial temperature range of 0°C to 70°C.
The AD844A and AD844B are specified for the industrial tem-
perature range of –40°C to +85°C and are available in the cerdip (Q)
6. The AD844 combines low distortion, low noise and low drift
with wide bandwidth, making it outstanding as an input
amplifier for flash A/D converters.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(@ T = 25ꢂC and V = ꢃ15 V dc, unless otherwise noted)
AD844–SPECIFICATIONS
A
S
AD844J/A
AD844B
Typ
AD844S
Min Typ
Model
Conditions
Min Typ
Max
Min
Max
Max
Unit
INPUT OFFSET VOLTAGE1
TMIN–TMAX
vs. Temperature
50
75
1
300
500
50
75
1
150
200
5
50
125
1
300
500
5
µV
µV
µV/°C
vs. Supply
5 V–18 V
Initial
TMIN–TMAX
vs. Common Mode
Initial
TMIN–TMAX
4
4
20
35
4
4
10
10
4
4
20
20
µV/V
µV/V
VCM = 10 V
10
10
10
10
20
20
10
10
35
35
µV/V
µV/V
INPUT BIAS CURRENT
–Input Bias Current1
TMIN–TMAX
vs. Temperature
vs. Supply
200
800
9
450
1500
150
750
9
250
1100
15
200
1900 2500
20
450
nA
nA
nA/°C
30
5 V–18 V
Initial
TMIN–TMAX
vs. Common Mode
Initial
175
220
250
160
175
220
200
240
175
220
250
300
nA/V
nA/V
VCM = 10 V
90
90
110
150
200
500
7
90
160
200
400
1300
15
nA/V
nA/V
nA
nA
nA/°C
TMIN–TMAX
110
150
350
3
110
100
300
3
120
100
800
7
+Input Bias Current1
TMIN–TMAX
400
700
vs. Temperature
vs. Supply
5 V–18 V
Initial
TMIN–TMAX
vs. Common Mode
Initial
TMIN–TMAX
80
100
150
150
80
100
100
120
80
120
150
200
nA/V
nA/V
VCM = 10 V
90
130
90
130
120
190
90
140
150
200
nA/V
nA/V
INPUT CHARACTERISTICS
Input Resistance
–Input
+Input
Input Capacitance
–Input
50
10
65
50
10
65
50
10
65
Ω
7
7
7
MΩ
2
2
2
2
2
2
pF
pF
+Input
Input Voltage Range
Common Mode
10
10
10
V
INPUT VOLTAGE NOISE
f ≥ 1 kHz
2
2
2
nV/√Hz
INPUT CURRENT NOISE
–Input
+Input
f ≥ 1 kHz
f ≥ 1 kHz
10
12
10
12
10
12
pA/√Hz
pA/√Hz
OPEN LOOP TRANSRESISTANCE
VOUT = 10 V
RLOAD = 500 Ω
2.2
1.3
3.0
2.0
4.5
2.8
1.6
3.0
2.0
4.5
2.2
1.3
3.0
1.6
4.5
MΩ
MΩ
pF
TMIN–TMAX
Transcapacitance
DIFFERENTIAL GAIN ERROR2
DIFFERENTIAL PHASE ERROR2
f = 4.4 MHz
f = 4.4 MHz
0.03
0.15
0.03
0.15
0.03
0.15
%
Degree
FREQUENCY RESPONSE
Small Signal Bandwidth
Gain = –13
60
33
60
33
60
33
MHz
MHz
Gain = –104
TOTAL HARMOMIC DISTORTION f = 100 kHz,
2 V rms5
0.005
0.005
0.005
%
SETTLING TIME
10 V Output Step
15 V Supplies
5 V Supplies
Gain = –1, to 0.1%5
Gain = –10, to 0.1%6
2 V Output Step
100
100
100
100
100
100
ns
ns
Gain = –1, to 0.1%5
Gain = –10, to 0.1%6
110
100
110
100
110
100
ns
ns
–2–
REV. D
AD844
AD844J/A
Min Typ
AD844B
Typ
AD844S
Min Typ
Model
Conditions
Max
Min
Max
Max
Unit
OUTPUT SLEW RATE
Overdriven
Input
1200 2000
1200
2000
1200 2000
V/µs
FULL POWER BANDWIDTH
VOUT = 20 V p-p5
VS = 15 V
VS = 5 V
THD = 3%
20
20
20
20
20
20
MHz
MHz
VOUT = 2 V p-p5
OUTPUT CHARACTERISTICS
Voltage
Short Circuit Current
TMIN–TMAX
RLOAD = 500 Ω
10
11
80
60
15
10
11
80
60
15
10
11
80
60
15
V
mA
mA
Ω
Output Resistance
Open Loop
POWER SUPPLY
Operating Range
Quiescent Current
TMIN–TMAX
4.5
18
7.5
8.5
4.5
18
7.5
8.5
+4.5
18
7.5
9.5
V
mA
mA
6.5
7.5
6.5
7.5
6.5
8.5
NOTES
1Rated performance after a 5 minute warmup at TA = 25°C.
2Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL= 100 Ω; R1, R2 = 300 Ω.
3Input signal 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 500 Ω in Figure 2.
4Input signal 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 2.
5CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in Figure 2.
6CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 2.
Specifications subject to change without notice. All min and max specifications are guaranteed.
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Inverting Input Current
28-Lead Plastic Package:
8-Lead Cerdip Package:
16-Lead SOIC Package:
θ
θ
θ
JA = 90°C/W
JA = 110°C/W
JA = 100°C/W
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimension shown in inches and (mm).
ORDERING GUIDE
Temperature
Range
Package
Option
*
Model
AD844AN
AD844ACHIPS
AD844AQ
AD844BQ
AD844JR-16
AD844JR-16-REEL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
N-8
Die
Q-8
Q-8
R-16
13" Tape
and Reel
7" Tape
and Reel
Die
0°C to 70°C
AD844JR-16-REEL7
0°C to 70°C
AD844SCHIPS
AD844SQ
AD844SQ/883B
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Q-8
Q-8
Q-8
5962-8964401PA
*
N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
REV. D
–3–
AD844–Typical Characteristics (TA = 25ꢂC and VS = ꢃ15 V, unless otherwise noted)
–60
70
60
50
40
30
5
4
3
2
1
0
R
=
L
–70
–80
R
= 500ꢁ
L
1V rms
–90
–100
–110
R
= 50ꢁ
L
2ND HARMONIC
–120
–130
3RD HARMONIC
10k 100k
100
1k
INPUT FREQUENCY – Hz
0
5
10
15
20
–50
0
50
100
150
TEMPERATURE – ꢂC
SUPPLYVOLTAGE – ꢃV
TPC 1. –3 dB Bandwidth vs.
Supply Voltage R1 = R2 = 500 Ω
TPC 3. Transresistance vs.
Temperature
TPC 2. Harmonic Distortion vs.
Frequency, R1 = R2 = 1 kΩ
20
10
9
20
T
= 25ꢂC
A
R
T
= 500ꢁ
= 25ꢂC
L
A
15
10
5
15
10
5
8
7
V
= ꢃ15V
S
6
V
= ꢃ5V
S
5
4
0
0
–60 –40 –20
0
20 40 60 80 100 120 140
0
5
10
15
20
0
5
10
15
20
SUPPLYVOLTAGE – ꢃV
TEMPERATURE – ꢂC
SUPPLYVOLTAGE – ꢃV
TPC 4. Noninverting Input Voltage
Swing vs. Supply Voltage
TPC 6. Quiescent Supply
Current vs. Temperature and
Supply Voltage
TPC 5. Output Voltage Swing
vs. Supply Voltage
40
35
30
25
20
100
2
1
V
= ꢃ15V
S
10
1
ꢃ5V SUPPLIES
I
BP
V
= ꢃ5V
0
S
0.1
–1
I
BN
15
10
0.01
10k
–2
–50
100k
1M
10M
100M
–60 –40 –20
0
20 40 60 80 100 120 140
0
50
100
150
TEMPERATURE – ꢂC
FREQUENCY – Hz
TEMPERATURE – ꢂC
TPC 7. Inverting Input Bias Cur-
rent (IBN) and Noninverting Input
Bias Current (IBP) vs. Temperature
TPC 9. –3 dB Bandwidth vs.
Temperature, Gain = –1,
R1 = R2 = 1 kΩ
TPC 8. Output Impedance vs.
Frequency, Gain = –1, R1 = R2 = 1 kΩ
–4–
REV. 0
AD844
Inverting Gain-of-1 AC Characteristics
–180
+V
6
S
R1 = R2 = 500ꢁ
4.7ꢁ
0.22ꢀF
–210
–240
–270
0
R1
R1 = R2 = 500ꢁ
R1 = R2 = 1kꢁ
–6
R2
V
–
IN
V
AD844
OUT
–12
+
R1 = R2 = 1kꢁ
R
L
C
L
–300
–330
–18
–24
0.22ꢀF
4.7ꢁ
100k
1M
10M
100M
0
25
50
–V
S
FREQUENCY – Hz
FREQUENCY – MHz
TPC 10. Inverting Amplifier,
Gain of –1 (R1 = R2)
TPC 11. Gain vs. Frequency for
Gain = –1, RL = 500 Ω, CL = 0 pF
TPC 12. Phase vs. Frequency
Gain = –1, RL = 500 Ω, CL = 0 pF
TPC 14. Small Signal Pulse
TPC 13. Large Signal Pulse
Response, Gain = –1, R1 = R2 = 1 kΩ
Response, Gain = –1, R1 = R2 = 1 kΩ
Inverting Gain-of-10 AC Characteristics
26
–180
+V
S
R
= 500ꢁ
L
4.7ꢁ
20
14
8
–210
–240
–270
0.22ꢀF
R
= 50ꢁ
500ꢁ
L
R
= 500ꢁ
L
50ꢁ
–
V
IN
R = 50ꢁ
L
AD844
V
OUT
+
2
–300
–330
R
C
L
L
–4
100k
0.22ꢀF
1M
10M
100M
0
25
50
4.7ꢁ
FREQUENCY – Hz
FREQUENCY – MHz
–V
S
TPC 16. Gain vs. Frequency,
Gain = –10
TPC 15. Gain of –10 Amplifier
TPC 17. Phase vs. Frequency,
Gain = –10
REV. D
–5–
AD844
Inverting Gain-of-10 Pulse Response
TPC 19. Small Signal Pulse
Response, Gain = –10, RL = 500 Ω
TPC 18. Large Signal Pulse
Response, Gain = –10, RL = 500 Ω
Noninverting Gain-of-10 AC Characteristics
26
–180
R
= 500ꢁ
L
+V
20
14
8
S
0.22ꢀF
450ꢁ
–210
–240
–270
4.7ꢁ
R
= 50ꢁ
R
= 500ꢁ
L
L
–
R
= 50kꢁ
L
V
OUT
50ꢁ
AD844
V
+
IN
0.22ꢀF
R
2
L
–300
–330
C
L
4.7ꢁ
–4
100k
–V
1M
10M
100M
S
0
25
FREQUENCY – MHz
50
FREQUENCY – Hz
TPC 20. Noninverting Gain of
+10 Amplifier
TPC 22. Phase vs. Frequency,
Gain = +10
TPC 21. Gain vs. Frequency,
Gain = +10
TPC 23. Noninverting Amplifier Large
Signal Pulse Response, Gain = +10,
RL = 500 Ω
TPC 24. Small Signal Pulse
Response, Gain = +10, RL = 500 Ω
–6–
REV. D
AD844
UNDERSTANDING THE AD844
Response as an Inverting Amplifier
The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband
applications. However, there are important differences in the
internal structure which need to be understood in order to
optimize the performance of the AD844 op amp.
Figure 2 shows the connections for an inverting amplifier.
Unlike a conventional amplifier the transient response and the
small signal bandwidth are determined primarily by the value of
the external feedback resistor, R1, rather than by the ratio of
R1/R2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed loop gain is –R1/R2.
Open Loop Behavior
Figure 1 shows a current feedback amplifier reduced to essen-
tials. Sources of fixed dc errors such as the inverting node bias
current and the offset voltage are excluded from this model and
are discussed later. The most important parameter limiting the
dc gain is the transresistance, Rt, which is ideally infinite. A finite
value of Rt is analogous to the finite open loop voltage gain in a
conventional op amp.
The closed loop transresistance is simply the parallel sum of R1
and Rt. Since R1 will generally be in the range 500 Ω to 2 kΩ
and Rt is about 3 MΩ the closed loop transresistance will be
only 0.02% to 0.07% lower than R1. This small error will often
be less than the resistor tolerance.
When R1 is fairly large (above 5 kΩ) but still much less than Rt,
the closed loop HF response is dominated by the time constant
R1Ct. Under such conditions the AD844 is over-damped and
will provide only a fraction of its bandwidth potential. Because
of the absence of slew rate limitations under these conditions,
the circuit will exhibit a simple single pole response even under
large signal conditions.
The current applied to the inverting input node is replicated by
the current conveyor so as to flow in resistor Rt. The voltage
developed across Rt is buffered by the unity gain voltage follower.
Voltage gain is the ratio Rt/ RIN. With typical values of Rt = 3 MΩ
and RIN = 50 Ω, the voltage gain is about 60,000. The open
loop current gain is another measure of gain and is determined
by the beta product of the transistors in the voltage follower
stage (see Figure 4); it is typically 40,000.
In Figure 2, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
lowered, the signal bandwidth increases, but the time constant
R1Ct becomes comparable to higher order poles in the closed
loop response. Therefore, the closed loop response becomes
complex, and the pulse response shows overshoot. When R2 is
much larger than the input resistance, RIN, at Pin 2, most of the
feedback current in R1 is delivered to this input; but as R2
becomes comparable to RIN, less of the feedback is absorbed at
Pin 2, resulting in a more heavily damped response. Conse-
quently, for low values of R2 it is possible to lower R1 without
causing instability in the closed loop response. Table I lists
combinations of R1 and R2 and the resulting frequency response
for the circuit of Figure 2. TPC 13 shows the very clean and fast
10 V pulse response of the AD844.
+1
I
R
C
t
IN
t
+1
R
I
IN
IN
Figure 1. Equivalent Schematic
The important parameters defining ac behavior are the trans-
capacitance, Ct, and the external feedback resistor (not shown).
The time constant formed by these components is analogous to
the dominant pole of a conventional op amp, and thus cannot
be reduced below a critical value if the closed loop system is to
be stable. In practice, Ct is held to as low a value as possible
(typically 4.5 pF) so that the feedback resistor can be maximized
while maintaining a fast response. The finite RIN also affects the
closed loop response in some applications as will be shown.
R1
V
IN
R2
AD844
V
C
OUT
R3
OPTIONAL
R
L
L
The open loop ac gain is also best understood in terms of the
transimpedance rather than as an open loop voltage gain. The
open loop pole is formed by Rt in parallel with Ct. Since Ct is
typically 4.5 pF, the open loop corner frequency occurs at
about 12 kHz. However, this parameter is of little value in
determining the closed loop response.
Figure 2. Inverting Amplifier
REV. D
–7–
AD844
Table I.
BW (MHz) GBW (MHz)
R1
I
SIG
Gain
R1
R2
AD844
V
C
C
OUT
S
–1
–1
–2
–2
–5
–5
–10
–10
–20
–100
+100
1 kΩ
500 Ω
2 kΩ
1 kΩ
5 kΩ
500 Ω
1 kΩ
500 Ω
1 kΩ
5 kΩ
5 kΩ
1 kΩ
35
60
15
30
5.2
49
23
33
21
3.2
9
35
60
30
60
500 Ω
1 kΩ
R
L
L
500 Ω
1 kΩ
26
100 Ω
100 Ω
50 Ω
50 Ω
50 Ω
50 Ω
245
230
330
420
320
900
Figure 3. Current-to-Voltage Converter
Circuit Description of the AD844
A simplified schematic is shown in Figure 4. The AD844 differs
from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset
voltage, ensured by the close matching of like polarity transis-
tors operating under essentially identical bias conditions. Laser
trimming nulls the residual offset voltage, down to a few
tens of microvolts. The inverting input is the common emitter
node of a complementary pair of grounded base stages and
behaves as a current summing node. In an ideal current feed-
back op amp the input resistance would be zero. In the AD844
it is about 50 Ω.
Response as an I-V Converter
The AD844 works well as the active element in an operational
current to voltage converter, used in conjunction with an exter-
nal scaling resistor, R1, in Figure 3. This analysis includes the
stray capacitance, CS, of the current source, which might be a
high speed DAC. Using a conventional op amp, this capacitance
forms a “nuisance pole” with R1 which destabilizes the closed
loop response of the system. Most op amps are internally com-
pensated for the fastest response at unity gain, so the pole due
to R1 and CS reduces the already narrow phase margin of the
system. For example, if R1 were 2.5 kΩ a CS of 15 pF would
place this pole at a frequency of about 4 MHz, well within the
response range of even a medium speed operational amplifier.
In a current feedback amp this nuisance pole is no longer deter-
mined by R1 but by the input resistance, RIN. Since this is about
50 Ω for the AD844, the same 15 pF forms a pole 212 MHz
and causes little trouble. It can be shown that theresponse of
this system is:
A current applied to the inverting input is transferred to a
complementary pair of unity-gain current mirrors which deliver
the same current to an internal node (Pin 5) at which the full
output voltage is generated. The unity-gain complementary
voltage follower then buffers this voltage and provides the load
driving power. This buffer is designed to drive low impedance
loads such as terminated cables, and can deliver 50 mA into a
50 Ω load while maintaining low distortion, even when operat-
ing at supply voltages of only 6 V. Current limiting (not
shown) ensures safe operation under short circuited conditions.
K R1
(1+ sTd )(1 + sTn)
VOUT = –Isig
+V
7
S
where K is a factor very close to unity and represents the finite
dc gain of the amplifier, Td is the dominant pole and Tn is the
nuisance pole:
I
B
Rt
K =
3
2
5
6
OUT
+IN
–IN
TZ
Rt + R1
Td = KR1Ct
Tn = RINCS (assuming RIN << R1)
I
B
Using typical values of R1 = 1 kΩ and Rt = 3 MΩ, K is 0.9997;
in other words, the “gain error” is only 0.03%. This is much less
than the scaling error of virtually all DACs and can be absorbed,
if necessary, by the trim needed in a precise system.
–V
4
S
Figure 4. Simplified Schematic
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of finite “gain” is negli-
gible unless high value feedback resistors are used. Since that
would result in slower response times than are possible, the
relatively low value of Rt in the AD844 will rarely be a signifi-
cant source of error.
–8–
REV. D
AD844
+V
It is important to understand that the low input impedance at
the inverting input is locally generated, and does not depend on
feedback. This is very different from the “virtual ground” of a
conventional operational amplifier used in the current summing
mode which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is settling.
Furthermore, all of the transient current is delivered to the
slewing (TZ) node (Pin 5) via a short signal path (the grounded
base stages and the wideband current mirrors).
S
4.7ꢁ
OFFSET
TRIM
R1
499ꢁ
C
20ꢁ
3nF
PK
0.22ꢀF
8
–
R2
4.99ꢁ
AD844
The current available to charge the capacitance (about 4.5 pF)
at TZ node, is always proportional to the input error current, and
the slew rate limitations associated with the large signal response
of op amps do not occur. For this reason, the rise and fall times
are almost independent of signal level. In practice, the input
current will eventually cause the mirrors to saturate. When using
15 V supplies, this occurs at about 10 mA (or 2200 V/µs).
Since signal currents are rarely this large, classical “slew rate”
limitations are absent.
V
+
IN
R
L
0.22ꢀF
4.7ꢁ
–V
S
Figure 5. Noninverting Amplifier Gain = 100, Optional
Offset Trim Is Shown
This inherent advantage would be lost if the voltage follower
used to buffer the output were to have slew rate limitations. The
AD844 has been designed to avoid this problem, and as a result
the output buffer exhibits a clean large signal transient response,
free from anomalous effects arising from internal saturation.
46
V
= ꢃ15V
S
40
34
28
Response as a Noninverting Amplifier
Since current feedback amplifiers are asymmetrical with regard
to their two inputs, performance will differ markedly in nonin-
verting and inverting modes. In noninverting modes, the large
signal high speed behavior of the AD844 deteriorates at low
gains because the biasing circuitry for the input system (not
shown in Figure 4) is not designed to provide high input voltage
slew rates.
V
= ꢃ5V
S
22
16
However, good results can be obtained with some care. The
noninverting input will not tolerate a large transient input; it
must be kept below 1 V for best results. Consequently this mode
is better suited to high gain applications (greater than ×10).
TPC 20 shows a noninverting amplifier with a gain of 10 and a
bandwidth of 30 MHz. The transient response is shown in
TPCs 23 and 24. To increase the bandwidth at higher gains, a
capacitor can be added across R2 whose value is approximately
the ratio of R1 and R2 times Ct.
100k
1M
10M 20M
FREQUENCY – Hz
Figure 6. AC Response for Gain = 100, Configuration
Shown in Figure 5
USING THE AD844
Board Layout
As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844.
A ground plane, to which the power supply decoupling capaci-
tors are connected by the shortest possible leads, is essential
to achieving clean pulse response. Even a continuous ground
plane will exhibit finite voltage drops between points on the
plane, and this must be kept in mind in selecting the grounding
points. Generally speaking, decoupling capacitors should be
taken to a point close to the load (or output connector) since
the load currents flow in these capacitors at high frequencies.
The +IN and –IN circuits (for example, a termination resistor
and Pin 3) must be taken to a common point on the ground
plane close to the amplifier package.
Noninverting Gain of 100
The AD844 provides very clean pulse response at high nonin-
verting gains. Figure 5 shows a typical configuration providing a
gain of 100 with high input resistance. The feedback resistor is
kept as low as practicable to maximize bandwidth, and a peak-
ing capacitor (CPK) can optionally be added to further extend
the bandwidth. Figure 6 shows the small signal response with
CPK = 3 nF, RL = 500 Ω, and supply voltages of either 5 V or
15 V. Gain bandwidth products of up to 900 MHz can be achieved
in this way.
The offset voltage of the AD844 is laser trimmed to the 50 µV
level and exhibits very low drift. In practice, there is an addi-
tional offset term due to the bias current at the inverting input
(IBN) which flows in the feedback resistor (R1). This can option-
ally be nulled by the trimming potentiometer shown in Figure 5.
Use low impedance capacitors (AVX SR305C224KAA or
equivalent) of 0.22 µF wherever ac coupling is required. Include
either ferrite beads and/or a small series resistance (approxi-
mately 4.7 Ω) in each supply line.
REV. D
–9–
AD844
Input Impedance
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ,
and RL = 500 Ω. For the gain of –10, R5 = 50 Ω, R6 = 500 Ω
and RL was not used since the summing network loads the
output with approximately 275 Ω. Using this network in a
unity-gain configuration, settling time is 100 ns to 0.1% for a
–5 V to +5 V step with CL = 10 pF.
At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input will increase from near zero to
the open loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The
capacitance is set so that the pole determined by this RC network
is about half the bandwidth of the op amp. This network is not
important if the input resistor is much larger than the termina-
tion used, or if frequencies are relatively low. In some cases, the
small peaking that occurs without the network can be of use in
extending the –3 dB bandwidth.
TO SCOPE
(TEK 7A11 FET PROBE)
R5
D1
R6
D2
R1
Driving Large Capacitive Loads
Capacitive drive capability is 100 pF without an external net-
work. With the addition of the network shown in Figure 7, the
capacitive drive can be extended to over 10,000 pF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current
limit. Since this is roughly 100 mA, under these conditions,
the maximum slew rate into a 1000 pF load is 100 V/µs.
Figure 8 shows the transient response of an inverting amplifier
(R1 = R2 = 1 kΩ) using the feed forward network shown in
Figure 7, driving a load of 1000 pF.
V
IN
R2
AD844
V
OUT
R3
R
C
L
L
D1, D2 IN6263 OR EQUIV. SCHOTTKY DIODE
Figure 9. Settling Time Test Fixture
DC Error Calculation
Figure 10 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, IBN, flows in the
feedback resistor. IBP, the noninverting input bias current, flows
in the resistance at Pin 3 (RP), and the resulting voltage (plus
any offset voltage) will appear at the inverting input. The total
error, VO, at the output is:
AD844
V
OUT
C
L
R1
R2
750ꢁ
22pF
VO = (IBP RP +VOS + IBN RIN ) 1+
+ I
R1
BN
Figure 7. Feed Forward Network for Large Capacitive
Loads
Since IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input will not
necessarily reduce dc error and may actually increase it.
R1
V
N
R
R2
IN
+
~
V
OS
I
I
BN
NN
I
I
BP
NP
AD844
R
P
Figure 8. Driving 1000 pF CL with Feed Forward Network
of Figure 7
Figure 10. Offset Voltage and Noise Model for the AD844
Settling Time
Settling time is measured with the circuit of Figure 9. This
circuit employs a false summing node, clamped by the two
–10–
REV. D
Applications–AD844
Noise
0.3
0.2
IRE = 7.14mV
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are INN, INP, VN, and the amplifier
induced noise at the output, VON, is:
R12
0.1
VON
=
((Inp R )2 +Vn2 ) 1+
+(Inn R1)2
P
R2
0
–0.1
–0.2
–0.3
Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1 kΩ, RP = 0,
Vn = 2 nV/√Hz, Inp = 10 pA/√Hz, Inn = 12 pA/√Hz, VON
calculates to 12 nV/√Hz. The current noise is dominant in
this case, as it will be in most low gain applications.
Video Cable Driver Using ꢃ5 Volt Supplies
0
18
36
54
– IRE
72
90
The AD844 can be used to drive low impedance cables. Using
5 V supplies, a 100 Ω load can be driven to 2.5 V with low
distortion. Figure 11a shows an illustrative application which
provides a noninverting gain of 2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
load. The –3 dB bandwidth of this circuit is typically 30 MHz.
Figure 11b shows a differential gain and phase test setup. In
video applications, differential-phase and differential-gain
characteristics are often important. Figure 11c shows the varia-
tion in phase as the load voltage varies. Figure 11d shows the
gain variation.
V
OUT
Figure 11c. Differential Phase for the Circuit of Figure 11a
0.06
IRE = 7.14mV
0.04
0.02
0
+5V
2.2ꢀF
–0.02
3
2
Z
= 50ꢁ
V
O
7
4
IN
50ꢁ
300ꢁ
300ꢁ
6
–0.04
–0.06
V
OUT
50ꢁ
R
L
2.2ꢀF
50ꢁ
–5V
0
18
36
72
54
– IRE
90
V
OUT
Figure 11d. Differential Gain for the Circuit of Figure 11a
Figure 11a. The AD844 as a Cable Driver
High Speed DAC Buffer
The AD844 performs very well in applications requiring
current-to-voltage conversion. Figure 12 shows connections for
use with the AD568 current output DAC. In this application the
bipolar offset is used so that the full-scale current is 5.12 mA,
which generates an output of 5.12 V usingdecoupling and
grounding techniques to achieve the full 12-bit accuracy and
realize the fast settling capabilities of the system. The unmarked
capacitors in this figure are 0.1 µF ceramic (for the 1 kΩ appli-
cation resistor on the AD568. Figure 13 shows the full-scale
transient response. Care is needed in power supply example,
AVX Type SR305C104KAA), and the ferrite inductors should
be about 2.5 µH (for example, Fair-Rite Type 2743002122).
The AD568 data sheet should be consulted for more complete
details about its use.
V
RF OUT
R
IN
IN
OUT
HP8753A
NETWORK
ANALYZER
CIRCUIT
UNDER
TEST
HP11850C
SPLITTER
V
OUT
IN
V
OUT
OUT
EXT
TRIG
50ꢁ
470ꢁ
(TERMINATOR)
SYNC OUT
HP3314A
STAIRCASE
GENERATOR
OUT
Figure 11b. Differential Gain/Phase Test Setup Figure
REV. D
–11–
AD844
+15V
MSB
1
+15V 24
23
*
*
*
*
2
REFCOM
3
22
21
20
19
18
17
16
15
14
13
–15V
–15V
I
4
BPD
5
I
OUT
V
AD844
OUT
6
R
L
AD568
DIGITAL
INPUTS
R
I
7
ACOM
LCOM
SPAN
ANALOG
SUPPLY
GROUND
8
9
10
SPAN
GROUND
11
THCOM
DIGITAL
SUPPLY
100pF
V
12 LSB
TH
–5V
*0.22ꢀF
TOP VIEW
(Not to Scale)
POWER SUPPLY
BYPASS CAPACITORS
Figure 12. High Speed DAC Amplifier
+V
S
TYP+6V
@15ꢀA
10ꢁ
10ꢁ
0.22ꢀF
0.22ꢀF
INPUTS
V
X
1
16
0TO 3V
V
Y
ꢃ2V FS
TOP VIEW
(Not to Scale)
AD539
AD844
3nF
OUTPUT
W
V
–V V
X
Y
V
=
W
0.22ꢀF
2V
I/P
GND
8
9
10ꢁ
Figure 13. DAC Amplifier Full-Scale Transient Response
–V
TYP+6V
0.22ꢀF
S
10ꢁ
20 MHz Variable Gain Amplifier
@15ꢀA
*V ANDV INPUTS MAY OPTIONALLY
BE TERMINATED –TYPICALLY BY USING
A 50ꢁ OR 75ꢁ RESISTORTO GROUND.
X
Y
The AD844 is an excellent choice as an output amplifier for the
AD539 multiplier, in all of its connection modes. (See AD539
data sheet for full details.) Figure 14 shows a simple multiplier
providing the output:
Figure 14. 20 MHz VGA Using the AD539
VX VY
VW = –
Figure 15 shows the small signal response for a 50 dB gain
control range (VX = 10 mV to 3.16 V). At small values of VX,
capacitive feedthrough on the PC board becomes troublesome,
and very careful layout techniques are needed to minimize this
problem. A ground strip between the pins of the AD539 will be
helpful in this regard. Figure 16 shows the response to a 2 V
pulse on VY for VX = 1 V, 2 V, and 3 V. For these results, a load
resistor of 500 Ω was used and the supplies were 9 V. The
multiplier will operate from supplies between 4.5 V and 16.5 V.
2V
where VX is the “gain control” input, a positive voltage of from
0 V to 3.2 V (max) and VY is the “signal voltage,” nominally
2 V FS but capable of operation up to 4.2 V. The peak out-
put in this configuration is thus 6.7 V. Using all four of the
internal application resistors provided on the AD539 in parallel
results in a feedback resistance of 1.5 kΩ, at which value the
bandwidth of the AD844 is about 22 MHz, and is essentially
independent of VX. The gain at VX = 3.16 V is +4 dB.
Disconnecting Pins 9 and 16 on the AD539 alters the denomi-
nator in the above expression to 1 V, and the bandwidth will be
approximately 10 MHz, with a maximum gain of 10 dB. Using
only Pin 9 or Pin 16 results in a denominator of 0.5 V, a band-
width of 5 MHz and a maximum gain of 16 dB.
–12–
REV. D
AD844
+4
–6
V
= 3.15V
= 1.0V
X
V
X
X
–16
–26
–36
–46
–56
V
= 0.316V
= 0.10V
V
X
V
= 0.032V
X
100k
1M
10M
60M
FREQUENCY – Hz
Figure 15. VGA AC Response
Figure 16. VGA Transient Response with VX = 1 V, 2 V, and 3 V
REV. D
–13–
AD844
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (N) Package
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
PLANE
Cerdip (Q) Package
(Q-8)
0.005 (0.13) 0.055 (1.4)
MIN
MAX
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15
0
0.023 (0.58) 0.070 (1.78)
0.014 (0.36) 0.030 (0.76)
16-Lead SOIC (R) Package
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
1
9
8
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
ꢄ 45ꢂ
8ꢂ
0ꢂ
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
–14–
REV. D
AD844
Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. D
–15–
–16–
相关型号：
AD844SQ-883B
IC OP-AMP, 500 uV OFFSET-MAX, 60 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier
ADI
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