AD849JR2 [ADI]
High Speed, Low Power Monolithic Op Amp; 高速，低功耗单片运算放大器
| 型号： | AD849JR2 |
| 厂家： | 
ADI |
| 描述： | High Speed, Low Power Monolithic Op Amp |
| 文件： | 总8页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Low Power
Monolithic Op Amp
a
AD848/AD849
FEATURES
CO NNECTIO N D IAGRAMS
725 MHz Gain Bandw idth – AD849
175 MHz Gain Bandw idth – AD848
4.8 m A Supply Current
P lastic (N),
Sm all O utline (R) and
Cer dip (Q ) P ackages
300 V/ s Slew Rate
80 ns Settling Tim e to 0.1% for a 10 V Step – AD849
Differential Gain: AD848 = 0.07%, AD849 = 0.08%
Differential Phase: AD848 = 0.08؇, AD849 = 0.04؇
Drives Capacitive Loads
AD848/49
1
2
3
4
8
7
6
5
NULL
–IN
NULL
+V
S
+IN
OUTPUT
NC
TOP VIEW
(Not to Scale)
–V
S
DC PERFORMANCE
NC = NO CONNECT
3 nV/ √Hz Input Voltage Noise – AD849
85 V/ m V Open Loop Gain into a 1 k⍀ Load – AD849
1 m V m ax Input Offset Voltage
Perform ance Specified for ؎5 V and ؎15 V Operation
Available in Plastic, Herm etic Cerdip and Sm all Outline
Packages. Chips and MIL-STD-883B Parts Available.
Available in Tape and Reel in Accordance w ith
EIA-481A Standard
20-Ter m inal LCC P inout
18 17 16 15 14
NC 19
13 NC
APPLICATIONS
Cable Drivers
8- and 10-Bit Data Acquisition System s
Video and RF Am plification
Signal Generators
OFFSET
20
1
12 NC
11 NC
10 V–
AD848SE/883B
TOP VIEW
(Not to Scale)
NULL
NC
OFFSET
NULL
2
NC
3
9
NC
4
5
7
8
6
P RO D UCT D ESCRIP TIO N
NC = NO CONNECT
T he AD848 and AD849 are high speed, low power monolithic
operational amplifiers. T he AD848 is internally compensated so
that it is stable for closed loop gains of 5 or greater. T he AD849
is fully decompensated and is stable at gains greater than 24.
T he AD848 and AD849 achieve their combination of fast ac
and good dc performance by utilizing Analog Devices’ junction
isolated complementary bipolar (CB) process. T his process
enables these op amps to achieve their high speed while only
requiring 4.8 mA of current from the power supplies.
AP P LICATIO NS H IGH LIGH TS
1. T he high slew rate and fast settling time of the AD848 and
AD849 make them ideal for video instrumentation circuitry,
low noise pre-amps and line drivers.
2. In order to meet the needs of both video and data acquisition
applications, the AD848 and AD849 are optimized and
tested for ±5 V and ±15 V power supply operation.
3. Both amplifiers offer full power bandwidth greater than
T he AD848 and AD849 are members of Analog Devices’ family
of high speed op amps. T his family includes, among others, the
AD847 which is unity gain stable, with a gain bandwidth of
50 MHz. For more demanding applications, the AD840,
AD841 and AD842 offer even greater precision and greater
output current drive.
20 MHz (for 2 V p-p with ±5 V supplies).
4. T he AD848 and AD849 remain stable when driving any
capacitive load.
5. Laser wafer trimming reduces the input offset voltage to
1 mV maximum on all grades, thus eliminating the need for
external offset nulling in many applications.
T he AD848 and AD849 have good dc performance. When
operating with ±5 V supplies, they offer open loop gains of
13 V/mV (AD848 with a 500 Ω load) and low input offset
voltage of 1 mV maximum. Common-mode rejection is a
minimum of 92 dB. Output voltage swing is ±3 V even into
loads as low as 150 Ω.
6. T he AD848 is an enhanced replacement for the LM6164
series and can function as a pin-for-pin replacement for
many high speed amplifiers such as the HA2520/2/5 and
EL2020 in applications where the gain is 5 or greater.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD848/AD849–SPECIFICATIONS(@ T = +25؇C, unless otherwise noted)
A
AD 848J
AD 848A/S
Min Typ Max
0.2
Model
Conditions
VS
Min
Typ Max
Units
INPUT OFFSET VOLT AGE1
±5 V
±15 V
±5 V
±15 V
0.2
0.5
1
1
mV
mV
mV
mV
2.3
1.5
3.0
0.5
2.3
2
T MIN to TMAX
3.5
Offset Drift
±5 V, ±15 V
7
7
µV/°C
INPUT BIAS CURRENT
±5 V, ±15 V
±5 V, ±15 V
3.3
6.6
7.2
3.3
6.6/5
7.5
µA
µA
T MIN to TMAX
T MIN to TMAX
INPUT OFFSET CURRENT
±5 V, ±15 V
±5 V, ±15 V
±5 V, ±15 V
50
300
400
50
300
400
nA
nA
nA/°C
Offset Current Drift
OPEN LOOP GAIN
0.3
0.3
VO = ±2.5 V
±5 V
RLOAD = 500 Ω
T MIN to TMAX
RLOAD = 150 Ω
VOUT = ±10 V
RLOAD = 1 kΩ
T MIN to TMAX
9
7
13
8
9
7/5
13
8
V/mV
V/mV
V/mV
±15 V
12
8
20
12
8/6
20
V/mV
V/mV
DYNAMIC PERFORMANCE
Gain Bandwidth
AVCL ≥ 5
±5 V
±15 V
125
175
125
175
MHz
MHz
Full Power Bandwidth2
VO = 2 V p-p,
RL = 500 Ω
VO = 20 V p-p,
RL = 1 kΩ
±5 V
24
24
MHz
±15 V
±5 V
±15 V
±5 V
±15 V
±15 V
4.7
200
300
65
4.7
200
300
65
MHz
V/µs
V/µs
ns
Slew Rate
RLOAD = 1 kΩ
225
225
Settling T ime to 0.1%
Phase Margin
–2.5 V to +2.5 V
10 V Step, AV = –4
CLOAD = 10 pF
RLOAD = 1 kΩ
100
100
ns
60
60
Degrees
%
DIFFERENT IAL GAIN
f = 4.4 MHz
f = 4.4 MHz
±15 V
±15 V
0.07
0.08
0.07
0.08
DIFFERENT IAL PHASE
COMMON-MODE REJECT ION
Degree
VCM = ±2.5 V
VCM = ±12 V
T MIN to TMAX
±5 V
±15 V
92
92
88
105
105
92
92
88
105
105
dB
dB
dB
POWER SUPPLY REJECT ION
VS = ±4.5 V to ±18 V
T MIN to TMAX
85
80
98
85
80
98
dB
dB
INPUT VOLT AGE NOISE
INPUT CURRENT NOISE
f = 10 kHz
f = 10 kHz
±15 V
±15 V
5
5
nV/√Hz
pA/√Hz
1.5
1.5
INPUT COMMON-MODE
VOLT AGE RANGE
±5 V
+4.3
–3.4
+14.3
–13.4
+4.3
–3.4
+14.3
–13.4
V
V
V
V
±15 V
OUT PUT VOLT AGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 50 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
±5 V
±5 V
±5 V
±15 V
±15 V
3.0
2.5
3.6
3
1.4
3.0
2.5
3.6
3
1.4
±V
±V
±V
±V
±V
12
10
12
10
SHORT CIRCUIT CURRENT
INPUT RESIST ANCE
±15 V
32
70
1.5
15
32
70
1.5
15
mA
kΩ
pF
Ω
INPUT CAPACIT ANCE
OUT PUT RESIST ANCE
Open Loop
POWER SUPPLY
Operating Range
Quiescent Current
؎4.5
؎18
6.0
7.4
6.8
8.0
؎4.5
؎18
6.0
7.4/8.3 mA
6.8 mA
8.0/9.0 mA
V
mA
±5 V
4.8
5.1
4.8
5.1
T MIN to TMAX
T MIN to TMAX
±15 V
NOT ES
1Input offset voltage specifications are guaranteed after 5 minutes at T A = +25°C.
2Full power bandwidth = slew rate/2 π VPEAK. Refer to Figure 1.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested.
Specifications subject to change without notice.
–2–
REV. B
AD848/AD849
AD 849J
Typ Max
AD 849A/S
Min Typ Max
Model
Conditions
VS
Min
Units
INPUT OFFSET VOLT AGE1
±5 V
±15 V
±5 V
±15 V
0.3
0.3
1
1
1.3
1.3
0.1
0.1
0.75
0.75
1.0
mV
mV
mV
mV
T MIN to T MAX
1.0
Offset Drift
±5 V, ±15 V
2
2
µV/°C
INPUT BIAS CURRENT
±5 V, ±15 V
±5 V, ±15 V
3.3
6.6
7.2
3.3
6.6/5
7.5
µA
µA
T MIN to T MAX
T MIN to T MAX
INPUT OFFSET CURRENT
±5 V, ±15 V
±5 V, ±15 V
±5 V, ±15 V
50
300
400
50
300
400
nA
nA
nA/°C
Offset Current Drift
OPEN LOOP GAIN
0.3
0.3
VO = ±2.5 V
±5 V
RLOAD = 500 Ω
T MIN to T MAX
RLOAD = 150 Ω
VOUT = ±10 V
RLOAD = 1 kΩ
T MIN to T MAX
30
20
50
32
85
30
20/15
50
32
85
V/mV
V/mV
V/mV
±15 V
45
30
45
30/25
V/mV
V/mV
DYNAMIC PERFORMANCE
Gain Bandwidth
AVCL ≥ 25
±5 V
±15 V
520
725
520
725
MHz
MHz
Full Power Bandwidth2
VO = 2 V p-p,
RL = 500 Ω
VO = 20 V p-p,
RL = 1 kΩ
±5 V
20
20
MHz
±15 V
±5 V
±15 V
±5 V
±15 V
±15 V
4.7
200
300
65
4.7
200
300
65
MHz
V/µs
V/µs
ns
Slew Rate
RLOAD = 1 kΩ
225
225
Settling T ime to 0.1%
Phase Margin
–2.5 V to +2.5 V
10 V Step, AV = –24
CLOAD = 10 pF
RLOAD = 1 kΩ
80
80
ns
60
60
Degrees
%
DIFFERENT IAL GAIN
f = 4.4 MHz
f = 4.4 MHz
±15 V
±15 V
0.08
0.04
0.08
0.04
DIFFERENT IAL PHASE
COMMON-MODE REJECT ION
Degrees
VCM = ±2.5 V
VCM = ±12 V
T MIN to T MAX
±5 V
±15 V
100
100
96
115
115
100
100
96
115
115
dB
dB
dB
POWER SUPPLY REJECT ION
VS = ±4.5 V to ±18 V
T MIN to T MAX
98
94
120
98
94
120
dB
dB
INPUT VOLT AGE NOISE
INPUT CURRENT NOISE
f = 10 kHz
f = 10 kHz
±15 V
±15 V
3
3
nV/√Hz
pA/√Hz
1.5
1.5
INPUT COMMON-MODE
VOLT AGE RANGE
±5 V
+4.3
–3.4
+14.3
–13.4
+4.3
–3.4
+14.3
–13.4
V
V
V
V
±15 V
OUT PUT VOLT AGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 50 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
±5 V
±5 V
±5 V
±15 V
±15 V
3.0
2.5
3.6
3
1.4
3.0
2.5
3.6
3
1.4
±V
±V
±V
±V
±V
12
10
12
10
SHORT CIRCUIT CURRENT
INPUT RESIST ANCE
±15 V
32
25
1.5
15
32
25
1.5
15
mA
kΩ
pF
Ω
INPUT CAPACIT ANCE
OUT PUT RESIST ANCE
Open Loop
POWER SUPPLY
Operating Range
Quiescent Current
؎4.5
؎18
6.0
7.4
6.8
8.0
؎4.5
؎18
6.0
7.4/8.3 mA
6.8 mA
8.0/9.0 mA
V
mA
±5 V
4.8
5.1
4.8
5.1
T MIN to T MAX
T MIN to T MAX
±15 V
NOT ES
1Input offset voltage specifications are guaranteed after 5 minutes at T A = +25°C.
2Full power bandwidth = slew rate/2 π VPEAK. Refer to Figure 1.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested.
Specifications subject to change without notice.
REV. B
–3–
AD848/AD849
ABSO LUTE MAXIMUM RATINGS 1
METALIZATIO N P H O TO GRAP H
Contact factory for latest dimensions. (AD 848 and AD 849 are identical
except for the part number in the upper right.)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
D imensions shown in inches and (mm).
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Storage T emperature Range (Q) . . . . . . . . –65°C to +150°C
(N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. T his is a stress rating only, and functional opera-
tion of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2LCC: θJA = 150°C/Watt
Mini-DIP Package: θJA = 110°C/Watt
Cerdip Package: θJA = 110°C/Watt
Small Outline Package: θJA = 155°C/Watt.
O RD ERING GUID E
Min Max
Stable O ffset Voltage Tem perature
Gain
Bandwidth
MH z
P ackage
O ption1
Model
Gain
m V
Range – ؇C
AD848JN
175
175
175
175
175
5
5
5
5
5
5
5
1
1
1
1
1
1
1
0 to +70
0 to +70
0 to +70
–40 to +85
–55 to +125
–55 to +125
–55 to +125
N-8
R-8
Die Form
Q-8
Q-8
AD848JR2
AD848JCHIPS
AD848AQ
AD848SQ
AD848SQ/883B 175
AD848SE/883B 175
Q-8
E-20A
AD849JN
AD849JR2
AD849AQ
AD849SQ
725
725
725
725
25
25
25
25
25
1
1
0.75
0.75
0.75
0 to +70
0 to +70
–40 to +85
–55 to +125
–55 to +125
N-8
R-8
Q-8
Q-8
Q-8
AD849SQ/883B 725
AD847J/A/S
50
1
1
See AD847 Data Sheet
NOT ES
1E = LCC; N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
2Plastic SOIC (R) available in tape and reel. AD848 available in S grade chips. AD849 available in J and S grade
chips.
–4–
REV. B
AD848/AD849
Figure 1. AD848 Inverting Am plifier Configuration
Figure 1a. AD848 Large Signal Pulse Response
Figure 1b. AD848 Sm all Signal Pulse Response
Figure 2. AD849 Inverting Am plifier Configuration
Figure 2a. AD849 Large Signal Pulse Response
Figure 2b. AD849 Sm all Signal Pulse Response
O FFSET NULLING
T he input voltage of the AD848 and AD849 are very low for
high speed op amps, but if additional nulling is required, the
circuit shown in Figure 3 can be used.
For high performance circuits it is recommended that a resistor
(RB in Figures 1 and 2) be used to reduce bias current errors by
matching the impedance at each input. T he offset voltage error
caused by the input currents is decreased by more than an order
of magnitude.
Figure 3. Offset Nulling
–5–
REV. B
AD848/AD849–Typical Characteristics
(@ T = +25؇C and V = ؎15 V, unless otherwise noted)
A
S
Figure 4. Quiescent Current vs.
Supply Voltage (AD848 and AD849)
Figure 6. Output Voltage Swing vs.
Load Resistance (AD848 and AD849)
Figure 5. Large Signal Frequency
Response (AD848 and AD849)
Figure 8. Open Loop Gain vs.
Load Resistance (AD849)
Figure 9. Output Swing and
Error vs. Settling Tim e (AD848)
Figure 7. Open Loop Gain vs.
Load Resistance (AD848)
Figure 11. Short Circuit Current
Lim it vs. Tem perature (AD848
and AD849)
Figure 10. Quiescent Current vs.
Tem perature (AD848 and AD849)
Figure 12. Input Bias Current vs.
Tem perature (AD848 and AD849)
–6–
REV. B
AD848/AD849
Figure 13. Open Loop Gain and
Phase Margin vs. Frequency (AD848)
Figure 14. Open Loop Gain and
Phase Margin vs. Frequency (AD849)
Figure 15. Norm alized Gain Band-
width Product vs. Tem perature
(AD848 and AD849)
Figure 16. Harm onic Distortion vs.
Frequency (AD848)
Figure 17. Harm onic Distortion vs.
Frequency (AD849)
Figure 18. Slew Rate vs. Tem perature
(AD848 and AD849)
Figure 19. Power Supply Rejection vs.
Frequency (AD848)
Figure 20. Power Supply Rejection vs.
Frequency (AD849)
Figure 21. Com m on-Mode
Rejection vs. Frequency
–7–
REV. B
AD848/AD849–Applications
GRO UND ING AND BYP ASSING
Often termination is not used, either because signal integrity
requirements are low or because too many high frequency
signals returned to ground contaminate the ground plane.
Unterminated cables appear as capacitive loads. Since the
AD848 and AD849 are stable into any capacitive load, the op
amp will not oscillate if the cable is not terminated; however
pulse integrity will be degraded. Figure 23 shows the AD848
driving both 100 pF and 1000 pF loads.
In designing practical circuits with the AD848 or AD849, the
user must remember that whenever high frequencies are
involved, some special precautions are in order. Circuits must
be built with short interconnect leads. A large ground plane
should be used whenever possible to provide a low resistance,
low inductance circuit path, as well as minimizing the effects of
high frequency coupling. Sockets should be avoided because the
increased interlead capacitance can degrade bandwidth.
LO W NO ISE P RE-AMP
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitances at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 kΩ are recommended. If a larger
resistor must be used, a small (< 10 pF) feedback capacitor in
parallel with the feedback resistor, RF, may be used to compen-
sate for the input capacitances and optimize the dynamic per-
formance of the amplifier.
T he input voltage noise spectral densities of the AD848 and the
AD849 are shown in Figure 24. T he low wideband noise and
high gain bandwidths of these devices makes them well suited as
pre-amps for high frequency systems.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. 0.1 µF ceramic disc capacitors are
recommended.
VID EO LINE D RIVER
T he AD848 functions very well as a low cost, high speed line
driver of either terminated or unterminated cables. Figure 22
shows the AD848 driving a doubly terminated cable.
T he termination resistor, RT , (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. While operating off ±5 V supplies, the AD848
maintains a typical slew rate of 200 V/µs, which means it can
drive a ±1 V, 24 MHz signal on the terminated cable.
Figure 24. Input Voltage Noise Spectral Density
Input voltage noise will be the dominant source of noise at the
output in most applications. Other noise sources can be
minimized by keeping resistor values as small as possible.
A back-termination resistor (RBT, also equal to the characteristic
impedance of the cable) may be placed between the AD848
output and the cable in order to damp any reflected signals
caused by a mismatch between RT and the cable’s characteristic
impedance. T his will result in a “cleaner” signal, although it
requires that the op amp supply ±2 V to the output in order to
achieve a ±1 V swing at the line.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Mini-D IP (N) P ackage
Cer dip (Q ) P ackage
Figure 22. Video Line Driver
100pF
LOAD
Sm all O utline (R) P ackage
1000pF
LOAD
Figure 23. AD848 Driving a Capacitive Load
–8–
REV. B
相关型号：
AD849SQ/883B
OP-AMP, 1000uV OFFSET-MAX, 725MHz BAND WIDTH, CDIP8, HERMETIC SEALED, CERDIP-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明