AD8505ARJZ-R7 [ADI]
20 µA Maximum, RRIO, Zero Input Crossover Distortion Single Op Amp;
| 型号： | AD8505ARJZ-R7 |
| 厂家： | 
ADI |
| 描述： | 20 µA Maximum, RRIO, Zero Input Crossover Distortion Single Op Amp 放大器 光电二极管 |
| 文件： | 总21页 (文件大小：742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 μA Maximum, Rail-to-Rail I/O,
Zero Input Crossover Distortion Amplifiers
AD8505/AD8506/AD8508
Data Sheet
FEATURES
PSRR: 100 dB minimum
CMRR: 105 dB typical
PIN CONFIGURATIONS
BALL A1
INDICATOR
OUT
A1
V+
A2
Very low supply current: 20 μA per amplifier maximum
1.8 V to 5 V single supply or 0.9 V to 2.5 V dual supply
Rail-to-rail input/output
V–
B1
NC
B2
Low noise: 45 nV/√Hz at 1 kHz
2.5 mV offset voltage maximum
Very low input bias current: 1 pA typical
+IN
C1
–IN
C2
OUT
V–
1
2
3
5
4
V+
AD8505
APPLICATIONS
Pressure and position sensors
Remote security
AD8505
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
TOP VIEW
(Not to Scale)
+IN
–IN
NC = NO CONNECT
Bio sensors
IR thermometers
Figure 1. 5-Lead SOT-23 (RJ-5)
Figure 2. 6-Ball WLCSP (CB-6-7)
BALL A1
CORNER
Battery-powered consumer equipment
Hazard detectors
OUT B
A1
V+
A2
OUT A
A3
GENERAL DESCRIPTION
The AD8505/AD8506/AD8508 are single, dual, and quad micro-
power amplifiers featuring rail-to-rail input/output swings while
operating from a single 1.8 V to 5 V power supply or from dual
±0.ꢀ V to ±±.5 V power supplies. Using a new circuit technology,
these amplifiers offer zero input crossover distortion (excellent
PSRR and CMRR performance) and low bias current while
operating with a supply current of less than ±0 μA per amplifier.
This amplifier family offers the lowest noise in its power class.
–IN B
B1
–IN A
B3
+IN B
C1
V–
C2
+IN A
C3
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8506
OUT B
–IN B
+IN B
AD8506
TOP VIEW
TOP VIEW
(Not to Scale)
(BALL SIDE DOWN)
Not to Scale
Figure 3. 8-Lead MSOP (RM-8)
Figure 4. 8-Ball WLCSP (CB-8-2)
This combination of features makes the AD8505/AD8506/AD8508
amplifiers ideal choices for battery-powered applications because
they minimize errors due to power supply voltage variations over
the lifetime of the battery and maintain high CMRR even for a rail-
to-rail input op amp. Remote battery-powered sensors, handheld
instrumentation, consumer equipment, hazard detection (for
example, smoke, fire, and gas), and patient monitors can benefit
from the features of the AD8505/AD8506/AD8508 amplifiers.
BALL A1
CORNER
OUTD
A1
OUTA
A2
–INA
A3
–IND
B1
V–
B2
+INA
B3
+IND
C1
+INB
C3
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
+INC
D1
V+
D2
–INB
D3
AD8508
–INC
E1
OUTC
E2
OUTB
E3
TOP VIEW
The AD8505/AD8506/AD8508 are specified for both the industrial
temperature range of −40°C to +85°C and the extended industrial
temperature range of −40°C to +1±5°C. The AD8505 single ampli-
fier is available in a tiny 5-lead SOT-±3 and a 6-ball WLCSP
packages. The AD8506 dual amplifier is available in 8-lead MSOP
and 8-ball WLCSP packages. The AD8508 quad amplifier is
available in 14-lead TSSOP and 14-ball WLCSP packages. The
AD8505/AD8506/AD8508 are members of a growing series of
zero crossover distortion op amps offered by Analog Devices,
Inc., including the ADA4505-1/ADA4505-±/ADA4505-4, that
operate from a single 1.8 V to 5 V supply or from dual ±0.ꢀ V to
±±.5 V power supplies.
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
AD8508
TOP VIEW
OUT C
(BALL SIDE DOWN)
Not to Scale
Figure 5. 14-Lead TSSOP (RU-14)
Figure 6. 14-Ball WLCSP (CB-14-1)
Rev. F
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Technical Support
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Data Sheet
AD8505/AD8506/AD8508
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 16
Pulse Oximeter Current Source ............................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics—1.8 V Operation ............................ 4
Electrical Characteristics—5 V Operation................................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Four-Pole, Low-Pass Butterworth Filter for Glucose Monitor
....................................................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 21
Rev. F | Page 2 of 21
Data Sheet
AD8505/AD8506/AD8508
REVISION HISTORY
7/2008—Rev. 0 to Rev. A
9/2017—Rev. E to Rev. F
Added AD8508................................................................... Universal
Added TSSOP Package...................................................... Universal
Changes to Features Section and General Description Section..1
Added Figure 2; Renumbered Sequentially...................................1
Changed Electrical Characteristics Heading to Electrical
Characteristics—5 V Operation......................................................3
Changes to Table 1 ............................................................................3
Added Electrical Characteristics—1.8 V Operation Heading ....4
Changes to Table 2 ............................................................................4
Changes to Table 3, Thermal Resistance Section, and Table 4....5
Updated Outline Dimensions........................................................18
Changes to Ordering Guide...........................................................21
5/2010—Rev. D to Rev. E
Added AD8505, 6-Ball WLCSP Package ........................ Universal
Changes to Large-Signal Voltage Gain Parameter (Table 1) .......4
Changes to Large-Signal Voltage Gain Parameter (Table 2) .......5
Changes to Table 4 ............................................................................6
Updated Outline Dimensions........................................................19
Changes to Ordering Guide...........................................................21
Added T
A = 25°C Condition to Typical Performance
10/2009—Rev. C to Rev. D
Characteristics Section.....................................................................6
Changes to Figure 3, Figure 4, Figure 6, and Figure 7..................6
Added Figure 11 and Figure 14.......................................................7
Changes to Figure 17 Through Figure 20 ......................................8
Changes to Figure 21 Through Figure 26 ......................................9
Changes to Figure 27, Figure 28, Figure 30, and Figure 31 .......10
Changes to Figure 34, Figure 37, and Figure 38..........................11
Added Figure 39 and Figure 40.....................................................12
Added Theory of Operation Section, Figure 41, and
Figure 42...........................................................................................13
Added Figure 43 and Figure 44.....................................................14
Added Applications Information Section and Figure 45...........15
Added Figure 46..............................................................................16
Updated Outline Dimensions........................................................17
Added Figure 48..............................................................................17
Changes to Ordering Guide...........................................................17
Added AD8505, 5-Lead SOT-23 Package....................... Universal
Changes to General Description, Added Figure 1........................1
Moved Electrical Characteristics—1.8 V Operation Section,
Changes to Supply Current per Amplifier Parameter, Table 1 ..... 3
Moved Electrical Characteristics—5 V Operation Section,
Changes to Supply Current per Amplifier Parameter, Table 2 ..... 4
Changes to Thermal Resistance Section and Table 4 ...................5
Changes to Figure 20 and Figure 23 ...............................................8
Updated Outline Dimensions........................................................16
Changes to Ordering Guide...........................................................17
3/2009—Rev. B to Rev. C
Added AD8508, 14-Ball WLCSP Package ...................... Universal
Updated Outline Dimensions........................................................17
Changes to Ordering Guide...........................................................18
10/2008—Rev. A to Rev. B
11/2007—Revision 0: Initial Version
Added WLCSP Package..................................................... Universal
Added Figure 2; Renumbered Sequentially ...................................1
Added Input Resistance Parameter.................................................3
Changes to Input Capacitance Differential Mode Parameter
Symbol and Input Capacitance Common Mode Parameter
Symbol ................................................................................................3
Added Input Resistance Parameter.................................................4
Changes to Input Capacitance Differential Mode Parameter
Symbol and Input Capacitance Common Mode Parameter
Symbol ................................................................................................4
Changes to Table 4 ............................................................................5
Changes to Figure 46 ......................................................................16
Updated Outline Dimensions........................................................17
Added Figure 49 ..............................................................................17
Changes to Ordering Guide...........................................................18
Rev. F | Page 3 of 21
AD8505/AD8506/AD8508
SPECIFICATIONS
Data Sheet
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
VSY = 1.8 V, VCM = VSY/2, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
0.5
1
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0 V ≤ VCM ≤ 1.8 V
−40°C ≤ TA ≤ +125°C
2.5
3.5
10
100
600
5
50
100
1.8
mV
mV
pA
pA
pA
pA
pA
pA
V
dB
dB
dB
dB
Input Bias Current
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
0 V ≤ VCM ≤ 1.8 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
0
CMRR
AVO
85
85
80
95
100
115
Large-Signal Voltage Gain
0.05 V ≤ VOUT ≤ 1.75 V,
RL = 100 kΩ to VCM
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
95
dB
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode CINDM
2.5
220
3
µV/°C
GΩ
pF
∆VOS/∆T
RIN
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
CINCM
VOH
4.2
pF
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VSY
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VSY
1.78
1.78
1.65
1.65
1.79
1.75
2
V
V
V
V
mV
mV
mV
mV
mA
Output Voltage Low
VOL
5
5
25
25
12
−40°C ≤ TA ≤ +125°C
VOUT = VSY or GND
Short-Circuit Limit
POWER SUPPLY
Power Supply Rejection Ratio
ISC
4.5
110
PSRR
VSY = 1.8 V to 5 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
100
100
95
dB
dB
dB
Supply Current per Amplifier
AD8506/AD8508
ISY
VOUT = VSY/2
−40°C ≤ TA ≤ +125°C
VOUT = VSY/2
16.5
16.5
20
25
24
27.5
µA
µA
µA
µA
AD8505
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
ΦM
RL = 100 kΩ, CL = 10 pF, G = 1
RL = 1 MΩ, CL = 20 pF, G = 1
RL = 1 MΩ, CL = 20 pF, G = 1
13
95
60
mV/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
2.8
45
15
µV p-p
nV/√Hz
fA/√Hz
Rev. F | Page 4 of 21
Data Sheet
AD8505/AD8506/AD8508
ELECTRICAL CHARACTERISTICS—5 V OPERATION
VSY = 5 V, V CM = VSY/2, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
0.5
1
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0 V ≤ VCM ≤ 5 V
−40°C ≤ TA ≤ +125°C
2.5
3.5
10
100
600
5
50
130
5
mV
mV
pA
pA
pA
pA
pA
pA
V
dB
dB
dB
dB
Input Bias Current
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
0 V ≤ VCM ≤ 5 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
0
CMRR
AVO
90
90
85
105
105
120
Large-Signal Voltage Gain
0.05 V ≤ VOUT ≤ 4.95 V,
RL = 100 kΩ to VCM
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
100
dB
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode CINDM
2
µV/°C
GΩ
pF
∆VOS/∆T
RIN
220
3
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
CINCM
VOH
4.2
pF
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VSY
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VSY
4.98
4.98
4.9
4.99
4.95
2
V
V
V
V
mV
mV
mV
mV
mA
4.9
Output Voltage Low
VOL
5
5
25
30
10
−40°C ≤ TA ≤ +125°C
VOUT = VSY or GND
Short-Circuit Limit
POWER SUPPLY
ISC
45
Power Supply Rejection Ratio
PSRR
VSY = 1.8 V to 5 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
100
100
95
110
dB
dB
dB
Supply Current per Amplifier
AD8506/AD8508
ISY
VOUT = VSY/2
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
15
20
25
25.5
µA
µA
µA
AD8505
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
ΦM
RL = 100 kΩ, CL = 10 pF, G = 1
RL = 1 MΩ, CL = 20 pF, G = 1
RL = 1 MΩ, CL = 20 pF, G = 1
13
95
60
mV/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
2.8
45
15
µV p-p
nV/√Hz
fA/√Hz
Rev. F | Page 5 of 21
AD8505/AD8506/AD8508
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages with its
exposed paddle soldered to a pad, if applicable. Table 4 shows
simulated thermal values for a 4-layer (2S2P) JEDEC standard
thermal test board, unless otherwise specified.
Parameter
Rating
5.5 V
VSY 0.1 V
10 mA
VSY
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage2
Output Short-Circuit Duration to GND Indefinite
Table 4.
Package Type
Storage Temperature Range
−65°C to +150°C
θJA
190
105
142
82
θJC
92
N/A
45
N/A
35
N/A
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
−40°C to +125°C
−65°C to +150°C
300°C
5-Lead SOT-23 (RJ-5)
6-Ball WLCSP (CB-6-7)
8-Lead MSOP (RM-8)
8-Ball WLCSP (CB-8-2)
14-Lead TSSOP (RU-14)
14-Ball WLCSP (CB-14-1)
1 Input pins have clamp diodes to the supply pins. The input current must be
limited to 10 mA or less whenever the input signal exceeds the power
supply rail by 0.5 V.
112
64
2 The differential input voltage is limited to 5 V or the supply voltage, whichever
is less.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. F | Page 6 of 21
Data Sheet
AD8505/AD8506/AD8508
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
250
200
150
100
50
250
V
V
= 1.8V
V
V
= 5V
SY
SY
= V /2
= V /2
CM
SY
CM
SY
200
150
100
50
0
–4
0
–4
–3
–2
–1
0
1
2
3
4
–3
–2
–1
0
1
2
3
4
V
(mV)
V
(mV)
OS
OS
Figure 7. Input Offset Voltage Distribution
Figure 10. Input Offset Voltage Distribution
16
14
12
10
8
12
10
8
V
= 5V
V
= 1.8V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
6
6
4
4
2
2
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13
TCV
(µV/°C)
TCV
(µV/°C)
OS
OS
Figure 8. Input Offset Voltage Drift Distribution
Figure 11. Input Offset Voltage Drift Distribution
2000
1500
1000
500
2000
1500
1000
500
V
= 1.8V
V
= 5V
SY
SY
0
0
–500
–1000
–1500
–2000
–500
–1000
–1500
–2000
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
0
1
2
3
4
5
V
V
(V)
CM
CM
Figure 9. Input Offset Voltage vs. Input Common-Mode Voltage
Figure 12. Input Offset Voltage vs. Input Common-Mode Voltage
Rev. F | Page 7 of 21
AD8505/AD8506/AD8508
Data Sheet
TA = 25°C, unless otherwise noted.
–115
–120
–125
–130
–135
–140
–145
–150
V
= 1.8V
V
= 5V
SY
SY
–120
–125
–130
–135
–140
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
0
1
2
3
4
5
V
V
(V)
CM
CM
Figure 13. Input Offset Voltage vs. Input Common-Mode Voltage
Figure 16. Input Offset Voltage vs. Input Common-Mode Voltage
600
600
V
= 1.8V
V
= 5V
SY
SY
550
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
V
V
CM
CM
Figure 14. Input Bias Current vs. Input Common-Mode Voltage at 125°C
Figure 17. Input Bias Current vs. Input Common-Mode Voltage at 125°C
1000
1000
V
V
= 1.8V
= V /2
SY
SY
V
V
= 5V
= V /2
SY
SY
CM
CM
100
10
1
100
10
1
0.1
0.1
0.01
0.01
25
35
45
55
65
75
85
95
105 115 125
25
35
45
55
65
75
85
95
105 115 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Input Bias Current vs. Temperature
Figure 18. Input Bias Current vs. Temperature
Rev. F | Page 8 of 21
Data Sheet
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
10k
10k
1k
V
= 1.8V
V
= 5V
SY
SY
1k
100
10
V
– V
OH
DD
100
10
V
OL
V
OL
V
– V
OH
DD
1
1
0.1
0.01
0.1
0.001
0.01
0.1
LOAD CURRENT (mA)
1
10
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 19. Output Voltage to Supply Rail vs. Load Current
Figure 22. Output Voltage to Supply Rail vs. Load Current
14
12
10
8
14
12
10
8
V
= 1.8V
V
= 5V
SY
SY
V
– V @ R = 10kΩ
OH L
V
– V @ R = 10kΩ
OH L
DD
DD
V
@ R = 10kΩ
V
@ R = 10kΩ
L
OL
L
OL
6
6
4
4
V
– V @ R = 100kΩ
OH L
DD
V
– V @ R = 100kΩ
OH L
DD
2
2
V
@ R = 100kΩ
V
@ R = 100kΩ
L
OL
L
OL
20
0
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Output Voltage to Supply Rail vs. Temperature
Figure 23. Output Voltage to Supply Rail vs. Temperature
90
90
80
70
AD8508
AD8506
AD8505
V
= V /2
SY
V
= V /2
SY
CM
CM
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
AD8508, 1.8V
AD8508, 5V
AD8506, 1.8V
AD8606, 5V
AD8505, 1.8V
AD8505, 5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
–40 –25 –10
5
20
35
50
65
80
95 110 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 21. Total Supply Current vs. Supply Voltage
Figure 24. Total Supply Current vs. Temperature
Rev. F | Page 9 of 21
AD8505/AD8506/AD8508
Data Sheet
TA = 25°C, unless otherwise noted.
120
120
100
80
120
100
80
120
V
= 1.8V
V
= 5V
SY
SY
100
80
PHASE
GAIN
100
80
PHASE
GAIN
60
60
60
40
60
40
40
40
20
20
20
20
0
0
0
0
–20
–40
–60
–80
–100
–120
–20
–40
–60
–80
–100
–120
–20
–20
GAIN, C = 0pF
GAIN, C = 0pF
L
PHASE, C = 0pF
L
GAIN, C = 50pF
L
PHASE, C = 50pF
L
GAIN, C = 100pF
L
PHASE, C = 100pF
L
L
PHASE, C = 0pF
L
–40
–60
–40
–60
–80
–100
GAIN, C = 50pF
L
PHASE, C = 50pF
L
GAIN, C = 100pF
L
–80
PHASE, C = 100pF
L
–100
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Open-Loop Gain and Phase vs. Frequency
Figure 28. Open-Loop Gain and Phase vs. Frequency
50
40
50
V
= 1.8V
SY
V
= 5V
SY
G = –100
G = –10
G = –100
G = –10
40
30
30
20
20
10
10
G = –1
G = –1
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. Closed-Loop Gain vs. Frequency
Figure 26. Closed-Loop Gain vs. Frequency
10k
1k
10k
V
= 5V
SY
V
= 1.8V
SY
1k
100
10
G = 100
G = 10
G = 1
G = 100
100
10
G = 10
G = 1
1
1
0.1
0.01
0.1
10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. ZOUT vs. Frequency
Figure 27. ZOUT vs. Frequency
Rev. F | Page 10 of 21
Data Sheet
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
100
100
90
V
= 1.8V
V
= 5V
SY
SY
90
80
70
60
80
70
60
50
40
50
40
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31. CMRR vs. Frequency
Figure 34. CMRR vs. Frequency
100
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V
V
= 5V
SY
SY
90
80
70
60
50
40
30
20
10
0
PSRR+
100k
PSRR+
100k
PSRR–
PSRR–
10
100
1k
10k
1M
10
100
1k
10k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. PSRR vs. Frequency
Figure 35. PSRR vs. Frequency
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
R
= 1.8V
= 100kΩ
SY
V
R
= 5V
= 100kΩ
SY
L
L
–OVERSHOOT
–OVERSHOOT
+OVERSHOOT
+OVERSHOOT
10
100
LOAD CAPACITANCE (pF)
600
10
100
LOAD CAPACITANCE (pF)
600
Figure 33. Small-Signal Overshoot vs. Load Capacitance
Figure 36. Small-Signal Overshoot vs. Load Capacitance
Rev. F | Page 11 of 21
AD8505/AD8506/AD8508
Data Sheet
TA = 25°C, unless otherwise noted.
V
R
C
= 1.8V
= 100kΩ
= 200pF
V
R
C
= 5V
SY
SY
= 100kΩ
L
L
L
= 200pF
L
G = 1
G = 1
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 37. Large-Signal Transient Response
Figure 40. Large-Signal Transient Response
V
R
C
G = 1
= 1.8V
= 100kΩ
= 200pF
V
R
C
= 5V
= 100kΩ
= 200pF
SY
SY
L
L
L
L
G = 1
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 38. Small-Signal Transient Response
Figure 41. Small-Signal Transient Response
1k
V
= 1.8V AND 5V
SY
2.78µV p-p
V
= 1.8V AND 5V
SY
100
10
1
TIME (4s/DIV)
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 39. Input Voltage Noise 0.1 Hz to 10 Hz
Figure 42. Voltage Noise Density vs. Frequency
Rev. F | Page 12 of 21
Data Sheet
AD8505/AD8506/AD8508
TA = 25°C, unless otherwise noted.
–40
–40
V
V
= 1.8V
= 1.5V p-p
V
V
= 5V
= 4V p-p
SY
IN
100kΩ
SY
IN
100kΩ
–50
–60
–70
–80
–50
–60
–70
–80
10kΩ
10kΩ
–90
–100
–110
–120
–90
–100
–110
–120
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. Channel Separation vs. Frequency
Figure 44. Channel Separation vs. Frequency
Rev. F | Page 13 of 21
AD8505/AD8506/AD8508
Data Sheet
THEORY OF OPERATION
V
DD
The AD8505/AD8506/AD8508 are unity-gain, stable, CMOS, rail-
to-rail input/output operational amplifiers designed to optimize
performance in current consumption, PSRR, CMRR, and zero
crossover distortion, all embedded in a small package. The
typical offset voltage is 500 μV, with a low peak-to-peak voltage
noise of 2.8 μV from 0.1 Hz to 10 Hz and a voltage noise density
of 45 nV/√Hz at 1 kHz.
V
BIAS
V
V
IN+
IN–
I
Q2
Q4
Q3
Q1
The AD8505/AD8506/AD8508 amplifiers are designed to solve
two key problems in low voltage battery-powered applications:
the battery voltage decrease over time and the rail-to-rail input
stage distortion.
I
B
B
V
SS
In battery-powered applications, the supply voltage available to
the IC is the voltage of the battery. Unfortunately, the voltage of
a battery decreases as it discharges itself through the load. This
voltage drop over the lifetime of the battery causes an error in
the output of the op amps. Some applications requiring precision
measurements during the entire lifetime of the battery use voltage
regulators to power up the op amps as a solution. If a design
uses standard battery cells, the op amps experience a supply
voltage change from roughly 3.2 V to 1.8 V during the lifetime
of the battery. This means that for a PSRR of 70 dB minimum in
a typical op amp, the input-referred offset error is approximately
440 μV. If the same application uses the AD8505/AD8506/
AD8508 amplifiers with a 100 dB minimum PSRR, the error is
only 14 μV. It is possible to calibrate out this error or to use an
external voltage regulator to power the op amp, but these solutions
can increase system cost and complexity. The AD8505/AD8506/
AD8508 amplifiers solve the impasse with no additional cost or
error-nullifying circuitry.
Figure 45. A Typical Dual Differential Pair Input Stage Op Amp
(Dual PMOS Q1 and Q2 Transistors Form the Lower End of the Input Voltage
Range, Whereas Dual NMOS Q3 and Q4 Compose the Upper End)
300
V
= 5V
SY
= 25°C
250
200
150
100
50
T
A
0
–50
–100
–150
–200
–250
–300
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
V
CM
Figure 46. Typical Input Offset Voltage vs. Common-Mode Voltage
Response in a Dual Differential Pair Input Stage Op Amp (Powered by 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
The second problem with battery-powered applications is the
distortion caused by the standard rail-to-rail input stage. Using
a CMOS non-rail-to-rail input stage (that is, a single differential
pair) limits the input voltage to approximately one VGS (gate-
source voltage) away from one of the supply lines. Because VGS
for normal operation is commonly over 1 V, a single differential
pair input stage op amp greatly restricts the allowable input
voltage range when using a low supply voltage. This limitation
restricts the number of applications where the non-rail-to-rail
input op amp was originally intended to be used. To solve this
problem, a dual differential pair input stage is usually implemented
(see Figure 45); however, this technique has its own drawbacks.
This distortion forces the designer to devise impractical ways
to avoid the crossover distortion areas, therefore narrowing the
common-mode dynamic range of the operational amplifier. The
AD8505/AD8506/AD8508 amplifiers solve this crossover dis-
tortion problem by using an on-chip charge pump to power the
input differential pair. The charge pump creates a supply voltage
higher than the voltage of the battery, allowing the input stage to
handle a wide range of input signal voltages without using a second
differential pair. With this solution, the input voltage can vary from
one supply extreme to the other with no distortion, thereby
restoring the full common-mode dynamic range of the op amp.
One differential pair amplifies the input signal when the common-
mode voltage is on the high end, whereas the other pair amplifies
the input signal when the common-mode voltage is on the low
end. This method also requires control circuitry to operate the
two differential pairs appropriately. Unfortunately, this topology
leads to a very noticeable and undesirable problem: if the signal
level moves through the range where one input stage turns off
and the other one turns on, noticeable distortion occurs (see
Figure 46).
Rev. F | Page 14 of 21
Data Sheet
AD8505/AD8506/AD8508
The charge pump has been carefully designed so that switching
noise components at any frequency, both within and beyond the
amplifier bandwidth, are much lower than the thermal noise floor.
Therefore, the spurious-free dynamic range (SFDR) is limited only
by the input signal and the thermal or flicker noise. There is no
intermodulation between the input signal and the switching noise.
Figure 48, the input offset voltage vs. input common-mode voltage
response, shows the typical response of 12 devices. Figure 48 is
expanded to make it easier to compare with Figure 46, the typical
input offset voltage vs. common-mode voltage response in a
dual differential pair input stage op amp.
300
250
Figure 47 displays a typical front-end section of an operational
amplifier with an on-chip charge pump.
V
= 5V, T = 25°C
SY A
200
150
100
50
V
= POSITIVE PUMPED VOLTAGE = V + 1.8V
PP
DD
V
PP
V
DD
V
BIAS
+IN
0
–50
CASCODE
STAGE
AND
–100
–150
Q2
Q1
–IN
RAIL-TO-RAIL
OUTPUT
OUT
–200
–250
–300
STAGE
0
0.5
1.0
1.5 2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
V
CM
V
SS
Figure 48. Input Offset Voltage vs. Input Common-Mode Voltage Response
(Powered by a 5 V Supply; Results of 12 Units Are Displayed)
Figure 47. Typical Front-End Section of an Op Amp
with Embedded Charge Pump
This solution improves the CMRR performance tremendously.
For instance, if the input varies from rail to rail on a 2.5 V
supply rail, using a part with a CMRR of 70 dB minimum, an
input-referred error of 790 µV is introduced. Another part with
a CMRR of 52 dB minimum generates a 6.3 mV error. The
AD8505/AD8506/AD8508 CMRR of 90 dB minimum causes only
a 79 µV error. As with the PSRR error, there are complex ways to
minimize this error, but the AD8505/AD8506/AD8508 amplifiers
solve this problem without incurring unnecessary circuitry
complexity or increased cost.
Rev. F | Page 15 of 21
AD8505/AD8506/AD8508
Data Sheet
APPLICATIONS INFORMATION
The maximum total quiescent currents for the AD8506 (that is,
half of the AD8506), ADR1581, and ADG733 are 25 µA, 70 µA,
and 1 µA, respectively, resulting in a total of 96 µA current con-
sumption (480 µW power consumption) per circuit, which is good
for a system powered by a battery. If the accuracy and temperature
drift of the total design need to be improved, then a more accurate
and low temperature coefficient drift voltage reference and current
source resistor must be utilized. C3 and C4 are used to improve
stabilization of U1; R3 and R7 are used to provide some current
limit into the U1 inverting pin; and R2 and R6 are used to slow
down the rise time of the N-MOSFET when it turns on. These
elements may not be needed, or some bench adjustments may
be required.
PULSE OXIMETER CURRENT SOURCE
A pulse oximeter is a noninvasive medical device used for con-
tinuously measuring the percentage of hemoglobin (Hb) saturated
with oxygen and the pulse rate of a patient. Hemoglobin that is
carrying oxygen (oxyhemoglobin) absorbs light in the infrared
(IR) region of the spectrum; hemoglobin that is not carrying
oxygen (deoxyhemoglobin) absorbs visible red (R) light. In
pulse oximetry, a clip containing two LEDs (sometimes more,
depending on the complexity of the measurement algorithm) and
the light sensor (photodiode) is placed on the finger or earlobe
of the patient. One LED emits red light (600 nm to 700 nm) and
the other emits light in the near IR (800 nm to 900 nm) region.
The clip is connected by a cable to a processor unit. The LEDs
are rapidly and sequentially excited by two current sources (one
for each LED), whose dc levels depend on the LED being driven,
based on manufacturer requirements, and the detector is synchro-
nized to capture the light from each LED as it is transmitted
through the tissue.
+5V
C2
0.1µF
CONNECT TO RED LED
+5V
U2
ADG733
C1
0.1µF
U1
1/2
16
+5V
62.5mA
R2
AD8506
V
DD
S1A 12
R4
53.6kΩ
8
14 D1
An example design of a dc current source driving the red and
infrared LEDs is shown in Figure 49. These dc current sources
allow 62.5 mA and 101 mA to flow through the red and infrared
LEDs, respectively. First, to prolong battery life, the LEDs are
driven only when needed. One-third of the ADG733 SPDT
analog switch is used to disconnect or connect the 1.25 V voltage
reference from or to each current circuit. When driving the LEDs,
the ADR1581 1.25 V voltage reference is buffered by half of the
AD8506; the presence of this voltage on the noninverting input
forces the output of the op amp (due to the negative feedback)
to maintain a level that causes its inverting input to track the
noninverting pin. Therefore, the 1.25 V appears in parallel with
the 20 Ω R1 or 12.4 Ω R5 current source resistor, creating the flow
of 62.5 mA or 101 mA current through the red or infrared LED
as the output of the op amp turns on the Q1 or Q2 N-MOSFET
IRLMS2002.
5
6
V
OUT1
S1B 13
22Ω
V+
7
V
= 1.25V
REF
V–
4
S2A
S2B
S3A
S3B
2
1
5
3
U3
Q1
IRLMS2002
D2
15
ADR1581
C3
22pF
R3
1kΩ
4
D3
R1
20Ω
0.1%
1/4W MIN
9
RED CURRENT
SOURCE
A2
A1
A0
EN
10
11
6
8
GND
V
SS
CONNECT TO INFRARED LED
7
+5V
U1
101mA
1/2
AD8506
8
R6
22Ω
I_BIT2
I_BIT1
I_BIT0
I_ENA
3
2
V
OUT2
V+
1
V–
4
Q2
IRLMS2002
C4
22pF
R7
1kΩ
R5
12.4Ω
0.1%
INFRARED CURRENT
SOURCE
1/2W MIN
Figure 49. Pulse Oximeter Red and Infrared Current Sources Using the
AD8506 as a Buffer to the Voltage Reference Device
Rev. F | Page 16 of 21
Data Sheet
AD8505/AD8506/AD8508
Another consideration is operation from a 3.3 V battery. Glucose
signal currents are usually less than 3 μA full scale; therefore,
the I-to-V converter requires low input bias current. The
AD8505/AD8506/AD8508 are excellent choices because these
amplifiers provide 1 pA typical and 10 pA maximum of input
bias current at ambient temperature.
FOUR-POLE, LOW-PASS BUTTERWORTH FILTER
FOR GLUCOSE MONITOR
There are several methods of glucose monitoring: spectroscopic
absorption of infrared light in the 2 μm to 2.5 μm range, reflec-
tance spectrophotometry, and the amperometric type using
electrochemical strips with glucose oxidase enzymes. The
amperometric type generally uses three electrodes: a reference
electrode, a control electrode, and a working electrode. Although
this is a well established and widely used technique, signal-to-noise
ratio and repeatability can be improved using the AD8505/
AD8506/AD8508 amplifiers with their low peak-to-peak voltage
noise of 2.8 μV from 0.1 Hz to 10 Hz and voltage noise density
of 45 nV/√Hz at 1 kHz.
A low-pass filter with a cutoff frequency of 80 Hz to 100 Hz is
desirable in a glucose meter device to remove extraneous noise;
this can be a simple two-pole or four-pole Butterworth filter. Low
power op amps with bandwidths of 50 kHz to 500 kHz are
adequate. The AD8505/AD8506/AD8508 amplifiers with their
95 kHz GBP and 15 μA typical current consumption meet these
requirements. A circuit design of a four-pole Butterworth filter
(preceded by a one-pole, low-pass filter) is shown in Figure 50.
With a 3.3 V battery, the total power consumption of this design
is 297 μW typical at ambient temperature.
C1
1000pF
R1
5MΩ
+3.3V
WORKING
+3.3V
U1
1/2
AD8506
8
3
2
CONTROL
R2
R3
U2
1/2
AD8506
+3.3V
V+
22.6kΩ 22.6kΩ
8
1
5
6
R4
R5
V–
4
C3
V+
22.6kΩ 22.6kΩ
REFERENCE
8
U1
1/2
AD8506
0.047µF
7
3
2
V–
4
C5
V+
0.047µF
1
V
OUT
V–
4
C2
0.1µF
C4
0.1µF
DUPLICATE OF CIRCUIT ABOVE
Figure 50. A Four-Pole Butterworth Filter That Can Be Used in a Glucose Meter
Rev. F | Page 17 of 21
AD8505/AD8506/AD8508
OUTLINE DIMENSIONS
Data Sheet
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 51. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
0.945
0.905
0.865
2
1
A
B
BALL A1
IDENTIFIER
1.425
1.385
1.345
0.80
REF
C
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
0.40 BSC
0.415
0.400
0.385
BOTTOM VIEW
(BALL SIDE UP)
0.645
0.600
0.555
SIDE VIEW
COPLANARITY
0.05
0.287
0.267
0.247
0.230
0.200
0.170
SEATING
PLANE
Figure 52. 6-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-6-7)
Dimensions shown in millimeters
Rev. F | Page 18 of 21
Data Sheet
AD8505/AD8506/AD8508
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1.460
1.420 SQ
1.380
3
2
1
A
B
C
BALL A1
IDENTIFIER
0.50
BSC
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.380
0.355
0.330
0.650
0.595
0.540
END VIEW
COPLANARITY
0.075
SEATING
PLANE
0.270
0.240
0.210
0.340
0.320
0.300
Figure 54. 8-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-8-2)
Dimensions shown in millimeters
Rev. F | Page 19 of 21
AD8505/AD8506/AD8508
Data Sheet
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
0.20
0.09
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
0.25
BSC
1.50
1.46
1.42
0.25
BSC
0.25
0.25
BSC
BSC
3
2
1
A
BALL A1
IDENTIFIER
0.50 BSC
3.00
2.96
2.92
B
C
D
E
0.50 BSC
0.50 BSC
2.00
BSC
0.50
BSC
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
1.00
BSC
0.380
0.355
0.330
0.650
0.595
0.540
END VIEW
COPLANARITY
0.10
0.270
0.240
0.210
SEATING
PLANE
0.340
0.320
0.300
Figure 56. 14-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-14-1)
Dimensions shown in millimeters
Rev. F | Page 20 of 21
Data Sheet
AD8505/AD8506/AD8508
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RJ-5
RJ-5
CB-6-7
CB-6-7
CB-8-2
RM-8
Branding
A2E
A2E
A2H
A2H
AD8505ARJZ-R2
AD8505ARJZ-R7
AD8505ACBZ-R7
AD8505ACBZ-RL
AD8506ACBZ-REEL7
AD8506ARMZ
AD8506ARMZ-R7
AD8506ARMZ-REEL
AD8508ARUZ
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
8-Ball Wafer Level Chip Scale Package [WLCSP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Ball Wafer Level Chip Scale Package [WLCSP]
A1X
A1X
A1X
A1X
RM-8
RM-8
RU-14
RU-14
CB-14-1
AD8508ARUZ-REEL
AD8508ACBZ-REEL7
A27
1 Z = RoHS Compliant Part.
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06900-0-9/17(F)
Rev. F | Page 21 of 21
相关型号：
AD8506ACBZ-REEL7
DUAL OP-AMP, 3500 uV OFFSET-MAX, 0.095 MHz BAND WIDTH, PBGA8, ROHS COMPLIANT, WLCSP-8
ROCHESTER
AD8506ARMZ
DUAL OP-AMP, 3500 uV OFFSET-MAX, 0.095 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
ROCHESTER
AD8506ARMZ-R2
DUAL OP-AMP, 3500 uV OFFSET-MAX, 0.095 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
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