AD8556ARZ-REEL [ADI]
Digitally Programmable Sensor Signal Amplifier with EMI Filters;
| 型号： | AD8556ARZ-REEL |
| 厂家： | 
ADI |
| 描述： | Digitally Programmable Sensor Signal Amplifier with EMI Filters 光电二极管 |
| 文件： | 总28页 (文件大小：714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digitally Programmable Sensor Signal
Amplifier with EMI Filters
Data Sheet
AD8556
FEATURES
APPLICATIONS
EMI filters at input pins
Pressure and position sensors
Precision current sensing
Strain gages
Specified from −40°C to +140°C
Low offset voltage: 10 µV maximum
Low input offset voltage drift:
65 nV/°C maximum
High CMRR: 94 dB minimum
Digitally programmable gain and output offset voltage
Programmable output clamp voltage
Open and short wire fault detection
Low-pass filtering
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_WQ packages
4.5 V to 5.5 V operation
FUNCTIONAL BLOCK DIAGRAM
DIGIN
VDD
VCLAMP
1
2
EMI
FILTER
+IN
A5
3
OUT
VSS
DAC
LOGIC
–IN
VDD
EMI
FILTER
1
2
+IN
A1
R5
P4
R7
VPOS
3
OUT
–IN
R2
VSS
P2
VDD
VDD
EMI
FILTER
R3
R1
1
2
RF
+IN
A3
3
EMI
FILTER
1
+IN
A4
OUT
VSS
3
V
OUT
P1
–IN
OUT
2
VDD
–IN
1
2
VSS
+IN
A2
R4
R5
3
OUT
EMI
FILTER
VNEG
–IN
P3
VSS
AD8556
VSS
FILT/DIGOUT
Figure 1.
Rev. B
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with EMI Filters Data Sheet
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Technical Books
• A Designer's Guide to Instrumentation Amplifiers, 3rd
Edition, 2006
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AD8556
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 17
Gain Values ................................................................................. 18
Open Wire Fault Detection....................................................... 19
Shorted Wire Fault Detection................................................... 19
Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 19
Device Programming................................................................. 19
EMI/RFI Performance ................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Electrical Specifications............................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
2/15—Rev. A to Rev. B
Changed LFCSP_VQ Package to
LFCSP_WQ Package..................................................... Throughout
Changes to Applications Section .................................................... 1
Changes to Table 4............................................................................ 7
Changes to Figure 3.......................................................................... 8
Added Table 5; Renumbered Sequentially .................................... 8
Changes to Figure 57...................................................................... 27
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 27
12/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 3
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/05—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
AD8556
GENERAL DESCRIPTION
The AD8556 is a zero-drift, sensor signal amplifier with
digitally programmable gain and output offset. Designed to
easily and accurately convert variable pressure sensor and
strain bridge outputs to a well-defined output voltage range,
the AD8556 accurately amplifies many other differential or
single-ended sensor outputs. The AD8556 uses the Analog
Devices, Inc. patented low noise, auto-zero and DigiTrim®
technologies to create an incredibly accurate and flexible
signal processing solution in a very compact footprint.
In addition to extremely low input offset voltage, low input offset
voltage drift, and very high dc and ac CMRR, the AD8556 also
includes a pull-up current source at the input pins and a pull-
down current source at the VCLAMP pin, which allows open
wire and shorted wire fault detection. A low-pass filter function
is implemented via a single low cost external capacitor. Output
clamping set via an external reference voltage allows the AD8556
to drive lower voltage ADCs safely and accurately.
When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment further
ensures field reliability.
Gain is digitally programmable in a wide range from 70 to
1280 through a serial data interface. Gain adjustment can
be fully simulated in-circuit and then permanently pro-
grammed with reliable polyfuse technology. Output offset
voltage is also digitally programmable and is ratiometric to
the supply voltage. The AD8556 also features internal EMI
filters on the VNEG, VPOS, FILT and VCLAMP pins.
The AD8556 is fully specified from −40°C to +140°C.
Operating from single-supply voltages of 4.5 V to 5.5 V, the
AD8556 is offered in the 8-lead SOIC_N and 4 mm × 4 mm
16-lead LFCSP_WQ.
Rev. B | Page 3 of 27
AD8556
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +140°C, unless otherwise specified.
Table 1.
Parameter
Symbol Conditions
Min Typ
Max Unit
INPUT STAGE
Input Offset Voltage
VOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +140°C
2
3
25
49
10
12
65
54
58
60
2.5
3.0
4.0
2.9
µV
µV
nV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
ppm
ppm
%
Input Offset Voltage Drift
Input Bias Current
TCVOS
IB
TA = 25°C
38
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +140°C
TA = 25°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +140°C
Input Offset Current
IOS
0.2
Input Voltage Range
Common-Mode Rejection Ratio
2.1
80
94
CMRR
VCM = 2.1 V to 2.9 V, AV = 70
VCM = 2.1 V to 2.9 V, AV = 1280
VO = 0.2 V to 3.4 V
92
112
20
1000
0.35
0.5
7
Linearity
VO = 0.2 V to 4.8 V
Differential Gain Accuracy
Differential Gain Temperature Coefficient
Second stage gain = 17.5 to 100
Second stage gain = 140 to 200
Second stage gain = 17.5 to 100
Second stage gain = 140 to 200
1.6
2.5
20
%
ppm/°C
ppm/°C
10
40
RF
14
18
22
kΩ
RF Temperature Coefficient
DAC
600
ppm/°C
Accuracy
AV = 70, offset codes = 8 to 248
AV = 70, offset codes = 8 to 248
AV = 70, offset codes = 8 to 248
−40°C ≤ TA ≤ +125°C
0.2
50
5
0.6
%
ppm
mV
ppm FS/°C
ppm FS/°C
Ratiometricity
Output Offset
Temperature Coefficient
35
15
25
3.3
−40°C ≤ TA ≤ +140°C
VCLAMP
Input Bias Current
TA = 25°C, VCLAMP = 5 V
−40°C ≤ TA ≤ +125°C, VCLAMP = 5 V
−40°C ≤ TA ≤ +140°C, VCLAMP = 5 V
200
nA
nA
nA
V
500
550
4.94
Input Voltage Range
OUTPUT BUFFER STAGE
Buffer Offset
Short-Circuit Current
Output Voltage, Low
Output Voltage, High
POWER SUPPLY
1.2
3
7
10
20
mV
mA
mV
V
ISC
VOL
VOH
5
RL = 10 kΩ to 5 V
RL = 10 kΩ to 0 V
4.94
Supply Current
ISY
−40°C ≤ TA ≤ +125°C, VO = 2.5 V,
2.0
2.7
mA
VPOS = VNEG = 2.5 V, VDAC code = 128
−40°C ≤ TA ≤ +140°C, VO = 2.5 V,
2.78 mA
VPOS = VNEG = 2.5 V, VDAC Code = 128
Power Supply Rejection Ratio
Supply Voltage Required During Programming
PSRR
AV = 70
109 125
5.0 5.25
dB
V
5.5
10°C < TPROG < 40°C, supply capable of
driving 250 mA
Rev. B | Page 4 of 27
Data Sheet
AD8556
Parameter
Symbol Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
First gain stage, TA = 25°C
Second gain stage, TA = 25°C
Output buffer stage, TA = 25°C
AV = 70, RL = 10 kΩ, CL = 100 pF, TA = 25°C
To 0.1%, AV = 70, 4 V output step, TA = 25°C
2
8
1.5
1.2
8
MHz
MHz
MHz
V/µs
µs
Output Buffer Slew Rate
Settling Time
SR
ts
NOISE PERFORMANCE
Input Referred Noise
Low Frequency Noise
Total Harmonic Distortion
TA = 25°C, f = 1 kHz
f = 0.1 Hz to 10 Hz, TA = 25°C
VIN = 16.75 mV rms, f = 1 kHz,
AV = 100, TA = 25°C
32
0.5
−100
nV/√Hz
µV p-p
dB
en p-p
THD
DIGITAL INTERFACE
Input Current
DIGIN Pulse Width to Load 0
DIGIN Pulse Width to Load 1
Time Between Pulses at DIGIN
DIGIN Low
DIGIN High
DIGOUT Logic 0
DIGOUT Logic 1
2
0.05
50
µA
µs
µs
µs
V
V
V
V
tw0
tw1
tws
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
10
10
1
1
4
4
Rev. B | Page 5 of 27
AD8556
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to
VSS or VDD
6 V
VSS − 0.3 V to VDD + 0.3 V
5.0 V
Indefinite
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature
−65°C to +150°C
−40°C to +150°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
1 Differential input voltage is limited to 5.0 V or the supply voltage,
whichever is less.
1
θJA
158
44
θJC
Unit
°C/W
°C/W
8-Lead SOIC_N (R)
16-Lead LFCSP_WQ (CP)
43
31.5
1 θJA is specified for the worst-case conditions, that is, θJA is specified for device
soldered in circuit board for LFCSP_WQ package.
ESD CAUTION
Rev. B | Page 6 of 27
Data Sheet
AD8556
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD
FILT/DIGOUT
DIGIN
1
2
3
4
8
7
6
5
VSS
AD8556
VOUT
VCLAMP
VPOS
TOP VIEW
(Not to Scale)
VNEG
Figure 2. 8-Lead SOIC_N Pin Configuration
Table 4. 8-Lead SOIC_N Pin Function Descriptions
SOIC_N
Mnemonic
Description
1
2
VDD
FILT/DIGOUT
Positive Supply Voltage.
Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS
implements a low-pass filtering function. In read mode, this pin functions as a digital output.
3
4
5
6
7
DIGIN
VNEG
VPOS
VCLAMP
VOUT
Digital Input.
Negative Amplifier Input (Inverting Input).
Positive Amplifier Input (Noninverting Input).
Set Clamp Voltage at Output.
Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a
buffered digital output.
8
VSS
Negative Supply Voltage.
Rev. B | Page 7 of 27
AD8556
Data Sheet
NC
FILT/DIGOUT
NC
1
2
3
4
12 VOUT
11 NC
AD8556
TOP VIEW
10
9
VCLAMP
NC
DIGIN
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED
TO DVSS (PIN 13).
Figure 3. 16-Lead LFCSP_WQ Pin Configuration
Table 5. 16-Lead LFCSP_WQ Pin Function Descriptions
LFCSP_WQ
Mnemonic
Description
0
EPAD
NC
FILT/DIGOUT
Exposed Pad. The exposed pad must be connected to DVSS (Pin 13).
Do Not Connect.
Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or
VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output.
1, 3, 5, 7, 9, 11
2
4
6
8
10
12
DIGIN
VNEG
VPOS
VCLAMP
VOUT
Digital Input.
Negative Amplifier Input (Inverting Input).
Positive Amplifier Input (Noninverting Input).
Set Clamp Voltage at Output.
Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is
a buffered digital output.
VSS
DVSS, AVSS
DVDD, AVDD
Negative Supply Voltage.
Negative Supply Voltage.
Positive Supply Voltage.
13, 14
15, 16
Rev. B | Page 8 of 27
Data Sheet
AD8556
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
N: 363
V
= 5V
SY
100
MEAN: –0.389938
SD: 1.65684
80
60
40
20
0
0
–10
–5
0
5
10
0
10
20
T
30
40
MORE
V
5V (µV)
V
(nV/°C)
OS
OS
C
Figure 4. Input Offset Voltage Distribution
Figure 7. TCVOS at VSY = 5 V
2.0
1.5
V
= 5V
SY
V
= 5V
= 25°C
SY
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
T
A
1.0
V
= 0.3V
OUT
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
= 4.7V
OUT
1.5
2.0
2.5
(V)
3.0
3.5
–50
–25
0
25
50
75
100
125
150
V
CM
TEMPERATURE (°C)
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 8. Output Buffer Offset Voltage vs. Temperature
10
8
100
10
1
V
= 5V
SY
V
= 5V
SY
6
4
2
0
–2
–4
–6
–8
–10
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Input Offset Voltage vs. Temperature
Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature
Rev. B | Page 9 of 27
AD8556
Data Sheet
100
1000
100
10
V
= 5V
V
= 5V
SY
SY
= 25°C
I
–
B
T
A
+125°C
I
+
B
+25°C
–40°C
10
1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
(V)
CM
VCLAMP VOLTAGE (V)
Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage
Figure 13. VCLAMP Current over Temperature at
VS = 5 V vs. VCLAMP Voltage
0.8
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
SY
T
= 25°C
A
0.6
0.5
0.3
0.2
0
–0.2
–0.3
–0.5
–0.6
–0.8
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 14. Supply Current (ISY) vs. Supply Voltage
Figure 11. Input Offset Current vs. Temperature
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
V
= 5.5V
SY
SY
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
TEMPERATURE (°C)
DIGITAL INPUT VOLTAGE (V)
Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)
Figure 15. Supply Current (ISY) vs. Temperature
Rev. B | Page 10 of 27
Data Sheet
AD8556
V
= ±2.5V
V
= ±2.5V
SY
GAIN = 70
SY
GAIN = 70
120
80
60
50
40
30
20
10
40
0
100
1k
10k
100k
1M
0
5
10
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 16. CMRR vs. Frequency
Figure 19. Voltage Noise Density vs. Frequency (0 Hz to 10 kHz)
V
= ±2.5V
SY
GAIN = 1280
V
= ±2.5V
SY
GAIN = 70
120
80
35
30
25
20
15
10
5
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
0
250
500
FREQUENCY (kHz)
Figure 17. CMRR vs. Frequency
Figure 20. Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)
V
= 5V
SY
145
135
125
115
105
95
V
= ±2.5V
SY
GAIN = 1000
0.6
0.4
GAIN = 800
GAIN = 400
GAIN = 1280
0.2
0
–0.2
–0.4
–0.6
GAIN = 70
GAIN = 100
85
75
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TIME (1s/DIV)
Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
Figure 18. CMRR vs. Temperature at Different Gains
Rev. B | Page 11 of 27
AD8556
Data Sheet
V
= ±2.5V
SY
V
= ±2.5V
SY
GAIN = 70
8
4
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–4
–8
1k
10k
100k
1M
10M
TIME (1s/DIV)
FREQUENCY (Hz)
Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
Figure 25. Output Buffer Gain vs. Frequency
60
V
C
= ±2.5V
= 40pF
SY
V
= ±2.5V
SY
GAIN = 1280
L
R
R
= 0Ω
S
S
50
40
30
20
10
0
60
40
20
0
C
L
OUTPUT
BUFFER
GAIN = 70
R
= 10Ω
S
R
= 50Ω
R
= 20Ω
S
S
R
= 100Ω
S
1k
10k
100k
1M
0.1
1
10
100
FREQUENCY (Hz)
LOAD CAPACITANCE (nF)
Figure 23. Closed-Loop Gain vs. Frequency Measured at FILT/DIGOUT Pin
Figure 26. Output Buffer Positive Overshoot
60
50
40
30
20
10
0
V
= ±2.5V
SY
V
= ±2.5V
SY
GAIN = 1280
R
S
60
40
20
0
R
= 0Ω
C
S
L
GAIN = 70
R
= 10Ω
S
R
= 50Ω
S
R
= 100Ω
R = 20Ω
S
S
1k
10k
100k
1M
0.1
1.0
10.0
100.0
FREQUENCY (Hz)
LOAD CAPACITANCE (nF)
Figure 24. Closed-Loop Gain vs. Frequency Measured at VOUT Pin
Figure 27. Output Buffer Negative Overshoot
Rev. B | Page 12 of 27
Data Sheet
AD8556
1.000
V
= ±2.5V
SY
6
5
4
3
2
1
0
SUPPLY VOLTAGE
SOURCE
SINK
0.100
0.010
V
OUT
0.001
0.01
0.10
1.00
10.0
TIME (100µs/DIV)
LOAD CURRENT (mA)
Figure 31. Power-On Response at 125°C
Figure 28. Output Voltage to Supply Rail vs. Load Current
15
12
9
SINK 5V
6
5
4
3
2
1
0
SUPPLY VOLTAGE
6
3
0
–3
–6
–9
–12
–15
SOURCE 5V
V
OUT
–75 –50 –25
0
25
50
75
100 125 150 175
TIME (100µs/DIV)
TEMPERATURE (°C)
Figure 29. Output Short Circuit vs. Temperature
Figure 32. Power-On Response at −40°C
150
145
140
135
130
125
120
115
110
105
100
V
= 2.7V TO 5.5V
SY
SUPPLY VOLTAGE
4
2
0
3
2
1
0
V
OUT
–75
–50
–25
0
25
50
75
100
125
150
TIME (100µs/DIV)
TEMPERATURE (°C)
Figure 33. PSRR vs. Temperature
Figure 30. Power-On Response at 25°C
Rev. B | Page 13 of 27
AD8556
Data Sheet
140
V
= 2.7V TO 2.5V
T
SY
V
= ±2.5V
SY
GAIN = 70
= 100pF
120
100
80
C
L
2
60
40
20
0
0.01
0.1
1
10
100
FREQUENCY (kHz)
TIME (10µs/DIV)
Figure 37. Large Signal Response at CL = 100 pF
Figure 34. PSRR vs. Frequency
T
V
= ±2.5V
SY
GAIN = 70
= 0.05µF
T
V
= ±2.5V
SY
GAIN = 70
C
L
C
= 0.1µF
= 10kHz
L
F
IN
2
2
TIME (10µs/DIV)
TIME (100µs/DIV)
Figure 38. Large Signal Response at CL = 0.05 μF
Figure 35. Small Signal Response at CL = 0.1 μF and FIN = 10 kHz
1k
V
= ±2.5V
SY
A
= 70
T
V
= ±2.5V
V
SY
GAIN = 70
C
= 100pF
= 1kHz
L
F
IN
100
10
1
2
0.1
1
10
100
1M
FREQUENCY (kHz)
TIME (100µs/DIV)
Figure 39. Output Impedance vs. Frequency
Figure 36. Small Signal Response at CL = 100 pF and FIN = 1 kHz
Rev. B | Page 14 of 27
Data Sheet
AD8556
1
0V
V
IN
1
0V
V
IN
2
0V
V
OUT
V
OUT
2
0V
CH1 10.0mV
CH2 2.00V
M 4.00µs A CH1
8.40mV
CH1 50.0mV
CH2 2.00V
M 1.00µs A CH1
–21.0mV
Figure 40. Negative Overload Recovery (Gain = 70)
Figure 43. Positive Overload Recovery (Gain = 1280)
V
IN
1
GAIN = 70
OFFSET = 128
1
V
= ±2.5V
SY
+V
0V
4V pp
0.1µF
6
7
1
20.5Ω
294Ω
4
5
V
OUT
2
DUT
8
0V
0.1µF
–V
1kΩ
10kΩ
10kΩ
OUT
CH2 2.00mV M 1.00µs
2
CH1 50.0mV
CH2 2.00V
M 1.00µs A CH1
57.0mV
CH1 2.00mV
A CH1
40.0mV
Figure 44. Settling Time 0.1%
Figure 41. Positive Overload Recovery (Gain = 70)
1
0V
GAIN = 70
OFFSET = 128
= ±2.5V
1
0V
V
SY
V
IN
+V
4V pp
0.1µF
1
20.5Ω
294Ω
4
5
6
7
2
0V
DUT
0.1µF
8
–2.5V
–V
10kΩ
1kΩ
10kΩ
OUT
CH2 2.00mV M 1.00µs
2
0V
CH1 2.00mV
A CH1
40.0mV
CH1 10.0mV
CH2 2.00V
M 4.00µs A CH1
–9.40mV
Figure 45. Settling Time 0.01%
Figure 42. Negative Overload Recovery (Gain = 1280)
Rev. B | Page 15 of 27
AD8556
Data Sheet
1.00
V
= ±2.5V
SY
0.50
0.20
0.10
0.05
0.02
0.01
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
Figure 46. THD vs. Frequency
Rev. B | Page 16 of 27
Data Sheet
AD8556
THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiometers,
guaranteed to be monotonic. Programming P1 and P2 allows
the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see Table 6 and Equation 1), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient; therefore, the first stage
gain temperature coefficient is lower than 100 ppm/°C.
A4 implements a rail-to-rail input and output unity-gain
voltage buffer. The output stage of A4 is supplied from a
buffered version of VCLAMP instead of VDD, allowing the
positive swing to be limited. The maximum output current is
limited between 5 mA to 10 mA.
An 8-bit DAC is used to generate a variable offset for the
amplifier output. This DAC is guaranteed to be monotonic.
To preserve the ratiometric nature of the input signal, the DAC
references are driven from VSS and VDD, and the DAC output
can swing from VSS (Code 0) to VDD (Code 255). The 8-bit
resolution is equivalent to 0.39% of the difference between
VDD and VSS, for example, 19.5 mV with a 5 V supply. The
DAC output voltage (VDAC) is given approximately by
Code
6.4 127
GAIN1≈ 4×
(1)
4
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of
the differential amplifier. A3 is also an auto-zeroed op amp that
minimizes input offset errors. P3 and P4 are digital potentiometers
that allow the second stage gain to be varied from 17.5 to 200 in
eight steps (see Table 7). R4, R5, R6, R7, P3, and P4 each have a
similar temperature coefficient; therefore, the second stage gain
temperature coefficient is lower than 100 ppm/°C.
Code +0.5
VDAC ≈
VDD −VSS +VSS
( )
(2)
256
where the temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
RF together with an external capacitor, connected between
FILT/DIGOUT and VSS or VDD, form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 18 kΩ, allowing an 880 Hz low-pass
filter to be implemented by connecting a 10 nF external capacitor
between FILT/DIGOUT and VSS or between FILT/DIGOUT
and VDD. If low-pass filtering is not needed, the FILT/DIGOUT
pin must be left floating.
VOUT = GAIN (VPOS − VNEG) + VDAC
(3)
where GAIN is the product of the first and second stage gains.
VDD
VCLAMP
VDD
A1
A5
P3
VNEG
R4
R1
R6
VDD
A3
VSS
VDD
VSS
P1
R3
P2
R2
A5 implements a voltage buffer that provides the positive supply
to A4, the amplifier output buffer. Its function is to limit VOUT
to a maximum value, useful for driving ADCs operating on
supply voltages lower than VDD. The input to A5, VCLAMP,
has a very high input resistance. It should be connected to a
known voltage and not left floating. However, the high input
impedance allows the clamp voltage to be set using a high
impedance source, such as a potential divider. If the maximum
value of VOUT does not need to be limited, VCLAMP should
be connected to VDD.
RF
VOUT
A4
VDD
A2
VSS
R7
FILT/
DIGOUT
VSS
R5
VPOS
P4
VDD
DAC
VSS
VSS
Figure 47. Functional Schematic
Rev. B | Page 17 of 27
AD8556
Data Sheet
GAIN VALUES
Table 6. First Stage Gain vs. First Stage Gain Code
First Stage
Gain Code
First Stage
Gain Code
First Stage
Gain Code
First Stage
Gain Code
First Stage Gain
4.000
4.015
4.030
4.045
4.060
4.075
4.090
4.105
4.120
4.135
4.151
4.166
4.182
4.197
4.213
4.228
4.244
4.260
4.276
4.291
4.307
4.323
4.339
4.355
4.372
4.388
4.404
4.420
4.437
4.453
4.470
4.486
First Stage Gain
4.503
4.520
4.536
4.553
4.570
4.587
4.604
4.621
4.638
4.655
4.673
4.690
4.707
4.725
4.742
4.760
4.778
4.795
4.813
4.831
4.849
4.867
4.885
4.903
4.921
4.939
4.958
4.976
4.995
5.013
5.032
5.050
First Stage Gain
5.069
5.088
5.107
5.126
5.145
5.164
5.183
5.202
5.221
5.241
5.260
5.280
5.299
5.319
5.339
5.358
5.378
5.398
5.418
5.438
5.458
5.479
5.499
5.519
5.540
5.560
5.581
5.602
5.622
5.643
5.664
5.685
First Stage Gain
5.706
5.727
5.749
5.770
5.791
5.813
5.834
5.856
5.878
5.900
5.921
5.943
5.965
5.988
6.010
6.032
6.054
6.077
6.099
6.122
6.145
6.167
6.190
6.213
6.236
6.259
6.283
6.306
6.329
6.353
6.376
6.400
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 7. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code
Second Stage Gain Code
Second Stage Gain
Minimum Combined Gain
Maximum Combined Gain
0
1
2
3
4
5
6
7
17.5
25
35
50
70
100
140
200
70
112
160
224
320
448
640
896
1280
100
140
200
280
400
560
800
Rev. B | Page 18 of 27
Data Sheet
AD8556
OPEN WIRE FAULT DETECTION
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or
(VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The i nput s
to A1 and A2, VNEG and VPOS, are also pulled up to VDD by
currents IP1 and IP2. These are both nominally 49 nA and
matched to within 3 nA. If the inputs to A1 or A2 are accidentally
left floating, as with an open wire fault, IP1 and IP2 pull them
to VDD, which would cause VOUT to swing to VSS, allowing
this fault to be detected. It is not possible to disable IP1 and IP2,
nor the clamping of VOUT to VSS, when VNEG or VPOS
approaches VDD.
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the Shorted Wire Fault
Detection section. In this way, the VOUT pin is shorted to VSS
when a floating input is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG, and
VCLAMP
Mnemonic
Typical Current
Goal of Current
VPOS
VNEG
VCLAMP
49 nA pull-up
49 nA pull-up
0.2 µA pull-down
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL
DEVICE PROGRAMMING
Digital Interface
SHORTED WIRE FAULT DETECTION
The AD8556 provides fault detection when VPOS, VNEG, or
VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage
regions at VPOS, VNEG, and VCLAMP that trigger an error
condition. When an error condition occurs, the VOUT pin is
shorted to VSS. Table 8 lists the voltage levels shown in Figure 48.
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input pin,
DIGIN, has hysteresis to minimize the possibility of inadvertent
triggering with slow signals. It also has a pull-down current sink
to allow it to be left floating when programming is not being
performed. The pull-down ensures inactive status of the digital
input by forcing a dc low voltage on DIGIN.
VPOS
VNEG
VCLAMP
VDD
VDD
VDD
ERROR
ERROR
VINH
VINH
NORMAL
ERROR
NORMAL
ERROR
NORMAL
ERROR
VCLL
VSS
A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 µs long, loads 0 into the shift register.
A long pulse at DIGIN, such as 50 µs or longer, loads 1 into the
shift register. The time between pulses should be at least 10 µs.
Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×
VDD are recognized as a low, and voltages at DIGIN between
0.8 × VDD and VDD are recognized as a high. The timing
diagram example in Figure 49 shows the waveform for entering
code 010011 into the shift register.
VINL
VSS
VINL
VSS
Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP
that Trigger a Fault Condition
Table 8. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
Min (V) Typ (V) Max (V)
VOUT Condition
VINH
2.95
1.95
1.05
3.0
2.0
1.1
3.05
2.05
1.15
Short to VSS fault
detection
Short to VSS fault
detection
Short to VSS fault
detection
VINL
VCLL
Rev. B | Page 19 of 27
AD8556
Data Sheet
tW1
tWS
tW1
tWS
tWS
tW0
tWS
tW0
tW0
tWS
tW1
WAVEFORM
CODE
0
1
0
0
1
1
Figure 49. Timing Diagram for Code 010011
Table 10. Timing Specifications
Timing Parameter
Description
Specification
tw0
tw1
tws
Pulse width for loading 0 into shift register
Pulse width for loading 1 into shift register
Width between pulses
Between 50 ns and 10 µs
≥50 µs
≥10 µs
Table 11. 38-Bit Serial Word Format
Field No.
Bits
Description
0
1
0 to 11
12 to 13
12-Bit Start of Packet 1000 0000 0001
2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2-Bit Parameter
2
14 to 15
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
3
4
16 to 17
18 to 25
2-Bit Dummy 10
8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
5
26 to 37
12-Bit End of Packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 µs, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Field 0 and Field 5 are the start-of-packet field and end-of-
packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to minimize
the risk of inadvertent programming; power-on reset occurs
when VDD is between 0.7 V and 2.2 V.
Rev. B | Page 20 of 27
Data Sheet
AD8556
Initial State
At least 10 µF (tantalum type) of decoupling capacitance is
needed across the power pins of the device during programming.
The capacitance can be on the programming apparatus as long
as it is within 2 inches of the device being programmed. An
additional 0.1 µF (ceramic type) in parallel with the 10 µF is
recommended within ½ inch of the device being programmed.
A minimum period of 1 ms should be allowed for each fuse to
blow. There is no need to measure the supply current during
programming.
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 12).
Table 12. Initial State Before Programming
Second Stage Gain Code = 0
First stage gain code = 0
Output offset code = 0
Master fuse = 0
Second Stage Gain = 17.5
First stage gain = 4.0
Output offset = VSS
Master fuse not blown
The best way to verify correct programming is to use the read
mode to read back the programmed values. Then, remeasure
the gain and offset to verify these values. Programmed fuses
have no effect on the gain and output offset until the master
fuse is blown. After blowing the master fuse, the gain and
output offset are determined solely by the blown fuses, and
the simulation mode is permanently deactivated.
When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown, or
from the polysilicon fuses, if the master fuse is blown. Programmed
values have no effect until the master fuse is blown. The internal
registers feature power-on reset; therefore, the unprogrammed
devices enter a known state after power-up. Power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
Parameters are programmed by setting Field 1 to 10, selecting
the desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.
Simulation Mode
The simulation mode allows any parameter to be temporarily
changed. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01, selecting
the desired parameter in Field 2, and the desired value for the
parameter in Field 4. Note that a value of 11 for Field 2 is ignored
during the simulation mode. Examples of temporary settings
are as follows:
As an example, suppose the user wants to permanently set the
second stage gain to 50. Parameter 00 needs to have the value
0000 0011 assigned. Two bits have the value 1; therefore, two
fuses need to be blown. Because only one fuse can be blown at a
time, this code can be used to blow one fuse:
1000 0000 0001 10 00 10 0000 0010 0111 1111 1110.
The MOS switch that blows the fuse closes when the complete
packet is recognized and opens when the start-of-packet,
dummy, or end-of-packet fields are no longer valid. After 1 ms,
this second code is entered to blow the second fuse:
• Setting the second stage gain code (Parameter 00) to 011 and
the second stage gain to 50 produces:
1000 0000 0001 01 00 10 0000 0011 0111 1111 1110.
• Setting the first stage gain code (Parameter 01) to 000 1011
and the first stage gain to 4.166 produces:
1000 0000 0001 01 01 10 0000 1011 0111 1111 1110.
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110.
To permanently set the first stage gain to a nominal value of
4.151, Parameter 01 needs to have the value 000 1011 assigned.
Three fuses need to be blown, and the following codes are used,
with a 1 ms delay after each code:
A first stage gain of 4.166 with a second stage gain of 50 gives a
total gain of 208.3. This gain has a maximum tolerance of 2.5%.
• Set the output offset code (Parameter 10) to 0100 0000 and
the output offset to 1.260 V when VDD = 5 V and VSS = 0 V.
This output offset has a maximum tolerance of 0.8%:
1000 0000 0001 01 10 10 0100 0000 0111 1111 1110.
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110.
To permanently set the output offset to a nominal value of
1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to
have the value 0100 0000 assigned. If one fuse needs to be
blown, use the following code:
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Because a relatively
large current is needed to blow a fuse, only one fuse can be
reliably blown at a time. Therefore, a given parameter value may
need several 38-bit words to allow reliable programming. A
5.25 V (±0.25 V) supply is required when blowing fuses to
minimize the on resistance of the internal MOS switches that
blow the fuse. The power supply voltage must not exceed the
absolute maximum rating and must be able to deliver 250 mA
of current.
1000 0000 0001 10 10 10 0100 0000 0111 1111 1110.
Finally, to blow the master fuse to deactivate the simulation
mode and prevent further programming, use code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110.
There are 20 programmable fuses. Because each fuse requires
1 ms to blow, and each serial word can be loaded in 2.3 ms,
the maximum time needed to program the fuses can be as
low as 66 ms.
Rev. B | Page 21 of 27
AD8556
Data Sheet
Parity Error Detection
The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18).
The output of Cell EOR18 is the DAT_SUM signal. If there is
an even number of 1s in the 18-bit word, DAT_SUM = 0; and if
there is an odd number of 1s in the 18-bit word, DAT_SUM = 1.
See Table 13 for examples.
A parity check is used to determine whether the programmed
data of an AD8556 is valid, or whether data corruption has
occurred in the nonvolatile memory. Figure 50 shows the
schematic implemented in the AD8556.
VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.
After the second stage gain, first stage gain, and output offset
are programmed, compute DAT_SUM and set the parity bit
equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should
not be blown in order for the PFUSE signal to be 0. If DAT_SUM is
1, the parity fuse should be blown to set the PFUSE signal to 1.
The code to blow the parity fuse is:
The function of the 2-input AND gate (Cell AND2) is to ignore
the output of the parity circuit (PAR_SUM signal) when the
master fuse is not blown. PARITY_ERROR is set to 0 when
MFUSE = 0. In the simulation mode, for example, parity check
is disabled. After the master fuse is blown, that is, after the
AD8556 is programmed, the output from the parity circuit
(PAR_SUM signal) is fed to PARITY_ERROR. When
PARITY_ERROR is 0, the AD8556 behaves as a programmed
amplifier. When PARITY_ERROR is 1, a parity error is detected,
and VOUT is connected to VSS.
1000 0000 0001 10 11 10 0000 0100 01111111 1110.
After setting the parity bit, the master fuse can be blown to
prevent further programming, using the code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110.
Signal PAR_SUM is the output of the 2-input exclusive-OR gate
(Cell EOR2). After the master fuse is blown, set PARITY_ERROR
to PAR_SUM. As previously mentioned, the AD8556 behaves as
a programmed amplifier when PARITY_ERROR = 0 (no parity
error). On the other hand, VOUT is connected to VSS when a
parity error is detected, that is, when PARITY_ERROR = 1.
I0
VA0
VA1
VA2
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VC0
VC1
VC2
VC3
VC4
VC5
VC6
VC7
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
DAT_SUM
PFUSE
EOR18 OUT
PAR_SUM
IN1
IN2
EOR2
I1
OUT
IN1
IN2
AND2
I2
OUT
PARITY_ERROR
MFUSE
Figure 50. Functional Circuit of AD8556 Parity Check
Table 13. Examples of DAT_SUM
Second Stage Gain Code
First Stage Gain Code
Output Offset Code
0000 0000
1000 0000
1000 0001
0000 0000
0000 0000
0000 0000
1000 0000
1111 1111
Number of Bits with 1
DAT_SUM
000
000
000
000
000
001
001
111
000 0000
0
1
2
1
2
1
3
18
0
1
0
1
0
1
1
0
000 0000
000 0000
000 0001
100 0001
000 0000
000 0001
111 1111
Rev. B | Page 22 of 27
Data Sheet
AD8556
Read Mode
It is theoretically possible, though very unlikely, for a fuse
to be incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance, neither low nor high, and a voltage
of approximately 1.5 V could be developed across the fuse.
Therefore, the OTP cell could output Logic 0 or Logic 1, depending
on temperature, supply voltage, and other variables.
The values stored by the polysilicon fuses can be sent to the
FILT/DIGOUT pin to verify correct programming. Normally,
the FILT/DIGOUT pin is only connected to the second gain stage
output via RF. During read mode, however, the FILT/DIGOUT pin
is also connected to the output of a shift register to allow the
polysilicon fuse contents to be read. Because VOUT is a buffered
version of FILT/DIGOUT, VOUT also outputs a digital signal
during read mode.
To detect this undesirable situation, the sense current can be
lowered by a factor of 4 using a specific code. The voltage
developed across the fuse would then change from 1.5 V to
0.38 V, and the output of the OTP would be Logic 0 instead of
the expected Logic 1 from a blown fuse. Fuses blown correctly
would still output Logic 1. In this way, fuses blown incorrectly
can be detected. Another specific code would return the sense
current to the normal (larger) value. The sense current cannot
be permanently programmed to the low value. When the AD8556
is powered up, the sense current defaults to the high value.
Read mode is entered by setting Field 1 to 11 and selecting the
desired parameter in Field 2. Field 4 is ignored. The parameter
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift
register contents to the FILT/DIGOUT pin, allowing the 8‒bit
parameter value to be read after seven additional pulses; shifting
occurs on the falling edge of DIGIN. An eighth pulse at DIGIN
disconnects FILT/DIGOUT from the shift register and terminates
the read mode. If a parameter value is less than eight bits long,
the MSBs of the shift register are padded with 0s.
The low sense current code is:
1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110.
The normal (high) sense current code is:
For example, to read the second stage gain, this code is used:
1000 0000 0001 11 00 10 0000 0000 0111 1111 1110. Because
the second stage gain parameter value is only three bits long,
the FILT/DIGOUT pin has a value of 0 when this code is
entered, and remains 0 during four additional pulses at DIGIN.
The fifth, sixth, and seventh pulses at DIGIN return the 3-bit
value at FILT/DIGOUT, the seventh pulse returns the LSB. An
eighth pulse at DIGIN terminates the read mode.
1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110.
Programming Procedure
For reliable fuse programming, it is imperative to follow the
programming procedure requirements, especially the proper
supply voltage during programming.
1. When programming the AD8556, the temperature of the
device must be between 10°C and 40°C.
2. Set VDD and VSS to the desired values in the application.
Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown
in Table 6, Table 7, Equation 2, and Equation 3; use the
codes corresponding to these values as a starting point.
However, because actual parameter values for given codes
vary from device to device, some fine tuning is necessary
for the best possible accuracy.
Sense Current
A sense current is sent across each polysilicon fuse to determine
whether it has been blown. When the voltage across the fuse is
less than approximately 1.5 V, the fuse is considered not blown,
and Logic 0 is output from the OTP cell. When the voltage across
the fuse is greater than approximately 1.5 V, the fuse is considered
blown, and Logic 1 is output.
When the AD8556 is manufactured, all fuses have a low
resistance. When a sense current is sent through the fuse, a
voltage less than 0.1 V is developed across the fuse, which is
much lower than 1.5 V; therefore, Logic 0 is output from the
OTP cell. When a fuse is electrically blown, it should have a
very high resistance. When the sense current is applied to the
blown fuse, the voltage across the fuse should be larger than
1.5 V; therefore, Logic 1 is output from the OTP cell.
One way to choose these values is to set the output offset
to an approximate value, such as Code 128 for midsupply,
to allow the required gain to be determined. Then set the
second stage gain so the minimum first stage gain (Code 0)
gives a lower gain than required, and the maximum first
stage gain (Code 127) gives a higher gain than required.
After choosing the second stage gain, the first stage gain
can be chosen to fine tune the total gain. Finally, the output
offset can be adjusted to give the desired value. After
determining the desired codes for second stage gain,
first stage gain, and output offset, the device is ready for
permanent programming.
Rev. B | Page 23 of 27
AD8556
Data Sheet
Important: Once a programming attempt is made for any
4. Measure the resulting gain, GB. GB should be within
fuse, there should be no further attempt to blow that fuse.
If a fuse does not program to the expected state, discard
the unit. The expected incidence rate of attempted but
unblown fuses is very small when following the proper
programming procedure and conditions.
3% of GA.
5. Calculate the first stage gain error (in relative terms)
E
G1 = GB/GA − 1.
6. Calculate the error (in the number of the first stage gain
codes) CEG1 = EG1/0.00370.
3. Set VSS to 0 V and VDD to 5.25 V (±0.25 V). Power
supplies should be capable of supplying 250 mA at the
required voltage and properly bypassed as described
in the Programming Mode section. Use program mode to
permanently enter the desired codes for the first stage gain,
second stage gain, and output offset. Blow the parity bit
fuse if necessary (see Parity Error Detection section). Blow
the master fuse to allow the AD8556 to read data from the
fuses and to prevent further programming.
7. Set the first stage gain code to CG1 − CEG1
.
8. Measure the gain, GC. GC should be closer to GA than to GB.
9. Calculate the error (in relative terms) EG2 = GC/GA − 1.
10. Calculate the error (in the number of the first stage gain
codes) CEG2 = EG2/0.00370.
11. Set the first stage gain code to CG1 − CEG1 − CEG2. The
resulting gain should be within one code of GA.
4. Set VDD and VSS to the desired values in the application.
Use read mode with low sense current followed by high
sense current to verify programmed codes.
Finally, determine the desired output offset:
5. Measure gain and offset to verify correct functionality.
1. Determine the desired output offset OA (using the
measurements obtained from the simulation).
Determining Optimal Gain and Offset Codes
2. Use Equation 2 to set the output offset code CO1 such that
the output offset is nominally OA.
First, determine the desired gain:
1. Determine the desired gain, GA (using the measurements
obtained from the simulation).
3. Measure the output offset, OB. OB should be within
3% of OA.
2. Use Table 7 to determine G2, the second stage gain, such
that (4.00 × 1.04) < (GA/G2) < (6.4/1.04). This ensures the
first and last codes for the first stage gain are not used,
thereby allowing enough first stage gain codes within each
second stage gain range to adjust for the 3% accuracy.
4. Calculate the error (in relative terms) EO1 = OB/OA − 1.
5. Calculate the error (in the number of the output offset
codes) CEO1 = EO1/0.00392.
6. Set the output offset code to CO1 − CEO1
.
Next, set the second stage gain:
7. Measure the output offset, OC. OC should be closer to OA
than to OB.
1. Use the simulation mode to set the second stage gain to G2.
2. Set the output offset to allow the AD8556 gain to be
measured, for example, use Code 128 to set it to
midsupply.
8. Calculate the error (in relative terms) EO2 = OC/OA − 1.
9. Calculate the error (in the number of the output offset
codes) CEO2 = EO2/0.00392.
3. Use Table 6 or Equation 1 to set the first stage gain code
CG1, so the first stage gain is nominally GA/G2.
10. Set the output offset code to CO1 − CEO1 − CEO2. The
resulting offset should be within one code of OA.
Rev. B | Page 24 of 27
Data Sheet
AD8556
EMI/RFI PERFORMANCE
Real-world applications must work with ever increasing
radio/magnetic frequency interference (RFI and EMI). In
situations where signal strength is low and transmission lines
are long, instrumentation amplifiers, such as the AD8556, are
needed to extract weak, small differential signals riding on
common-mode noise and interference. Additionally, wires and
PCB traces act as antennas and pick up high frequency EMI
signals. The longer the wire, the larger the voltage it picks up.
The amount of voltages picked up is dependent on the impedances
at the wires, as well as the EMI frequency. These high frequency
voltages are then passed into the in-amp through its pins. All
instrumentation amplifiers can rectify high frequency out-of-
band signals. Unfortunately, the EMI/RFI rectification occurs
because amplifiers do not have any significant common-mode
rejection above 100 kHz. Once these high frequency signals are
rectified, they appear as dc offset errors at the output.
The AD8556 features internal EMI filters on the VNEG, VPOS,
FILT, and VCLAMP pins. These built-in filters on the pins limit
the interference bandwidth and provide good RFI suppression
without reducing performance within the pass-band of the
instrumentation amplifier. A functional diagram of the
AD8556 along with its EMI/RFI filters is shown in Figure 51.
The AD8556 has built-in filters on its inputs, VCLAMP, and
filter pins. The first-order, low-pass filters inside the AD8556
are useful to reject high frequency EMI signals picked up by
wires and PCB traces outside the AD8556. The most sensitive
pin of any amplifier to RFI/EMI signal is the noninverting pin.
Signals present at this pin appear as common-mode signals and
create problems.
The filters built at the input of the AD8556 have two different
bandwidths: common mode and differential mode. The common-
mode bandwidth defines what a common-mode RF signal sees
between the two inputs tied together and ground. The EMI
filters placed on the input pins of the AD8556 reject EMI/RFI
suppressions that appear as common-mode signals.
DIGIN
VDD
VCLAMP
1
2
EMI
FILTER
+IN
A5
3
OUT
VSS
DAC
LOGIC
–IN
VDD
EMI
FILTER
1
2
+IN
A1
R5
P4
R7
VPOS
3
OUT
–IN
R2
VSS
P2
VDD
VDD
EMI
FILTER
R3
R1
1
2
RF
+IN
–IN
3
EMI
FILTER
1
A3
+IN
A4
OUT
VSS
3
V
OUT
P1
OUT
2
VDD
–IN
1
2
VSS
+IN
A2
R4
R5
3
OUT
EMI
FILTER
VNEG
–IN
P3
VSS
AD8556
VSS
FILT/DIGOUT
Figure 51. Block Diagram Showing EMI/RFI Built-In Filters
Rev. B | Page 25 of 27
AD8556
Data Sheet
To show the benefits that the AD8556 brings to new applications
where EMI/RFI signals are present, a part was programmed
with a gain of 70 and a dc offset of 2.5 V to produce a VOUT of
0 V. A test circuit like that shown in Figure 52 was used.
The differential bandwidth defines the frequency response of
the filters with a differential signal applied between the two
inputs, VPOS (that is, +IN ) and VNEG (that is, –IN). Figure 54
shows the circuit used to test for AD8556 EMI/RFI susceptibility.
The part is programmed as previously stated during the
common-mode testing.
Figure 52 simulates the presence of a noisy common-mode
signal, and Figure 53 shows the response dc values at VOUT.
+2.5V
–2.5V
+2.5V
–2.5V
U2
U3
1
2
3
4
8
7
6
5
VCC
VEE
1
2
3
4
8
7
6
5
VCC
VEE
VOUT
VOUT
FILTER
VOUT
FILTER
VOUT
DATA
–IN
VCLAMP
+IN
+2.5V
V2
VCLAMP
DATA
–IN
+2.5V
+IN
AD8556
AD8556
+
–
200mV p-p
Figure 54. Test Circuit to Show AD8556 Performance Exposed to
Differential Mode RFI/EMI Signals
V3
+
–
VARIABLE
The response of AD8556 to EMI/RFI differential signals is
shown in Figure 55.
Figure 52. Test Circuit to Show AD8556 Performance
Exposed to Common-Mode RFI/EMI Signals
600
100
80
60
40
20
0
400
200
AD8556
0
–200
–400
NON-ENHANCED FOR EMI
–600
–800
–1000
NON-ENHANCED PART
–1200
AD8556 (ENHANCED PART FOR EMI)
–1400
0
200
400
600
800
1000
1200
–20
FREQUENCY (MHz)
0
200
400
600
800
1000
1200
FREQUENCY (MHz)
Figure 55. Response of AD8556 to EMI/RFI Differential Signals
Figure 53. DC Offset Values at VOUT Caused by Frequency Seep of Input
To make a board robust against EMI, the leads at VPOS and
VNEG should be as similar as possible. In this way, any EMI
received by the VPOS and VNEG pins will be similar (that is, a
common-mode input), and rejected by the AD8556. Furthermore,
additional filtering at the VPOS and VNEG pins should give a
better reduction of unwanted behavior compared with filtering
at the other pins.
Rev. B | Page 26 of 27
Data Sheet
AD8556
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
1
4
12
EXPOSED
PAD
2.40
2.35 SQ
2.30
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3.
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +140°C
−40°C to +140°C
−40°C to +140°C
−40°C to +140°C
−40°C to +140°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Package Option
AD8556ARZ
R-8
R-8
R-8
CP-16-20
CP-16-20
AD8556ARZ-REEL
AD8556ARZ-REEL7
AD8556ACPZ-R2
AD8556ACPZ-REEL7
1 Z = RoHS Compliant Part.
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05448-0-2/15(B)
Rev. B | Page 27 of 27
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