AD8560 [ADI]
16 V Rail-to-Rail Buffer Amplifier; 16 V轨到轨缓冲放大器
| 型号： | AD8560 |
| 厂家： | 
ADI |
| 描述： | 16 V Rail-to-Rail Buffer Amplifier |
| 文件： | 总12页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 V Rail-to-Rail
Buffer Amplifier
a
AD8560
FEATURES
BLOCK DIAGRAM
Single-Supply Operation: 4.5 V to 16 V
Dual-Supply Capability from ؎2.25 V to ؎8 V
Input Capability Beyond the Rails
Rail-to-Rail Output Swing
Continuous Output Current: 35 mA
Peak Output Current: 250 mA
Offset Voltage: 10 mV Max
Slew Rate: 8 V/s
V+
IN A
1
2
3
4
5
10
9
OUT A
OUT B
OUT C
OUT D
OUT E
IN B
IN C
IN D
8
Stable with 1 F Loads
Supply Current
7
APPLICATIONS
6
IN E
LCD Reference Drivers
Portable Electronics
Communications Equipment
GND
16-Lead LFCSP
(CP Suffix)
GENERAL DESCRIPTION
The AD8560 is a low cost, five-channel, single-supply buffer
amplifier with rail-to-rail input and output capability. The AD8560
is optimized for LCD monitor applications.
These LCD buffers have high slew rates, a 35 mA continuous
output drive, and high capacitive load drive capability. They have
wide supply range and offset voltages below 10 mV.
PIN 1
12 OUT A
11 OUT B
10 OUT C
IN A 1
IN B 2
IN C 3
IN D 4
INDICATOR
AD8560
TOP VIEW
9
OUT D
The AD8560 is specified over the –40°C to +85°C temperature
range. They are available on tape and reel in a 16-lead LFCSP.
NC = NO CONNECT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD8560–SPECIFICATIONS
(4.5 V ≤ V ≤ 16 V, VCM = VS/2, TA = 25ꢀC, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
S
Parameter
Symbol Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
VOS
2
5
80
10
mV
µV/°C
nA
∆VOS/∆T –40°C ≤ TA ≤ +85°C
IB
Input Bias Current
600
–40°C ≤ TA ≤ +85°C
800
VS + 0.5
nA
V
kΩ
pF
Input Voltage Range
Input Impedance
Input Capacitance
–0.5
ZIN
CIN
400
1
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
IL = 100 µA
VS – 0.005
15.95
V
V
V
V
VS = 16 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
IL = 100 µA
15.85
15.75
4.2
4.38
4.1
V
Output Voltage Low
VOL
5
42
mV
mV
mV
mV
mV
mA
mA
VS = 16 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
–40°C ≤ TA ≤ +85°C
150
250
300
400
95
Continuous Output Current
Peak Output Current
IOUT
IPK
35
250
VS = 16 V
TRANSFER CHARACTERISTICS
Gain
AVCL
NL
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ, VO = 0.5 to (VS – 0.5 V)
0.995
0.995
0.9985
0.9980
0.01
1.005
1.005
V/V
V/V
%
Gain Linearity
POWER SUPPLY
Supply Voltage
Power Supply Rejection Ratio
VS
PSRR
4.5
70
16
V
VS = 4 V to 17 V
–40°C ≤ TA ≤ +85°C
VO = VS/2, No Load
–40°C ≤ TA ≤ +85°C
90
780
dB
µA
µA
Supply Current/Amplifier
ISY
1,000
1,200
DYNAMIC PERFORMANCE
Slew Rate
Bandwidth
Phase Margin
Channel Separation
SR
BW
Øo
RL = 10 kΩ, CL = 200 pF
–3 dB, RL = 10 kΩ, CL = 10 pF
RL = 10 kΩ, CL = 10 pF
4.5
8
8
65
75
V/µs
MHz
Degrees
dB
NOISE PERFORMANCE
Voltage Noise Density
en
en
in
f = 1 kHz
f = 10 kHz
f = 10 kHz
27
25
0.8
nV/√Hz
nV/√Hz
pA/√Hz
Current Noise Density
Specifications subject to change without notice.
REV. 0
–2–
AD8560
ABSOLUTE MAXIMUM RATINGS*
1
2
Package Type
ꢁJA
ꢁJC
ꢂJB
Unit
°C/W
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VS + 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
ESD Tolerance (HBM) . . . . . . . . . . . . . . . . . . . . . . . . .1.5 kV
ESD Tolerance (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
16-Lead LFCSP (CP)
35
13
NOTES
1θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered
onto a circuit board for surface-mount packages.
JB is applied for calculating the junction temperature by reference to the board
2
⌿
temperature.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8560ACP
–40°C to +85°C
16-Lead LFCSP
CP-16
Available in reels only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8560 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8560–Typical Performance Characteristics
100
0
ꢃ50
T
= 25ꢀC
V
= V /2
S
A
CM
90
80
70
60
50
40
30
20
10
0
4.5V <V < 16V
S
V
= 16V
S
ꢃ100
ꢃ150
ꢃ200
ꢃ250
ꢃ300
ꢃ350
V
= 4.5V
S
0
3
6
9
12
+25
TEMPERATURE – ꢀC
+85
ꢃ12
ꢃ9
ꢃ6
ꢃ3
ꢃ40
INPUT OFFSETVOLTAGE – mV
TPC 1. Input Offset Voltage Distribution
TPC 4. Input Bias Current vs. Temperature
300
5
4
3
2
1
4.5V <V < 16V
S
250
200
150
100
50
V
= 4.5V
S
0
ꢃ1
ꢃ2
ꢃ3
ꢃ4
ꢃ5
V
= 16V
S
0
+25
TEMPERATURE – ꢀC
+85
ꢃ40
0
10
20
30
40
50
60
70
80
90
100
TCVOS – ꢄV/ꢀC
TPC 2. Input Offset Voltage Drift Distribution
TPC 5. Input Offset Current vs. Temperature
15.96
15.95
15.94
15.93
15.92
15.91
15.90
15.89
15.88
15.87
15.86
4.46
4.45
4.44
4.43
4.42
4.41
4.40
4.39
4.38
4.37
4.36
0
I
= 5mA
LOAD
V
= V /2
S
CM
V
= 16V
S
ꢃ0.25
ꢃ0.50
ꢃ0.75
ꢃ1.00
ꢃ1.25
ꢃ1.50
V
= 16V
S
V
= 4.5V
S
V
= 4.5V
S
+25
TEMPERATURE – ꢀC
+85
+25
TEMPERATURE – ꢀC
+85
ꢃ40
ꢃ40
TPC 3. Input Offset Voltage vs. Temperature
TPC 6. Output Voltage Swing vs. Temperature
REV. 0
–4–
AD8560
150
135
120
105
90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
I
= 5mA
LOAD
V
= V /2
S
CM
V
= 16V
S
V
= 4.5V
S
75
60
45
V
= 16V
S
V
= 4.5V
30
S
15
0
+25
TEMPERATURE – ꢀC
+85
ꢃ40
+25
TEMPERATURE – ꢀC
+85
ꢃ40
TPC 7. Output Voltage Swing vs. Temperature
TPC 10. Supply Current/Amplifier vs. Temperature
0.9999
8
R
C
= 10kꢅ
= 200pF
L
L
4.5V < V < 16V
S
V
= 0.5V TO 15V
OUT
7
6
5
4
3
2
1
V
= 16V
S
R
= 2kꢅ
L
V
= 4.5V
S
0.9997
R
= 600ꢅ
L
0.9995
+25
TEMPERATURE – ꢀC
+85
+25
TEMPERATURE – ꢀC
+85
ꢃ40
ꢃ40
TPC 8. Voltage Gain vs. Temperature
TPC 11. Slew Rate vs. Temperature
1k
1.1
T
A
V
= 25ꢀC
= 1
A
T
= 25ꢀC
A
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
=V /2
O
S
100
10
V
= 4.5V
S
V
= 16V
S
1
0.1
0
2
4
6
8
10
12
14
16
18
0.001
0.01
0.1
1
10
100
LOAD CURRENT – mA
SUPPLYVOLTAGE –V
TPC 12. Supply Current/Amplifier vs. Supply Voltage
TPC 9. Output Voltage to Supply Rail vs. Load Current
REV. 0
–5–
AD8560
10
18
16
14
12
10
8
5
1kꢅ
T
V
A
= 25ꢀC
= 16V
= 1
A
10kꢅ
0
S
V
ꢃ5
ꢃ10
ꢃ15
ꢃ20
R
= 10kꢅ
T
V
V
C
= 25ꢀC
= 8V
L
A
DISTORTION < 1%
S
= 50mV rms
= 40pF
= 1
IN
560ꢅ
L
V
A
150ꢅ
6
ꢃ25
ꢃ30
ꢃ35
ꢃ40
4
2
0
100k
1M
10M
FREQUENCY – Hz
100M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 13. Frequency Response vs. Resistive Loading
TPC 16. Closed-Loop Output Swing vs. Frequency
25
160
T
= 25ꢀC
A
T
V
= 25ꢀC
= 16V
A
V
= 8V
20
15
S
140
120
100
80
S
V
= 50mV rms
= 10kꢅ
= 1
IN
R
A
L
V
10
5
50pF
+PSRR
0
60
ꢃ5
ꢃ10
ꢃ15
ꢃ20
40
ꢃPSRR
20
100pF
1040pF
540pF
0
ꢃ20
ꢃ40
ꢃ25
100k
1M
10M
FREQUENCY – Hz
100M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 14. Frequency Response vs. Capacitive Loading
TPC 17. Power Supply Rejection Ratio vs. Frequency
500
450
400
350
160
T
V
= 25ꢀC
= 4.5V
A
140
120
100
80
S
+PSRR
V
= 4.5V
S
300
250
200
150
100
50
ꢃPSRR
60
40
20
0
V
S
= 16V
ꢃ20
ꢃ40
0
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 15. Closed-Loop Output Impedance vs. Frequency
TPC 18. Power Supply Rejection Ratio vs. Frequency
REV. 0
–6–
AD8560
1,000
100
10
100
90
80
70
60
50
40
30
20
10
0
T
4.5V
= 25ꢀC
A
T
V
V
V
A
R
= 25ꢀC
= 4.5V
A
V
16V
S
S
= 2.25V
CM
= 100mV p-p
= 1
IN
V
L
= 10kꢅ
ꢃOS
+OS
1
10
100
FREQUENCY – Hz
1k
10k
10
100
LOAD CAPACITANCE – pF
1k
TPC 22. Small Signal Overshoot vs. Load Capacitance
TPC 19. Voltage Noise Density vs. Frequency
20
15
T
A
= 25ꢀC
= ꢆ8V
= 10kꢅ
T
= 25ꢀC
A
0
ꢃ20
V
4.5V <V < 16V
S
S
10
5
R
L
ꢃ40
ꢃ60
OVERSHOOT SETTLINGTO 0.1%
0
ꢃ80
ꢃ100
ꢃ120
ꢃ140
ꢃ160
ꢃ180
ꢃ5
ꢃ10
ꢃ15
UNDERSHOOT SETTLINGTO 0.1%
0
0.5
1.0
1.5
2.0
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
SETTLINGTIME – ꢄs
TPC 20. Channel Separation vs. Frequency
TPC 23. Settling Time vs. Step Size
100
90
80
70
60
50
40
30
20
10
0
0
0
0
0
0
0
0
0
0
T
V
V
V
A
= 25ꢀC
= 16V
= 8V
T
V
A
R
C
= 25ꢀC
= 16V
= 1
= 10kꢅ
= 300pF
A
A
S
S
CM
V
L
L
= 100mV p-p
IN
= 1
= 10kꢅ
V
L
R
ꢃOS
+OS
10
100
LOAD CAPACITANCE – pF
1k
0
0
0
0
0
0
0
0
0
TIME – 2ꢄs/DIV
TPC 24. Large Signal Transient Response
TPC 21. Small Signal Overshoot vs. Load Capacitance
REV. 0
–7–
AD8560
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
V
A
R
C
= 25ꢀC
= 4.5V
= 1
= 10kꢅ
= 300pF
T
V
A
R
C
= 25ꢀC
= 4.5V
= 1
= 10kꢅ
= 100pF
A
A
S
S
V
L
L
V
L
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME – 2ꢄs/DIV
TIME – 1ꢄs/DIV
TPC 25. Large Signal Transient Response
TPC 27. Small Signal Transient Response
0
0
T
V
A
R
C
= 25ꢀC
= 16V
= 1
= 10kꢅ
= 100pF
A
T
V
A
R
= 25ꢀC
= 16V
= 1
A
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S
V
L
L
V
L
= 10kꢅ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME – 1ꢄs/DIV
TIME – 40ꢄs/DIV
TPC 26. Small Signal Transient Response
TPC 28. No Phase Reversal
REV. 0
–8–
AD8560
APPLICATIONS
Short Circuit Output Conditions
Theory of Operation
The buffer family does not have internal short circuit protection
circuitry. As a precautionary measure, do not short the output
directly to the positive power supply or to the ground.
These buffers are designed to drive large capacitive loads in LCD
applications. Each has a high output current drive and rail-to-
rail input/output operation and can be powered from a single 16
V supply. They are also intended for other applications where low
distortion and high output current drive are needed.
It is not recommended to operate the AD8560 with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using the following equation:
Input Overvoltage Protection
As with any semiconductor device, whenever the input exceeds
either supply voltage, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged depending on the voltage level and the magnitude
of the fault current. When the input voltage exceeds either supply
by more than 0.6 V, internal pin junctions will allow current to
flow from the input to the supplies.
VS
35mA
RX
≥
For a 5 V single-supply operation, RX should have a minimum
value of 143 Ω.
Recommended Land Pattern for the AD8560
Figure 2 is a recommended land pattern for the AD8560 PCB
design. The recommended thermal pad size for the PCB design
matches the dimensions of the exposed pad on the bottom of
the package. The solder mask design for improved thermal pad
contact to the exposed pad and reliability uses a stencil pattern
for approximately 85% solder coverage. A minimum clearance
of 0.25 mm is maintained on the PCB between the outer edges
of the thermal pad and the inner edges of the pattern for the
land to avoid shorting. For better thermal performance, thermal
vias should also be used. Since the AD8560 is relatively a low
power part, just soldering the exposed package pad to the PCB
thermal pad should provide sufficient electrical performance.
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the buffers where the input exceeds the supply by more than 0.6 V,
a series external resistor should be added. The size of the resistor
can be calculated by using the maximum overvoltage divided by
5 mA. This resistance should be placed in series with the input
exposed to an overvoltage.
Output Phase Reversal
The buffer family is immune to phase reversal. Although the device’s
output will not change phase, large currents due to input overvoltage
could damage the device. In applications where the possibility exists
of an input voltage exceeding the supply voltage, overvoltage protec-
tion should be used as described in the previous section.
SYMM C
L
0.28 ꢇ 0.75
TYP 16 PL
Total Harmonic Distortion (THD+N)
The buffer family features low total harmonic distortion. The total
harmonic distortion plus noise for the buffer over the entire
supply range is below 0.08%. When the device is powered from
a 16 V supply, the THD + N stays below 0.03%. Figure 1 shows
the AD8560’s THD + N versus the frequency performance.
0.9
0.4
2.1 1.95
0.65
SYMM C
L
10
0.05
0.1
1
0.875
0.20
0.25
0.1
V
= ꢆ2.5V
S
SOLDER MASK
BOARD METALLIZATION
V
= ꢆ8V
S
Figure 2. 16-Lead 4 x 4 Land Pattern
0.01
20
1k
FREQUENCY – Hz
10k
30k
100
Figure 1. THD + N vs. Frequency
REV. 0
–9–
AD8560
OUTLINE DIMENSIONS
16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm ꢀ 4 mm Body
(CP-16)
Dimensions shown in millimeters
4.0
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
16
12
1
PIN 1
INDICATOR
0.65 BSC
TOP
VIEW
3.75
BSC SQ
BOTTOM
VIEW
0.75
0.60
0.50
2.25
2.10 SQ
1.95
4
9
8
5
1.95 BSC
0.80 MAX
12ꢁ MAX
0.65 NOM
0.05 MAX
0.02 NOM
1.00
0.90
0.80
0.35
0.28
0.25
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
REV. 0
–10–
–11–
–12–
相关型号：
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