AD8591 [ADI]
CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifiers with Shutdown; 具有关断功能的CMOS单电源轨到轨输入/输出运算放大器
| 型号： | AD8591 |
| 厂家： | 
ADI |
| 描述： | CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifiers with Shutdown |
| 文件： | 总15页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Single Supply
Rail-to-Rail Input/Output
Operational Amplifiers with Shutdown
a
AD8591/AD8592/AD8594
PIN CONFIGURATIONS
6-Lead SOT
FEATURES
Single Supply Operation: +2.5 V to +6 V
High Output Current: ؎250 mA
Extremely Low Shutdown Supply Current: 100 nA
Low Supply Current: 750 A/Amp
Wide Bandwidth: 3 MHz
(RT Suffix)
1
2
3
6
5
4
V؉
OUT A
V؊
AD8591
SD
؉IN A
؊IN A
Slew Rate: 5 V/s
No Phase Reversal
Very Low Input Bias Current
High Impedance Outputs When in Shutdown Mode
Unity Gain Stable
10-Lead SOIC
(RM Suffix)
V+
1
2
10
9
OUT A
–IN A
APPLICATIONS
Mobile Communication Handset Audio
PC Audio
PCMCIA/Modem Line Driving
Battery Powered Instrumentation
Data Acquisition
OUT B
AD8592
(Not to Scale)
+IN A
V–
3
4
8
7
6
–IN B
+IN B
SDB
SDA
5
ASIC Input or Output Amplifier
LCD Display Reference Level Driver
16-Lead Narrow SOIC
(R Suffix)
GENERAL DESCRIPTION
The AD8591, AD8592 and AD8594 are single, dual and quad
rail-to-rail input and output single supply amplifiers featuring
250 mA output drive current and a power saving shutdown
mode. The AD8592 includes an independent shutdown func-
tion for each amplifier. When both amplifiers are in shutdown
mode the total supply current is reduced to less than 1 µA. The
AD8591 and AD8594 include a single master shutdown func-
tion that reduces total supply current to less than 1 µA. All
amplifier outputs are in a high impedance state when in shut-
down mode.
1
2
3
4
5
6
7
8
16
15
14
13
12
OUT A
؊IN A
؉IN A
V؉
OUT D
؊IN D
؉IN D
AD8594
TOP VIEW
(Not to Scale)
V؊
؉IN B
؉IN C
11 ؊IN C
؊IN B
OUT B
NC
10
9
OUT C
SD
NC = NO CONNECT
These amplifiers have very low input bias currents, making them
suitable for integrators and diode amplification. Outputs are
stable with virtually any capacitive load. Supply current is less
than 750 µA per amplifier in active mode.
16-Lead TSSOP
(RU Suffix)
1
OUT A
؊IN A
؉IN A
OUT D
؊IN D
؉IN D
V؊
+IN C
؊IN C
16
Applications for these amplifiers include audio amplification for
portable computers, portable phone headsets, sound ports, sound
cards and set-top boxes. The AD859x family is capable of driving
heavy capacitive loads such as LCD panel reference levels.
V؉
؉IN B
؊IN B
AD8594
OUT B
NC
OUT C
SD
8
9
The ability to swing rail-to-rail at both the input and output
enables designers to buffer CMOS DACs, ASICs and other
wide output swing devices in single supply systems.
NC = NO CONNECT
The AD8591, AD8592 and AD8594 are specified over the indus-
trial (–40°C to +85°C) temperature range. The AD8591, single,
is available in the tiny 6-lead SOT package. The AD8592, dual, is
available in the 10-lead µSOIC surface mount package. The
AD8594, quad, is available in 16-lead narrow SOIC and 16-lead
TSSOP packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD8591/AD8592/AD8594–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = +2.7 V, VCM = +1.35 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
25
30
50
60
25
mV
mV
pA
pA
pA
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
Input Bias Current
Input Offset Current
5
1
IOS
30
pA
Input Voltage Range
0
38
+2.7
V
dB
V/mV
µV/°C
fA/°C
fA/°C
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
CMRR
AVO
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
VCM = 0 V to +2.7 V
RL = 2 kΩ , VO = +0.3 V to +2.4 V
45
25
20
50
20
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 10 mA
–40°C to +85°C
IL = 10 mA
–40°C to +85°C
+2.55 +2.61
V
V
mV
mV
mA
Ω
+2.5
Output Voltage Low
60
100
125
Output Current
Open-Loop Impedance
IOUT
ZOUT
±250
60
f = 1 MHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = +2.5 V to +6 V
VO = 0 V
–40°C < TA < +85°C
All Amplifiers Shut Down
–40°C < TA < +85°C
45
55
dB
1
1.25
1
mA
mA
µA
Supply Current Shutdown Mode
ISD
0.1
1
µA
ISD1
ISD2
Amplifier 1 Shut Down (AD8592)
Amplifier 2 Shut Down (AD8592)
1.4
1.4
mA
mA
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
VINH
VINL
IIN
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
+1.6
V
V
µA
+0.5
1
Logic Input Current
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
Φo
CS
RL = 2 kΩ
To 0.01%
3.5
1.4
2.2
67
V/µs
µs
MHz
Degrees
dB
Channel Separation
f = 1 kHz, RL = 2 kΩ
65
NOISE PERFORMANCE
Voltage Noise Density
en
in
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Current Noise Density
Specifications subject to change without notice.
–2–
REV. A
AD8591/AD8592/AD8594
ELECTRICAL CHARACTERISTICS (VS = +5.0 V, VCM = +2.5 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
2
5
1
25
30
50
60
25
30
+5
mV
mV
pA
pA
pA
pA
V
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
Input Bias Current
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
CMRR
AVO
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
VCM = 0 V to +5 V
RL = 2 kΩ , VO = +0.5 V to +4.5 V
–40°C < TA < +85°C
38
15
47
30
20
50
20
dB
V/mV
µV/°C
fA/°C
fA/°C
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 10 mA
–40°C to +85°C
IL = 10 mA
–40°C to +85°C
+4.9
+4.85
+4.94
50
V
V
mV
mV
mA
Ω
Output Voltage Low
100
125
Output Current
Open-Loop Impedance
IOUT
ZOUT
±250
40
f = 1 MHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = +2.5 V to +6 V
VO = 0 V
–40°C < TA < +85°C
All Amplifiers Shut Down
–40°C < TA < +85°C
45
55
dB
1.25
1.75
1
mA
mA
µA
Supply Current-Shutdown Mode
ISD
0.1
1
µA
ISD1
ISD2
Amplifier 1 Shut Down (AD8592)
Amplifier 2 Shut Down (AD8592)
1.6
1.6
mA
mA
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
VINH
VINL
IIN
–40°C < TA < +85°C
–40°C < TA < +85°C
–40°C < TA < +85°C
+2.4
V
V
µA
+0.8
1
Logic Input Current
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
Φo
CS
RL = 2 kΩ
1% Distortion
To 0.01%
5
V/µs
kHz
µs
MHz
Degrees
dB
325
1.6
3
70
65
f = 1 kHz, RL = 10 kΩ
NOISE PERFORMANCE
Voltage Noise Density
en
in
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Current Noise Density
Specifications subject to change without notice.
REV. A
–3–
AD8591/AD8592/AD8594
ABSOLUTE MAXIMUM RATINGS1
1
Package Type
JA
Units
JC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit
6-Lead SOT-23 (RT)
10-Lead µSOIC (RM)
16-Lead SOIC (R)
230
200
120
180
92
44
36
35
°C/W
°C/W
°C/W
°C/W
Duration to GND2 . . . . . . . . . . . . Observe Derating Curves
Storage Temperature Range
16-Lead TSSOP (RU)
NOTE
1θJA is specified for worst case conditions, i.e., θJA is specified for device in socket
R, RT, RM, RU Packages . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
for surface mount packages.
AD8591/AD8592/AD8594 . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
ORDERING GUIDE
R, RT, RM, RU Packages . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . .+300°C
Temperature
Range
Package
Description
Package
Option
Model
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
AD8591ART –40°C to +85°C 6-Lead SOT-23
AD8592ARM –40°C to +85°C 10-Lead µSOIC
–40°C to +85°C 16-Lead SOIC
AD8594ARU –40°C to +85°C 16-Lead TSSOP RU-16
RT-6
RM-10
R-16A
AD8594AR
2For supplies less than ±5 V the differential input voltage is limited to the supplies.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8591/AD8592/AD8594 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Typical Performance Characteristics
10k
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1k
V
= +5V
S
V
= +2.7V
S
T
= +25؇C
T
= +25؇C
A
A
1k
100
10
100
10
SOURCE
SINK
SOURCE
V
= +5V
S
SINK
1
1
V
= +2.7V
60
S
0.1
0.01
0.1
0.01
0.1
1
10
100
1k
0.1
1
10
100
1k
؊40 ؊20
0
20
40
80
100
LOAD CURRENT – mA
LOAD CURRENT – mA
TEMPERATURE – ؇C
Figure 1. Output Voltage to Supply
Rail vs. Load Current
Figure 2. Output Voltage to Supply
Rail vs. Load Current
Figure 3. Supply Current per
Amplifier vs. Temperature
–4–
REV. A
AD8591/AD8592/AD8594
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
؊2
؊3
؊4
؊5
؊6
؊7
؊8
8
V
= +5V
S
= +2.5V
V
V
= +2.7V, +5V
= V /2
T
= +25؇C
S
A
V
CM
CM
S
7
6
5
4
3
2
0.75
1.25
1.75
2.25
2.75
3
؊50 ؊35 ؊15
5
25
45
65
85
؊50 ؊35 ؊15
5
25
45
65
85
SUPPLY VOLTAGE – ؎Volts
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 4. Supply Current per
Amplifier vs. Supply Voltage
Figure 5. Input Offset Voltage vs.
Temperature
Figure 6. Input Bias Current vs.
Temperature
4
3
2
1
0
8
80
V
V
= +2.7V, +5V
S
V
R
= +2.7V
= NO LOAD
= +25؇C
S
= V /2
V
= +5V
CM
S
S
7
6
5
4
3
2
1
60
40
20
0
45
L
T
= +25؇C
A
T
A
90
135
180
؊1
؊2
؊50 ؊35 ؊15
5
25
45
65
85
0
1
2
3
4
5
1k
10k
100k
1M
10M
100M
TEMPERATURE – ؇C
COMMON-MODE VOLTAGE – Volts
FREQUENCY – Hz
Figure 7. Input Offset Current vs.
Temperature
Figure 8. Input Bias Current vs.
Common-Mode Voltage
Figure 9. Open-Loop Gain and Phase
vs. Frequency
5
5
80
V
= +2.7V
= 2k⍀
S
V
R
= +5V
= NO LOAD
= +25؇C
V
= +5V
S
S
R
T
L
60
40
20
0
45
L
R
= 2k⍀
L
= +25؇C
= 2.5V p-p
4
3
2
1
0
4
3
2
1
0
A
T
A
T
= +25؇C
= 4.9V p-p
A
V
IN
V
90
IN
135
180
1k
10k
100k
1M
10M
1k
10k
100k
FREQUENCY – Hz
1M
10M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 10. Open-Loop Gain and
Phase vs. Frequency
Figure 11. Closed-Loop Output
Voltage Swing vs. Frequency
Figure 12. Closed-Loop Output
Voltage Swing vs. Frequency
REV. A
–5–
AD8591/AD8592/AD8594
110
100
200
140
120
100
80
V
= +5V
S
V
T
= +2.5V
V
T
= +5V
S
S
180
160
140
120
100
80
T
= +25؇C
A
= +25؇C
= +25؇C
A
A
90
80
A
= 10
60
40
V
+PSRR
؊PSRR
20
70
60
50
A
= 1
60
0
V
40
؊20
20
؊40
؊60
0
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Closed-Loop Output
Impedance vs. Frequency
Figure 14. Common-Mode Rejection
Ratio vs. Frequency
Figure 15. Power Supply Rejection
Ratio vs. Frequency
60
60
140
V
= +5V
S
V
= +2.5V
= 2k⍀
V
= +5V
S
S
120
100
80
T
= +25؇C
A
R
R
= 2k⍀
= +25؇C
L
L
50
40
30
20
10
0
50
40
30
20
10
0
T
= +25؇C
T
A
A
+OS
؊PSRR
60
40
؊OS
؊OS
+PSRR
+OS
20
0
؊20
؊40
؊60
10
100
1k
10k
10
100
1k
10k
100
1k
10k
100k
1M
10M
CAPACITANCE – pF
CAPACITANCE – pF
FREQUENCY – Hz
Figure 16. Power Supply Rejection
Ratio vs. Frequency
Figure 17. Small Signal Overshoot
vs. Load Capacitance
Figure 18. Small Signal Overshoot
vs. Load Capacitance
V
= ؎1.35V
= 1
S
A
R
T
V
L
100
90
= 2k⍀
= +25؇C
A
0V
0V
V
= ؎2.5V
= ؎50mV
= 1
V
= ؎1.35V
= ؎50mV
= 1
S
S
V
V
IN
IN
A
R
C
T
A
R
C
T
10
V
L
L
V
L
L
= 2k⍀
= 2k⍀
0%
= 300pF
= +25؇C
= 300pF
= +25؇C
500mV
500ns
A
A
500 ns/DIV
500 ns/DIV
Figure 19. Small Signal Transient
Response
Figure 20. Small Signal Transient
Response
Figure 21. Large Signal Transient
Response
–6–
REV. A
AD8591/AD8592/AD8594
1
V
= +5V
S
V
= ؎2.5V
= 1
1V
10s
S
T
= +25؇C
A
A
R
T
V
L
100
90
100
90
= 2k⍀
= +25؇C
A
0.1
V
= ؎2.5V
= 1
S
10
10
A
T
V
0%
0%
= +25؇C
A
1V
500mV
500ns
0.01
1k
10
100
10k
100k
FREQUENCY – Hz
Figure 22. Large Signal Transient
Response
Figure 23. No Phase Reversal
Figure 24. Current Noise Density vs.
Frequency
V
V
T
= +2.7V
S
V
= +5V
V
A
= +5V
= 1000
S
S
= +1.35V
CM
100
90
100
90
A
= 1000
500
400
300
200
100
V
V
= +25؇C
A
T
= +25؇C
T
= +25؇C
A
A
FREQUENCY = 1kHz
FREQUENCY = 10kHz
10
10
0%
0%
MARKER 41V/ Hz
MARKER 25.9 V/ Hz
–12 –10 –8 –6 –4 –2
0
2
4
INPUT OFFSET VOLTAGE – mV
Figure 25. Voltage Noise Density vs.
Frequency
Figure 26. Voltage Noise Density vs.
Frequency
Figure 27. Input Offset Voltage
Distribution
V
V
T
= +5V
S
= +2.5V
CM
500
400
300
200
100
= +25؇C
A
–12 –10 –8 –6 –4 –2
0
2
4
INPUT OFFSET VOLTAGE – mV
Figure 28. Input Offset Voltage
Distribution
REV. A
–7–
AD8591/AD8592/AD8594
AD8591/AD8592/AD8594 APPLICATION SECTION
Theory of Operation
Output Phase Reversal
The AD8591/AD8592/AD8594 are immune to output voltage
phase reversal with an input voltage within the supply voltages
of the device. However, if either of the device’s inputs exceeds
+0.6 V outside of the supply rails, the output could exhibit
phase reversal. This is due to the ESD protection diodes be-
coming forward biased, thus causing the polarity of the input
terminals of the device to switch.
The AD859x family of amplifiers are all CMOS, high output drive,
rail-to-rail input and output single supply amplifiers designed for
low cost and high output current drive. The parts include a power
saving shutdown function making the AD8591/AD8592/AD8594
op amps ideal for portable multimedia and telecom applications.
Figure 29 shows the simplified schematic for an AD8591/AD8592/
AD8594 amplifier. Two input differential pairs, consisting of an
n-channel pair (M1-M2) and a p-channel pair (M3-M4), provide
a rail-to-rail input common-mode range. The outputs of the input
differential pairs are combined in a compound folded-cascode
stage, which drives the input to a second differential pair gain
stage. The outputs of the second gain stage provide the gate volt-
age drive to the rail-to-rail output stage.
The technique recommended in the Input Overvoltage Protection
section should be applied in applications where the possibility of
input voltages exceeding the supply voltages exists.
Output Short Circuit Protection
To achieve high output current drive and rail-to-rail performance,
the outputs of the AD859x family do not have internal short cir-
cuit protection circuitry. Although these amplifiers are designed to
sink or source as much as 250 mA of output current, shorting the
output directly to the positive supply could damage or destroy the
device. To protect the output stage, the maximum output current
should be limited to ±250 mA.
The rail-to-rail output stage consists of M15 and M16, which are
configured in a complementary common-source configuration.
As with any rail-to-rail output amplifier, the gain of the output
stage, and thus the open-loop gain of the amplifier, is dependent
on the load resistance. Also, the maximum output voltage swing
is directly proportional to the load current. The difference be-
tween the maximum output voltage to the supply rails, known as
the dropout voltage, is determined by the AD8591/AD8592/
AD8594 output transistors’ on-channel resistance. The output
dropout voltage is given in Figure 1 and Figure 2.
By placing a resistor in series with the output of the amplifier as
shown in Figure 30, the output current can be limited. The
minimum value for RX can be found from Equation 2.
VSY
250 mA
RX
≥
(2)
For a +5 V single supply application, RX should be at least 20 Ω.
Because RX is inside the feedback loop, VOUT is not affected. The
tradeoff in using RX is a slight reduction in output voltage swing
under heavy output current loads. RX will also increase the effec-
tive output impedance of the amplifier to RO + RX, where RO is
the output impedance of the device.
V+
100A
*
*
*
*
50A
100A
20A
M11
INV
M1
M337
M5
M12
SD
M30
M8
V
B2
+5V
M3
M4
M15
M16
IN–
IN+
R
V
X
OUT
IN
M2
20⍀
AD8592
V
OUT
M6
M7
V
M9
20A
B3
M14
*
INV
Figure 30. Output Short Circuit Protection
Power Dissipation
M340
M13
*
M10
M31
50A
Although the AD859x family of amplifiers are able to provide
load currents of up to 250 mA, proper attention should be
given to not exceeding the maximum junction temperature for
the device. The equation for finding the junction temperature is
given as:
V–
*NOTE: ALL CURRENT SOURCES GO
TO 0 A IN SHUTDOWN MODE
Figure 29. AD8591/AD8592/AD8594 Simplified Schematic
(3)
TJ = PDISS × θJA + TA
Input Voltage Protection
Although not shown on the simplified schematic, ESD protec-
tion diodes are connected from each input to each power supply
rail. These diodes are normally reverse biased, but will turn on
if either input voltage exceeds either supply rail by more than
+0.6 V. Should this condition occur, the input current should
be limited to less than ±5 mA. This can be done by placing a
resistor in series with the input(s). The minimum resistor value
should be:
Where TJ = AD859x junction temperature
P
DISS = AD859x power dissipation
θ
JA = AD859x junction-to-ambient thermal resistance
of the package; and
TA = The ambient temperature of the circuit
VIN, MAX
5 mA
RIN
≥
(1)
–8–
REV. A
AD8591/AD8592/AD8594
In any application, the absolute maximum junction temperature
must be limited to +150°C. If this junction temperature is ex-
ceeded, the device could suffer premature failure. If the output
voltage and output current are in phase, for example, with a
purely resistive load, the power dissipated by the AD859x can
be found as:
50mV
100
90
47nF LOAD
ONLY
PDISS = ILOAD × VSY – VOUT
(4)
(
)
SNUBBER
IN CIRCUIT
10
0%
10s
50mV
Where
I
LOAD = AD859x output load current
V
V
SY = AD859x supply voltage; and
OUT = The output voltage
Figure 33. Snubber Network Reduces Overshoot and
Ringing Caused from Driving Heavy Capacitive Loads
By calculating the power dissipation of the device and using the
thermal resistance value for a given package type, the maximum
allowable ambient temperature for an application can be found
using Equation 3.
The optimum values for the snubber network should be determined
empirically based on the size of the capacitive load. Table I shows a
few sample snubber network values for a given load capacitance.
Capacitive Loading
Table I. Snubber Networks for Large Capacitive Loads
The AD859x exhibits excellent capacitive load driving capabilities
and can drive up to 10 nF directly. Although the device is stable
with large capacitive loads, there is a decrease in amplifier band-
width as the capacitive load increases. Figure 31 shows a graph of
the AD8592 unity gain bandwidth under various capacitive loads.
Load Capacitance
(CL)
Snubber Network
(RS, CS)
0.47 nF
4.7 nF
47 nF
300 Ω, 0.1 µF
30 Ω, 1 µF
5 Ω, 1 µF
4
V
R
T
= ؎2.5V
= 1k⍀
S
A PC-98 Compliant Headphone/Speaker Amplifier
3.5
3
L
= +25؇C
Because of its high output current performance and shutdown
feature, the AD8592 makes an excellent amplifier for driving an
audio output jack in a computer application. Figure 34 shows
how the AD8592 can be interfaced with an AC97 codec to drive
A
2.5
2
headphones or speakers.
+5V
1.5
1
+5V
10
V
DD
C1
100F
R4
20⍀
28
35
V
2
3
DD
U1-A
0.5
0
1
NC
4
R2
2k⍀
LEFT
OUT
+5V
R1
5
0.01
0.1
1
10
100
CAPACITIVE LOAD – nF
AD1881
(AC97)
100k⍀
Figure 31. Unity Gain Bandwidth vs. Capacitive Load
When driving heavy capacitive loads directly from the AD859x
output, a snubber network can be used to improve transient
response. This network consists of a series R-C connected from
the amplifier’s output to ground, placing it in parallel with the
capacitive load. The configuration is shown in Figure 32. Al-
though this network will not increase the bandwidth of the am-
plifier, it will significantly reduce the amount of overshoot, as
shown in Figure 33.
6
C2
100F
R5
20⍀
36
RIGHT
OUT
7
8
U1-B
V
SS
9
R3
2k⍀
NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY
U1 = AD8592
Figure 34. A PC-98 Compliant Headphone/Line Out Amplifier
When headphones are plugged into the jack, the normalizing con-
tacts disconnect from the audio contacts. This allows the voltage to
the AD8592 shutdown pins to be pulled up to +5 V, activating the
amplifiers. With no plug in the output jack, the shutdown voltage is
pulled to 100 mV through the R1 and R3 + R5 voltage divider.
This powers the AD8592 down when it is not needed, saving
current from the power supply or battery.
+5V
V
AD8592
OUT
R
V
S
IN
100mV p-p
5⍀
C
C
S
1F
L
47nF
Figure 32. Configuration for Snubber Network to
Compensate for Capacitive Loads
REV. A
–9–
AD8591/AD8592/AD8594
If gain is required from the output amplifier, four additional
resistors should be added as shown in Figure 35. The gain of
the AD8592 can be set as:
A Combined Microphone and Speaker Amplifier for
Cellphone and Portable Headsets
The dual amplifiers in the AD8592 make an efficient design for
interfacing with a headset containing a microphone and speaker.
Figure 36 demonstrates a simple method for constructing an
interface to a codec.
R7
A
V
=
(5)
R6
+5V
R3
100k⍀
R7
20k⍀
+5V
V
V
DD
R1
2.2k⍀
C1
0.1F
R2
10k⍀
+5V
10
+5V
38
35
DD
C1
100F
R4
20⍀
LEFT
10
OUT
2
3
2
3
NC
TO
R6
10k⍀
U1-A
U1-A
CODEC
1
1
NC
4
4
R2
2k⍀
+5V
R1
5
R7
1k⍀
MIC + SPEAKER
JACK
5
+5V
R8
100k⍀
V
REF
100k⍀
27
V
REF
FROM CODEC
6
C2
10F
6
AD1881
(AC97)
7
8
C2
100F
R5
20⍀
R4
10k⍀
U1-B
FROM CODEC
MONO OUT
(OR LEFT OUT)
7
8
9
R6
10k⍀
U1-B
9
R3
2k⍀
36
RIGHT
OUT
U1 = AD8592
(RIGHT OUT)
R5
10k⍀
R6
10k⍀
(OPTIONAL)
V
SS
R7
20k⍀
U1 = AD8592
Figure 36. A Speaker/Mic Headset Amplifier Circuit
R7
R6
NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY
A
=
= +6dB WITH VALUES SHOWN
V
U1-A is used as a microphone preamplifier, where the gain of
the preamplifier is set as R3/R2. R1 is used to bias an electret
microphone and C1 blocks any dc voltages from the amplifier.
U1-B is the speaker amplifier, and its gain is set at R5/R4. To
sum a stereo output, R6 should be added, equal in value to R4.
Figure 35. A PC-98 Compliant Headphone/Line Out
Amplifier With Gain
Input coupling capacitors are not required for either circuit as
the reference voltage is supplied from the AD1881.
Using the same principle as described in the previous section,
the normalizing contact on the microphone/speaker jack can be
used to put the AD8592 into shutdown when the headset is not
plugged in. The AD8592 shutdown inputs can also be con-
trolled with TTL or CMOS compatible logic, allowing micro-
phone or speaker muting if desired.
R4 and R5 help protect the AD8592 output in case the output
jack or headphone wires accidentally get shorted to ground.
The output coupling capacitors C1 and C2 block dc current
from the headphones and create a high-pass filter with a corner
frequency of:
1
An Inexpensive Sample-and-Hold Circuit
f –3 dB
=
(6)
The independent shutdown control of each amplifier in the
AD8592 allows a degree of flexibility in circuit design. One par-
ticular application for which this feature is useful is in designing a
sample-and-hold circuit for data acquisition. Figure 37 shows a
schematic of a simple, yet extremely effective sample-and-hold
circuit using a single AD8592 and one capacitor.
2π C1 R4 + RL
(
)
Where RL is the resistance of the headphones.
8
+5V
SAMPLE
AND HOLD
OUTPUT
9
2
3
10
U1-B
U1-A
+5V
6
1
7
4
C1
1nF
V
IN
5
SAMPLE
CLOCK
U1 = AD8592
Figure 37. An Efficient Sample-and-Hold Circuit
–10–
REV. A
AD8591/AD8592/AD8594
The U1-A amplifier is configured as a unity gain buffer driving a
1 nF capacitor. The input signal is connected to the noninverting
input, while the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows VIN. Once the sample clock goes
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
Single Supply Differential Line Driver
Figure 39 shows a single supply differential line driver circuit that
can drive a 600 Ω load with less than 0.7% distortion from 20 Hz
to 15 kHz with an input signal of 4 V p-p and a single +5 V supply.
The design uses an AD8594 to mimic the performance of a fully
balanced transformer based solution. However, this design occu-
pies much less board space while maintaining low distortion and
can operate down to dc. Like the transformer based design, either
output can be shorted to ground for unbalanced line driver applica-
tions without changing the circuit gain of 1.
The U1-B amplifier is used as a unity gain buffer to prevent load-
ing on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is very little voltage droop from C1
during the Hold period. This circuit can be used with sample
frequencies as high as 500 kHz and as low as below 1 Hz. Even
lower voltage droop can be achieved for very low sample rates
by increasing the value of C1.
R3
10k⍀
C3
47F
R5
50⍀
2
3
1
A2
V
O1
R6
10k⍀
R2
R7
10k⍀
Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface)
10k⍀
+5V
+5V
A1
+5V
Figure 38 illustrates a +5 V transmit/receive telephone line
interface for 600 Ω systems. It allows full duplex transmission of
signals on a transformer-coupled 600 Ω line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the AD8594’s high output
current drive and low dropout voltages, the largest signal avail-
able on a single +5 V supply is approximately 4.5 V p-p into a
600 Ω transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons: (1) It prevents the transmit
signal from interfering with the receive signal and (2) it extracts
the receive signal from the transmission line for amplification by
A4. Amplifier A4’s gain can be adjusted in the same manner as
A1’s to meet the modem’s input signal requirements. Standard
resistor values permit the use of SIP (Single In-line Package)
format resistor arrays. Couple this with the AD8594 16-lead
TSSOP or SOIC footprint, and this circuit offers a compact,
cost effective solution.
2
3
8
10
C1
22F
10
R8
100k⍀
1
R
7
L
A1
7
600⍀
9
V
4
4
IN
C2
1F
R9
100k⍀
R1
R11
10k⍀
R12
10k⍀
10k⍀
A1, A2 = 1/2 AD8592
C4
R10
R14
50⍀
8
47F
10k⍀
R3
R2
9
GAIN =
A2
V
O2
7
R13
10k⍀
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
Figure 39. A Low Noise, Single Supply Differential
Line Driver
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the input’s dc voltage is equal to half of
the supply voltage.
The circuit can also be configured to provide additional gain if
desired. The gain of the circuit is:
VOUT
VIN
R3
R2
P1
A
=
=
Tx GAIN
V
(7)
ADJUST
R2
9.09k⍀
C1
0.1F
TRANSMIT
TxA
Where:
VOUT = VO1 – VO2,
R2 = R7 = R10 = R11 and,
R3 = R6 = R12 = R13
R1
10k⍀
TO TELEPHONE
LINE
2k⍀
R3
360⍀
2
3
1
1:1
A1
R5
5
6.2V
6.2V
Z
SHUTDOWN
+5V
O
10k⍀
600⍀
T1
R6
10k⍀
6
8
7
MIDCOM
671-8005
R7
10k⍀
9
A2
R8
10k⍀
10F
R9
R10
P2
10k⍀
10k⍀
Rx GAIN
ADJUST
R13
10k⍀ 14.3k⍀
R14
5
RECEIVE
RxA
2
3
R11
10k⍀
1
A3
2k⍀
8
7
6
C2
0.1F
R12
10k⍀
9
A4
A1, A2 = 1/2 AD8592
A3, A4 = 1/2 AD8592
Figure 38. A Single Supply Direct Access Arrangement for
PCMCIA Modems
REV. A
–11–
AD8591/AD8592/AD8594
SPICE Model for the AD8591/AD8592/AD8594 Amplifier
The SPICE model for the AD8591/AD8592/AD8594 amplifier is
one of the more realistic computer simulation macro-models
available, providing a high degree of realism with respect to char-
acteristics of the actual amplifier. This model, shown in Listing 1,
is based on typical values for the device and can be downloaded
from Analog Devices’ Internet site at www.analog.com.
A number of secondary characteristics are also accurately por-
trayed in the SPICE model. Flicker noise is accurately modeled
with the 1/f corner frequency set through the KF and AF terms
in the input stage transistors. C1 and C2 are used in the input
section to create secondary poles to achieve an accurate phase
margin characteristic for the model.
The AD8591/AD8592/AD8594 shutdown circuitry is included
in the model. Switches S1 through S7 deactivate the op amp
circuitry in shutdown mode. The logic threshold for the shut-
down circuitry is accurately modeled through the VSWITCH
model parameters near the end of the listing. The active supply
current versus supply voltage is also modeled through the volt-
age-controlled current source GSY.
The model uses a common source output stage to provide rail-
to-rail performance. This allows realistic simulation of open-
loop gain dependency on load resistance as well as maximum
output voltage versus output current. Two differential pairs are
used in the input stage of the model, simulating the rail-to-rail
input stage of the AD8591/AD8592/AD8594 amplifier.
The EOS voltage source establishes the input offset voltage and
is also used to simulate the common-mode rejection power
supply rejection, and input voltage noise characteristics for the
model. In addition, G2, R2 and CF are used to help set the
open-loop gain and gain-bandwidth product of the model.
Characteristics of this model are based on typical values for the
AD8591/AD8592/AD8594 amplifier at +27°C. The model’s
characteristics are optimized specifically at +27°C, and may lose
accuracy at different simulation temperatures.
–12–
REV. A
AD8591/AD8592/AD8594
Listing 1: AD859x SPICE Macro-Model
* AD8592 SPICE Macro-Model Typical Values
* 9/98, Ver. 1
* TAM / ADSC
*
* Copyright 1998 by Analog Devices
*
* Refer to “README.DOC” file for License
* Statement. Use of this
* model indicates your acceptance of the
* terms and provisions in
* the License Statement.
*
* Node Assignments
*
noninverting input
*
|
|
|
|
|
|
1
inverting input
*
|
|
|
|
|
2
positive supply
*
|
|
|
|
negative supply
*
|
|
|
output
|
|
*
shutdown
*
|
.SUBCKT AD8592
99 50 45 80
*
* INPUT STAGE
*
M1
M2
4
6
1 3 3 PIX L=0.8E-6 W=125E-6
7 3 3 PIX L=0.8E-6 W=125E-6
RC1 4 50 4E3
RC2 6 50 4E3
C1
4
6 2E-12
I1 99 8 100E-6
M3 10 1 12 12 NIX L=0.8E-6 W=125E-6
M4 11 7 12 12 NIX L=0.8E-6 W=125E-6
RC3 10 99 4E3
RC4 11 99 4E3
C2 10 11 2E-12
I2 13 50 100E-6
EOS
+1E-3 1 1 1
IOS 2 2.5E-12
V1 99 9 0.9
D1 9 DX
7
2 POLY(3) (21,98) (73,98) (61,0)
1
3
V2 14 50 0.9
D2 14 12 DX
S1
3
8 (82,98) SOPEN
S2 99 8 (98,82) SCLOSE
S3 12 13 (82,98) SOPEN
S4 13 50 (98,82) SCLOSE
*
* CMRR=64dB, ZERO AT 20kHz
*
ECM1 20 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 20 21 79.6E3
CCM1 20 21 100E-12
RCM2 21 98 50
*
* PSRR=80dB, ZERO AT 200Hz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5
REV. A
–13–
AD8591/AD8592/AD8594
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 80
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 POLY(1) (99,50) 20E-6 10E-7
*
* SHUTDOWN SECTION
*
E1 81 98 (80,50) 1
R1 81 82 1E3
C3 82 98 1E-9
*
* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz)
*
VN1 60 0 0
RN1 60 0 16.45E-3
HN 61 0 VN1 30
RN2 61 0 1
*
* GAIN STAGE
*
G2 98 30 POLY(2) (4,6) (10,11) 0 2.19E-5 +2.19E-5
R2 30 98 13E6
CF 45 30 5E-12
S5 30 98 (98,82) SCLOSE
D3 30 31 DX
D4 32 30 DX
V3 99 31 0.6
V4 32 50 0.6
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=0.8E-6 W=16E-3
M6 45 47 50 50 NOX L=0.8E-6 W=16E-3
EG1 99 48 POLY(1) (98,30) 1.06 1
EG2 49 50 POLY(1) (30,98) 1.05 1
RG1 48 46 10E3
RG2 49 47 10E3
S6 46 99 (98,82) SCLOSE
S7 47 50 (98,82) SCLOSE
*
* MODELS
*
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL POX PMOS (LEVEL=2,KP=8E-6,VTO=-1, LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=13.4E-6,VTO=1, LAMBDA=0.067)
.MODEL SOPEN VSWITCH(VON=2.4,VOFF=0.8, RON=10,ROFF=1E9)
.MODEL SCLOSE VSWITCH(VON=-0.8,VOFF=-2.4, RON=10,ROFF=1E9)
.MODEL DX D(IS=1E-14)
.ENDS AD8592
–14–
REV. A
AD8591/AD8592/AD8594
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead SOT
(RT-6)
10-Lead SOIC
(RM-10)
0.124 (3.15)
0.112 (2.84)
0.122 (3.10)
0.106 (2.70)
10
1
6
5
6
1
5
2
4
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
0.124 (3.15)
0.112 (2.84)
0.199 (5.05)
0.187 (4.75)
3
PIN 1
0.037 (0.95) BSC
PIN 1
0.0197 (0.50) BSC
0.075 (1.90)
BSC
0.122 (3.10)
0.110 (2.79)
0.120 (3.05)
0.112 (2.84)
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.038 (0.97)
0.030 (0.76)
0.043 (1.09)
0.037 (0.94)
10؇
0؇
6؇
0؇
0.020 (0.50)
0.010 (0.25)
0.022 (0.55)
0.014 (0.35)
0.059 (0.15)
0.000 (0.00)
SEATING
PLANE
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
0.006 (0.15)
0.002 (0.05)
0.016 (0.41)
0.006 (0.15)
0.022 (0.56)
0.021 (0.53)
0.011 (0.28)
0.003 (0.08)
16-Lead Thin Shrink Small Outline
(RU-16)
16-Lead Narrow Body SO
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
0.201 (5.10)
0.193 (4.90)
16
1
9
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
16
9
8
8
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
1
8°
0°
PIN 1
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8؇
0؇
0.0256 0.0118 (0.30)
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0075 (0.19)
REV. A
–15–
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