AD8652_15 [ADI]
50 MHz, Precision, Low Distortion;
| 型号： | AD8652_15 |
| 厂家： | 
ADI |
| 描述： | 50 MHz, Precision, Low Distortion |
| 文件： | 总20页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz, Precision, Low Distortion,
Low Noise CMOS Amplifiers
Data Sheet
AD8651/AD8652
FEATURES
PIN CONFIGURATIONS
Bandwidth: 50 MHz at 5 V
Low noise: 4.5 nV/√Hz
Offset voltage: 100 μV typical, specified over
entire common-mode range
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
AD8652
OUT B
–IN B
+IN B
AD8651
+
V
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
OUT
NC
–
V
Slew rate: 41 V/μs
–
V
Rail-to-rail input and output swing
Input bias current: 1 pA
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM-8)
Figure 2. 8-Lead MSOP (RM-8)
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC_N packaging
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
+
AD8651
V
AD8652
OUT B
–IN B
+IN B
OUT
NC
TOP VIEW
(Not to Scale)
APPLICATIONS
TOP VIEW
(Not to Scale)
–
V
–
V
Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADCs and DACs
Microwave link interface
Cell phone PA control
Video line drivers
NC = NO CONNECT
Figure 3. 8-Lead SOIC_N (R-8)
Figure 4. 8-Lead SOIC_N (R-8)
Audio
GENERAL DESCRIPTION
The AD865x family features the newest generation of DigiTrim®
in-package trimming. This new generation measures and corrects
the offset over the entire input common-mode range, providing
less distortion from VOS variation than is typical of other rail-to-
rail amplifiers. Offset voltage and CMRR are both specified and
guaranteed over the entire common-mode range as well as over
the extended industrial temperature range.
The AD865x family consists of high precision, low noise, low
distortion, rail-to-rail CMOS operational amplifiers that run
from a single-supply voltage of 2.7 V to 5.5 V.
The AD865x family is made up of rail-to-rail input and output
amplifiers with a gain bandwidth of 50 MHz and a typical
voltage offset of 100 μV across common mode from a 5 V
supply. It also features low noise—4.5 nV/√Hz.
The AD865x family is offered in the narrow 8-lead SOIC
package and the 8-lead MSOP package. The amplifiers are
specified over the extended industrial temperature range
(−40°C to +125°C).
The AD865x family can be used in communications applications,
such as cell phone transmission power control, fiber optic
networking, wireless networking, and video line drivers.
Rev. D
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Technical Support
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AD8651/AD8652
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................5
Typical Performance Characteristics ..............................................6
Applications..................................................................................... 14
Theory of Operation.................................................................. 14
Layout, Grounding, and Bypassing Considerations.............. 15
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
2/14—Rev. C to Rev. D
6/04—Rev. 0 to Rev. A
Change to Figure 18 .............................................................................8
Change to Figure 21 .............................................................................9
Change to Figure 29 .............................................................................10
Change to Figure 30 .............................................................................10
Change to Figure 43 .............................................................................12
Change to Figure 44 .............................................................................12
Change to Figure 47 .............................................................................13
Change to Figure 57 .............................................................................17
Changes to Figure 21........................................................................ 8
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
8/06—Rev. B. to Rev. C
Changes to Figure 1 to Figure 4...................................................... 1
Changes to Figure 7 and Figure 9................................................... 6
Changes to Figure 23........................................................................ 9
Changes to Figure 53...................................................................... 14
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
10/03 Revision 0: Initial Version
9/04—Rev. A to Rev. B
Added AD8652 ....................................................................Universal
Change to General Description....................................................... 1
Changes to Electrical Characteristics ............................................. 3
Changes to Absolute Maximum Ratings........................................ 5
Change to Figure 23 .......................................................................... 9
Change to Figure 26 .......................................................................... 9
Change to Figure 36 ........................................................................ 11
Change to Figure 42 ........................................................................ 12
Change to Figure 49 ........................................................................ 13
Change to Figure 51 ........................................................................ 13
Inserted Figure 52............................................................................ 13
Change to Theory of Operation section....................................... 14
Change to Input Protection section .............................................. 15
Changes to Ordering Guide ........................................................... 20
Rev. D | Page 2 of 20
Data Sheet
AD8651/AD8652
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = 2.7 V, V– = 0 V, V CM = V+/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8651
VOS
0 V ≤ VCM ≤ 2.7 V
100
350
1.4
1.6
300
1.3
μV
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V
0 V ≤ VCM ≤ 2.7 V
mV
mV
μV
AD8652
90
0.4
4
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V
mV
μV/°C
pA
pA
pA
pA
pA
V
Offset Voltage Drift
Input Bias Current
TCVOS
IB
1
10
–40°C ≤ TA ≤ +125°C
600
10
Input Offset Current
IOS
1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
30
600
+2.8
Input Voltage Range
Common-Mode Rejection Ratio
AD8651
VCM
–0.1
CMRR
V+ = 2.7 V, –0.1 V < VCM < +2.8 V
75
95
dB
dB
dB
dB
dB
dB
dB
dB
–40°C ≤ TA ≤ +85°C, –0.1 V < VCM < +2.8 V
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V
V+ = 2.7 V, –0.1 V < VCM < +2.8 V
70
88
65
85
AD8652
77
95
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V
RL = 1 kΩ, 200 mV < VO < 2.5 V
73
90
Large Signal Voltage Gain
AVO
100
100
95
115
114
108
RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C
RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
VOH
VOL
ISC
IL = 250 μA, –40°C ≤ TA ≤ +125°C
IL = 250 μA, –40°C ≤ TA ≤ +125°C
Sourcing
2.67
V
30
mV
mA
mA
mA
80
80
40
Sinking
Output Current
IO
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V, VCM = 0 V
–40°C ≤ TA ≤ +125°C
76
74
94
93
dB
dB
Supply Current
AD8651
IO = 0
9
12
mA
mA
mA
mA
–40°C ≤ TA ≤ +125°C
IO = 0
14.5
19.5
22.5
AD8652
17.5
–40°C ≤ TA ≤ +125°C
INPUT CAPACITANCE
Differential
CIN
6
9
pF
pF
Common Mode
DYNAMIC PERFORMANCE
Slew Rate
SR
G = 1, RL = 10 kΩ
41
V/μs
MHz
μs
Gain Bandwidth Product
Settling Time, 0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Voltage Noise Density
GBP
G = 1
50
G = 1, 2 V step
VIN × G = 1.48 V+
0.2
0.1
μs
THD + N
G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p
0.0006
%
en
in
f = 10 kHz
f = 100 kHz
f = 10 kHz
5
nV/√Hz
nV/√Hz
fA/√Hz
4.5
4
Current Noise Density
Rev. D | Page 3 of 20
AD8651/AD8652
Data Sheet
V+ = 5 V, V – = 0 V, V CM = V+/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8651
VOS
0 V ≤ VCM ≤ 5 V
100
350
1.4
1.7
300
1.4
μV
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V
0 V ≤ VCM ≤ 5 V
mV
mV
μV
AD8652
90
0.4
4
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V
mV
μV/°C
pA
pA
pA
pA
pA
pA
V
Offset Voltage Drift
Input Bias Current
TCVOS
IB
1
10
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
30
600
10
Input Offset Current
IOS
1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
30
600
+5.1
Input Voltage Range
Common-Mode Rejection Ratio
AD8651
VCM
–0.1
CMRR
0.1 V < VCM < 5.1 V
80
75
70
84
76
100
98
95
95
dB
dB
dB
dB
dB
dB
dB
dB
–40°C ≤ TA ≤ +85°C, 0.1 V < VCM < 5.1 V
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V
0.1 V < VCM < 5.1 V
94
90
AD8652
100
95
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V
RL = 1 kΩ, 200 mV < VO < 4.8 V
Large Signal Voltage Gain
AVO
115
114
111
RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C
RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
VOH
VOL
ISC
IL = 250 µA, –40°C ≤ TA ≤ +125°C
IL = 250 µA, –40°C ≤ TA ≤ +125°C
Sourcing
4.97
V
30
mV
mA
mA
mA
80
80
40
Sinking
Output Current
IO
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V, VCM = 0 V
–40°C ≤ TA ≤ +125°C
76
74
94
93
dB
dB
Supply Current
AD8651
IO = 0
9.5
14.0
15
mA
mA
mA
mA
–40°C ≤ TA ≤ +125°C
IO = 0
AD8652
17.5
20.0
23.5
–40°C ≤ TA ≤ +125°C
INPUT CAPACITANCE
Differential
CIN
6
9
pF
pF
Common Mode
DYNAMIC PERFORMANCE
Slew Rate
SR
G = 1, RL = 10 kΩ
41
V/µs
MHz
μs
Gain Bandwidth Product
Settling Time, 0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Voltage Noise Density
GBP
G = 1
50
G = 1, 2 V step
VIN × G = 1.2 V+
0.2
0.1
μs
THD + N
G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p
0.0006
%
en
in
f = 10 kHz
f = 100 kHz
f = 10 kHz
5
nV/√Hz
nV/√Hz
fA/√Hz
4.5
4
Current Noise Density
Rev. D | Page 4 of 20
Data Sheet
AD8651/AD8652
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3.
ESD CAUTION
Parameter
Rating
Supply Voltage
6.0 V
Input Voltage
GND to VS + 0.3 V
6.0 V
Indefinite
4000 V
Differential Input Voltage
Output Short-Circuit Duration to GND
Electrostatic Discharge (HBM)
Storage Temperature Range
RM, R Package
Operating Temperature Range
Junction Temperature Range
RM, R Package
THERMAL RESISTANCE
−65°C to +150°C
−40°C to +125°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
−65°C to +150°C
300°C
Package Type
θJA
θJC
45
43
Unit
°C/W
°C/W
Lead Temperature (Soldering, 10 sec)
8-Lead MSOP (RM)
8-Lead SOIC_N (R)
210
158
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 5 of 20
AD8651/AD8652
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
60
100
80
60
40
20
V
= 5V
V
= ±2.5V
S
S
V
= 0V
CM
50
40
30
20
10
0
0
–20
0
1
2
3
4
5
6
140
6
COMMON-MODE VOLTAGE (V)
V
(µV)
OS
Figure 5. Input Offset Voltage Distribution
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
300
500
400
300
200
100
0
V
= ±2.5V
V
V
= ±2.5V
S
S
= 0V
CM
200
100
0
–100
–200
–300
–50
0
50
100
150
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Input Offset Voltage vs. Temperature
Figure 9. Input Bias Current vs. Temperature
60
50
40
30
20
10
V
V
= ±2.5V
S
= 0V
CM
T
: –40°C TO +125°C
A
8
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
TCV (µV/°C)
OS
SUPPLY VOLTAGE (V)
Figure 7. TCVOS Distribution
Figure 10. Supply Current vs. Supply Voltage
Rev. D | Page 6 of 20
Data Sheet
AD8651/AD8652
12
11
10
9
2.50
V
= 5V
= 250µA
V
= ±2.5V
S
S
I
L
2.00
1.50
1.00
8
0.50
0
7
6
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Supply Current vs. Temperature
Figure 14. Output Voltage Swing Low vs. Temperature
500
400
300
200
100
80
60
40
20
0
V
= ±2.5V
V
= ±2.5V
S
S
V
OH
V
OL
100
0
0
20
40
60
80
100
10
100
1k
10k
100k
1M
10M
CURRENT LOAD (mA)
FREQUENCY (Hz)
Figure 12. Output Voltage to Supply Rail vs. Load Current
Figure 15. CMRR vs. Frequency
4.997
110
105
100
95
V
S
= ±2.5V
V
= 5V
= 250µA
S
I
L
4.996
4.995
4.994
4.993
4.992
4.991
4.990
90
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Output Voltage Swing High vs. Temperature
Figure 16. CMRR vs. Temperature
Rev. D | Page 7 of 20
AD8651/AD8652
Data Sheet
100
97
94
91
88
100
V
= ±2.5V
S
10
85
82
1
10
–50
0
50
100
150
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 17. CMRR vs. Temperature
Figure 20. Voltage Noise Density vs. Frequency
100
40
30
20
V
= ±2.5V
V = ±2.5V
S
S
80
60
40
20
0
+PSRR
–PSRR
10
0
1
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. PSRR vs. Frequency
Figure 21. Current Noise Density vs. Frequency
100
95
90
85
80
V
V
= ±2.5V
S
V
= ±2.5V
S
= 6.4V
IN
V
IN
V
OUT
0
–50
0
50
100
150
TIME (200µs/DIV)
TEMPERATURE (°C)
Figure 19. PSRR vs. Temperature
Figure 22. No Phase Reversal
Rev. D | Page 8 of 20
Data Sheet
AD8651/AD8652
140
0
60
40
20
V
R
C
= ±2.5V
= 1MΩ
= 47pF
S
V
= ±2.5V
S
L
L
120
G = 100
100
80
60
40
20
–45
G = 10
G = 1
–90
0
–20
–40
–135
–180
0
–20
10
100
1k
10k
100k
1M
10M
100M
5k
50k
500k
5M
50M
300M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Open-Loop Gain and Phase vs. Frequency
Figure 26. Closed-Loop Gain vs. Frequency
117
6
5
4
V
R
= ±2.5V
= 1kΩ
S
L
116
115
V
= 5V
S
3
2
114
V
= 2.7V
S
113
112
1
0
100k
1M
10M
FREQUENCY (Hz)
100M
–50
0
50
100
150
TEMPERATURE (°C)
Figure 24. Open-Loop Gain vs. Temperature
Figure 27. Maximum Output Swing vs. Frequency
140
130
V
C
A
= ±2.5V
= 47pF
= 1
S
V
= ±2.5V
S
L
V
I
I
= 250µA
= 2.5mA
L
L
120
110
100
90
I
= 4.2mA
L
80
70
60
0
50
100
150
200
250
TIME (100µs/DIV)
OUTPUT VOLTAGE SWING FROM THE RAILS (mV)
Figure 25. Open-Loop Gain vs. Output Voltage Swing
Figure 28. Large Signal Response
Rev. D | Page 9 of 20
AD8651/AD8652
Data Sheet
V
V
A
= ±2.5V
= 200mV
= 1
S
V
V
= ±2.5V
S
IN
= 200mV
IN
V
GAIN = –15
0V
OUTPUT
–2.5V
200mV
0V
INPUT
TIME (10µs/DIV)
TIME (200ns/DIV)
Figure 29. Small Signal Response
Figure 32. Positive Overload Recovery Time
30
25
20
15
10
40
30
20
V = ±2.5V
S
V
V
A
= ±2.5V
S
= 200mV
= 1
IN
V
–OS
GAIN = 10
+OS
GAIN = 1
10
0
5
0
GAIN = 100
0
10
20
30
40
50
60
70
10
100
1k
FREQUENCY (Hz)
10k
100k
CAPACITANCE (pF)
Figure 30. Small Signal Overshoot vs. Load Capacitance
Figure 33. Output Impedance vs. Frequency
60
50
40
30
20
V
V
= ±2.5V
V
S
= ±1.35V
= 0V
S
2.5V
= 200mV
V
IN
CM
GAIN = –15
0V
0V
–200mV
10
0
TIME (200ns/DIV)
V
(µV)
OS
Figure 31. Negative Overload Recovery Time
Figure 34. Input Offset Voltage Distribution
Rev. D | Page 10 of 20
Data Sheet
AD8651/AD8652
300
500
400
300
200
V
= ±1.35V
V
V
= ±1.35V
S
S
= 0V
CM
200
100
0
V
OH
V
–100
OL
100
0
–200
–300
–50
0
50
100
150
0
20
40
60
80
100
TEMPERATURE (°C)
CURRENT LOAD (mA)
Figure 35. Input Offset Voltage vs. Temperature
Figure 38. Output Voltage to Supply Rail vs. Load Current
80
60
40
20
2.697
V
S
= 2.7V
V
= 2.7V
= 250µA
S
I
L
2.696
2.695
2.694
2.693
2.692
2.691
2.690
0
–20
0
1
2
3
–50
0
50
100
150
INPUT COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 36. Input Offset Voltage vs. Common-Mode Voltage
Figure 39. Output Voltage Swing High vs. Temperature
11
3.00
2.50
2.00
1.50
1.00
V
= ±1.35V
V
= 2.7V
S
S
I
= 250µA
L
10
9
8
7
0.50
0
6
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. Supply Current vs. Temperature
Figure 40. Output Voltage Swing Low vs. Temperature
Rev. D | Page 11 of 20
AD8651/AD8652
Data Sheet
30
25
20
15
10
5
V
A
= ±1.35V
= 1
V
V
= ±1.35V
= 200mV
S
S
V
IN
–OS
+OS
0
0
10
20
30
40
50
60
70
TIME (200µs/DIV)
CAPACITANCE (pF)
Figure 41. No Phase Reversal
Figure 44. Small Signal Overshoot vs. Load Capacitance
V
C
A
= ±1.35V
= 47pF
= 1
V
V
= ±1.35V
S
S
= 200mV
L
V
IN
GAIN = –10
1.35V
0V
0V
–200mV
TIME (100µs/DIV)
TIME (200ns/DIV)
Figure 42. Large Signal Response
Figure 45. Negative Overload Recovery Time
V
V
C
A
= ±1.35V
= 200mV
= 47pF
= 1
S
V
V
= ±1.35V
= 200mV
S
IN
IN
L
V
GAIN = –10
0V
–1.35V
200mV
0V
TIME (200ns/DIV)
TIME (10µs/DIV)
Figure 43. Small Signal Response
Figure 46. Positive Overload Recovery Time
Rev. D | Page 12 of 20
Data Sheet
AD8651/AD8652
100
80
60
40
20
0
120
118
116
114
V
= ±1.35V
V
R
= ±1.35V
= 1kΩ
S
S
L
112
110
108
10
100
1k
10k
100k
1M
10M
–50
0
50
100
150
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 47. CMRR vs. Frequency
Figure 50. Open-Loop Gain vs. Temperature
60
40
20
100
V
= ±1.35V
V
R
C
= ±1.35V
= 1MΩ
= 47pF
S
S
L
L
80
60
40
20
0
G = 100
G = 10
G = 1
+PSRR
–PSRR
0
–20
–40
1
10
100
1k
10k
100k
1M
10M
5k
50k
500k
5M
50M
300M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 48. PSRR vs. Frequency
Figure 51. Closed-Loop Gain vs. Frequency
0
–20
140
120
0
R1
10kΩ
V
= ±1.35V
S
+2.5V
R2
100Ω
V+
V–
V–
V+
V
IN
28mV p-p
100
80
60
40
20
–45
–40
V
OUT
–60
–2.5V
–90
–80
–100
–120
–140
–135
–180
0
V
= ±2.5V
S
–20
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 49. Open-Loop Gain and Phase vs. Frequency
Figure 52. Channel Separation vs. Frequency
Rev. D | Page 13 of 20
AD8651/AD8652
Data Sheet
APPLICATIONS
THEORY OF OPERATION
The NMOS and PMOS input stages are separately trimmed
using DigiTrim to minimize the offset voltage in both differen-
tial pairs. Both NMOS and PMOS input differential pairs are
active in a 500 mV transition region when the input common-
mode voltage is approximately 1.5 V below the positive supply
voltage. A special design technique improves the input offset
voltage in the transition region that traditionally exhibits a
slight VOS variation. As a result, the common-mode rejection
ratio is improved within this transition band. Compared to the
Burr Brown OPA350 amplifier, shown in Figure 53, the
AD865x, shown in Figure 54, exhibits much lower offset voltage
shift across the entire input common-mode range, including the
transition region.
The AD865x family consists of voltage feedback, rail-to-rail
input and output precision CMOS amplifiers that operate from
2.7 V to 5.5 V of power supply voltage. These amplifiers use
Analog Devices, Inc. DigiTrim technology to achieve a higher
degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of Analog
Devices amplifiers, is a method of trimming the offset voltage of
the amplifier after it has been assembled. The advantage of
post-package trimming is that it corrects any offset voltages
caused by the mechanical stresses of assembly.
The AD865x family is available in standard op amp pinouts,
making DigiTrim completely transparent to the user. The input
stage of the amplifiers is a true rail-to-rail architecture, allowing
the input common-mode voltage range of the op amp to extend
to both positive and negative supply rails. The open-loop gain
of the AD865x with a load of 1 kΩ is typically 115 dB.
600
400
200
0
The AD865x can be used in any precision op amp application.
The amplifiers do not exhibit phase reversal for common-mode
voltages within the power supply. With voltage noise of
4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals,
the AD865x is a great choice for high resolution data
acquisition systems. Their low noise, sub-pA input bias current,
precision offset, and high speed make them superb preamps for
fast photodiode applications. The speed and output drive
capabilities of the AD865x also make the amplifiers useful in
video applications.
–200
–400
–600
0
1
2
3
4
5
6
COMMON-MODE VOLTAGE (V)
Figure 53. Input Offset Distribution over Common-Mode
Voltage for the OPA350
Rail-to-Rail Output Stage
The voltage swing of the output stage is rail-to-rail and is
achieved by using an NMOS and PMOS transistor pair con-
nected in a common source configuration. The maximum
output voltage swing is proportional to the output current, and
larger currents will limit how close the output voltage can get to
the proximity of the output voltage to the supply rail. This is a
characteristic of all rail-to-rail output amplifiers. With 40 mA of
output current, the output voltage can reach within 5 mV of the
positive and negative rails. At light loads of >100 kΩ, the output
swings within ~1 mV of the supplies.
600
400
200
0
–200
–400
–600
Rail-to-Rail Input Stage
The input common-mode voltage range of the AD865x extends
to both positive and negative supply voltages. This maximizes
the usable voltage range of the amplifier, an important feature
for single-supply and low voltage applications. This rail-to-rail
input range is achieved by using two input differential pairs, one
NMOS and one PMOS, placed in parallel. The NMOS pair is active
at the upper end of the common-mode voltage range, and the
PMOS pair is active at the lower end of the common-mode range.
0
1
2
3
4
5
6
COMMON-MODE VOLTAGE (V)
Figure 54. Input Offset Distribution over Common-Mode
Input Protection for the AD865x
Rev. D | Page 14 of 20
Data Sheet
AD8651/AD8652
Bypassing schemes are designed to minimize the supply
Input Protection
impedance at all frequencies with a parallel combination of
capacitors of 0.1 µF and 4.7 µF. Chip capacitors of 0.1 µF (X7R
or NPO) are critical and should be as close as possible to the
amplifier package. The 4.7 µF tantalum capacitor is less critical
for high frequency bypassing, and, in most cases, only one is
needed per board at the supply inputs.
As with any semiconductor device, if a condition exists for the
input voltage to exceed the power supply, the device input
overvoltage characteristic must be considered. The inputs of the
AD865x family are protected with ESD diodes to either power
supply. Excess input voltage energizes internal PN junctions in
the AD865x, allowing current to flow from the input to the
supplies. This results in an input stage with picoamps of input
current that can withstand up to 4000 V ESD events (human
body model) with no degradation.
Grounding
A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and, therefore, the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.
Excessive power dissipation through the protection devices
destroys or degrades the performance of any amplifier. Differential
voltages greater than 7 V result in an input current of approximately
(| VCC – VEE | – 0.7 V)/RI, where RI is the resistance in series with
the inputs. For input voltages beyond the positive supply, the
input current is approximately (VIN – VCC – 0.7)/RI. For input
voltages beyond the negative supply, the input current is about
(VIN – VEE + 0.7)/RI. If the inputs of the amplifier sustain
differential voltages greater than 7 V or input voltages beyond
the amplifier power supply, limit the input current to 10 mA by
using an appropriately sized input resistor (RI), as shown in
Figure 55.
The length of the high frequency bypass capacitor leads is
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents also flow from the
supplies, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, intended to be effective at lower
frequencies, the current return path distance is less critical.
(V – V – 0.7V)
(| V – V | – 0.7V)
IN
EE
CC
EE
R >
I
R >
I
30mA
30mA
(V – V + 0.7V)
IN
EE
R >
I
FOR LARGE | V – V
CC EE
|
30mA
+
FOR V BEYOND
IN
SUPPLY VOLTAGES
O
AD865x
–
Leakage Currents
+ V
– V
+
IN
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias current of the AD865x family. Any voltage differential
between the inputs and nearby traces sets up leakage currents
through the PC board insulator, for example 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem).
R
I
Figure 55. Input Protection Method
Overdrive Recovery
Overdrive recovery is defined as the time it takes for the output
of an amplifier to come off the supply rail after an overload signal is
initiated. This is usually tested by placing the amplifier in a closed-
loop gain of 15 with an input square wave of 200 mV p-p while the
amplifier is powered from either 5 V or 3 V. T h e AD865x family
has excellent recovery time from overload conditions (see Figure 31
and Figure 32). The output recovers from the positive supply rail
within 200 ns at all supply voltages. Recovery from the negative rail
is within 100 ns at 5 V supply.
To significantly reduce leakages, put a guard ring (shield)
around the inputs and the input leads that are driven to the
same voltage potential as the inputs. This ensures that there is
no voltage potential between the inputs and the surrounding
area to set up any leakage currents. To be effective, the guard
ring must be driven by a relatively low impedance source and
should completely surround the input leads on all sides, above
and below, using a multilayer board.
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard
ring helps to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, may be necessary in
some instances.
Power supply pins can act as inputs for noise, so care must be
taken that a noise-free, stable dc voltage is applied. The purpose
of bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.
Rev. D | Page 15 of 20
AD8651/AD8652
Data Sheet
Input Capacitance
•
Another way to stabilize an op amp driving a large capacitive
load is to use a snubber network, as shown in Figure 57. Because
there is not any isolation resistor in the signal path, this method
has the significant advantage of not reducing the output swing.
The exact values of RS and CS are derived experimentally. In
Figure 57, an optimum RS and CS combination for a capacitive
load drive ranging from 50 pF to 1 nF was chosen. For this,
RS = 3 Ω and CS = 10 nF were chosen.
Along with bypassing and grounding, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, which in turn increases the amplifier gain, causing
peaking in the frequency response or oscillations. With the
AD865x, additional input damping is required for stability with
capacitive loads greater than 47 pF with direct input to output
feedback (see the Output Capacitance section).
+
V
Output Capacitance
+
+
V
V
When using high speed amplifiers, it is important to consider
the effects of the capacitive loading on amplifier stability.
Capacitive loading interacts with the output impedance of the
amplifier, causing reduction of the BW as well as peaking and
ringing of the frequency response. To reduce the effects of the
capacitive loading and allow higher capacitive loads, there are
two commonly used methods.
OUT
AD865x
R
C
–
S
S
V
–
C
R
L
L
200mV
–
V
Figure 57. Snubber Network
Settling Time
The settling time of an amplifier is defined as the time it takes
for the output to respond to a step change of input and enter
and remain within a defined error band, as measured relative to
the 50% point of the input pulse. This parameter is especially
important in measurements and control circuits where amplifi-
ers are used to buffer A/D inputs or DAC outputs. The design of
the AD865x family combines a high slew rate and a wide gain
bandwidth product to produce an amplifier with very fast
settling time. The AD865x is configured in the noninverting
gain of 1 with a 2 V p-p step applied to its input. The AD865x
family has a settling time of about 130 ns to 0.01% (2 mV). The
output is monitored with a 10×, 10 M, 11.2 pF scope probe.
•
As shown in Figure 56, place a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amplifier output. Heavy capacitive loads can reduce the
phase margin of an amplifier and cause the amplifier
response to peak or become unstable. The AD865x is able
to drive up to 47 pF in a unity gain buffer configuration
without oscillation or external compensation. However, if
an application requires a higher capacitive load drive when
the AD865x is in unity gain, the use of external isolation
networks can be used. The effect produced by this resistor
is to isolate the op amp output from the capacitive load.
The required amount of series resistance has been
THD Readings vs. Common-Mode Voltage
tabulated in Table 5 for different capacitive loads. While
this technique improves the overall capacitive load drive
for the amplifier, its biggest drawback is that it reduces the
output swing of the overall circuit.
Total harmonic distortion of the AD865x family is well below
0.0004% with any load down to 600 Ω. The distortion is a
function of the circuit configuration, the voltage applied, and
the layout, in addition to other factors. The AD865x family
outperforms its competitor for distortion, especially at
frequencies below 20 kHz, as shown in Figure 58.
V
CC
U1
3
2
V
+
IN
+
V
V
R
OUT
S
0.1
AD865x
V
V
= +3.5V/–1.5V
= 2.0V p-p
SY
OUT
–
V
0.05
–
C
R
L
L
0.02
0.01
0
0
0
Figure 56. Driving Large Capacitive Loads
0.005
0.002
0.001
OPA350
Table 5. Optimum Values for Driving Large Capacitive Loads
CL
RS
0.0005
100 pF
500 pF
1.0 nF
50 Ω
35 Ω
25 Ω
AD8651
0.0002
0.0001
20
50
100
500
1k
2k
5k
20k
FREQUENCY (Hz)
Figure 58. Total Harmonic Distortion
Rev. D | Page 16 of 20
Data Sheet
AD8651/AD8652
5V
+3.5V
+
10kΩ
10kΩ
U1
3
2
V
AD865x
–
OUT
+
V
+
V
CC
33Ω
600Ω
47pF
AD865x
IN
1µF
AD7685
–
V
V
–
IN
2.7nF
–1.5V
2V p-p
1kΩ
V
IN
0V TO 5V
= 45kHz
f
IN
Figure 59. THD + N Test Circuit
1kΩ
Figure 61. AD865x Driving a 16-Bit ADC
Driving a 16-Bit ADC
The AD865x family is an excellent choice for driving high
speed, high precision ADCs. The driver amplifier for this type
of application needs low THD + N as well as quick settling time.
Figure 61 shows a complete single-supply data acquisition
solution. The AD865x family drives the AD7685, a 250 kSPS,
16-bit data converter.1
Table 6. Data Acquisition Solution of Figure 60
Parameter
Reading (dB)
THD + N
105.2
SFDR
106.6
2nd Harmonics
3rd Harmonics
107.7
113.6
The AD865x is configured in an inverting gain of 1 with a 5 V
single supply. Input of 45 kHz is applied, and the ADC samples
at 250 kSPS. The results of this solution are listed in Table 6.
The advantage of this circuit is that the amplifier and ADC can
be powered with the same power supply. For the case of
a noninverting gain of 1, the input common-mode voltage
encompasses both supplies.
1 For more information about the AD7685 data converter, go to
http://www.analog.com/Analog_Root/productPage/productHome/0%2C21
21%2CAD7685%2C00.html
0
f
f
= 250kSPS
SAMPLE
= 45kHz
IN
–20
–40
INPUT RANGE = 0V TO 5V
–60
–80
–100
–120
–140
–160
0
10 20
30 40 50 60 70 80 90 100 110 120
FREQUENCY (kHz)
Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC
Rev. D | Page 17 of 20
AD8651/AD8652
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 62. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 18 of 20
Data Sheet
AD8651/AD8652
ORDERING GUIDE
Model1
AD8651ARMZ-REEL
AD8651ARMZ
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
Package Option
Branding
BEA#
BEA#
RM-8
RM-8
R-8
R-8
R-8
AD8651ARZ
AD8651ARZ-REEL
AD8651ARZ-REEL7
AD8652ARMZ
AD8652ARMZ-REEL
AD8652ARZ
RM-8
RM-8
R-8
R-8
R-8
A05
A05
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
AD8652ARZ-REEL
AD8652ARZ-REEL7
1 Z = RoHS compliant part; # denotes lead-free product may be top or bottom marked.
Rev. D | Page 19 of 20
AD8651/AD8652
NOTES
Data Sheet
©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03301-0-2/14(D)
Rev. D | Page 20 of 20
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