AD8657_11 [ADI]
18 V, Precision, Micropower CMOS RRIO Operational Amplifier; 18 V ，精密，微功耗CMOS RRIO运算放大器
| 型号： | AD8657_11 |
| 厂家： | 
ADI |
| 描述： | 18 V, Precision, Micropower CMOS RRIO Operational Amplifier |
| 文件： | 总24页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18 V, Precision, Micropower
CMOS RRIO Operational Amplifier
AD8657
FEATURES
PIN CONFIGURATION
Micropower at high voltage (18 V): 18 μA typical
Low offset voltage: 350 ꢀV maximum
Single-supply operation: 2.7 V to 18 V
Dual-supply operation: 1.35 V to 9 V
Low input bias current: 20 pA
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8657
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead MSOP
Gain bandwidth: 200 kHz
Unity-gain stable
OUT A 1
–IN A 2
+IN A 3
V– 4
8
7
V+
Excellent electromagnetic interference immunity
AD8657
TOP VIEW
(Not to Scale)
OUT B
APPLICATIONS
6 –IN B
5 +IN B
Portable operating systems
Current monitors
NOTES
1. IT IS RECOMMENDED TO CONNECT
THE EXPOSED PAD TO V–.
4 mA to 20 mA loop drivers
Buffer/level shifting
Multipole filters
Figure 2. 8-Lead LFCSP
Remote/wireless sensors
Low power transimpedance amplifiers
GENERAL DESCRIPTION
Table 1. Micropower Op Amps
The AD8657 is a dual, micropower, precision, rail-to-rail
input/output amplifier optimized for low power and wide
operating supply voltage range applications.
Supply Voltage
5 V
12 V to 16 V 36 V
Single
AD8500
ADA4505-1
AD8505
AD8541
AD8603
AD8502
ADA4505-2
AD8506
AD8542
AD8607
AD8504
ADA4505-4
AD8508
AD8544
AD8609
AD8663
The AD8657 operates from 2.7 V up to 18 V with a typical
quiescent supply current of 18 μA. It uses the Analog Devices,
Inc., patented DigiTrim® trimming technique, which achieves
low offset voltage. The AD8657 also has high immunity to
electromagnetic interference.
Dual
AD8667
OP281
OP295
ADA4062-2
The combination of low supply current, low offset voltage, very
low input bias current, wide supply range, and rail-to-rail input
and output makes the AD8657 ideal for current monitoring and
current loops in process and motor control applications. The
combination of precision specifications makes this device ideal
for dc gain and buffering of sensor front ends or high impedance
input sources in wireless or remote sensors or transmitters.
Quad
AD8669
OP481
OP495
ADA4062-4
The AD8657 is specified over the extended industrial tempera-
ture range (−40°C to +125°C) and is available in an 8-lead MSOP
package and an 8-lead LFCSP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD8657
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 17
Input Stage................................................................................... 17
Output Stage................................................................................ 17
Rail to Rail................................................................................... 18
Resistive Load ............................................................................. 18
Comparator Operation.............................................................. 19
EMI Rejection Ratio .................................................................. 20
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—2.7 V Operation ............................ 3
Electrical Characteristics—10 V Operation ............................. 4
Electrical Characteristics—18 V Operation ............................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
4 mA to 20 mA Process Control Current Loop
Transmitter.................................................................................. 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/11—Rev. 0 to Rev. A
Added LFCSP Package Information ........................... Throughout
Added Figure 2, Renumbered Subsequent Figures ...................1
Changes to Table 2, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments; and Dynamic Performance, Phase
Margin Values ................................................................................... 3
Changes to Table 3, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments .................................................................... 4
Changes to Table 4, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments .................................................................... 5
Changes to Thermal Resistance Section and Table 5................... 6
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
1/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8657
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—2.7 V OPERATION
VSY = 2.7 V, V CM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 2.7 V
350
1
2.5
4
10
2.6
20
500
2.7
µV
mV
mV
mV
pA
nA
pA
pA
V
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V; −40°C ≤ TA ≤ +125°C
Input Bias Current
IB
1
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 2.7 V
79
70
63
60
94
75
65
95
dB
dB
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 2.2 V
−40°C ≤ TA ≤ +85°C
Large Signal Voltage Gain
105
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode CINDM
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
2
10
3.5
3.5
CINCM
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
2.69
V
10
mV
mA
Ω
4
20
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
105
70
125
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
SR
ts
GBP
ΦM
CS
RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
RL = 1 MΩ, CL = 10 pF, AV = 1
RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
38
14
170
60
105
90
V/ms
µs
kHz
Degrees
dB
Channel Separation
EMI Rejection Ratio of +IN x
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
6
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
60
56
0.1
Current Noise Density
in
f = 1 kHz
Rev. A | Page 3 of 24
AD8657
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VSY = 10 V, V CM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
VCM = 0 V to 10 V
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
350
9
15
2.6
30
500
10
µV
mV
pA
nA
pA
pA
V
Input Bias Current
2
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 10 V
90
64
105
95
67
105
120
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 9.5 V
−40°C ≤ TA ≤ +85°C
Large Signal Voltage Gain
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
CINDM
CINCM
2
10
3.5
3.5
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
9.98
V
20
mV
mA
Ω
11
15
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
105
70
125
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
SR
ts
GBP
ΦM
CS
RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
RL = 1 MΩ, CL = 10 pF, AV = 1
RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
60
13
200
60
105
90
V/ms
µs
kHz
Degrees
dB
Channel Separation
EMI Rejection Ratio of +IN x
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. A | Page 4 of 24
AD8657
ELECTRICAL CHARACTERISTICS—18 V OPERATION
VSY = 18 V, V CM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 4.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 18 V
350
1.2
2
11
20
2.9
40
500
18
µV
mV
mV
mV
pA
nA
pA
pA
V
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
Input Bias Current
IB
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 18 V
95
83
80
67
110
105
73
110
120
dB
dB
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 17.5 V
−40°C ≤ TA ≤ +85°C
Large Signal Voltage Gain
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
CINDM
CINCM
2
10
3.5
10.5
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
17.97
V
30
mV
mA
Ω
12
15
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
105
70
125
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
SR
ts
GBP
ΦM
CS
RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
RL = 1 MΩ, CL = 10 pF, AV = 1
RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
70
12
200
60
105
90
V/ms
µs
kHz
Degrees
dB
Channel Separation
EMI Rejection Ratio of +IN x
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. A | Page 5 of 24
AD8657
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board. The exposed pad is soldered to
the board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit
Duration to GND
Temperature Range
Storage
Operating
Junction
Lead Temperature
(Soldering, 60 sec)
20.5 V
(V−) − 300 mV to (V+) + 300 mV
10 mA
VSY
Table 5. Thermal Resistance
Indefinite
Package Type
θJA
142
75
θJC
45
12
Unit
°C/W
°C/W
8-Lead MSOP (RM-8)
8-Lead LFCSP (CP-8-11)
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
ESD CAUTION
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 24
AD8657
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
160
160
140
120
100
80
V
V
= 2.7V
= V /2
SY
V
V
= 18V
= V /2
SY
SY
SY
140
120
100
80
CM
CM
60
60
40
40
20
20
0
0
V
(µV)
V
(µV)
OS
OS
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage Distribution
18
16
14
12
10
8
20
18
16
14
12
10
8
V
= 2.7V
V
= 18V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
6
6
4
4
2
2
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TCV (µV/°C)
OS
TCV (µV/°C)
OS
Figure 4. Input Offset Voltage Drift Distribution
Figure 7. Input Offset Voltage Drift Distribution
300
200
100
0
300
200
100
0
V
= 2.7V
V
= 18V
SY
SY
–100
–200
–300
–100
–200
–300
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
Rev. A | Page 7 of 24
AD8657
2.0
4
3
V
= 2.7V
SY
–40°C ≤ T ≤ +85°C
V
= 18V
1.5
SY
–40°C ≤ T ≤ +85°C
A
A
2
1.0
1
0.5
0
0
–1
–2
–3
–4
–0.5
–1.0
–1.5
–2.0
0
0
2
4
6
8
10
(V)
12
14
16
18
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
V
CM
V
CM
Figure 12. Input Offset Voltage vs. Common-Mode Voltage
Figure 9. Input Offset Voltage vs. Common-Mode Voltage
6
2.0
1.5
V
= 2.7V
SY
–40°C ≤ T ≤ +125°C
V
= 18V
SY
–40°C ≤ T ≤ +125°C
4
2
A
A
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2
–4
–6
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
CM
V
CM
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
10000
1000
100
10
10000
1000
100
10
V
= 18V
V
= 2.7V
SY
SY
I
I
+
–
I
I
+
–
B
B
B
B
1
1
0.1
0.1
25
50
75
100
125
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Input Bias Current vs. Temperature
Figure 14. Input Bias Current vs. Temperature
Rev. A | Page 8 of 24
AD8657
4
3
4
3
V
= 2.7V
V
= 18V
SY
SY
2
2
1
1
0
0
125°C
85°C
25°C
125°C
85°C
25°C
–1
–2
–3
–4
–1
–2
–3
–4
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 15. Input Bias Current vs. Common-Mode Voltage
Figure 18. Input Bias Current vs. Common-Mode Voltage
10
1
10
1
V
= 2.7V
V
= 18V
SY
SY
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
100m
10m
1m
100m
10m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current
Figure 19. Output Voltage (VOH) to Supply Rail vs. Load Current
10
10
V
= 2.7V
V
= 18V
SY
SY
1
100m
10m
1
100m
10m
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
1m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 17. Output Voltage (VOL) to Supply Rail vs. Load Current
Figure 20. Output Voltage (VOL) to Supply Rail vs. Load Current
Rev. A | Page 9 of 24
AD8657
2.700
18.000
17.995
17.990
17.985
17.980
17.975
R = 1MΩ
L
R
= 1MΩ
L
2.699
2.698
2.697
R
= 100kΩ
L
R
= 100kΩ
L
2.696
V
= 2.7V
V
= 18V
–25
SY
SY
2.695
–50
–50
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Output Voltage (VOH) vs. Temperature
Figure 24. Output Voltage (VOH) vs. Temperature
12
10
8
12
10
8
V
= 2.7V
V
= 18V
SY
SY
R
= 100kΩ
L
6
6
4
4
R
= 100kΩ
L
2
2
R
= 1MΩ
L
R
= 1MΩ
L
0
–50
0
–50
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Output Voltage (VOL) vs. Temperature
Figure 25. Output Voltage (VOL) vs. Temperature
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= 18V
V
= 2.7V
SY
SY
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
0
0
0
0
3
6
9
12
15
18
0.3
0.6
0.9
1.2
V
1.5
(V)
1.8
2.1
2.4
2.7
V
(V)
CM
CM
Figure 23. Supply Current vs. Common-Mode Voltage
Figure 26. Supply Current vs. Common-Mode Voltage
Rev. A | Page 10 of 24
AD8657
35
30
25
20
15
10
5
60
50
40
30
20
10
0
V
V
= 2.7V
= 18V
SY
SY
–40°C
+25°C
+85°C
+125°C
0
0
3
6
9
12
15
18
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
V
(V)
SY
Figure 27. Supply Current vs. Supply Voltage
Figure 30. Supply Current vs. Temperature
135
90
135
90
60
40
60
40
V
R
= 18V
= 1MΩ
V
R
= 2.7V
SY
SY
= 1MΩ
PHASE
PHASE
L
L
45
45
20
20
GAIN
0
0
0
0
GAIN
–45
–90
–135
–45
–90
–20
–40
–60
–20
–40
–60
C
C
= 10pF
C
C
= 10pF
L
L
L
= 100pF
= 100pF
L
–135
1M
1k
10k
100k
1M
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28. Open-Loop Gain and Phase vs. Frequency
Figure 31. Open-Loop Gain and Phase vs. Frequency
60
40
60
40
V
= 2.7V
V
= 18V
SY
SY
A
= 100
A
= 100
V
V
A
A
= 10
= 1
A
A
= 10
= 1
V
V
V
V
20
20
0
0
–20
–40
–60
–20
–40
–60
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. Closed-Loop Gain vs. Frequency
Figure 29. Closed-Loop Gain vs. Frequency
Rev. A | Page 11 of 24
AD8657
1000
1000
100
10
A
= 100
A = 100
V
V
A
= 10
A = 10
V
V
100
10
A
= 1
A = 1
V
V
V
= 2.7V
V
= 18V
SY
SY
1
1
100
1k
FREQUENCY (Hz)
10k
100k
100
1k
FREQUENCY (Hz)
10k
100k
Figure 33. Output Impedance vs. Frequency
Figure 36. Output Impedance vs. Frequency
140
120
100
80
140
120
100
80
V
V
= 2.7V
= 2.4V
V
V
= 18V
SY
SY
= V /2
SY
CM
CM
60
60
40
40
20
20
0
0
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. CMRR vs. Frequency
Figure 37. CMRR vs. Frequency
100
80
60
40
20
100
80
60
40
20
0
V
= 2.7V
V
= 18V
SY
SY
PSRR+
PSRR–
PSRR+
PSRR–
0
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. PSRR vs. Frequency
Figure 38. PSRR vs. Frequency
Rev. A | Page 12 of 24
AD8657
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
V
R
= 2.7V
= 10mV p-p
= 1MΩ
V
V
R
= 18V
= 10mV p-p
= 1MΩ
SY
IN
SY
IN
OS+
OS–
OS+
OS–
L
L
10
100
CAPACITANCE (pF)
1000
10
100
CAPACITANCE (pF)
1000
Figure 39. Small Signal Overshoot vs. Load Capacitance
Figure 42. Small Signal Overshoot vs. Load Capacitance
V
= ±1.35V
SY
A
R
C
= 1
= 1MΩ
= 100pF
V
L
L
V
= ±9V
= 1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 40. Large Signal Transient Response
Figure 43. Large Signal Transient Response
V
= ±1.35V
= 1
= 1MΩ
= 100pF
SY
V
= ±9V
= 1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
A
R
C
V
L
L
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 41. Small Signal Transient Response
Figure 44. Small Signal Transient Response
Rev. A | Page 13 of 24
AD8657
V
A
R
= ±9V
= –10
= 1MΩ
SY
0
–0.2
–0.4
V
L
INPUT
INPUT
0
–1
–2
V
A
R
= ±1.35
= –10
= 1MΩ
SY
V
L
2
1
0
10
5
OUTPUT
OUTPUT
0
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 45. Positive Overload Recovery
Figure 48. Positive Overload Recovery
V
A
R
= ±9V
= –10
= 1MΩ
SY
0.4
0.2
0
2
1
0
V
L
INPUT
INPUT
OUTPUT
OUTPUT
0
0
V
A
R
= ±1.35V
= –10
= 1MΩ
SY
–1
–2
–5
–10
V
L
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 46. Negative Overload Recovery
Figure 49. Negative Overload Recovery
INPUT
INPUT
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
= 18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
+5mV
0
+5mV
0
ERROR BAND
ERROR BAND
OUTPUT
OUTPUT
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 47. Positive Settling Time to 0.1%
Figure 50. Positive Settling Time to 0.1%
Rev. A | Page 14 of 24
AD8657
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
=18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
INPUT
INPUT
+5mV
0
+5mV
0
OUTPUT
OUTPUT
ERROR BAND
ERROR BAND
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 51. Negative Settling Time to 0.1%
Figure 54. Negative Settling Time to 0.1%
1000
100
10
1000
100
10
V
= 2.7V
V
= 18V
SY
SY
1
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 52. Voltage Noise Density vs. Frequency
Figure 55. Voltage Noise Density vs. Frequency
V
= 2.7V
V
= 18V
SY
SY
TIME (2s/DIV)
TIME (2s/DIV)
Figure 53. 0.1 Hz to 10 Hz Noise
Figure 56. 0.1 Hz to 10 Hz Noise
Rev. A | Page 15 of 24
AD8657
20
18
16
14
12
10
8
3.0
2.5
2.0
1.5
1.0
0.5
V
V
R
= 18V
= 17.9V
= 1MΩ
= 1
V
V
R
= 2.7V
= 2.6V
= 1MΩ
= 1
SY
IN
SY
IN
L
V
L
V
A
A
6
4
2
0
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
100k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 60. Output Swing vs. Frequency
Figure 57. Output Swing vs. Frequency
100
10
1
100
10
V
V
R
A
= 2.7V
= 0.2V rms
= 1MΩ
V
V
R
A
= 18V
= 0.2V rms
= 1MΩ
SY
IN
SY
IN
L
V
L
V
= 1
= 1
1
0.1
0.1
0.01
0.01
10
100
1k
10k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 58. THD + N vs. Frequency
Figure 61. THD + N vs. Frequency
0
–20
0
–20
1MΩ
1MΩ
10kΩ
V
R
A
= 2.7V
= 1MΩ
= –100
V
R
A
= 18V
SY
= 1MΩ
= –100
SY
10kΩ
L
V
L
V
R
L
R
–40
–40
L
V
V
V
V
V
= 1V p-p
= 5V p-p
= 10V p-p
= 15V p-p
= 17V p-p
IN
IN
IN
IN
IN
–60
–60
V
V
V
= 0.5V p-p
= 1.5V p-p
= 2.6V p-p
IN
IN
IN
–80
–80
–100
–120
–100
–120
–140
–140
100
1k
10k
FREQUENCY (Hz)
100
1k
10k
FREQUENCY (Hz)
100k
Figure 59. Channel Separation vs. Frequency
Figure 62. Channel Separation vs. Frequency
Rev. A | Page 16 of 24
AD8657
APPLICATIONS INFORMATION
The AD8657 is a low power, rail-to-rail input and output
precision CMOS amplifier that operates over a wide supply
voltage range of 2.7 V to 18 V. This amplifier uses the Analog
Devices DigiTrim technique to achieve a higher degree of
precision than is available from other CMOS amplifiers. The
DigiTrim technique is a method of trimming the offset voltage
of an amplifier after assembly. The advantage of postpackage
trimming is that it corrects any shifts in offset voltage caused by
mechanical stresses of assembly.
Figure 9, Figure 10, Figure 12, and Figure 13 for typical perfor-
mance data).
Current Source I1 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper rail, I1 is steered
away from the PMOS differential pair through the M5 transistor.
The bias voltage, VB1, controls the point where this transfer occurs.
M5 diverts the tail current into a current mirror consisting of the
M6 and M7 transistors. The output of the current mirror then
drives the NMOS pair. Note that the activation of this current
mirror causes a slight increase in supply current at high common-
mode voltages (see Figure 23 and Figure 26 for more details).
The AD8657 also employs unique input and output stages to
achieve a rail-to-rail input and output range with a very low
supply current.
The AD8657 achieves its high performance by using low voltage
MOS devices for its differential inputs. These low voltage MOS
devices offer excellent noise and bandwidth per unit of current.
Each differential input pair is protected by proprietary regulation
circuitry (not shown in the simplified schematic). The regula-
tion circuitry consists of a combination of active devices that
maintain the proper voltages across the input pairs during normal
operation and passive clamping devices that protect the amplifier
during fast transients. However, these passive clamping devices
begin to forward bias as the common-mode voltage approaches
either power supply rail. This causes an increase in the input
bias current (see Figure 15 and Figure 18).
INPUT STAGE
Figure 63 shows the simplified schematic of the AD8657. The
input stage comprises two differential transistor pairs, an NMOS
pair (M1, M2) and a PMOS pair (M3, M4). The input common-
mode voltage determines which differential pair turns on and is
more active than the other.
The PMOS differential pair is active when the input voltage
approaches and reaches the lower supply rail. The NMOS pair
is needed for input voltages up to and including the upper supply
rail. This topology allows the amplifier to maintain a wide
dynamic input voltage range and to maximize signal swing to
both supply rails.
The input devices are also protected from large differential
input voltages by clamp diodes (D1 and D2). These diodes are
buffered from the inputs with two 10 kΩ resistors (R1 and R2).
The differential diodes turn on whenever the differential voltage
exceeds approximately 600 mV; in this condition, the differential
input resistance drops to 20 kΩ.
For the majority of the input common-mode voltage range, the
PMOS differential pair is active. Differential pairs commonly
exhibit different offset voltages. The handoff from one pair to the
other creates a step-like characteristic that is visible in the VOS vs.
VCM graph (see Figure 5 and Figure 8). This is inherent in all rail-
OUTPUT STAGE
to-rail amplifiers that use the dual differential pair topology.
Therefore, always choose a common-mode voltage that does not
include the region of handoff from one input differential pair to
the other.
The AD8657 features a complementary output stage consisting
of the M16 and M17 transistors. These transistors are configured
in Class AB topology and are biased by the voltage source, VB2.
This topology allows the output voltage to go within millivolts
of the supply rails, achieving a rail-to-rail output swing. The output
voltage is limited by the output impedance of the transistors, which
are low RON MOS devices. The output voltage swing is a function
of the load current and can be estimated using the output voltage to
the supply rail vs. load current diagrams (see Figure 16, Figure 17,
Figure 19, and Figure 20).
Additional steps in the VOS vs. VCM curves are also visible as the
input common-mode voltage approaches the power supply rails.
These changes are a result of the load transistors (M8, M9, M14,
and M15) running out of headroom. As the load transistors are
forced into the triode region of operation, the mismatch of their
drain impedances contributes to the offset voltage of the amplifier.
This problem is exacerbated at high temperatures due to the
decrease in the threshold voltage of the input transistors (see
Rev. A | Page 17 of 24
AD8657
V+
VB1
I1
M8
M9
M5
M10
M11
M3
M4
+IN x
–IN x
M16
M17
R1
R2
D1
D2
VB2
OUT x
M1 M2
M12
M14
M13
M15
M7
M6
V–
Figure 63. Simplified Schematic
Inverting Configuration
RAIL TO RAIL
Figure 65 shows AD8657 in an inverting configuration with
a resistive load, RL, at the output. The actual load seen by the
amplifier is the parallel combination of the feedback resistor,
R2, and load, RL. Having a feedback resistor of 1 kΩ and a load
of 1 MΩ results in an equivalent load resistance of 999 Ω at the
output. In this condition, the AD8657 is incapable of driving
such a heavy load; therefore, its performance degrades greatly.
To avoid loading the output, use a larger feedback resistor, but
consider the resistor thermal noise effect on the overall circuit.
R2
The AD8657 features rail-to-rail input and output with a supply
voltage from 2.7 V to 18 V. Figure 64 shows the input and output
waveforms of the AD8657 configured as a unity-gain buffer with
a supply voltage of 9 V and a resistive load of 1 MΩ. With an
input voltage of 9 V, the AD8657 allows the output to swing
very close to both rails. Additionally, it does not exhibit phase
reversal.
V
R
= ±9V
= 1MΩ
SY
INPUT
L
OUTPUT
+V
SY
R1
V
IN
AD8657
1/2
V
OUT
R
L
–V
SY
R
= R || R2
L, EFF
L
Figure 65. Inverting Op Amp
Noninverting Configuration
TIME (200µs/DIV)
Figure 66 shows the AD8657 in a noninverting configuration
with a resistive load, RL, at the output. The actual load seen by
the amplifier is the parallel combination of R1 + R2 and RL.
R2
Figure 64. Rail-to-Rail Input and Output
RESISTIVE LOAD
The feedback resistor alters the load resistance that an amplifier
sees. It is, therefore, important to be aware of the value of feed-
back resistors chosen for use with the AD8657. The AD8657 is
capable of driving resistive loads down to 100 kΩ. The following
two examples, inverting and noninverting configurations, show
how the feedback resistor changes the actual load resistance
seen at the output of the amplifier.
+V
SY
R1
AD8657
1/2
V
OUT
R
L
V
IN
–V
SY
R
= R || (R1 + R2)
L, EFF
L
Figure 66. Noninverting Op Amp
Rev. A | Page 18 of 24
AD8657
consist of substrate PNP bipolar transistors, and conduct whenever
the differential input voltage exceeds approximately 600 mV; how-
ever, these diodes also allow a current path from the input to the
lower supply rail, thus resulting in an increase in the total supply
current of the system. As shown in Figure 71, both configurations
yield the same result. At 18 V of power supply, ISY+ remains at
36 μA per dual amplifier, but ISY− increases to 140 μA in magni-
tude per dual amplifier.
COMPARATOR OPERATION
Op amps are designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 67
shows the AD8657 configured as a voltage follower with an input
voltage that is always kept at midpoint of the power supplies.
The same configuration is applied to the unused channel. A1 and
A2 indicate the placement of ammeters to measure supply current.
ISY+ refers to the current flowing from the upper supply rail to
the op amp, and ISY− refers to the current flowing from the op
amp to the lower supply rail. As shown in Figure 68, as expected,
in normal operating condition, the total current flowing into the
op amp is equivalent to the total current flowing out of the op amp,
where, ISY+ = ISY− = 36 μA for the dual AD8657 at VSY = 18 V.
+V
SY
A1
I
+
SY
100kΩ
100kΩ
AD8657
+V
V
SY
OUT
1/2
A1
I
+
SY
A2
I
–
SY
100kΩ
100kΩ
–V
SY
AD8657
V
OUT
1/2
Figure 69. Comparator A
+V
SY
A2
I
–
SY
A1
I
+
SY
–V
SY
100kΩ
Figure 67. Voltage Follower
AD8657
V
OUT
40
35
30
25
20
15
10
5
1/2
100kΩ
A2
I
–
SY
–V
SY
Figure 70. Comparator B
160
140
120
100
80
I
I
–
+
SY
SY
0
0
2
4
6
8
10
(V)
12
14
16
18
V
I
–
+
SY
SY
I
SY
Figure 68. Supply Current vs. Supply Voltage (Voltage Follower)
60
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual op amp is used as a comparator to save board
space and cost; however, this is not recommended.
40
20
0
0
2
4
6
8
10
(V)
12
14
16
18
V
SY
Figure 69 and Figure 70 show the AD8657 configured as a com-
parator, with 100 kΩ resistors in series with the input pins. Any
unused channels are configured as buffers with the input voltage
kept at the midpoint of the power supplies. The AD8657 has input
devices that are protected from large differential input voltages
by Diode D1 and Diode D2 (refer to Figure 63). These diodes
Figure 71. Supply Current vs. Supply Voltage (AD8657 as a Comparator)
Note that 100 kΩ resistors are used in series with the input of
the op amp. If smaller resistor values are used, the supply current of
the system increases much more. For more details on op amps as
comparators, refer to the AN-849 Application Note Using Op
Amps as Comparators.
Rev. A | Page 19 of 24
AD8657
choice due to its low supply current of 33 μA per amplifier over
temperature and supply voltage. The current transmitter controls
the current flowing in the loop, where a zero-scale input signal
is represented by 4 mA of current and a full-scale input signal
is represented by 20 mA. The transmitter also floats from the
control loop power supply, VDD, while signal ground is in the
receiver. The loop current is measured at the load resistor, RL,
at the receiver side.
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). In the event where signal
strength is low and transmission lines are long, an op amp must
accurately amplify the input signals. However, all op amp pins—
the noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These
high frequency signals are coupled into an op amp by various
means such as conduction, near field radiation, or far field radi-
ation. For instance, wires and PCB traces can act as antennas and
pick up high frequency EMI signals.
With a zero-scale input, a current of VREF/RNULL flows through
R. This creates a current flowing through the sense resistor,
I
SENSE, determined by the following equation (see Figure 73 for
details):
SENSE, MIN = (VREF × R)/(RNULL × RSENSE
Precision op amps, such as the AD8657, do not amplify EMI or
RF signals because of their relatively low bandwidth. However,
due to the nonlinearities of the input devices, op amps can rectify
these out-of-band signals. When these high frequency signals
are rectified, they appear as a dc offset at the output.
I
)
With a full-scale input voltage, current flowing through R is
increased by the full-scale change in VIN/RSPAN. This creates an
increase in the current flowing through the sense resistor.
To describe the ability of the AD8657 to perform as intended in
the presence of an electromagnetic energy, the electromagnetic
interference rejection ratio (EMIRR) of the noninverting pin is
specified in Table 2, Table 3, and Table 4 of the Specifications
section. A mathematical method of measuring EMIRR is
defined as follows:
I
SENSE, DELTA = (Full-Scale Change in VIN × R)/(RSPAN × RSENSE
)
Therefore
ISENSE, MAX = ISENSE, MIN + ISENSE, DELTA
When R >> RSENSE, the current through the load resistor at the
receiver side is almost equivalent to ISENSE
.
EMIRR = 20 log (VIN_PEAK/ΔVOS)
140
Figure 73 is designed for a full-scale input voltage of 5 V. At 0 V
of input, loop current is 3.5 mA, and at a full scale of 5 V, the
loop current is 21 mA. This allows software calibration to fine
tune the current loop to the 4 mA to 20 mA range.
120
100
80
The AD8657 and ADR125 both consume only 160 µA quiescent
current, making 3.34 mA current available to power additional
signal conditioning circuitry or to power a bridge circuit.
ADR125
V
REF
V
V
OUT
IN
60
GND
R
NULL
1MΩ
1%
C2
C3
C4
C5
10µF 0.1µF
0.1µF 10µF
40
V
V
= 100mV
PEAK
= 2.7V TO 18V
IN
SY
R
SPAN
20
10M
200kΩ
1/2
AD8657
100M
1G
10G
1%
V
Q1
IN
0V TO 5V
V
FREQUENCY (Hz)
DD
18V
R4
3.3kΩ
R1
68kΩ
1%
Figure 72. EMIRR vs. Frequency
D1
4mA
TO
20mA
R3
1.2kΩ
C1
390pF
4 mA TO 20 mA PROCESS CONTROL CURRENT
LOOP TRANSMITTER
R
R2
2kΩ
1%
L
100Ω
R
SENSE
100Ω
1%
The 2-wire current transmitters are often used in distributed
control systems and process control applications to transmit
analog signals between sensors and process controllers. Figure 73
shows a 4 mA to 20 mA current loop transmitter.
NOTES
1. R1 + R2 = R´.
Figure 73. 4 mA to 20 mA Current Loop Transmitter
The transmitter powers directly from the control loop power
supply, and the current in the loop carries signal from 4 mA to
20 mA. Thus, 4 mA establishes the baseline current budget within
which the circuit must operate. Using the AD8657 is an excellent
Rev. A | Page 20 of 24
AD8657
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 74. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
0.50 BSC
2.90
8
5
PIN 1 INDEX
EXPOSED
PAD
1.70
1.60
1.50
AREA
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TOJEDEC STANDARDS MO-229-WEED
Figure 75. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RM-8
RM-8
RM-8
CP-8-11
CP-8-11
Branding
A2N
A2N
A2N
A2N
AD8657ARMZ
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
AD8657ARMZ-R7
AD8657ARMZ-RL
AD8657ACPZ-R7
AD8657ACPZ-RL
A2N
1 Z = RoHS Compliant Part.
Rev. A | Page 21 of 24
AD8657
NOTES
Rev. A | Page 22 of 24
AD8657
NOTES
Rev. A | Page 23 of 24
AD8657
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08804-0-3/11(A)
Rev. A | Page 24 of 24
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