AD9002BJ [ADI]
High Speed 8-Bit Monolithic A/D Converter; 高速8位单片机A / D转换器型号: | AD9002BJ |
厂家: | ADI |
描述: | High Speed 8-Bit Monolithic A/D Converter |
文件: | 总8页 (文件大小:157K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High Speed 8-Bit
a
Monolithic A/D Converter
AD9002
FEATURES
FUNCTIONAL BLOCK DIAGRAM
150 MSPS Encode Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available
OVERFLOW
AD9002
INHIBIT
ANALOG IN
256
255
R
OVERFLOW
BIT 8 (MSB)
+V
REF
R
R
APPLICATIONS
Radar Systems
D
E
C
O
D
I
BIT 7
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
BIT 6
BIT 5
128
127
L
A
T
C
H
N
G
R/2
R/2
REF
MID
L
O
G
I
BIT 4
BIT 3
C
R
R
2
1
GENERAL DESCRIPTION
BIT 2
The AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 megasamples/
second. Functionally, the AD9002 is comprised of 256 parallel
comparator stages whose outputs are decoded to drive the ECL
compatible output latches.
BIT 1 (LSB)
–V
REF
ENCODE
ENCODE
GND
HYSTERESIS
–V
S
An exceptionally wide large signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs, without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
bit to indicate overrange inputs. This overflow output can be
disabled with the overflow inhibit pin.
The AD9002 is available in two grades, one with 0.5 LSB lin-
earity and one with 0.75 LSB linearity. Both versions are offered
in an industrial grade, –25°C to +85°C, packaged in a 28-lead
DIP and a 28-leaded JLCC. The military temperature range
devices, –55°C to +125°C, are available in ceramic DIP and
LCC packages and comply with MIL-STD-883 Class B.
The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further im-
prove performance. Additionally, the AD9002’s low power
dissipation of 750 mW makes it usable over the full extended
temperature range. The AD9002 also incorporates an overflow
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD9002–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (–VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
AD9002AD/AJ
AD9002BD/BJ
AD9002SD/SE
AD9002TD/TE
Parameter
Temp
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
8
8
8
8
Bits
DC ACCURACY
Differential Linearity
+25°C
Full
+25°C
Full
Full
0.6
0.6
0.75
1.0
1.0
1.2
0.4
0.4
0.5
0.75
0.5
1.2
0.6
0.6
0.75
1.0
1.0
1.2
0.4
0.4
0.5
0.75
0.5
1.2
LSB
LSB
LSB
LSB
Integral Linearity
No Missing Codes
GUARANTEED
GUARANTEED
GUARANTEED
GUARANTEED
INITIAL OFFSET ERROR
Top of Reference Ladder
+25°C
Full
+25°C
Full
Full
8
14
17
10
12
8
14
17
10
12
8
14
17
10
12
8
14
17
10
12
mV
mV
Bottom of Reference Ladder
Offset Drift Coefficient
4
4
4
4
mV
mV
µV/°C
20
20
20
20
ANALOG INPUT
Input Bias Current1
+25°C
60
200
200
60
200
200
60
200
200
60
200
200
µA
Full
µA
Input Resistance
+25°C 25
+25°C
+25°C
+25°C
200
17
160
440
25
40
200
17
160
440
25
40
200
17
160
440
25
40
200
17
160
440
kΩ
pF
MHz
V/µs
Input Capacitance
Large Signal Bandwidth2
Input Slew Rate3
22
22
22
22
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
+25°C 40
+25°C
80
0.25
10
110
80
0.25
10
110
80
0.25
10
110
80
0.25
10
110
Ω
Ω/°C
MHz
DYNAMIC PERFORMANCE
Conversion Rate
+25°C 125
+25°C
150
1.3
15
3.7
6
125
2.5
150
1.3
15
3.7
6
125
2.5
150
1.3
15
3.7
6
125
2.5
150
1.3
15
3.7
6
MSPS
ns
Aperture Delay
Aperture Uncertainty (Jitter)
+25°C
ps
4, 5
Output Delay (tPD
)
+25°C 2.5
+25°C
5.5
5.5
5.5
5.5
ns
Transient Response6
Overvoltage Recovery Time7
Output Rise Time4
ns
+25°C
6
6
6
6
ns
+25°C
3.0
2.5
3.0
2.5
3.0
2.5
3.0
2.5
ns
Output Fall Time4
+25°C
ns
Output Time Skew4, 8
+25°C
0.6
0.6
0.6
0.6
ns
ENCODE INPUT
Logic “1” Voltage4
Full
–1.1
–1.1
–1.1
–1.1
V
Logic “0” Voltage4
Full
–1.5
150
120
–1.5
150
120
–1.5
150
120
–1.5
150
120
V
Logic “1” Current
Full
Full
+25°C
+25°C 1.5
+25°C 1.5
µA
µA
pF
ns
ns
Logic “0” Current
Input Capacitance
3
3
3
3
Encode Pulsewidth (Low)9
Encode Pulsewidth (High)9
1.5
1.5
1.5
1.5
1.5
1.5
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
144
7.6
300
144
7.6
300
144
7.6
300
144
7.6
300
µA
AC LINEARITY10
Effective Bits11
+25°C
Bits
In-Band Harmonics
dc to 1.23 MHz
+25°C 48
+25°C
55
48
46
55
48
46
55
48
46
55
dB
dB
dB
dB
dB
dc to 9.3 MHz
50
50
50
50
dc to 19.3 MHz
+25°C
44
47.6
60
44
47.6
60
44
47.6
60
44
47.6
60
Signal-to-Noise Ratio12
+25°C 46
Two Tone Intermod Rejection13 +25°C
DIGITAL OUTPUTS4
Logic “1” Voltage
Logic “0” Voltage
Full
Full
–1.1
–1.1
–1.1
–1.1
V
V
–1.5
–1.5
–1.5
–1.5
POWER SUPPLY14
Supply Current (–5.2 V)
+25°C
Full
145
175
200
145
175
200
145
175
200
145
175
200
mA
mA
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio15
+25°C
+25°C
+25°C
750
50
0.8
750
50
0.8
750
50
0.8
750
50
0.8
mW
mW
mV/V
1.5
1.5
1.5
1.5
bit-to-bit time skew differences.
NOTES
9ENCODE signal rise/fall times should be less than 10 ns for normal operation.
10Measured at 125 MSPS encode rate.
1Measured with AIN = 0 V.
2Measured by FFT analysis where fundamental is –3 dBc.
11Analog input frequency = 1.23 MHz.
3Input slew rate derived from rise time (10 to 90%) of full scale input.
40utputs terminated through 100 Ω to –2 V.
12RMS signal to rms noise, with 1.23 MHz analog input signal.
13Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz.
14Supplies should remain stable within ±5% for normal operation.
15Measured at –5.2 V ±5%.
5Measured from ENCODE in to data out for LSB only.
6For full-scale step input, 8-bit accuracy is attained in specified time.
7Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage.
8Output time skew includes high-to-low and low-to-high transitions as well as
Specifications subject to change without notice.
–2–
REV. D
AD9002
Recommended Operating Conditions
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog-to-Digital Supply Voltage Differential . . . . . . . . .0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –VS to +0.5 V
Input Voltage
Nominal
Parameter
Min
Max
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
–VS
+VREF
–VREF
Analog Input
–5.46
–VREF
–2.1
–5.20
0.0 V
–2.0
–4.94
+0.1
+VREF
+VREF
2
Reference Input Voltage (+VREF – VREF
)
. . . . –3.5 V to 0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ±4 mA
ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
–VREF
EXPLANATION OF TEST LEVELS
AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . . –25°C to +85°C
AD9002SE/SD/TD/TE . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
Test Level I
Test Level II
–
–
100% production tested.
100% production tested at +25°C, and
sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and
characterization testing.
Test Level III
Test Level IV
–
–
NOTES
1Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device
reliability.
Test Level V
Test Level VI
–
–
Parameter is a typical value only.
All devices are 100% production tested at
+25°C. 100% production tested at tempera-
ture extremes for extended temperature
devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
2+VREF ≥ –VREF under all circumstances.
3Maximum junction temperature (tJ max) should not exceed +175°C for ceramic
packages, and +150°C for plastic packages:
tJ = PD (θJA) + tA
PD (θJC) + tC
where
ORDERING GUIDE
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
Package
Model
Linearity Temperature Range Option*
tC = case temperature (°C)
AD9002AD
AD9002BD
AD9002AJ
AD9002BJ
0.75 LSB –25°C to +85°C
0.50 LSB –25°C to +85°C
0.75 LSB –25°C to +85°C
0.50 LSB –25°C to +85°C
D-28
D-28
J-28
Typical thermal impedances are:
Ceramic DIP θJA = 56°C/W; θJC = 20°C/W
Ceramic LCC θJA = 69°C/W; θJC = 23°C/W
PLCC θJA = 60°C/W; θJC = 19°C/W.
J-28
AD9002SD/883B 0.75 LSB –55°C to +125°C
AD9002SE/883B 0.75 LSB –55°C to +125°C
AD9002TD/883B 0.50 LSB –55°C to +125°C
AD9002TE/883B 0.50 LSB –55°C to +125°C
D-28
E-28A
D-28
E-28A
*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip
Carrier, J-Formed Leads.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD9002
FUNCTIONAL DESCRIPTION
Pin #
Name
Description
1
2
DIGITAL GROUND
OVERFLOW INH
One of four digital ground pins. All digital ground pins should be connected together.
OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs.
Overflow Enabled
(Floating or –5.2 V)
of D1–D8
Overflow Inhibited (GND)
of D1–D8
Analog Input
VIN > +VREF
1 0
0
0
0
0
0
0
0
0 1
1
1
1
1
1
1 1
V
IN ≤ +VREF
0 X X X X X X X X
0 X X X X X X X X
3
HYSTERESIS
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change
from –5.2 V to –2.2 V at the Hysteresis control pin. Normally converted to –5.2 V.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
Noninverted input of the differential encode input. This pin is driven in conjunction with
ENCODE. Data is latched on the rising edge of the ENCODE signal.
Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE.
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
4
5
6
7
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
8
9
ENCODE
ANALOG GROUND
ANALOG INPUT
–VREF
REFMID
DIGITAL GROUND
DIGITAL –VS
10
11
12
13
14
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be con-
nected together.
15
D1 (LSB)
Digital data output.
16–19
20
21, 22
D2–D5
DIGITAL GROUND
ANALOG –VS
Digital data output.
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be con-
nected together.
23
24, 25
26
DIGITAL GROUND
D6, D7
D8 (MSB)
One of four digital ground pins. All digital ground pins should be connected together.
Digital data output.
Digital data output.
27
OVERFLOW
Overflow data output. Logic high indicates an input overvoltage (VIN > +VREF) if OVERFLOW
INHIBIT is enabled (overflow enabled, –5.2 V). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
28
DIGITAL –VS
PIN DESIGNATIONS
LCC
JLCC
DIP
DIGITAL
1
28
27
26
25
24
23
22
21
20
19
DIGITAL –V
S
GROUND
2
3
OVERFLOW INH
OVERFLOW
D8(MSB)
HYSTERESIS
+V
4
REF
D7
D6
ANALOG INPUT
5
4
3
1 28 27 26
2
25 24 23 22 21 20 19
ANALOG
GROUND
DIGITAL
GROUND
6
AD9002
D8(MSB)
D4
26
27
28
1
18
17
16
15
5
6
ANALOG INPUT
25
D7
7
ENCODE
ANALOG –V
S
S
TOP VIEW
(Not to Scale)
OVERFLOW
D3
ANALOG
GROUND
ENCODE
24 D6
8
ANALOG –V
ENCODE
DIGITAL –V
S
DIGITAL
GROUND
D2
DIGITAL
GROUND
ANALOG –V
7
8
9
AD9002
23
22
AD9002
ANALOG
GROUND
ANALOG INPUT
DIGITAL
GROUND
D1(LSB)
9
TOP VIEW
ENCODE
ANALOG
GROUND
TOP VIEW
S
S
(Not to Scale)
2
14 DIGITAL –V
(Not to Scale)
OVERFLOW INH
S
10
11
12
13
14
21 ANALOG –V
D5
DIGITAL
13
3
DIGITAL
HYSTERESIS
10
11
20
ANALOG INPUT
GROUND
–V
18 D4
GROUND
REF
12
+V
4
REF
REF
19
MID
–V
D 5
REF
REF
MID
17
16
15
D3
5
6
7
8
9
10 11
DIGITAL
GROUND
D2
12
13 14 15 16 17 18
DIGITAL –V
D1(LSB)
S
REV. D
–4–
AD9002
N + 1
ANALOG
INPUT
N
N + 2
APERTURE
DELAY
ENCODE
tPD
OUTPUT
DATA
N + 1
N – 1
N
Figure 1. Timing Diagram
+V
AD9002
REF
AD9002
R
AD9002
R/2
R/2
ENCODE
REF
MID
ANALOG
INPUT
DIGITAL
OUTPUT
–5.2V
–5.2V
ENCODE
R
–V
REF
–5.2V
–5.2V
–5.2V
COMPARATOR CELLS
Figure 2. Input/Output Circuits
OVERFLOW
INHIBIT
DIGITAL –V
S
HYSTERESIS
DIGITAL
GROUND
OVERFLOW
0.1F
+V
D8 (MSB)
–5.2V
REF
–V
D7
D6
S
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
ANALOG
INPUT
OVERFLOW
HYSTERESIS
D8
D7
D6
D5
OVERFLOW INH
100⍀
1k⍀
ANALOG
GROUND
DIGITAL
GROUND
AD1
AD2
AD3
ANALOG IN
ENCODE
ENCODE
1k⍀
ANALOG –V
S
ENCODE
1k⍀
1k⍀
1k⍀
1k⍀
ENCODE
DIGITAL
GROUND
D4
D3
–V
–2V
REF
ANALOG
GROUND
0.1F
AD9002
D2
D1
D5
D4
+V
REF
ANALOG
INPUT
GROUND
STATIC BURN IN
AD1 = 0V
AD2 = ECL HIGH
AD3 = ECL LOW
D2
D1 (LSB)
DIGITAL
D3
DYNAMIC BURN IN
DIGITAL
GROUND
MID
–V
REF
0V
REF
–V
AD1
S
–2V
ECL HIGH
ECL LOW
AD2
Figure 4. Die Layout and Mechanical Information
ECL HIGH
ECL LOW
AD3
Die Dimensions . . . . . . . . . . . . . . . . .106 × 114 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)
Bond Wire . . . . . . . . . . . . . 1-1.3 mil Gold; Gold Ball Bonding
ALL RESISTORS ؎ 5%, ⍀
ALL CAPACITORS ؎ 20%, F
ALL SUPPLIES ؎ 5%
Figure 3. Burn-in Diagram
REV. D
–5–
AD9002
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL’s logic levels are tempera-
ture compensated, and are therefore compatible with the
AD9002 (and most other ECL device families) only over a
limited temperature range. To operate at the highest encode
rates, the supporting logic around the AD9002 will need to be
equally fast. Whichever of the ECL logic families is used, special
care must be exercised to keep digital switching noise away from
the analog circuits around the AD9002. The two most critical
items are digital supply lines and digital ground return.
Designs using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9002. Separate ground plane areas for the digital and analog
components may be useful, but these separate grounds should
be connected together at the AD9002 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention in-
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more tradi-
tional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 Ω resistor in series with the amplifier output.
volves the three reference inputs, +VREF, REFMID, and –VREF
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews. The application circuit shown below demonstrates a
simple and effective means of driving the reference circuit.
.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compactible ENCODE signal (see
timing diagram). In applications where only a single-ended
signal is available, the AD96685, a high speed, ECL voltage
comparator, can be employed to generate the differential sig-
nals. All ECL signals (including the overflow bit) should be
terminated properly to avoid ringing and reflection.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical con-
nections. Otherwise, aperture delay errors may degrade con-
verter performance at high frequencies.
–15V
The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
1k⍀
4k⍀
100⍀
ANALOG
INPUT
(0V TO +2V)
0.1F
1.5k⍀
2N3906
10⍀
AD741
The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN ≥ +VREF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW, and all other outputs will be at logic HIGH
for overrange inputs (nonreturn-to-zero operation).
NYQUEST
FILTER
0.1F
A
IN
–V
+V
REF
REF
OVERFLOW
40⍀
EQUAL
D8 (MSB)
DISTANCE
50⍀
D7
AD9611
A
D6
IN
AD9002
D5
ENCODE
INPUT
D4
ENCODE
D3
(GROUND
THRESHOLD)
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely im-
portant in fault-sensitive applications such as digital radio
(QAM).
D2
50⍀
ENCODE
D1 (LSB)
–5.2D
–5.2A
AD96685
0.1F
0.01F
0.01F
0.1F
Figure 5. Typical Application
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is par-
ticularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.
REV. D
–6–
AD9002
LINEARITY OUTPUT
(ERROR WAVEFORM)
RECONSTRUCTED
OUTPUT
HOS100
HOS100
50⍀
1k⍀
–15V
1k⍀
4.3k⍀
3.75⍀
150⍀
0.1F
90⍀ 20⍀ 90⍀
2N3906
AD741
AD9768
DAC
0.01F
0.1F
50⍀
–V
IN
+V
REF
REF
REF
MID
ANALOG
INPUT
A
75⍀
OVERFLOW
D8(MSB)
D7
10F
EQUAL
DISTANCE
50⍀
HOS200
2k⍀
A
IN
D6
D5
AD96687
ENCODE
REGISTER
100151
LINE
DRIVER
100114
37 PIN
D
CONNECTOR
AD9002*
ENCODE
D4
1k⍀
0.1F
3.9k⍀
OVERFLOW
INH
D3
D2
HYSTERESIS
D1(LSB)
–15V
1k⍀
0.1F
–5.2A
–5.2D
625⍀
–5.2V
ENCODE INPUT
(GROUND
THRESHOLD)
0.1F
0.1F
0.01F
0.01F
NOTE:
100114 LINE DRIVER OUTPUTS
REQUIRE 510⍀ PULL-DOWN
RESISTORS TO –5.2V. ALL OTHER
ECL OUTPUTS SHOULD BE
TERMINATED TO –2V WITH
100⍀ RESISTERS, UNLESS
OTHERWISE SPECIFIED.
AD96687
AD96687
AD96687
510⍀
50⍀
510⍀
–5.2V
RESISTORS ARE IN ⍀.
CAPACITORS ARE IN F.
–5.2V
DELAY
0.1F
1k⍀
13k⍀
–15V
1k⍀ DELAY
*CONTACT FACTORY ABOUT
EVALUATION BOARD AVAILABILITY
880⍀
13k⍀
–15V
880⍀
Figure 6. AD9002 Evaluation Circuit
65
60
55
50
2ND HARMONIC
3RD HARMONIC
SNR
45
40
35
30
1MHz
10MHz
100MHz
ANALOG INPUT FREQUENCY (0.1dB BELOW FULL SCALE)
125 MSPS ENCODE RATE
Figure 7. Dynamic Performance
REV. D
–7–
AD9002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic Side-Brazed DIP
(D-28)
0.098 (2.49) MAX
0.005 (0.13) MIN
28
15
0.310 (7.87)
0.220 (5.59)
14
1
0.606 (15.4)
0.58 (14.74)
PIN 1
0.060 (1.52)
0.015 (0.38)
1.490 (37.85) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.110 (2.79) 0.070 (1.78)
0.090 (2.29) 0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
28-Lead Ceramic Leadless Chip Carrier
(E-28A)
0.300 (7.62)
BSC
0.150
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.458 (11.63)
0.442 (11.23)
SQ
(3.51)
BSC
0.015 (0.38)
MIN
0.095 (2.41)
0.075 (1.90)
4
26
28
25
5
0.028 (0.71)
0.022 (0.56)
1
0.458
0.011 (0.28)
0.007 (0.18)
R TYP
TOP
VIEW
BOTTOM
VIEW
(11.63)
MAX
SQ
0.050
(1.27)
BSC
12
19
18
0.075
(1.91)
REF
11
45؇ TYP
0.200
(5.08)
BSC
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
28-Leaded JLCC
(J-28)
0.171 (4.34)
MAX
0.450 ؎0.006
SQ
(11.43 ؎0.152)
19
0.039 ؎0.005
(0.991 ؎0.127)
25
26
18
0.028 ؎0.002
(0.711 ؎0.051)
0.050
(1.27)
BSC
PIN 1
0.300
(7.62)
TYP
TOP VIEW
(PINS DOWN)
0.420 ؎0.010
(10.668 ؎0.254)
BOTTOM VIEW
0.019 ؎0.002
(0.483 ؎0.051)
12
4
11
5
0.006 ؎0.0006
(0.152 ؎0.015)
0.488 ؎0.010
(11.43 ؎0.254)
SQ
0.022 ؎0.003
(0.559 ؎0.076)
0.102 ؎0.010
(1.448 ؎0.254)
REV. D
–8–
相关型号:
AD9002BN
IC 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28, PLASTIC, DIP-28, Analog to Digital Converter
ADI
AD9002BP
IC 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC28, PLASTIC, LCC-28, Analog to Digital Converter
ADI
AD9002SD
IC 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, SIDE BRAZED, CERAMIC, DIP-28, Analog to Digital Converter
ADI
AD9002TD
IC 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, SIDE BRAZED, CERAMIC, DIP-28, Analog to Digital Converter
ADI
©2020 ICPDF网 联系我们和版权申明