AD9012TE [ADI]
High Speed 8-Bit TTL A/D Converter; 高速8位TTL A / D转换器
| 型号： | AD9012TE |
| 厂家： | 
ADI |
| 描述： | High Speed 8-Bit TTL A/D Converter |
| 文件： | 总8页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed 8-Bit
TTL A/D Converter
a
AD9012
FUNCTIONAL BLOCK DIAGRAM
FEATURES
100 MSPS Encode Rate
Very Low Input Capacitance—16 pF
Low Power—1 W
OVERFLOW
INHIBIT
AD9012
ANALOG IN
256
255
R
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available
OVERFLOW
؉V
REF
R
R
D
D
(MSB)
8
7
APPLICATIONS
Radar Guidance
D
E
C
O
D
I
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
D
D
128
127
6
L
A
T
C
H
N
G
R/2
R/2
5
REF
MID
L
O
G
I
D
D
4
C
3
R
R
2
1
GENERAL DESCRIPTION
D
D
2
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process that allows operation at sampling rates up to one hun-
dred megasamples/second. Functionally, the AD9012 is com-
prised of 256 parallel comparator stages whose outputs are
decoded to drive the TTL compatible output latches.
(LSB)
1
؊V
REF
ENCODE
GND
HYSTERESIS ؊V ؉V
S S
The exceptionally wide large-signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
an industrial grade, –25°C to +85°C, packaged in a 28-lead DIP
and a 28-lead JLCC. The military temperature range devices,
–55°C to +125°C, are available in ceramic DIP and LCC pack-
ages and are compliant to MIL-STD-883 Class B.
The AD9012 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Databook
or current AD9012/883B data sheet for detailed specifications.
The AD9012 is available in two grades: one with 0.5 LSB linear-
ity and one with 0.75 LSB linearity. Both versions are offered in
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+VS = +5.0 V; –VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
Test
AD9012AQ/AJ
AD9012BQ/BJ
AD9012SQ/SE
AD9012TQ/TE
Parameter
Temp
Level Min Typ
Max Min
Typ
Max Min
Typ Max Min Typ Max
Units
RESOLUTION
8
8
8
8
Bits
DC ACCURACY
Differential Linearity
+25°C
Full
+25°C
Full
I
VI
I
VI
VI
0.6
0.6
0.75
1.0
1.0
0.4
0.4
0.5
0.75
0.5
0.6
0.6
0.75
1.0
1.0
0.4
0.4
0.5
0.75
0.5
1.2
LSB
LSB
LSB
LSB
Integral Linearity
No Missing Codes
1.2
1.2
1.2
Full
GUARANTEED
GUARANTEED
GUARANTEED
GUARANTEED
INITIAL OFFSET ERROR
Top of Reference Ladder
+25°C
Full
+25°C
Full
I
VI
I
VI
V
7
15
18
10
13
7
15
18
10
13
7
15
18
10
13
7
15
18
10
13
mV
mV
mV
mV
Bottom of Reference Ladder
Offset Drift Coefficient
6
6
6
6
Full
25
25
25
25
µV/°C
ANALOG INPUT
Input Bias Current1
+25°C
Full
+25°C
+25°C III
+25°C
+25°C
I
VI
I
60
200
200
60
200
200
60
200
200
60
200
200
µA
µA
kΩ
pF
MHz
V/µs
Input Resistance
25
40
200
16
160
440
25
40
200
16
160
440
25
40
200
16
160
440
25
40
200
16
160
440
Input Capacitance
18
18
18
18
Large Signal Bandwidth2
Analog Input Slew Rate3
V
V
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
+25°C VI
80
0.25
10
110
80
0.25
10
110
80
0.25
10
110
80
0.25
10
110
Ω
Ω/°C
MHz
V
V
+25°C
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
75
4
100
3.8
15
4.9
8
75
4
100
3.8
15
4.9
8
75
4
100
3.8
15
4.9
8
75
4
100
3.8
15
4.9
8
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
I
V
V
I
Aperture Uncertainty (Jitter)
4, 5
Output Delay (tPD
)
11
11
11
11
Transient Response6
Overvoltage Recovery Time7
Output Rise Time4
8
8
8
8
6.6
3.3
3.0
8.0
4.3
6.6
3.3
3.0
8.0
4.3
6.6
3.3
3.0
8.0
4.3
6.6
3.3
3.0
8.0
4.3
Output Fall Time4
I
V
Output Time Skew4, 8
ENCODE INPUT
Logic “1” Voltage4
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
I
I
2.0
2.0
2.0
2.0
V
V
µA
µA
pF
ns
ns
Logic “0” Voltage4
0.8
250
400
0.8
250
400
0.8
250
400
0.8
250
400
Logic “1” Current
Logic “0” Current
Input Capacitance
2.5
2.5
2.5
2.5
Encode Pulsewidth (Low)9
Encode Pulsewidth (High)9
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
VI
V
200
7.5
250
200
7.5
250
200
7.5
250
200
7.5
250
µA
AC LINEARITY10
Effective Bits11
+25°C
Bits
In-Band Harmonics
dc to 1.23 MHz
dc to 9.3 MHz
+25°C
+25°C
+25°C
+25°C
+25°C
I
48
46
55
50
44
47.6
37
48
46
55
50
44
47.6
37
48
46
55
50
44
47.6
37
48
46
55
50
44
47.6
37
dBc
dBc
dBc
dBc
dBc
V
V
I
dc to 19.3 MHz
Signal-to-Noise Ratio12
Noise Power Ratio13
V
DIGITAL OUTPUT
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
2.4
2.4
2.4
2.4
V
V
0.4
0.4
0.4
0.4
POWER SUPPLY14
Positive Supply Current (+5.0 V) +25°C
I
33
45
33
45
33
45
33
45
mA
Full
+25°C
Full
+25°C
+25°C
+25°C
VI
I
VI
V
V
I
48
179
191
48
179
191
48
179
191
48
179
191
mA
mA
mA
mW
mW
mV/V
Supply Current (–5.2 V)
152
152
152
152
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio15
955
44
0.85
955
44
0.85
955
44
0.8
955
44
0.8
2.5
2.5
2.5
2.5
REV. D
–2–
AD9012
9ENCODE signal rise/fall times should be less than 30 ns for normal operation.
NOTES
1Measured with Analog Input = 0 V.
10Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics.
11Analog input frequency = 1.23 MHz.
2Measured by FFT analysis where fundamental is –3 dBc.
3Input slew rate derived from rise time (10% to 90%) of full-scale step input.
4Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)
5Measured from ENCODE into data out for LSB only.
6For full-scale step input, 8-bit accuracy is attained in specified time.
7Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.
12RMS signal to rms noise, including harmonics with 1.23 MHz. analog input
signal.
13NPR measured @ 0.5 MHz. Noise Source is 250 mW (rms) from 0.5 MHz
to 8 MHz.
14Supplies should remain stable within ±5% for normal operation.
15Measured at –5.2 V ± 5% and +5.0 V ± 5%.
8Output time skew includes high-to-low and low-to-high transitions as well a
bit-to-bit time skew differences.
s
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
V
S
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . +6 V
Analog to Digital Supply Voltage Differential (–VS) . . . .0.5 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –6 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –VS to +0.5 V
ENCODE Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to +5 V
1k⍀
TTL
OUTPUT
15pF
OVERFLOW INH Input Voltage . . . . . . . . . . . –5.2 V to 0 V
2
Reference Input Voltage (+VREF –VREF
)
. . . . –3.5 V to +0.1 V
Figure 1. Load Circuit
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ±4 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
EXPLANATION OF TEST LEVELS
Test Level
AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . . –25°C to +85°C
AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
I
– 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample tested only.
NOTES
IV – Parameter is guaranteed by design and characterization
testing.
1Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and
characterization testing for industrial devices.
2+VREF ≥ –VREF under all circumstances.
3Maximum junction temperature (tJ max) should not exceed +175°C for ceramic
packages, and +150°C for plastic packages:
tJ = PD (θJA) + tA
PD (θJC) + tc
where
ORDERING GUIDE
PD = power dissipation
Temperature
Ranges
Package
Options*
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
Device
Linearity
AD9012AQ
AD9012BQ
AD9012AJ
AD9012BJ
AD9012SQ
AD9012SE
AD9012TQ
AD9012TE
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
0.75 LSB
0.75 LSB
0.50 LSB
0.50 LSB
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Q-28
Q-28
J-28A
J-28A
Q-28
E-28A
Q-28
E-28A
tC = case temperature (°C)
typical thermal impedances are:
Ceramic DIP θJA = 42°C/W; θJC = 10°C/W
Ceramic LCC θJA = 50°C/W; θJC = 15°C/W
JLCC θJA = 59°C/W; θJC = 15°C/W.
Recommended Operating Conditions
Input Voltage
Parameter
Min
Nominal
Max
*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;
Q = Cerdip.
–VS
+VS
+VREF
–VREF
–5.46
+4.75
–VREF
–2.1
–5.20
5.00
0.0 V
–2.0
–4.94
+5.25
+0.1
+VREF
Analog Input
–VREF
+VREF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9012 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD9012
PIN FUNCTION DESCRIPTIONS
Description
Pin #
Name
11
12
DIGITAL +VS
OVERFLOW INH
One of three positive digital supply pins (nominally +5.0 V).
OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN ≥ + VREF).
ANALOG
INPUT
OVERFLOW ENABLED (FLOATING)
OF Dl D2 D3 D4 D5 D6 D7 D8
OVERFLOW INHIBITED (GND)
OF Dl D2 D3 D4 D5 D6 D7 D8
V
IN ≥ + VREF
1
0
0
0
0
0
0
X
0
0
0
0
0
1
1
1
1
1
1 1 1
VIN < + VREF
X X X X
X X X
X X X X X X X X
13
HYSTERESIS
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a
change from –5.2 V to –2.2 V at the Hysteresis control pin.
14
15
16
17
18
19
10
11
12
13
14
+VREF
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
TTL level encode command input. ENCODE is rising edge sensitive.
One of three positive digital supply pins (nominally +5.0 V).
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL +VS
ANALOG GROUND
ANALOG INPUT
–VREF
REFMID
DIGITAL +VS
DIGITAL –VS
One of three positive digital supply pins (nominally +5.0 V).
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
15
16–19
D1 (LSB)
D2–D5
Digital data output. D1 (LSB) is the least significant bit of the digital output word.
Digital data output.
20
21, 22
DIGITAL GROUND
ANALOG –VS
One of two digital ground pins. Both digital grounds pins should be connected together.
One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be
connected together.
23
24, 25
26
DIGITAL GROUND
D6, D7
D8 (MSB)
One of two digital ground pins. Both digital ground pins should be connected together.
Digital data output.
Digital data output D8 (MSB) is the most significant bit of the digital output word.
Overflow data output. Logic HIGH indicates an input overvoltage (VIN > + VREF), if
OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
27
OVERFLOW
28
DIGITAL –VS
PIN CONFIGURATIONS
DIGITAL V +
S
1
28
DIGITAL V –
S
2
3
27 OVERFLOW
26
OVERFLOW INH
HYSTERESIS
D
D
D
(MSB)
8
7
6
4
3
1
28 27 26
2
4
25
24
23
+V
REF
5
ANALOG INPUT
ANALOG GROUND
ENCODE
5
6
25
24
ANALOG INPUT
ANALOG GROUND
ENCODE
D
D
7
6
6
DIGITAL GROUND
AD9012
TOP VIEW
7
8
23
22
DIGITAL GROUND
AD9012
TOP VIEW
(Not to Scale)
7
22 ANALOG V –
S
DIGITAL V +
S
ANALOG V –
S
(Not to Scale)
8
DIGITAL V +
S
21 ANALOG V –
S
9
21
ANALOG V –
S
ANALOG GROUND
ANALOG INPUT
9
20 DIGITAL GROUND
ANALOG GROUND
ANALOG INPUT
20
19
10
11
DIGITAL GROUND
10
11
12
13
14
19
18
17
16
15
D
5
D
D
D
D
–V
5
4
3
2
REF
–V
REF
12
13 14 15 16 17 18
REF
MID
DIGITAL V +
S
DIGITAL V –
S
D
(LSB)
1
REV. D
–4–
AD9012
N + 1
ANALOG
INPUT
N
N + 2
APERTURE
DELAY
ENCODE
tPD
OUTPUT
DATA
N + 1
N – 1
N
Figure 2. Timing Diagram
؉V
REF
R
؉5.0V
؉5.0V
ANALOG
INPUT
R/2
R/2
ENCODE
REF
MID
DIGITAL
OUTPUTS
R
؊V
256 COMPARATOR
CELLS
REF
؊5.2V
Figure 3. Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATION
–5.2V
+5.0V
0.1F
0.1F
ONE JUMPER
PER BOARD
–V
S
+V
S
1k⍀
1k⍀
OVERFLOW
(MSB)
100⍀
D
AIN
AD1
8
1k⍀
1k⍀
1k⍀
D
7
AD9012
D
D
D
6
5
510⍀
AD2
ENCODE
1k⍀
1k⍀
1k⍀
–V
–2.0V
REF
4
D
3
V
H
D
2
1k⍀
+V
D (LSB)
D 1(LSB)
1
REF
LOAD
RESISTORS
ANALOG
GROUND
DIGITAL
GROUND
ALL RESISTORS ؎ 5%
ALL CAPACITORS ؎ 20%
ALL SUPPLY VOLTAGES ؎ 5%
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC) SEE WAVEFORMS
0V
AD1
–2V
640s
+2.4V
+0.4V
Die Dimensions . . . . . . . . . . . . . . . . 111 × 123 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
Epoxy (Plastic)
AD2
5s
Figure 4. Burn-In Diagram
Bond Wire . . . . . . . . . . . . . 1–1.3 mil Gold; Gold Ball Bonding
REV. D
–5–
AD9012
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9012 is compatible with all standard TTL logic fami-
lies. However, to operate at the highest encode rates, the sup-
porting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Which-
ever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.
Designs using the AD9012, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high-speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.
The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier
like the AD9610/AD9611 will be required. For those applica-
tions that do not require the full input bandwidth of the AD9012,
some of the more traditional monolithic amplifiers, like the
AD846, should work very well. Overall performance with mono-
lithic amplifiers can be improved by inserting a 40 Ω resistor in
series with the amplifier output.
The second area that requires an extra degree of attention
involves the three reference inputs, +VREF, REFMID, and –VREF
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
.
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews.
The output data is buffered through the TTL compatible out-
put latches. In addition to the latch propagation delay (tPD), all
data is delayed by one clock cycle, before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL-compatible ENCODE signal (see timing diagram).
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors should be very effective.
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.
The AD9012 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
–15V
The OVERFLOW INHIBIT pin of the AD9012 determines
how the converter handles overrange inputs (AIN ≥ + VREF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW for overrange inputs, and all other digital out-
puts will be at logic HIGH (nonreturn-to-zero operation).
1k⍀
4k⍀
100⍀
2N3906
0.1F
10⍀
AD741
ANALOG
INPUT
(0 TO +2V)
0.1F
–V
+V
REF
NYQUEST
FILTER
REF
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely impor-
tant in fault sensitive applications such as digital radio (QAM).
1.5k⍀
OVERFLOW
D
(MSB)
8
A
IN
40⍀
D
7
EQUAL
DISTANCE
50⍀
D
6
A
IN
AD9611
D
5
AD9012
D
D
D
4
3
2
TTL
ENCODE
INPUT
ENCODE
Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly im-
portant in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.
50⍀
D
(LSB)
1
+5.0V
–5.2V
0.01F
0.01F 0.1F
0.1F
Figure 5. Typical Application
REV. D
–6–
AD9012
LINEARITY OUTPUT
(ERROR WAVEFORM)
RECONSTRUCTED
OUTPUT
430⍀
430⍀
50⍀
NOTE:
10124, ECL OUTPUTS,
SHOULD BE TERMINATED
TO –2V WITH
100⍀
–5.2V
AD642
AD642
50⍀
100⍀ REGISTERS.
160⍀
82⍀
2N3906
37.5⍀
2N3906
10⍀
AD741
100⍀
240⍀
1N747
500⍀
240⍀
AD9768
0.1F
0.01F
0.1F
REF
0.1F
+V
10124
10124
–V
REF
MID
REF
50⍀
OVERFLOW
D
(MSB)
8
A
A
IN
ANALOG
INPUT
(2V p-p MAX)
D
7
EQUAL
DISTANCE
D
6
LATCH
AD9012
100⍀
IN
D
5
HOS200
74AS843
25 PIN
D
D
4
ENCODE
CONNECTOR
D
3
OVERFLOW
INH
D
2
D
(LSB)
HYSTERESIS
+5.0V
1
CLK
0.1F
–5.2V
1k⍀
560⍀
1k⍀
–5.2V
0.01F
0.1F
0.1F 0.01F
1k⍀
TTL
ENCODE
INPUT
74AS04
Figure 6. Evaluation Circuit
70
65
60
2ND HARMONIC
55
50
45
40
3RD HARMONIC
SNR*
*WITH HARMONICS
INPUT = 0.1dB BELOW FULL SCALE
ENCODE RATE = 75MSPS
35
30
1
10
100
ANALOG INPUT FREQUENCY – MHz
Figure 7. Dynamic Performance
REV. D
–7–
AD9012
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead JLCC
(J-28A)
0.171 (4.34)
MAX
0.456 (11.582)
0.444 (11.278)
0.044 (1.118)
0.034 (0.864)
SQ
25
19
26
18
0.030 (0.762)
0.026 (0.660)
0.050
(1.27)
BSC
PIN 1
0.300
(7.62)
TYP
0.430 (10.922)
0.410 (10.414)
0.021 (0.534)
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
0.017 (0.432)
12
4
5
11
0.0066 (0.167)
0.0054 (0.137)
0.498 (12.649)
0.478 (12.141)
SQ
0.025 (0.635)
0.019 (0.483)
0.112 (1.702)
0.092 (1.194)
28-Lead Cerdip
(Q-28)
1.490 (37.84) MAX
28
15
0.525 (13.33)
0.515 (13.08)
PIN 1
1
14
0.62 (15.74)
0.59 (14.93)
0.18 (4.57)
MAX
GLASS SEALANT
0.22
(5.59)
MAX
0.125
(3.175)
MIN
0.012 (0.305)
0.008 (0.203)
0.02 (0.5)
0.016 (0.406) 0.099 (2.28)
0.11 (2.79)
0.06 (1.52)
0.05 (1.27)
15؇
0؇
SEATING
PLANE
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42
28-Terminal Leadless Chip Carrier
(E-28A)
1
0.100 (2.54)
0.064 (1.63)
PIN 1
INDEX
0.075 (1.91)
REF
2
0.458 (11.63)
0.442 (11.23)
0.020
؋
45؇ (0.51
؋
45؇) REF
4
26
25
28
5
1
0.055 (1.40)
0.045 (1.14)
0.028 (0.71)
0.022 (0.56)
TOP
VIEW
BOTTOM
VIEW
19
18
12
11
0.040
؋
45؇ (1.02
؋
45؇) REF 3 PLCS
0.055 (1.40)
0.045 (1.14)
NOTES
1
THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS.
APPLIES TO ALL FOUR SIDES.
2
TERMINALS ARE GOLD PLATED OR SOLDER DIPPED.
–8–
REV. D
相关型号：
AD9012TE/883B
IC 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQCC28, CERAMIC, LCC-28, Analog to Digital Converter
ADI
AD9012TE/883B
ADC, Proprietary Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, Bipolar, CQCC28, CERAMIC, LCC-28
ROCHESTER
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